CN104051466B

CN104051466B - Array arrangement for 3D NAND memory

Info

Publication number: CN104051466B
Application number: CN201310409202.7A
Authority: CN
Inventors: 施彦豪; 萧逸璿
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2013-03-13
Filing date: 2013-09-10
Publication date: 2017-01-11
Anticipated expiration: 2033-09-10
Also published as: CN104051466A

Abstract

The invention relates to a semiconductor device and an operating method thereof. The semiconductor device includes a plurality of active strips, where active strips in the plurality are coupled together at one end by a pad and terminated at another end by a conductive line. The device includes memory cells at cross-points between the plurality of active strips and a plurality of word lines. The device includes string select structures arranged in an interlaced configuration as side gates for active strips. The device includes control circuitry, configured to turn on a particular active strip by applying a turn-on voltage to two adjacent and staggered string select structures for the particular active strip, and to turn off a second particular active strip by applying a turn-off bias to at least one adjacent and staggered string select structure for the second particular active strip. The turn-off bias applied to at least one adjacent and staggered string select structure can be a ground voltage, a non-negative voltage, and a floating condition.

Description

3DNAND storage arrangement and operational approach thereof

Technical field

The application is related to high density memory devices, in particular to storage arrangement memory element therein one The most decoded storage arrangement chosen and operational approach thereof in three-dimensional (3D) array.

Background technology

High density memory devices is designed to comprise the array of the memory element of flash cell or other kenel.One In a little examples, those memory element comprise the thin film transistor (TFT) being configured in three-dimensional (3D) framework.

In an example, 3D storage arrangement comprises the multiple layer stack of many NAND string of multiple memory cell.Those are folded Layer comprises by insulant separate multiple active positions bar.This 3D storage arrangement comprises and includes multiple word line structure, many Individual bit string choice structure and multiple ground connection select an array of line, and this array is configured on this multiple layer stack orthogonally. The multiple memory element comprising multiple charge storing structure are the multiple active position strips being formed in this multiple layer stack The both side surface of the crossover location between thing and the plurality of word line structure.3D nand memory containing multiple bit string choice structures The array configuration mode of element can affect array efficiency, and/or the ON/OFF of the NAND bit string lamination of multiple 3D storage arrangement is special Property.

One 3D storage arrangement uses finger shape wordline layout to design (VG) with vertical gate wordline, and has relatively low Array efficiency because it uses two bit strings to select the set of line (SSL) grid structure, two horizontal groundings to select lines (GSL) with two ground connection contact point set.It is dynamic that another 3D storage arrangement uses independent bigrid (IDG) to carry out bit line decoding Make.This method has higher array efficiency, because it uses a SSL grid structure set (rather than two), a level connects Ground selects line (rather than two) and an earth lead (rather than two ground connection contact point set).But, the second 3D memorizer Device shows the electric current on/off characteristics when switching the current channel that SSL grid structure is controlled with relative mistake.

Accordingly, it is desirable to provide the array structure of a kind of 3D integrated circuit storage with high array efficiency, and possess The electric current on/off characteristics of outstanding NAND position lamination string.

Summary of the invention

A kind of semiconductor device includes multiple active positions bar, and the end at the plurality of active position bar connects coupling Close to a connection pad, be connected by a wire at the other end.This device comprises a plurality of wordline.At the plurality of active position bar And the intersection between the plurality of wordline defines multiple memory element.This device comprises multiple bit string choice structure, arranges Multiple sides in this multiple active position bar, and arrangement mode be designed to one alternating expression configuration.

The plurality of bit string choice structure is configured to as multiple sides grid of multiple passages in the bar of the plurality of active position Pole, thereby forms multiple bit string and selects switch.The plurality of bit string choice structure is arranged on this connection pad and the plurality of memory element Between.The plurality of bit string choice structure comprises one first subclass and one second subclass, and this first subclass is away from this connection pad Being placed in one first distance range, this second subclass is being placed in the range of this connection pad one second distance, this first away from Different from this second distance scope from scope.In one embodiment, this first distance range does not weigh with this second distance scope Folded.In another embodiment, this first distance range has a part of overlapping with this second distance scope.In the plurality of active position The plurality of string choice structure between bar has enough length can effectively control the portion in the bar of multiple active positions Part channel switching, and it is formed at the side grid between two neighbouring active position bars.

Multiple active position bar in the bar of the plurality of active position is coupled to this first subclass on one first side With the bit string choice structure in this second subclass one, and relative to be coupled on one second side of this first side this A bit string choice structure in one subclass and this second subclass its another.

This device comprises the insulation material being filled in the bar of the plurality of active position between the bar of the plurality of active position Material, this insulant is configured such that this insulant is arranged in this first distance range of this connection pad, and this connection pad is adjacent to This second side of the plurality of active position bar, the plurality of active position bar and the plurality of bit string being coupled to this first side are selected Selecting structure relative, and this insulator is set away from this connection pad in the range of a second distance, this connection pad is adjacent to the plurality of to be had This first side of position, source bar, the plurality of active position bar and the plurality of bit string choice structure phase being coupled to this second side Right.

The plurality of bit string choice structure selects a specific active position bar in the bar of the plurality of active position.Polynary A specific bit line, this specific active position bar and a combination selection of the particular word line in this polynary wordline in bit line A particular memory location in the plurality of memory element of identification.A specific bit string in the plurality of bit string choice structure selects knot Structure controls one first active band and the electric conductivity of one second active band in the bar of the plurality of active position.

This device further includes the control circuit being coupled to the plurality of bit string choice structure, and in order at the plurality of active position bar Selecting a specific active position bar in shape thing, this control circuit applies a connection voltage and configures conduct in this first subclass One first bit string choice structure of the side grid of this specific active position bar, and this control circuit apply this connection voltage to This second subclass configures one second string choice structure of side grid as this specific active position bar.

In order to not select be adjacent to this specific active position bar one first adjacent to active position bar and one second neighbour Nearly active position bar, wherein this first this second bit string selection being coupled in this second subclass adjacent to active position bar Structure, and this second this first bit string choice structure being coupled in this first subclass adjacent to active position bar, this control Circuit applies one the 3rd bit string choice structure that a shutoff is biased in this first subclass, the 3rd bit string choice structure configuration As this first adjacent to the side grid of active position bar, and this control circuit applies this shutoff and is biased into this second subclass In one the 4th bit string choice structure, the 4th bit string choice structure configuration as this second adjacent to the side of active position bar Grid.This shutoff bias comprises a ground voltage, a non-negative voltage and is applied to the one of the 3rd and the 4th string choice structure One of them of quick condition.

The plurality of active position bar and this connection pad are provided on a multiple structure.This multiple structure comprises multiple leading Electric layer and multiple insulating barriers, each conductive layer includes multiple bit line and a connection pad.And each bit string choice structure is vertically On direction, multiple position conductive layers can be controlled simultaneously within each active position bar, allow the plurality of bit string select knot Multiple sides grid of the active position bar that structure is configured as in the plurality of layer.

Other are found in following graphic, detailed embodiment and claim model about embodiments of the invention and advantage Enclose.

Accompanying drawing explanation

In conjunction with accompanying drawing, this technology can be understood in more detail, wherein from the following description provided with example:

Fig. 1 is the perspective view illustrating a 3D NAND memory array structure；

Fig. 2 illustrates the layout of the one first array configuration for a 3D NAND memory device；

Fig. 3 is a form, in this form sign picture 2 first array configuration in multiple bit string choice structures on multiple Voltage is in order to turn on active position bar 2；

Fig. 4 is the layout of the one second array configuration for a 3D NAND memory device；

Fig. 5 A is a form, many on the multiple bit string choice structures in the second array configuration in this form sign picture 3 Individual voltage is in order to turn on active position bar 2；

Fig. 5 B illustrates the I-E characteristic of the plurality of bit string choice structure in the second array configuration；

Fig. 6 is the illustration of an array configuration for a 3D NAND memory device of the embodiment according to this technology Layout；

Fig. 7 A is a form, this form illustrate shown in Fig. 6 multiple alternating expressions configuration string choice structure on multiple Voltage is in order to turn on active position bar 2；

Fig. 7 B illustrates the I-E characteristic of the string choice structure of the multiple alternating expressions configuration shown in Fig. 6；

Fig. 8 illustrate the string choice structure that configures for this array of a 3D NAND memory device as shown in Figure 6 with The dopant species of active position bar inner conducting layer sets with the analog parameter of concentration；

Fig. 9 illustrates this array for a 3D NAND memory device as shown in Figure 6 electron density when operation Simulation result in order to prove that this method can correctly turn on active position bar 2 and close neighbouring active position bar 1 With 3；And

Figure 10 is the 3D comprising the string choice structure with the configuration of multiple alternating expression of the embodiment according to this technology The schematic diagram of the semiconductor device of NAND storage array.

[symbol description]

102,103,104,105 active bars

102B, 103B, 104B, 105B connection pad

112,113,114,115 active bars

112A, 113A, 114A, 115A connection pad

119,109 bit string choice structure

125-1WL to 125-NWL wordline

GSL126,127 ground connection select line

210,215 connection pad

211,241,251 length

220,225 interval

230 wordline

232 wordline live widths

234 insulated lengths

410 connection pads

411,441,451,461 length

422,425 first side

423,424 offside

421,422,426 opposite side

430 wordline

610 connection pads

611 length

621 and 626 opposite sides

623 second sides

624 first sides

630 wordline

632 wordline live widths

634 insulation live widths

651 length

645 bottoms

646 tops

661 conducting wires

690 insulant

810,820,830 bit string choice structure

815,825 active bars

860 share earth lead

910,920,930 bit string choice structure

915,925 active bars

926,927 two ends

1058 plane decoders

1059 bit lines

1060 storage arrays

1061 column decoders

1062 wordline

1063 line decoders

1064 bit strings select line

1065 buses

1066,1068 block

1067 data/address bus

1069 bias arrangement state machines

1071 Data In-Lines

1072 DOL Data Output Lines

1074 circuit

ML1, ML2, ML3 metal level

Bar 1-active position, BL1-BL6 active position bar 6

SSL1-SSL7 bit string choice structure 1-bit string choice structure 7

D1 the first distance range

D2 second distance scope

W1, W2 width

WL0 wordline 0

Detailed description of the invention

There is provided and describe in detail about graphic embodiment.

Fig. 1 is the side view illustrating a 3D NAND memory array structure.For illustrative purposes, do not paint in graphic Insulant is shown so that extra structure can be visible.For example, between multiple active positions bar in multiple laminations Insulating barrier between (such as: 112-115) is removed, and the insulating barrier quilt between multiple laminations of multiple active positions bar Remove.

Multiple tier array is formed on an insulating barrier, and comprises multiple wordline of conformal with the plurality of lamination (conformal) 125-1WL、…、125-N WL.The plurality of lamination comprises multiple active positions bar 112,113,114,115.At same level In multiple active position bar by a connection pad electrical couplings together, this connection pad is configured with to contact top and leads One touchdown area of line.As it is shown in figure 1, the plurality of connection pad for multiple layers can be configured to multiple hierarchic structure, and each This touchdown area on connection pad has one or more columnar metal thing, in order to connect the plain conductor of top.If Wanting or need a special technique initialization, the plurality of connection pad is designed to the touchdown area of the touchdown area on connection pad Multiple patterns in addition to a simple ladder.

The wordline number illustrated, cumulative to N by 1 toward front from the integrally-built back side, it is adaptable to the storage page of even number. For the storage page of odd number, this wordline number is from the integrally-built back side toward front by N to 1 decrescence.

Multiple connection pad 112A, 113A, 114A and 115A are connected to multiple active position bar alternately, in the most each layer Active position bar 112,113,114 and 115.As illustrated, these multiple connection pad 112A, 113A, 114A the most upwards connect with 115A It is connected to the different metal bit line being connected to decoding circuit to select multiple plane in the array.These multiple connection pad 112A, 113A, 114A can complete when forming multiple active position bar with 115A the most simultaneously.

Multiple connection pad 102B, 103B, 104B and 105B terminate other active position bars alternately, the most in each layer Multiple active position bar 102,103,104 and 105.As illustrated, these multiple connection pad 102B, 103B, 104B are electrical with 105B It is connected to the not corresponding lines being connected to decoding circuit to select multiple plane in the array.These multiple connection pad 102B, 103B, 104B can complete when forming multiple active position bar with 105B the most simultaneously.

The lamination of any given multiple active position bar coupled to the plurality of connection pad 112A, 113A, 114A and 115A, Or the plurality of connection pad 102B, 103B, 104B and 105B, but this two groups of connection pads will not be simultaneously coupled to.One multiple active position One lamination of bar has the described of the orientation orientation of line end (orientation of bit line end to source electrode line end or the source electrode line end put in place) One of them of two kinds of relative orientations.Such as, this lamination of multiple active positions bar 112,113,114 and 115 has bit line End is to the orientation (orientation) of source electrode line end, and this lamination of multiple active positions bar 102,103,104 and 105 tool There is the source electrode line end orientation to bit line end.

One end of this lamination of multiple active positions bar 112,113,114 and 115 and the plurality of connection pad 112A, 113A, 114A with 115A couples, and selects line (SSL) grid structure 119, ground connection to select line GSL126, wordline 125-1WL extremely by bit string 125-N WL, ground connection select line GSL127, and are connected with source electrode line 128 at the other end.Multiple active positions bar 112, 113, this lamination of 114 and 115 does not extend to the plurality of connection pad 102B, 103B, 104B and 105B.

One end of this lamination of multiple active positions bar 102,103,104 and 105 and the plurality of connection pad 102B, 103B, 104B with 105B couples, and selects line (SSL) grid structure 109, ground connection to select line GSL127, wordline 125-1WL extremely by bit string 125-N WL, ground connection select line GSL126, and are connected with source electrode line (being covered by other graphic parts) at the other end.Multiple This lamination of active position bar 102,103,104 and 105 does not extend to the plurality of connection pad 112A, 113A, 114A and 115A.

One storage material layer is by the plurality of wordline 125-1WL to 125-N WL and the plurality of active position bar 112- 115 and 102-105 divide out.Multiple ground connection select line GSL126 and GSL127 conformal with the plurality of active position bar (conformal), similar to the plurality of wordline.

One end of each lamination of active position bar couples with multiple connection pads, and in the other end and source line phase Even.Such as, one end of this lamination of multiple active positions bar 112,113,114 and 115 and multiple connection pad 112A, 113A, 114A with 115A couples, and is connected with source electrode line 128 at the other end.At the near-end of Fig. 1, active position bar be often separated by one One end of individual lamination couples with 105B with the plurality of connection pad 102B, 103B, 104B, and active position bar be often separated by one The source electrode line that separates of the other end and of lamination be connected.Long-range at Fig. 1, the lamination being often separated by of active position bar One end couple with 115A with the plurality of connection pad 112A, 113A, 114A, and active position bar be often separated by the lamination of with One source electrode line separated is connected.

Multiple bit lines and multiple bit strings select line to be formed at metal level ML1, ML2 and ML3.Multiple transistors are formed at Cross point between the plurality of active position bar (such as, 112-115) and the plurality of wordline 125-1WL to 125-N WL Place.In the plurality of transistor, this active position bar (such as, 113) is as the passage area of this device.

The phase that multiple bit string choice structures (such as, 119 and 109) are defined at the plurality of wordline 125-1WL to 125-NWL It is patterned with the period of step.Multiple transistors are formed between the plurality of active position bar (such as, 112-115) and are somebody's turn to do Intersection between multiple bit string choice structures (such as, 119 and 109).These multiple transistors are as coupleding to decoding circuit Position selects switch, in order to select specific lamination in the array.

Fig. 2 illustrates the layout of the one first array configuration for finger type vertical gate (VG) 3D NAND memory device Figure.In order to reference, (such as, the 125-1WL in Fig. 1 is extremely with the plurality of wordline in the structure shown here to be positioned at " X " axle of horizontal direction In 125-N WL with Fig. 2 230) parallel, and it is positioned at " Y " axle and the plurality of active position strip in the structure shown here of horizontal direction Thing (such as, the BL1-BL6 in 112-115 or Fig. 2 in Fig. 1) is parallel, and is positioned at " Z " axle of vertical direction and in this structure In the plurality of wordline and the plurality of active position bar orthogonal.

In the layout of Fig. 2, the configuration of this array comprises multiple active positions bar.The plurality of memory element is arranged at multiple Active position bar (such as, BL1-BL6) and multiple intersections of multiple wordline (such as, 230).Multiple neighbouring active positions Bar between the relative orientation orientation of line end (orientation of bit line end to source electrode line end and the source electrode line end put in place) alternately.Many at this In one orientation of individual active position bar, the active position bar being often separated by is prolonged by the connection pad (such as, 210) at top Reach the source electrode line at bottom.In a relative direction of the plurality of active position bar, often it is separated by the active position bar of Shape thing is extended to the connection pad bottom this (such as, 215) by the source electrode line at this top.

Cover on the plurality of active position bar (such as, BL1-BL6) be multiple horizontal wordline (such as, 230) with And multiple horizontal grounding selects line GSL (even number) and GSL (odd number).And, cover and on the bar of the plurality of active position be Multiple bit strings select line SSL grid structure.In an orientation of the plurality of active position bar, the plurality of string choice structure (example As, SSL1, SSL3 and SSL5) cover every at this top of the plurality of active position bar (such as, BL1, BL3 and BL5) It is separated by the active position bar of.In this relative direction of the plurality of active position bar, the plurality of bit string selects knot Structure (such as, SSL2, SSL4 and SSL6) covers at the bottom of the plurality of active position bar (such as, BL2, BL4 and BL6) Often it is separated by the active position bar of.In the either case of above two, the plurality of bit string choice structure control between Electric connection between any active position bar and the relative connection pad (such as, 210 and 215) of this active position bar.

The plurality of connection pad (such as, 210 and 215) can have the length (such as, 211) of about 0.5 micron.The plurality of position String choice structure (such as, SSL1-SSL6) all can have the length (such as, 241) of about 0.25 micron.The plurality of level connects Ground selects the length (such as, 251) that line GSL (odd number) and GSL (even number) all can have about 0.25 micron.Many between this The plurality of bit string choice structure (such as, SSL1, SSL3 of the top end of individual active position bar (such as, BL1, BL3 and BL5) And (such as, the interval 220 SSL5) and between this horizontal grounding selection line GSL (odd number) allows the plurality of active position bar BL2, BL4 and BL6) source terminal be connected to multiple ground connection contact point GND.This interval 220 can be of about 0.4 micron.It is situated between In the bottom end at the plurality of active position bar (such as, BL2, BL4 and BL6) the plurality of bit string choice structure (such as, SSL2, SSL4 and SSL6) and this horizontal grounding select the interval 225 between line GSL (even number), it is allowed to the plurality of active position strip The source terminal of thing (such as, BL1, BL3 and BL5) is connected to multiple ground connection contact point GND.This interval 225 can be of about 0.4 Micron.

The plurality of horizontal wordline (such as, 230) is interlocked with insulant (not illustrating).Each horizontal wordline can have greatly The wordline live width (such as, 232) of about 33 nanometers (nm) or less.Insulant between two wordline can have about 33 The insulation live width (such as, 234) of nanometer or less.The plurality of horizontal grounding selects can between line GSL (odd number) and GSL (even number) It is provided with 66 wordline.The plurality of wordline can with oneself align double patterning (SADP) manufacture.

The array efficiency of the 3D NAND memory device that Fig. 2 illustrates is relatively low, because this storage arrangement is necessarily To middle use for one group of bit string choice structure (such as, SSL1, SSL3 and SSL5) of the plurality of active position bar, and In this relative orientation use for the plurality of active position bar another group bit string choice structure (such as, SSL2, SSL4 with SSL6).This storage arrangement also uses this horizontal grounding for the plurality of active position bar to select line GSL in an orientation (even number), and use this horizontal grounding for the plurality of active position bar to select line GSL (strange in this relative orientation Number).Additionally, this storage arrangement one orientation in use the plurality of active position bar source terminal at one group of ground connection Contact point (such as, BL1, BL3 and BL5), and use in this relative orientation the plurality of active position bar this source Another extreme group ground connection contact point (such as, BL2, BL4 and BL6).These two groups of SSL grid structures, these two horizontal grounding choosings Select line and reduce this array efficiency with these two groups of ground connection contact points.Such as, this battle array of the 3D NAND memory device illustrated in Fig. 2 Row usefulness can be 65.4%, and the space that wherein this array efficiency is used by multiple memory element is relative to multiple memory element The space used and the ratio comprising SSL/GSL grid and the space of the plurality of connection pad.

This 3D NAND memory device comprises multiple planes of multiple memory element.Multiple bit lines are via connection pad (such as, In Fig. 2 210 and 215) and in the plurality of plane of multiple memory element, select a specific plane.This specific plane is by many Individual bit string choice structure, multiple horizontal grounding select line GSL (odd number) with GSL (even number) and multiple wordline and decoded.In order to In each plane, select a specific lamination (such as, BL2), apply a positive SSL voltage (V_ssL) to this bit string choice structure (example As, SSL2), this bit string choice structure (such as, SSL2) is coupled to the multiple grid at multiple opposite sides of this specific lamination Pole.In order to not select other lamination (such as, BL1 and BL3-6), apply the voltage of one 0 volts (0V) to being coupled in this its The plurality of bit string choice structure (such as, SSL1 and SSL3-6) of the multiple grids at multiple opposite sides of his lamination.

Fig. 3 is a form, and it is shown in the multiple voltages on the multiple string choice structures in the configuration of this first array, wherein This first array configures in order to select the specific lamination in multiple laminations of many NAND bit string of multiple memory element.Fig. 3 Example show, for this positive SSL voltage (V_SSL) value be 3.3V.In order to not select other laminations (such as, BL1 and BL3- 6) voltage of one about 0 volt, is applied to the plurality of bit string choice structure (such as, SSL1 and SSL3-being coupled in other laminations 6)。

Fig. 4 joins for one second array for an independent bigrid, vertical gate (IDG, VG) 3D NAND memory device The layout put.In order to reference, it is positioned at " X " axle of horizontal direction with the plurality of wordline in the structure shown here (such as, in Fig. 1 In 125-1WL to 125-N WL or Fig. 4 430) parallel, and it is positioned at the plurality of with in the structure shown here of " Y " axle of horizontal direction Active position bar (such as, the BL1-BL6 in 112-115 or Fig. 4 in Fig. 1) is parallel, and is positioned at " Z " axle of vertical direction Orthogonal with the plurality of wordline in the structure shown here and the plurality of active position bar.

In the layout of Fig. 4, the configuration of this array comprises multiple active positions bar.Memory element is arranged at multiple active On the cross point of position bar (such as BL1-BL6) and wordline (such as 430).Depicted in multiple relative orientations with Fig. 2 The plurality of active position bar of middle extension contrasts, the plurality of active position bar (such as, BL1-BL6) in Fig. 4 from This connection pad (such as, 410) at this top arrives this source electrode line, extends in an orientation, and this source electrode line is attached to bottom this locate One share earth lead GND.

Covering on the plurality of active position bar (such as, BL1-BL6) is the plurality of horizontal wordline (such as, 430) And this horizontal grounding selects line GSL.Also covering on the bar of the plurality of active position is the plurality of bit string choice structure (example As, SSL1-SSL7).The plurality of bit string choice structure (such as, SSL1-SSL7) covers in the plurality of active position bar (example Such as, BL1-BL6) this top end the plurality of active position bar on.The plurality of bit string choice structure controls any active Electric connection between position bar and the corresponding connection pad (such as, 410) of this active position bar.

The plurality of connection pad (such as, 410) can have the length (such as, 411) of about 0.5 micron (μm).The plurality of position String choice structure (such as, SSL1-SSL6) all can have the length (such as, 441) of about 0.25 micron.This horizontal grounding selects Select line GSL and can have the length (such as, 451) of about 0.25 micron.Bottom this, this shared earth lead GND at place can have There is the size (such as, 461) of about 0.2 micron.

The plurality of horizontal wordline (such as, 230) is interlocked with insulant (not illustrating).Each horizontal wordline can have greatly The wordline live width (such as, 232) of about 33 nanometers (nm).Insulant between two wordline can have about 33 nanometers Insulation live width (such as, 234).This horizontal grounding selects arrange between line GSL and the plurality of string choice structure (SSL1-SSL7) There are 66 wordline.

Compared to the array efficiency of the 3D NAND memory device being used in depicted in Fig. 2, it is used in the 3D depicted in Fig. 4 The array efficiency of NAND memory device is relatively high, this in the diagram depicted storage arrangement that results from use for One group of string choice structure of the plurality of active position bar, rather than use two groups of string choice structures as shown in Figure 2.Fig. 4 illustrates This storage arrangement also use single horizontal grounding to select line GSL, rather than in Fig. 2, double horizontal groundings select line GSL (even number) With GSL (odd number).Share additionally, this storage arrangement illustrated in Fig. 4 uses for the single of the plurality of active position bar Earth lead, rather than use one group at this source terminal of the plurality of active position bar to connect in an orientation as shown in Figure 2 Ground contact point, and in this relative orientation, use another group ground connection contact at this source terminal of the plurality of active position bar Point.Result is, this storage arrangement illustrated in Fig. 4 improves this array efficiency.Such as, the 3D NAND storage illustrated in Fig. 4 The array efficiency of device device can be 83.7%.

This 3D NAND memory device comprises multiple planes of multiple memory cell.Multiple bit lines are via multiple connection pads 410 Selecting a specific plane in the plurality of plane of multiple memory cell, such as, the plurality of connection pad 410 is configured to a ladder knot Structure.This specific plane is decoded by multiple bit string choice structures, a horizontal grounding selection line GSL and multiple wordline.In order to In each plane, select a specific active band (such as, BL2), apply a positive SSL voltage (V_ssL) specific have at this to being coupled in Multiple bit string choice structure (such as, SSL2 at multiple opposite sides (such as, the 423 and 424) place of position, source bar (such as, BL2) With SSL3).But, this positive SSL voltage (V_ssL) be also applied in multiple neighbouring active positions bar (such as, BL1 and BL3) Multiple first sides (such as, 422 and 425).In general, in order to effectively close neighbouring active position bar, need to apply one Individual shutoff voltage (V_inhibit) at the bit string choice structure of multiple correspondences.For the structure of Fig. 4, selected in order to not select to be adjacent to Multiple neighbouring active position bar (such as, BL1 and BL3) of the active position bar (such as, BL2) selected, needs to apply one negative Turn off voltage (V_inhibit) on the bit string choice structure (such as, SSL1-SSL4) that multiple correspondences are neighbouring, the plurality of correspondence is neighbouring Bit string choice structure (such as, SSL1-SSL4) be coupled in the plurality of neighbouring active position bar (such as, BL1 and BL3) Multiple grids at opposite side (such as, 422 and 426) place, in order to offset multiple neighbouring active position bars (such as, BL1 with BL3) the plurality of first side is at multiple bit string choice structures (such as, SSL2 and SSL3) this positive SSL voltage upper of multiple grids (V_ssL) impact.

Fig. 5 A is a table of the multiple voltages being shown on the multiple string choice structures in this second array configuration (IDG), Wherein the configuration of this second array is in order to select a specific active position bar in the bar of multiple active positions.Paint at such as Fig. 5 A This positive SSL voltage (V in the example shown, on multiple opposite sides of a selected active band (such as, BL2)_SSL) value is 3.3V, and it is adjacent to the multiple unselected active position bar of this selected active position bar (such as, BL2) (such as, BL1 and BL3) on this shutoff voltage (V_inhibit) value be-7V.In order to not select to be not adjacent to this selected active position bar The multiple active position bar (such as, BL4-6) of shape thing, to be not adjacent to this selected to being coupled in apply the voltage of about 0 volt The plurality of unselected active position bar (such as, BL4, BL5 and BL6) the plurality of bit string of active band (such as, BL2) selects Structure (such as, SSL5-7).

Therefore, technology described herein comprises semiconductor device, and this semiconductor device comprises a memory cell array, This memory cell array comprises multiple laminations of multiple bit strings of multiple memory element and multiple bit lines, and in the plurality of lamination The plurality of bit string coupled to the plurality of bit line via multiple connection pads, the plurality of connection pad is arranged in the plurality of lamination the plurality of One end of bit string, and the plurality of bit string choice structure is arranged at the plurality of connection pad with these are many in the plurality of lamination Between this first end of individual bit string, and for configure alternately.One alternating expression configuration comprises a layout, the most the plurality of bit string Two bit string choice structures in choice structure are to arrange along each lamination in the plurality of lamination, being somebody's turn to do on each lamination Two bit string choice structures are along the plurality of stack excursions to form the configuration of this alternating expression.

And, technology described herein comprises semiconductor device, and this semiconductor device comprises and is coupled to multiple bit string The control circuit of choice structure, wherein this control circuit applies multiple non-zeros, on-state voltage to the plurality of bit string selects knot Two bit string choice structures in structure, these two bit string choice structures are all adjacent to a selected bit string, and apply multiple Turn off remaining the bit string choice structure in voltage extremely the plurality of bit string choice structure to block the electric current in other bit strings.A kind of The method manufacturing semiconductor device, the method comprises provides the control circuit being coupled to multiple bit string choice structure, wherein should Control circuit applies two bit string choice structures in multiple non-zeros, on-state voltage to the plurality of bit string choice structure, should Two bit string choice structures are all adjacent to a selected bit string, and apply multiple shutoff voltage to the plurality of bit string selection knot Remaining bit string choice structure in structure is to block the electric current in other bit strings.A kind of method operating semiconductor device, should Method comprises two the bit string choice structures applied in multiple non-zeros, on-state voltage to the plurality of bit string choice structure, should Two bit string choice structures are all adjacent to a selected bit string, and apply multiple shutoff voltage to the plurality of bit string selection knot Remaining bit string choice structure in structure is to block the electric current in other bit strings.

Fig. 5 B illustrates the multiple I-E characteristics for the plurality of bit string choice structure shown in Fig. 4.From top to bottom, Eight current-voltage curves are corresponding to this shutoff voltage V_inhibit=0V ,-1V ... ,-7V.As shown in Figure 4, a positive SSL is applied Voltage (V_SSL) to the grid at non-selected one first side (such as, a 422) place adjacent to active position bar (such as, BL1) Pole, and apply a shutoff voltage (V_inhibit) to the phase in non-selected neighbouring active position bar (such as, BL1) The grid at offside (such as, 421) place.As shown in Figure 5 B, in this first side (such as, 422 in Fig. 4), there is this positive SSL voltage (such as, the VSSL=3.3V in Fig. 5 A), and in this non-selected neighbouring active position bar (such as, the BL1 in Fig. 4) This opposite side (such as, 421 in Fig. 4) place has the scope this shutoff voltage (V between-1V to-7V_inhibit), turn off one For this non-selected drain current adjacent to active position bar between V in state_inhibitAbout the 3 × 10 of=-7V place^-9 Ampere and at V_inhibitAbout the 10 of=-1V place^-7Between An Pei.At V_SSLAt=3.3V, selected for one in an on-state The drain current (such as, the BL2 of Fig. 4) of the active position bar selected is between 10^-7To 10^-6Between An Pei.Therefore, connect for this Logical and this off state the plurality of drain current is by less than about 10³Graph One factor and be distinguished, so show relative mistake Current turns ON/turn-off characteristic.

Fig. 6 is the 3D NAND of the bit string choice structure comprising the configuration of multiple alternating expression of the embodiment according to this technology The illustration layout of an array configuration of storage arrangement.In order to reference, be positioned at " X " axle of horizontal direction with in the structure shown here The plurality of wordline (such as, 630 in 125-1WL to 125-N WL in Fig. 1 or Fig. 6) is parallel, and is positioned at level side in structure To " Y " axle and the plurality of active position bar (such as, the BL1-in 112-115 or Fig. 6 in Fig. 1 in the structure shown here BL6) parallel, and it is positioned at " Z " axle and the plurality of wordline in the structure shown here and the plurality of active position bar of vertical direction Orthogonal.

This device comprises multiple active positions bar (such as, BL1-BL6), wherein in the bar of the plurality of active position One end one connection pad (such as, 610) of multiple active positions bar couples, and the other end and a conducting wire (such as, 661) phase Even.This device comprises multiple wordline (such as, 630) and in the plurality of active position bar (such as, BL1-BL6) with the plurality of Multiple memory element of the intersection between wordline (such as, 630).This device comprises covering in the plurality of wordline and this conduction A horizontal grounding on the plurality of active position bar between circuit (such as, 661) selects line GSL.This device comprises multiple Bit string choice structure (such as, SSL1-SSL7), the plurality of bit string choice structure configures using as the plurality of active position bar Multiple sides grid, and these side grids to be configured to one staggered.Contrast with this first array configuration illustrated in Fig. 2, should Multiple active positions bar has a bit line end identical orientation to source electrode line end.Such as, the multiple active position bar in Fig. 6 (such as, BL1-BL6) extends to this source electrode line from this connection pad (such as, 610) at this top, and extends in an orientation, should Source electrode line is coupled to this conducting wire (such as, 661) in this bottom end.

The plurality of bit string choice structure (such as, SSL1-SSL7) is configured to as the plurality of active position bar (example Such as, BL1-BL6) in multiple sides grid of multiple passages, thereby form multiple bit string and select switch.The plurality of bit string choice structure It is disposed between this connection pad (such as, 610) and the plurality of memory element.The plurality of bit string choice structure comprises one first subset Close (such as, comprising SSL1, SSL3, SSL5 and SSL7) and one second subclass (such as, comprise SSL2, SSL4, SSL6 with SSL8), this first subclass is arranged in this connection pad (such as, 610) one first distance range (such as, D1), this second son Set is arranged in this connection pad (such as, 610) a second distance scope (such as, D2).This first scope and this second scope Different.The plurality of bit string choice structure has enough length between the bar of the plurality of active position and the plurality of bit string is selected Structure is as the plurality of side grid of in the bar of the plurality of active position two neighbouring active position bars (such as, BL2 and BL3) Pole.

In one embodiment, this first scope and this second scope are along the one of active position bar (such as, BL1-BL6) Direction is without overlapping each other.Such as, multiple bit string choice structure SSL5 and SSL6 can be placed so that many along this One direction of individual active position bar, a top 646 of this bit string choice structure SSL6 is less than this bit string choice structure SSL5's One bottom 645.

In another alternate embodiment, this first scope and this second scope can be along directions of active position bar Have and partly overlap.Such as, multiple bit string choice structure SSL5 and SSL6 can be placed so that along the plurality of active position One direction of bar, this this bottom 645 higher than bit string choice structure SSL5, top 646 of this bit string choice structure SSL6.

Multiple active position bar (such as, BL2) in the bar of the plurality of active position is coupling on one first side To at this first subclass (such as, SSL1, SSL3, SSL5 and SSL7) and this second subclass (such as, SSL2, SSL4, SSL6 With SSL8) a bit string choice structure (such as, SSL3) in one, and relative on one second side of this first side being coupling A bit string choice structure (such as, SSL2) in this first subclass and this second subclass its another.In the plurality of bit string The difference that different bit string choice structures in choice structure are electrically coupled in the bar of the plurality of active position is right.Such as, should Bit string choice structure SSL2 is to arrange along a pair active bar BL1 and BL2, but this bit string choice structure SSL3 is edge A pair active bar BL2 and BL3 to arrange.

This device comprises the insulation material being filled in the bar of the plurality of active position between the bar of the plurality of active position Material 690 (such as, between BL1 and BL2 and between BL2 and BL3), this insulant 690 is configured such that this insulation Material 690 is set in this first distance range (such as, D1) away from this connection pad (such as, 610), and this connection pad (such as, 610) is adjacent Be bordering on this second (left) side of the plurality of active position bar (such as, BL2), the plurality of active position bar (such as, BL2) with The plurality of bit string choice structure (such as, SSL3) being coupled to this first (right) side is relative, and this insulant 690 is away from this connection pad Being set in a second distance scope (such as, D2), this connection pad (such as, 610) is adjacent to the plurality of active position bar This first (right) side, the plurality of active position bar (such as, BL2) and the plurality of bit string being coupled to this second side (left) select Structure (such as, SSL2) is relative.

In one embodiment, this connection pad (such as, 610) can have the length (such as, 611) of about 0.5 micron (μm).Should Every a string choice structure energy in one first subclass (such as, SSL1, SSL3, SSL5 and SSL7) of multiple bit string choice structures Enough there is the width W1 of about 0.25 micron.One second subclass of the plurality of string choice structure (such as, SSL2, SSL4 with SSL6) the every a string choice structure in can have the width W2 of about 0.25 micron.The plurality of width W2 with W1 can be identical Or it is different.The plurality of width W1 with W2 is to be chosen so as to operation the most in manner described herein control the plurality of active Electric current in position bar (such as, BL1-BL6).

The plurality of horizontal wordline (such as, 630) is interlocked with insulant (not illustrating).Each horizontal wordline can have greatly The one wordline live width (such as, 632) of about 33 nanometers (nm).Insulant between two wordline can have about 33 nanometers Insulation live width (such as, 634).This horizontal grounding select line GSL and the plurality of string choice structure (SSL2, SSL4 and SSL6) it Between can be provided with 66 characters.This horizontal grounding selects the length (such as, 651) that line GSL can have about 0.25 micron.At this This common ground line GND at Di Bu can have the size (such as, 661) of about 0.2 micron.

The plurality of bit string choice structure selects a specific active position bar in the bar of multiple active positions.Utilize multiple One combination selection of the particular word line in a specific bit line, this specific active position bar and the plurality of wordline in bit line Carry out a particular memory location of identification the plurality of memory element 3D array.Such as, utilization coupled to a certain bits of this connection pad 610 Line, it coupled to the plurality of bit string choice structure SSL2 and SSL3 and this horizontal grounding and select a specific active position strip of line GSL Thing BL2 and particular word line WL0 are debated and are known the one of the intersection being positioned at this particular word line WL0 and this active position bar BL2 Particular memory location.

This storage arrangement can comprise an extra bit string choice structure further, and this extra bit string choice structure exists On side in the plurality of bit string choice structure, there is a terminal position so that this extra bit string choice structure is only along this One active position bar of multiple active positions bar is arranged.Such as, an extra bit string choice structure SSL1 is the plurality of There is on the left of in bit string choice structure one terminal position so that this extra bit string choice structure SSL1 is only along one Individual active position bar BL1 is arranged.

This storage arrangement can further comprise two extra bit string choice structures, these two extra bit string choosings Select structure, on multiple opposite sides of the plurality of bit string choice structure, there is multiple terminal position so that each these two extra Bit string choice structure is to arrange only along an active position bar in the bar of the plurality of active position.Such as, two extra Bit string choice structure (SSL1 and SSL7) in the plurality of bit string choice structure one on the left of and one on the right side of be respectively provided with multiple Terminal position so that this extra bit string choice structure SSL1 is to arrange only along an active position bar BL1, and this volume Outer bit string choice structure SSL7 is to arrange only along an active position bar BL6.

The array efficiency of this 3D NAND memory device depicted in Fig. 6 is deposited compared with this 3D NAND depicted in Fig. 4 The array efficiency of reservoir device is slightly lower, results from the plurality of bit string choosing in this storage arrangement depicted in Fig. 6 Selecting structure is the diverse location setting along the plurality of active position bar, rather than such as the same position in Fig. 4.Such as, it is used for The array efficiency of this 3D NAND memory device depicted in Fig. 6 is 79.8%, itself and this 3D depicted in Fig. 4 The array efficiency of NAND memory device 83.7% is in a ratio of relatively low.But far beyond this 3D NAND memory device depicted in Fig. 1 Array efficiency 65.4% be in a ratio of higher.

This 3D NAND memory device comprises multiple planes of multiple memory element.Multiple bit lines are via multiple connection pad (examples As, 610) in the plurality of plane of multiple memory cell, select a specific plane.This specific plane is selected by multiple bit strings Structure, a horizontal grounding select line GSL and multiple wordline and decoded.Multiple voltages can be applied to the plurality of bit string and select Structure is to select or not select the specific active position bar in the bar of the plurality of active position.

In order to select specific active position bar (such as, BL2) in the bar of the plurality of active position, apply one Connect voltage (such as, V_ssL) to the one first bit string choice structure (such as, SSL3) in this first subclass, this first bit string Choice structure (such as, SSL3) is configured on one first side 624 the side grid as this specific active position bar, and Apply this connection voltage to select to the one second bit string choice structure (such as, SSL2) in this second subclass, this second bit string Structure (such as, SSL2) is configured on one second side 623 the side grid as this specific active position bar, and this is second years old Side 623 is relative to this first side 624.

In order to not select be adjacent to this selected specific active position bar one first adjacent to active position bar and One second adjacent to active position bar, and wherein this first is coupled to this second subset adjacent to active position bar (such as, BL1) This second bit string choice structure (such as, SSL2) in conjunction, and this second is coupling adjacent to active position bar (such as, BL3) This first bit string choice structure (such as, SSL3) being bonded in this first subclass, applies a shutoff and is biased into this first subset One the 3rd bit string choice structure (such as, SSL1) in conjunction, the 3rd bit string choice structure (such as, SSL1) is configured to conduct This first adjacent to the side grid of active position bar (such as, BL1) according to being used for, and apply this shutoff be biased into this second One the 4th bit string choice structure (such as, SSL4) in subclass, the 4th bit string choice structure (such as, SSL4) is configured to As this second adjacent to the side grid of active position bar (such as, BL3).This shutoff bias comprises a ground voltage, non- Negative voltage with apply the quick condition (high impedance status or off-state) to the 3rd and the 4th bit string choice structure One of them.Although a non-negative turns off bias and also can work together with this technology, but this technology allows and does not uses negative voltage real Execute the plurality of SSL structure to be possibly realized, as used-7V not select the multiple active band of the neighbouring one active band selected, such as Fig. 4 Described in this second array configuration of 3D NAND memory device required.

Therefore, with Fig. 4 described in 3D NAND memory device this second array configuration compare, in order to not select Be adjacent to a selected active position bar (such as, BL2) multiple neighbouring active position bar (such as, BL1 and BL3), it is not necessary at neighbouring bit string choice structure (such as, SSL1 and SSL4) the upper applying one negative shutoff voltage of multiple correspondences, should The adjacent strings choice structure (such as, SSL1 and SSL4) of multiple correspondences is coupled at the plurality of neighbouring active position bar Multiple sides grid at multiple opposite sides (such as, the 621 and 626) place of (such as, BL1 and BL3).In order to not select multiple active position Bar, applies the voltage of one about 0 volt to the plurality of bit string choice structure (such as, SSL1, SSL4-7), the plurality of bit string Choice structure (such as, SSL1, SSL4-7) coupled to the plurality of active position bar (such as, BL1 and BL3-being not selected 6) (such as, whether the plurality of active position bar, no matter being not selected be adjacent to a selected active position bar BL2)。

The plurality of active position bar (such as, BL1-BL6) and this connection pad (such as, 610) are provided in a multiple structure One layer in, this multiple structure comprises multiple layer, and the plurality of layer comprises other multiple active position bars and connection pad, and wherein Multiple bit string choice structures (such as, SSL1-SSL7) in the plurality of bit string choice structure via the plurality of layer in this correspondence Extend between the bar of multiple active positions, and the plurality of bit string choice structure (such as, SSL1-SSL7) configures using as the plurality of Multiple sides grid of the multiple active position bar in Ceng.

Fig. 7 A is a form, and this form illustrates the voltage on the string choice structure of the multiple alternating expressions configuration shown in Fig. 6, To select a specific active position bar.In the example depicted in Fig. 7 A, at a selected active position bar (such as, BL2) the connection voltage (V on multiple opposite sides (such as, 623 and 624)_ssL) value be 3.3V.In order to not select having of other Position, source bar (such as, BL1 and BL3-6), no matter whether to be adjacent to this selected active for these other active position bar Position bar (such as, BL2), applies a shutoff and is biased into multiple bit string choice structure (such as, SSL1 and SSL4-of this correspondence 7).This shutoff bias comprises one of them of a ground voltage, a non-negative voltage and a quick condition.Although negative a shutoff biases Also can work together with this technology, but this this technology allows and do not uses negative voltage to be possibly realized to implement the plurality of SSL structure, as -7V is used not select the multiple active band of the neighbouring one active band selected, the 3D NAND memory device as described in Fig. 4 The configuration of this second array required.

Fig. 7 B illustrates multiple I-E characteristics of the bit string choice structure of the multiple alternating expressions configuration shown in Fig. 6.As Shown in Fig. 7 B, there is the shutoff voltage (V being in about 0V or-2V_inhibit), selected for one in an on-state This drain current of the bit string choice structure of alternating expression configuration can arrive 1e-5 ampere and have the gate critical electricity of about 1V Pressure Vt, and be adjacent to the bit string choice structure of this selected alternating expression configuration and configure for multiple non-selected alternating expressions String choice structure this drain current can be less than 1e-11 ampere in an off state.Therefore, for this on-state and The plurality of drain current mat of this off state has 10⁶On/off characteristics difference and distinguished, so provide compared to figure The on/off characteristics that the on/off characteristics of this second array comprising multiple bit string choice structure configuration depicted in 5B is preferred.

Fig. 8 illustrates a 3D nand memory dress of the bit string choice structure comprising the configuration of multiple alternating expression as shown in Figure 6 The simulation result of the doping content of this array configuration put.As shown in Figure 8, in the plurality of bit string choice structure described herein Multiple neighbouring bit string choice structure (such as, 810,820 and 830) be along the plurality of active position bar (such as, 815 With 825) diverse location and arrange, the plurality of active position bar (such as, 815 and 825) is coupled to one and shares earth lead (such as, 860).

Showing as depicted in figure 8, multiple active positions bar (such as, 815 and 825) has each cubic centimeter volume about The N-shaped doping content of 5.1E+16.The bit string choice structure (such as, 810,820 and 830) of multiple alternating expressions configuration, multiple wordline WL and multiple ground connection select line GSL to be coupled to the plurality of active position bar, and have each cubic centimeter volume about The p-type doping content of 5.0E+18.

Fig. 9 illustrates a 3D nand memory dress of the bit string choice structure comprising the configuration of multiple alternating expression as shown in Figure 6 The analog result of electron density (e-density) profile of this array configuration put.As it is shown in figure 9, it is described herein at this Multiple neighbouring bit string choice structure (such as, 910,920 and 930) in multiple bit string choice structures is along the plurality of active Position bar (such as, 915 and 925) and in diverse location arrange, the plurality of active position bar (such as, 915 and 925) is It is connected to one and shares earth lead (such as, 960).This active position bar 915 is to apply a connection voltage (V_ssL) 3.3V is at this Being chosen on multiple bit string choice structures 910 and 920, the plurality of bit string choice structure 910 and 920 is along this active position bar Shape thing 915 and be arranged on diverse location.Active position bar 925 is that the shutoff voltage applying a 0V is at this bit string choice structure On 930 not selected, this bit string choice structure 930 is to arrange along the side of this active position bar 925.

As it is shown in figure 9, the active position bar in this selected active position bar (such as, 915) has each The electron density of cubic centimeter volume about 1.0E+18, but in this non-selected active position bar (such as, 925) The part of this active position bar along this bit string choice structure 930, there is each cubic centimeter volume about 1.0E+11 Electron density.At the two ends of this part (such as, 926 and 927), electron density can be each cubic centimeter volume about 1.0E+18.Therefore, the electron density in this selected active position bar is higher than along this position with about 1.0E+7 times The string choice structure 930 electron density in this part of this non-selected active position bar (such as, 925).

Figure 10 is the 3D comprising the bit string choice structure with the configuration of multiple alternating expression of the embodiment according to this technology The schematic diagram of the semiconductor device of NAND storage array.This semiconductor device 1075 is included in the string with the configuration of multiple alternating expression A 3D NAND memory array 1060 (implementing as described herein) on the semiconductor substrate of choice structure, the plurality of The string choice structure of alternating expression configuration be the multiple active position bar of the many NAND bit string along multiple memory cell and in difference Position centers.One column decoder 1061 is coupled to multiple wordline 1062, and along in this memory array more than 1060 Individual row (rows) and configure.One line decoder 1063 is coupled to multiple SSL line 1064, and the plurality of SSL line 1064 comprises multiple Alternating expression configuration bit string choice structure, this line decoder 1063 along correspondence to this memory array 1060 in multiple active positions Multiple row (columns) of bar and be configured, read and programming number with the plurality of memory element from this array 1060 According to.One plane decoder 1058 coupled to the multiple planes in this memory array 1060 via multiple bit lines 1059.Total at this Multiple address be supplied to line decoder 1063, column decoder 1061 and plane decoder 1058 on line 1065.In block 1066 Multiple sensing amplifiers and multiple data input structure be to coupled to this row translate via data/address bus 1067 in this example Code device 1063.Data input/output end port from integrated circuit 1075 or from integrated circuit 1075 interiorly or exteriorly other The plurality of data input structure that data source is supplied in block 1066 via this Data In-Line 1071.In the reality illustrated Executing in example, other circuit 1074 is comprised in this integrated circuit (such as one general processor or proprietary application circuit, or offer One combination of system functional multiple modules on a chip, this is functional is supported by this nand flash memory cell array) On.Data be via DOL Data Output Line 1072 from the plurality of sensing amplifier supply block 1066 to integrated circuit 1075 On multiple input/output end ports, or supply is to interiorly or exteriorly other data destinatioies of this integrated circuit 1075.

The controller implemented in this example uses bias arrangement state machine 1069 to control bias arrangement supply Voltage (as read, wipe, program, wipe checking with programming verifying voltage) applying, this bias arrangement supply voltage via Voltage supply or multiple voltage supply in block 1068 and be generated or provide.

In order to select a specific active position bar in the bar of the plurality of active position, this controller can apply one and connect Energising is pressed onto two bit string choice structures, and these two bit string choice structures all configure using many as this specific active position bar Individual side grid.

In order to not select one second specific active position bar in the bar of active position, the plurality of position, this controller can Applying a shutoff voltage at least one bit string choice structure, this at least one bit string choice structure is configured to as this second specific The side grid of active position bar.This shutoff bias comprises a ground voltage, a non-negative voltage and a quick condition wherein One of.

As known in the art, this controller can use dedicated logic circuit to be carried out.In alternate embodiments, This controller comprises a general processor, and this general processor can be carried out on identical integrated circuit, this identical collection Circuit is become to perform a computer program to control multiple operations of this device.In other embodiments also having, special logic electricity The combination of road and general processor can be used in the enforcement of this controller.

Although this technology discloses by with reference to preferred embodiments described above and example, it should be understood that these examples Subsystem is only used for illustrating and being not used to restriction scope.It is contemplated that this area prior art person can revise and group easily Closing, those revise with combination the most within the spirit of the invention, without departing from the scope of appended claims of the present invention.

Claims

1. a semiconductor device, including:

Multiple active positions bar, one end of the multiple active position bar in the bar of the most the plurality of active position and a connection pad It is coupled, and the other end and a wire are connected；

Multiple wordline；

Multiple memory element, are positioned at the intersection between the plurality of active position bar and the plurality of wordline；And

Multiple bit string choice structures, it is as the side grid of the active position bar in the bar of the plurality of active position, the plurality of It is staggered that bit string choice structure is configured to one；

Wherein, the plurality of bit string choice structure is arranged between this connection pad and the plurality of memory element, and the plurality of bit string selects Structure comprises one first subclass and one second subclass, and this first subclass is arranged at away from this connection pad one first distance range In, this second subclass is arranged in the range of this connection pad one second distance, this first distance range and this second distance scope Different；Multiple active position bar in the bar of the plurality of active position is coupled to this first subclass on one first side and is somebody's turn to do A bit string choice structure in second subclass one, and relative to being coupled to this first son on one second side of this first side A bit string choice structure in set and this second subclass its another.

Device the most according to claim 1, the most the plurality of bit string choice structure is configured to as the plurality of active position Multiple sides grid of multiple passages in bar, thereby forms multiple bit string and selects switch.

Device the most according to claim 1, comprises and is filled in the plurality of active position strip in the bar of the plurality of active position An insulant between thing, this insulant is configured such that this insulant is at quilt in this first distance range of this connection pad Arranging, this connection pad is adjacent to this second side of the plurality of active position bar, the plurality of active position bar be coupled to this The plurality of bit string choice structure of side is relative, and this insulant is being set in the range of this connection pad one second distance, should Connection pad is adjacent to this first side of the plurality of active position bar, the plurality of active position bar be coupled to this second side should Multiple bit string choice structures are relative.

Device the most according to claim 1, the multiple bit string choice structures in the most the plurality of bit string choice structure are at this Having enough length between the bar of multiple active positions makes at least some of the plurality of bit string choice structure be configured to make For the plurality of side grid of two neighbouring active position bars in the bar of the plurality of active position.

Device the most according to claim 1, wherein this first distance range does not has overlapping with this second distance scope.

Device the most according to claim 1, wherein this first distance range and this second distance scope have part weight Folded.

Device the most according to claim 1, the most the plurality of bit string choice structure selects in the bar of the plurality of active position Select one and select active position bar.

Device the most according to claim 7, wherein in multiple bit lines select bit line, this select active position bar With the selected memory cell in a plurality of memory element of combination selection identification of the selected word line in the plurality of wordline.

Device the most according to claim 1, in the most the plurality of bit string choice structure selectes bit string choice structure control Make first active bar and the electric conductivity of second active bar in the bar of the plurality of active position.

Device the most according to claim 1, further includes the control circuit being coupled to the plurality of bit string choice structure, and is Select in the bar of the plurality of active position one to select active position bar, this control circuit apply a connection voltage to this One first bit string choice structure in one subclass, this first bit string choice structure configures to select active position bar as this Side grid, and this control circuit applies this connection voltage to one second bit string choice structure in this second subclass, should Second bit string choice structure configures using the side grid selecting active position bar as this.

11. devices according to claim 10, in order to not select to be adjacent to this one first neighbour selecting active position bar Nearly active position bar and one second adjacent to active position bar, wherein this first adjacent to active position bar be coupled to this second This second bit string choice structure in subclass, and this second adjacent to active position bar be coupled in this first subclass should First bit string choice structure, this control circuit applies one the 3rd bit string selection knot that a shutoff is biased in this first subclass Structure, the 3rd bit string choice structure configuration using as this first adjacent to the side grid of active position bar, and this control circuit Apply one the 4th bit string choice structure that this shutoff is biased in this second subclass, the 4th bit string choice structure configuration with As this second adjacent to the side grid of active position bar.

12. devices according to claim 11, wherein this shutoff bias comprises a ground voltage, a non-negative voltage and executes It is added to one of them of a quick condition of the 3rd and the 4th bit string choice structure.

13. devices according to claim 1, the most the plurality of active position bar and this connection pad are provided in a multilamellar knot In a layer of structure, this multiple structure comprises multiple layer, and the plurality of layer includes an other multiple active position bar and connection pad, and its In multiple bit string choice structures in the plurality of bit string choice structure via the plurality of layer at corresponding multiple active position bar It is extended between shape thing, and is configured to as multiple sides grid of multiple active positions bar in the plurality of layer.

14. 1 kinds of semiconductor devices, including:

Multiple wordline；

Multiple memory element, are positioned at the intersection between the plurality of active position bar and the plurality of wordline；

Multiple bit string choice structures, it is as the side grid of the active position bar in the bar of the plurality of active position, the plurality of It is staggered that bit string choice structure is configured to one；And

Control circuit, it is coupled to the plurality of bit string choice structure, and this control circuit is configured to by applying a connection voltage Selecting active position bar to two bit string choice structures, these two bit string choice structures are configured to as this choosing Multiple sides grid of fixed active position bar.

15. devices according to claim 14, wherein this control circuit be configured to by apply a shutoff be biased into A few bit string choice structure turns off one second in the bar of the plurality of active position and selectes active position bar, this at least String choice structure is configured to as this second side grid selecting active position bar.

16. devices according to claim 15, wherein this shutoff bias comprises a ground voltage, a non-negative voltage and executes It is added to one of them of a quick condition of this at least one bit string choice structure.

17. 1 kinds of methods operating semiconductor device, this semiconductor device comprise multiple active positions bar, multiple wordline, And multiple memory element of the intersection between the plurality of active position bar and the plurality of wordline, the method includes:

Apply multiple voltage to configure to multiple bit string choice structures, the plurality of bit string choice structure using as the plurality of active position bar The side grid of the active position bar in shape thing, it is staggered that the plurality of bit string choice structure is configured to one；

Applying connection voltage to a two bit string choice structure to select one to select active position bar, these two bit strings select Structure configuration is so that in the bar of the plurality of active position, this selectes multiple sides grid of active position bar.

18. methods according to claim 17, further include:

Applying a connection voltage to one first bit string choice structure, this first bit string choice structure is configured to have as the plurality of In the bar of position, source, one selectes one first side grid of active position bar；And

Applying a shutoff and be biased into one second bit string choice structure, this second bit string choice structure is configured to selected to have as this One second side grid of position, source bar,

Not select this to select active position bar, this is selected active position bar and is adjacent to be coupled to this first side grid One selected active position bar, and this selectes active position bar and is adjacent to be coupled to the most selected of this second side grid The active position bar selected.

19. methods according to claim 17, further include:

Applying a shutoff and be biased at least one bit string choice structure, this at least one bit string choice structure is configured to as the plurality of In the bar of active position, one selectes one first side grid of active position bar, in order to do not select this to select active position bar, This is selected active position bar and is only adjacent in the bar of the plurality of active position remaining non-selected active position bar.

20. 1 kinds of methods operating semiconductor device, this semiconductor device comprise multiple active positions bar, multiple wordline, And multiple memory element of the intersection between the plurality of active position bar and the plurality of wordline, the method includes:

Apply multiple voltage to configure to multiple bit string choice structures, the plurality of bit string choice structure using as the plurality of active position bar The side grid of the active position bar in shape thing, it is staggered that the plurality of bit string choice structure is configured to one, in order to does not selects In the bar of the plurality of active position one selectes active position bar, and the plurality of voltage comprises a connection voltage and one and turns off partially Pressure, this connection voltage is applied in one first bit string knot of the one first side grid configured to select active position bar as this Structure, this shutoff bias is applied to configure one second bit string choosing of the one second side grid to select active position bar as this Select structure.

21. 1 kinds of semiconductor devices, including:

One memory cell array, comprises multiple laminations of multiple memory cell string and multiple bit lines, and this in the plurality of lamination is many Individual bit string is coupled to the plurality of bit line via multiple connection pads, and the plurality of connection pad is arranged on the plurality of bit string in the plurality of lamination One first end；And

Multiple bit string choice structures, its be arranged in the plurality of connection pad and the plurality of lamination this first end of the plurality of bit string it Between, and configure with being staggered；

Two bit string choice structures in the most the plurality of bit string choice structure are to set along each lamination in the plurality of lamination Putting, these two the bit string choice structures on each lamination are interconnected to form one along the plurality of stack excursions.

22. 1 kinds of semiconductor devices, including:

One control circuit, coupled to multiple bit string choice structure, and wherein this control circuit applies multiple non-zeros, on-state voltage Two bit string choice structures to the plurality of bit string choice structure, it is selected that these two bit string choice structures are all adjacent to one Bit string, and apply remaining the bit string choice structure in multiple shutoff voltage extremely the plurality of bit string choice structure to block at other Electric current in bit string.

23. 1 kinds of methods manufacturing semiconductor device, including:

Thering is provided a control circuit, this control circuit coupled to multiple bit string choice structure, and wherein this control circuit applies multiple non- Zero, two bit string choice structures in on-state voltage extremely the plurality of bit string choice structure, these two bit string choice structures are all It is adjacent to a selected bit string, and remaining bit string applied in multiple shutoff voltage extremely the plurality of bit string choice structure selects Structure is to block the electric current in other bit strings.

24. 1 kinds of methods operating semiconductor device, including:

Apply multiple non-zero, on-state voltage to two bit string choice structures in the plurality of bit string choice structure, these two Bit string choice structure is all adjacent to a selected bit string, and applies in multiple shutoff voltage extremely the plurality of bit string choice structure Remaining bit string choice structure to block electric current in other bit strings.