TWI520343B - Double trench power semiconductor device and fabrication method thereof - Google Patents

Description

Double-groove power semiconductor component and method of manufacturing same

The present invention relates to a semiconductor device structure and a method of fabricating the same, and more particularly to a trench power semiconductor device and a method of fabricating the same.

Compared with the conventional planar power semiconductor, the on current flows along the parallel substrate surface, and the trench power semiconductor places the gate in the trench to change the position of the gate channel to make the conduction. The current flows in a direction perpendicular to the substrate. Therefore, the size of the component can be reduced, and the integration of the component can be improved. Common power semiconductors include metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), and the like.

Embodiments of the present invention provide a dual-trench power semiconductor device including a substrate, a first trench in the substrate, a second trench in the substrate, and a first conductive The drift region of the type, a first dielectric layer, a first gate structure, a first doped layer of a second conductivity type, and a source region of a first conductivity type. A drift region is located between and below the first trench and the second trench. A first dielectric layer covers an inner side surface of the first trench, and a first gate structure is located within the first trench. A first doped layer is located in the drift region and in close proximity to the second trench, wherein electrical properties of the second conductivity type are opposite to electrical properties of the first conductivity type. A source region is located in an upper portion of the drift region.

Embodiments of the present invention provide a method of fabricating a method of fabricating a dual-trench power semiconductor device, comprising the steps of: providing a substrate, the substrate having a first a conductive drift region; forming a first trench in the substrate; forming a second trench in the substrate, the drift region being located in the first trench and the second trench Forming a first doped layer of a second conductivity type in the drift region, the first doped layer is adjacent to the second trench, and the electrical conductivity of the second conductivity type is The first conductivity type is electrically opposite; forming a first dielectric layer covering the inner surface of the first trench; forming a first gate structure in the first trench; and forming a first conductivity type The source region is in the upper portion of the drift region.

For a better understanding of the features and technical aspects of the present invention, reference should be made to the accompanying drawings.

110‧‧‧Substrate

120‧‧‧ epitaxial layer

130‧‧‧First trench

132‧‧‧First dielectric layer

134‧‧‧First gate structure

140‧‧‧Second trench

142‧‧‧Second dielectric layer

144‧‧‧Second gate structure

146‧‧‧Virtual gate structure

150‧‧‧First doped layer

160‧‧‧Second doped layer

170‧‧‧ source area

180‧‧‧ source metal layer

190‧‧‧汲metal layer

200‧‧‧hard mask

300‧‧‧ photoresist layer

1 is a cross-sectional view of a dual trench power semiconductor device according to an embodiment of the present invention; and FIG. 2 is a cross-sectional view of a dual trench power semiconductor device according to another embodiment of the present invention; FIG. 3A to FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 4A to FIG. 4E are schematic cross-sectional views showing a double-trench power semiconductor device according to another embodiment of the present invention in a manufacturing process. FIG.

Referring to FIG. 1, FIG. 1 is a cross-sectional view of a dual trench power semiconductor device according to an embodiment of the present invention. The power semiconductor device includes an N-type substrate 110, an N-type epitaxial layer 120, a first trench 130, a second trench 140, a first dielectric layer 132, a first gate structure 134, a dummy gate structure 146, and a P-type The first doped layer 150, the N-type source region 170, the source metal layer 180, and the drain metal layer 190. The substrate 110 and the epitaxial layer 120 formed on the substrate 110 constitute a substrate of the power semiconductor element, wherein the material of the substrate includes, for example, tantalum carbide. The N-type substrate 110 can serve as a drain region of a power semiconductor device, and the N-type epitaxial layer 120 can serve as a drift region of a power semiconductor device. The first trench 130 and the second trench 140 are both located within the substrate of the power semiconductor component. The first dielectric layer 132 covers the inner side surface of the first trench 130 , and the first gate structure 134 is located in the first trench 130 . The dummy gate structure 146 is located within the second trench 140, and the dummy gate structure 146 can include an insulating material that fills the second trench 140. The P-type first doped layer 150 is located in the drift region and in close proximity to the second trench 140. Source region 170 is located in the upper portion of the drift region.

Referring to FIG. 2, FIG. 2 is a cross-sectional view of a dual trench power semiconductor device according to another embodiment of the present invention. The power semiconductor device includes an N-type substrate 110, an N-type epitaxial layer 120, a first trench 130, a second trench 140, a first dielectric layer 132, a first gate structure 134, a second dielectric layer 142, and a first The second gate structure 144, the P-type first doped layer 150, the P-type second doped layer 160, the N-type source region 170, the source metal layer 180, and the gate metal layer 190.

The power semiconductor device of the present embodiment does not have a dummy gate structure, but has a bilateral trench gate structure in which the second dielectric layer 142 covers the inner side surface of the second trench 140, and the second gate structure 144 is located at the second Inside the trench 140. In addition, the power semiconductor device of the present embodiment further includes a P-type first doped layer 150, and further includes a P-type second doped layer, wherein the P-type second doped layer 160 is located in the drift region and adjacent to the first trench. Slot 130.

Referring to FIG. 3A to FIG. 3H, FIG. 3A to FIG. 3H are schematic cross-sectional views showing a double-trench power semiconductor device in a manufacturing process according to an embodiment of the present invention. The N-type power semiconductor device is described as an example in FIGS. 3A to 3H, but the embodiment of the present invention is not limited thereto. Embodiments of the invention are of course also applicable to P-type power semiconductor components.

As shown in FIG. 3A, first, an N-type epitaxial layer 120 is formed on an N-type substrate 110 to form a substrate on which a double trench power semiconductor device is fabricated. In the present embodiment, the material of the substrate includes, for example, tantalum carbide. Next, a second trench 140 is first formed in the epitaxial layer 120. Next, as shown in FIG. 3B, a hard mask 200 may be formed prior to the surface of the substrate to define the position of the subsequently formed P-type first doped layer. Then, the substrate can be obliquely implanted through the hard mask 200 (as indicated by the arrow in FIG. 3B). The P-type dopant is implanted into the substrate through the sidewalls and the bottom of the second trench 140, and the P-type dopant is activated to form the P-type first doped layer 150. As shown in FIG. 3C, the P-type first doping layer 150 is located in the drift region and adjacent to the sidewalls and bottom of the second trench 140. Subsequently, the hard mask 200 is removed. It should be noted that in another embodiment of the present invention, the P-type first doping layer 150 may be adjacent to only one of the sidewalls and the bottom of the second trench 140.

Next, as shown in FIG. 3D, a patterned photoresist layer 300 may be formed prior to the surface of the substrate to define the location of the subsequently formed N-type source region. Then, the substrate can be ion-implanted through the photoresist layer 300 (as indicated by the arrow in FIG. 3D) to inject the N-type dopant into the substrate and pass through the high-temperature activation process to activate the N-type dopant. An N-type source region 170 is formed in an upper portion of the drift region 120, as shown in FIG. 3E. Subsequently, the photoresist layer 300 is removed.

It is to be noted that, in another embodiment of the present invention, the high temperature activation process for forming the P-type first doping layer 150 may be performed after the ion implantation of the N-type doping is completed. The N-type source region 170 high temperature activation process is combined and implemented in the same step.

Next, as shown in FIG. 3F, a first trench 130 is formed in the epitaxial layer 120, wherein the trench depth of the first trench 130 is smaller than the trench depth of the second trench 140, but the embodiment of the present invention Not limited to this. In addition, the first trench 130 and the second trench 140 may be formed in different steps, respectively, or in the same step. In detail, a photomask (not shown) having a pattern of the first trench 130 and the second trench 140 may be disposed on the surface of the substrate, and the same process may be performed by lithography and etching, respectively. The different masks form the first trench 130 and the second trench 140.

Next, as shown in FIG. 3G, along the inner side surface of the first trench 130, a first dielectric layer 132 is formed to cover the inner side surface of the first trench 130. Then, a first gate structure 134 is formed in the first trench 130 as the first gate of the dual trench power semiconductor device of the present embodiment.

Next, as shown in FIG. 3H, an insulating material is filled in the second trench 140 (for example). As an oxide material, to form the dummy gate structure 146 in the second trench 140, a power semiconductor device having a double trench according to an embodiment of the present invention can be completed. It is worth mentioning that in order to electrically isolate the subsequently formed electrode metal layer, an insulating oxide layer may be deposited on the surface of the substrate before the step of forming the electrode metal layer. The step of forming the dummy gate structure 146 in the embodiment of the present invention may be completed in the same deposition process as the step of depositing the insulating oxide layer.

Referring to FIG. 4A to FIG. 4E, FIG. 4A to FIG. 4E are schematic cross-sectional views showing a double-trench power semiconductor device according to another embodiment of the present invention in a manufacturing process. 4A to 4E, an N-type power semiconductor device is taken as an example, but the embodiment of the invention is not limited thereto. Embodiments of the invention are of course also applicable to P-type power semiconductor components.

As shown in FIG. 4A, first, an N-type epitaxial layer 120 is formed on an N-type substrate 110 to form a substrate on which a double trench power semiconductor device is fabricated. In the present embodiment, the material of the substrate includes, for example, tantalum carbide. Then, the first trench 130 and the second trench 140 are simultaneously formed in the epitaxial layer 120, wherein the trench depth of the first trench 130 may be substantially the same as the trench depth of the second trench 140, but in this embodiment Not limited to this.

Next, as shown in FIG. 4B, a hard mask (not shown) may be formed on the surface of the substrate to define the positions of the subsequently formed P-type first doped layer and P-type second doped layer. Then, the substrate can be obliquely implanted through the hard mask to dope P-type doping through the sidewalls and bottom of the first trench 130 to inject into the substrate, and P-type doping through the second The sidewalls and the bottom of the trench 140 are implanted into the substrate and passed through a high temperature activation process to activate the P-type dopant to form a P-type first doped layer 150 and a P-type second doped layer 160. As shown, the P-type first doped layer 150 is located in the drift region and adjacent to the sidewalls and the bottom of the second trench 140, and the P-type second doped layer 160 is located in the drift region and adjacent to the sidewall of the first trench 130. With the bottom. Subsequently, the hard mask is removed. It should be noted that, in another embodiment of the present invention, the P-type first doping layer 150 may be adjacent to only one of the sidewalls and the bottom of the second trench 140, or P-type second. The doped layer 160 may also be adjacent to only one of the sidewalls and the bottom of the first trench 130.

Next, as shown in FIG. 4C, an ion implantation can be applied to the substrate to The N-type dopant is implanted into the substrate and passed through a high temperature activation process to activate the N-type dopant to form an N-type source region 170 in an upper portion of the drift region 120.

Next, as shown in FIG. 4D, along the surface of the epitaxial layer 120, the first dielectric layer 132 is formed to cover the inner surface of the first trench 130, and the second dielectric layer 142 is formed to cover the second trench. The inside surface of 140. Then, as shown in FIG. 4E, a first gate structure 134 is formed in the first trench 130 as the first gate of the dual trench power semiconductor device of the present embodiment, and a second gate structure 144 is formed. In the second trench 140, as the second gate of the dual trench power semiconductor device of the present embodiment, a power semiconductor device having a double trench according to an embodiment of the present invention can be completed.

In summary, in the embodiment of the present invention, the tantalum carbide material having the same conductivity type as the source region is used as a channel for conducting the carrier, thereby reducing the resistance of the on-current, and eliminating the action of conducting the inversion of the channel material. In addition, the embodiment of the present invention defines the depth of the first doped layer by using the trench depth of the second trench, and/or defines the depth of the second doped layer by using the trench depth of the first trench, which may reduce the first, The thickness of the second doped layer can precisely control the thickness of the first and second doped layers to avoid the problem of unstable process or poor yield. In a preferred embodiment of the invention, the thickness of the first and second doped layers 150, 160 is, for example, approximately 0.1 to 0.3 microns.

Furthermore, in the embodiment of the present invention, the depletion region formed between the gate conductive material, the dielectric layer material and the tantalum carbide material can make the double trench power semiconductor component turn off a part when no voltage is applied. Carrier channel. On the other hand, by using another depletion region formed by the PN junction between the second conductivity type doping layer and the drift region of the first conductivity type, the double trench type power semiconductor device can be made without voltage applied. , can close another part of the carrier channel. By properly designing the spacing between the first trench and the second trench, the dual-trench power semiconductor device of the embodiment of the present invention can also exhibit a non-conducting and electrical off state when no voltage is applied. In turn, the phenomenon of component leakage is avoided.

In the embodiment shown in FIG. 1, in the state in which the double-trench power semiconductor component is applied, the carrier can pass through the path as indicated by the arrow in FIG. The side close to the gate flows from the source region to the drain region, so that the double-trench power semiconductor device is electrically turned on. In the embodiment shown in FIG. 2, in the state in which the double-trench power semiconductor component is applied, the carrier can be in the middle of the channel away from the bilateral gate via a path as indicated by the arrow in FIG. The self-source region flows to the drain region, so that the double-trench power semiconductor device is electrically turned on.

It is worth mentioning that the dual-trench power semiconductor device of the embodiment of the present invention can form a symmetric or asymmetric structure, and the trench depth, the first trench and the first trench of the first trench and the second trench The width of the channel between the two trenches can be set according to the actual process requirements, so this embodiment is not limited. In a preferred embodiment of the invention, the trench depth of the first trench is not less than the trench depth of the second trench.

The above is only an embodiment of the present invention, and is not intended to limit the scope of the invention. It is still within the scope of patent protection of the present invention to make any substitutions and modifications of the modifications made by those skilled in the art without departing from the spirit and scope of the invention.

110‧‧‧Substrate

120‧‧‧ epitaxial layer

130‧‧‧First trench

132‧‧‧First dielectric layer

134‧‧‧First gate structure

140‧‧‧Second trench

146‧‧‧Virtual gate structure

150‧‧‧First doped layer

170‧‧‧ source area

180‧‧‧ source metal layer

190‧‧‧汲metal layer

Claims (16)

A dual trench power semiconductor device comprising: a substrate; a first trench located in the substrate; a second trench located in the substrate; a drift region of the first conductivity type Between the first trench and the second trench, and the drift region is located under the first trench and the second trench; a first dielectric layer covering the first An inner side surface of a trench; a first gate structure located in the first trench; a first doped layer of a second conductivity type located in the drift region and adjacent to the second trench The electrical conductivity of the second conductivity type is opposite to the electrical conductivity of the first conductivity type; and a source region of a first conductivity type is located at an upper portion of the drift region. The double-trench power semiconductor device of claim 1, wherein the material of the substrate comprises tantalum carbide, the first doped layer is adjacent to the sidewall and the bottom of the second trench or both One of them. The dual-trench power semiconductor device of claim 1, further comprising: a dummy gate structure located in the second trench, wherein the dummy gate structure includes a fill in the first The insulating material in the two trenches. The dual-trench power semiconductor device of claim 1, further comprising: a second doped layer of a second conductivity type, located in the drift region and adjacent to a sidewall of the first trench and Bottom either or both. The dual-trench power semiconductor device of claim 4, further comprising: a second dielectric layer covering an inner side surface of the second trench; and a second gate structure located in the second trench. The dual trench power semiconductor device of claim 1, wherein the first trench has a trench depth less than or equal to a trench depth of the second trench. A method for manufacturing a dual-trench power semiconductor device, comprising: providing a substrate having a drift region of a first conductivity type; forming a first trench and a second trench in the drift region Forming a first doped layer of a second conductivity type in the drift region, the first doped layer is adjacent to the second trench, and the electrical conductivity of the second conductivity type is An electrically conductive type is opposite in polarity; a first dielectric layer is formed to cover an inner side surface of the first trench; a first gate structure is formed in the first trench; and a first conductivity type is formed The source region is in the upper portion of the drift region. The method of manufacturing the double-trench power semiconductor device of claim 7, wherein the material of the substrate comprises tantalum carbide; and the step of forming the first doped layer therein further comprises: performing a The implant is obliquely implanted to inject at least one doping through one or both of the sidewalls and the bottom of the second trench. The method of fabricating the dual trench power semiconductor device of claim 7, further comprising: forming a dummy gate structure in the second trench. The method of manufacturing the dual trench power semiconductor device of claim 9, wherein the step of forming the dummy gate structure further comprises: filling an insulating material into the second trench. The method of fabricating the dual trench power semiconductor device of claim 9, wherein the trench depth of the first trench is less than or equal to the trench depth of the second trench. The method for fabricating the dual-trench power semiconductor device of claim 7, further comprising: forming a second doping layer of a second conductivity type in the drift region, the second doping layer Adjacent to the first groove. The method of manufacturing the dual-trench power semiconductor device of claim 12, wherein the step of forming the second doped layer further comprises: performing an oblique implant to do at least one doping The substrate is implanted through one or both of the sidewalls and the bottom of the first trench. The method of fabricating a dual trench power semiconductor device according to claim 12, wherein the step of forming the second doped layer is performed simultaneously with the step of forming the first doped layer. The method of fabricating the dual trench power semiconductor device of claim 12, further comprising: forming a second dielectric layer to cover an inner side surface of the second trench; and forming a second gate Structured in the second trench. The method of manufacturing the dual trench power semiconductor device of claim 15, wherein the step of forming the second dielectric layer is performed simultaneously with the step of forming the first dielectric layer, and forming the The steps of the two gate structure are performed simultaneously with the step of forming the first gate structure.