TWI518867B - Protection component and electrostatic discharge protection device with the same - Google Patents

Description

Protective element and electrostatic discharge protection device having the same

The present invention relates to a protective element and an electrostatic discharge protection device having the same, and more particularly to an electrostatic discharge protection element provided with an N-type transistor and an electrostatic discharge protection device having the same.

In order to avoid damage caused by electrostatic discharge (ESD), existing integrated circuits tend to incorporate the design of electrostatic discharge protection devices. In addition, silicon controlled rectifier (SCR) is a common protection component and is widely used in various types of ESD protection devices.

The dual direction SCR is a bidirectionally triggered step-controlled rectifier. Therefore, for some specific integrated circuits, since they must be processed for the positive input signal and the negative input signal, the use of a bidirectional controlled rectifier as the basic component of the electrostatic discharge device design will help to meet the requirements. System requirements.

However, like most of the 矽-controlled rectifiers, the bidirectional 矽-controlled rectifiers are often not fast enough to operate, which in turn affects the protection of the ESD protection device. Therefore, various manufacturers are all committed to improving the above problems in order to improve the protection capability of the electrostatic discharge protection device.

The invention provides a protection component which can be based on the voltage level of the control terminal The bit controls the conduction state of the internal N-type transistor, which in turn contributes to the improvement of the conduction speed.

The invention provides an electrostatic discharge protection device, which can control the conduction state of the N-type transistor in the protection component through the component controller, thereby helping to improve the protection capability of the electrostatic discharge protection device.

The present invention provides a protective element comprising a P-type substrate, a first N-type transistor and a second N-type transistor. The P-type substrate comprises an N-type deep well region, a first P-type well region and a second P-type well region, and the first and second P-type well regions are disposed in the N-type deep well region. The first N-type transistor is formed in the N-type deep well region and the first P-type well region. The second N-type transistor is formed in the N-type deep well region and the second P-type well region.

In an embodiment of the invention, the protection element has a first connection end, a second connection end, and first to third control ends. The first 汲/source of the first and second N-type transistors are electrically connected to the first control end, and the second 源/source of the first and second N-type transistors are electrically connected to the first and the second The two terminals are connected to each other, and the gates of the first and second N-type transistors are electrically connected to the second and third control terminals, respectively.

The invention provides an electrostatic discharge protection device electrically connecting a first pad and a second pad, and comprises the above-mentioned protection component and component controller. The protection component is electrically connected to the first and second pads through the first and second connection ends, respectively. The component controller is electrically connected to the first to third control terminals. In addition, when an electrostatic pulse is present on the first pad or the second pad, the component controller turns on one of the first and second N-type transistors to discharge the electrostatic pulse through the current path in the protection element. When the first and second operation signals are supplied to the first and second pads, the component controller is based on The first and second operational signals turn off the first and second N-type transistors such that the protection element is unable to form a current path.

In an embodiment of the invention, when an electrostatic pulse is present on the first pad, the component controller directs an electrostatic pulse to the first control terminal, and the component controller turns on the second N-type transistor and turns off The first N-type transistor.

In an embodiment of the invention, the component controller further directs the electrostatic pulse to the third control terminal, and pulls the voltage level of the second control terminal to the ground voltage.

In an embodiment of the invention, the component controller described above includes a first selection circuit and a first control circuit. The first selection circuit is electrically connected to the first pad, the second pad and the first control end. In addition, the first selection circuit selects a high level signal from the signals from the first and second pads, and outputs a high level signal to the first control end. The first control circuit is electrically connected to the first pad, the second pad, the second control end and the third control end. In addition, the first control circuit adjusts the voltage levels of the second control terminal and the third control terminal according to the frequency of the signals from the first and second pads.

In an embodiment of the invention, the component controller further directs the electrostatic pulse to the second control terminal and the third control terminal.

Based on the above, the protection component of the present invention can control the conduction state of its internal N-type transistor according to the voltage level of the control terminal, thereby helping to increase its own conduction speed. In addition, the electrostatic discharge protection device of the present invention can control the conduction state of the N-type transistor in the protection element through the component controller, thereby accelerating the conduction speed of the protection component or suppressing the protection. The formation of the current path of the component. As a result, it will help to improve the protection of the ESD protection device.

The above described features and advantages of the present invention will be more apparent from the following description.

In order to make the content of the present invention easier to understand, the following specific embodiments are illustrative of the embodiments of the present invention. In addition, wherever possible, the same reference numerals in the drawings

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of an electrostatic discharge protection device in accordance with one embodiment of the present invention. Referring to FIG. 1, the electrostatic discharge protection device is adapted to be electrically connected to the first pad 101 and the second pad 102, and the electrostatic discharge protection device includes the protection element 110 and the component controller 120.

In view of the protective element 110, the protective element 110 includes a P-type substrate 130, an N-type deep well region 140, P-type well regions 151 and 152, and N-type transistors MN1 and MN2. The N-type deep well area 140 is disposed in the P-type base 130, and the P-type well areas 151 and 152 are disposed in the N-type deep well area 140. Further, an N-type transistor MN1 is formed in the N-type deep well region 140 and the P-type well region 151, and the N-type transistor MN2 is formed in the N-type deep well region 140 and the P-type well region 152.

Further, the N-type transistor MN1 includes a gate structure 161 and N-type doping regions 171 and 172. The gate structure 161 is disposed on the P-type well region 151 and is used to form the gate of the N-type transistor MN1. In a preferred embodiment, the gate structure 161 can be, for example, a gate The electrical layer is formed by a gate conductive layer. In addition, the gate structure 161 is adjacent to a sidewall of the P-type well region 151, and the N-type doping regions 171 and 172 are respectively located on both sides of the gate structure 161. Therefore, in configuration, the N-type doping region 171 is disposed in the N-type deep well region 140 and adjacent to the P-type well region 151. The N-type doped region 172 is disposed in the P-type well region 151. Thereby, the first 源/source and the second 汲/source of the N-type transistor MN1 will be formed by the N-type doping regions 171 and 172, respectively.

Similarly, N-type transistor MN2 includes a gate structure 162 and N-type doped regions 173 and 174. The gate structure 162 is disposed on the P-type well region 152 and is used to form the gate of the N-type transistor MN2. In a preferred embodiment, the gate structure 162 can be formed, for example, by a gate dielectric layer and a gate conductive layer. In addition, the gate structure 162 is adjacent to a sidewall of the P-type well region 152, and the N-type doped regions 173 and 174 are respectively located on opposite sides of the gate structure 162. Therefore, in configuration, the N-type doping region 173 is disposed in the N-type deep well region 140 and adjacent to the P-type well region 152. The N-type doped region 174 is disposed within the P-type well region 152. Thereby, the first 源/source and the second 汲/source of the N-type transistor MN2 will be formed by the N-type doping regions 173 and 174, respectively.

In addition, in a preferred embodiment, the N-type transistor MN1 further includes an N-type shallow doped region 181, and the N-type transistor MN2 further includes an N-type shallow doped region 182. The N-type shallow doped region 181 is disposed in the P-type well region 151 below the gate structure 161 and surrounds the periphery of the N-type doped region 171. Furthermore, the N-type shallow doped region 182 is disposed in the P-type well region 152 below the gate structure 162 and surrounds the periphery of the N-type doped region 173. Thereby, the protection element 110 will be able to be lifted by using the N-type shallow doping regions 181 and 182. Its ability to withstand voltage is applied to high voltage integrated circuits. On the other hand, the protection element 110 further includes P-type doping regions 191 and 192, and the P-type doping regions 191 and 192 are disposed in the P-type well regions 151 and 152, respectively.

With continued reference to FIG. 1, the protective element 110 has a symmetrical structure. Further, in response to this symmetrical structure, the protection element 110 has a first connection terminal TM1, a second connection terminal TM2, and first to third control terminals CT1 to CT3. The first control terminal CT1 is electrically connected to the first 汲/source of the N-type transistors MN1 and MN2. The first connection terminal TM1 is electrically connected to the second 汲/source of the N-type transistor MN1 and the P-type doping region 191. The second connection terminal TM2 is electrically connected to the second 汲/source of the N-type transistor MN2 and the P-type doping region 192. The second control terminal CT2 is electrically connected to the gate of the N-type transistor MN1. The third control terminal CT3 is electrically connected to the gate of the N-type transistor MN2.

Further, the P-type well region 151, the N-type deep well region 140, the P-type well region 152, and the N-type doped region 174 in the protection element 110 will constitute a PNPN structure, and the P-type well region in the protection element 110 152. The N-type deep well region 140, the P-type well region 151, and the N-type doped region 172 will constitute another PNPN structure. In other words, the protection component 110 corresponds to a bidirectionally controlled rectifier, and the first connection terminal TM1 and the second connection terminal TM2 correspond to the two input terminals of the bidirectionally controlled rectifier. In addition, in the operation of the protection component 110, the conduction states of the N-type transistors MN1 and MN2 in the protection component 110 can be controlled through the first to third control terminals CT1~CT3, thereby accelerating the conduction speed of the protection component 110 or The formation of a current path of the protection element 110 is suppressed.

Therefore, in practical applications, the protection component 110 can be, for example, an application. In the electrostatic discharge protection device shown in Figure 1, it is not intended to limit the invention. In order to make those skilled in the art more aware of the FIG. 1 embodiment, the operational mechanisms of the protection element 110 and the component controller 120 will be further described below. Referring to FIG. 1 again, the component controller 120 includes a selection circuit 121 and a control circuit 122. Further, the selection circuit 121 includes P-type transistors MP1 to MP4, and the control circuit 122 includes capacitors C1 and C2 and resistors R1 and R2.

In view of the circuit architecture of the selection circuit 121, the P-type transistors MP1 and MP2 are connected in series between the second pad 102 and the first control terminal CT1. That is, the second 汲/source of the P-type transistor MP1 is electrically connected to the second pad 102, and the second 源/source of the P-type transistor MP2 is electrically connected to the first 汲/source of the P-type transistor MP1. The first 汲/source of the P-type transistor MP2 is electrically connected to the first control terminal CT1. In addition, the gates of the P-type transistors MP1 and MP2 are electrically connected to the first pad 101. On the other hand, the P-type transistors MP3 and MP4 are connected in series between the first pad 101 and the first control terminal CT1. That is, the second 汲/source of the P-type transistor MP3 is electrically connected to the first pad 101, and the second 源/source of the P-type transistor MP4 is electrically connected to the first 汲/source of the P-type transistor MP3. The first 汲/source of the P-type transistor MP4 is electrically connected to the first control terminal CT1. In addition, the gates of the P-type transistors MP3 and MP4 are electrically connected to the second pad 102.

In operation, the P-type transistor will be conductive because the gate of the P-type transistor receives a low-level signal. Therefore, when the level of the signal from the first pad 101 is low, that is, when the two pads 101 and 102 respectively receive the low level signal and the high level signal, the two P-type transistors MP1 are connected in series. And MP2 will be turned on, thereby causing the selection circuit 121 output to come from The high level signal of the second pad 102. In contrast, when the level of the signal from the first pad 101 is higher, that is, when the two pads 101 and 102 respectively receive the high level signal and the low level signal, the two P type transistors are connected in series. MP3 and MP4 will be turned on, thereby causing selection circuit 121 to output a high level signal from first pad 101. In other words, the selection circuit 121 selects a signal having a high level (ie, a high level signal) from the signals from the two pads 101 and 102, and outputs the selected high level signal accordingly.

As for the circuit structure of the control circuit 122, the capacitor C1 and the resistor R1 are connected in series between the first pad 101 and the second pad 102, and the connection point between the capacitor C1 and the resistor R1 is electrically connected to the third control. End CT3. That is, the first end of the capacitor C1 is electrically connected to the first pad 101, and the second end of the capacitor C1 is electrically connected to the third control terminal CT3. The first end of the resistor R1 is electrically connected to the second end of the capacitor C1, and the second end of the resistor R1 is electrically connected to the second pad 102. On the other hand, the capacitor C2 and the resistor R2 are connected in series between the second pad 102 and the first pad 101, and the connection point between the capacitor C2 and the resistor R2 is electrically connected to the second control terminal CT2. That is, the first end of the capacitor C2 is electrically connected to the second pad 102, and the second end of the capacitor C2 is electrically connected to the second control end CT2. The first end of the resistor R2 is electrically connected to the second end of the capacitor C2, and the second end of the resistor R2 is electrically connected to the first pad 101.

In operation, the series connected capacitors and resistors can be used as low pass filters or high pass filters. Therefore, if the voltage level of the second pad 102 approaches the reference potential of the system (eg, the ground voltage), then the signal from the first pad 101 is a high frequency signal (eg, an electrostatic pulse), which is high. The frequency signal can be transmitted to the third control terminal CT3 through a current loop formed by the capacitor C1 and the resistor R1, thereby increasing the voltage level of the third control terminal CT3. In addition, the voltage level of the second control terminal CT2 at this time can be pulled down to the ground voltage through the current loop formed by the resistor R2 and the capacitor C2. In contrast, when the signal from the first pad 101 is a low frequency signal (for example, a positive/negative input signal), the low frequency signal can be transmitted to the second control terminal CT2 through a current loop formed by the resistor R2 and the capacitor C2. And adjusting the voltage level of the second control terminal CT2. In addition, the voltage level of the third control terminal CT3 will also be adjusted to the ground voltage through the current loop formed by the capacitor C1 and the resistor R1. In other words, the control circuit 122 adjusts the voltage levels of the second control terminal CT2 and the third control terminal CT3 according to the frequency of the signals from the two pads 101 and 102.

In practical applications, the electrostatic discharge protection device is mainly used to guide the electrostatic pulse from the solder pad to prevent the electrostatic pulse from damaging the integrated circuit (not shown). In addition, when the integrated circuit is operating normally, the integrated circuit will receive a positive input signal or a negative input signal through the pad, and the ESD protection device will turn off its internal current path to avoid leakage current. In other words, for the electrostatic discharge protection device of the embodiment of FIG. 1, in different cases, it may receive an electrostatic pulse, a positive input signal or a negative input signal from the pad. Therefore, the electrostatic discharge protection device of FIG. 1 will be further described below for the above three cases.

FIG. 2 is a schematic view showing a state of the protection element of FIG. 1 under an electrostatic discharge event. Referring to FIG. 1 and FIG. 2 simultaneously, when the electrostatic pulse VESD appears on the first pad 101, the first pad at this time 101 is equivalent to receiving a high level signal (for example: electrostatic pulse VESD), and the voltage level of the second pad 102 will approach the ground voltage GND. Therefore, when the electrostatic pulse VESD appears on the first pad 101, the selection circuit 121 outputs a high level signal composed of the electrostatic pulse VESD to the first control terminal CT1.

In addition, the electrostatic pulse VESD is a high frequency signal, so the control circuit 122 outputs the electrostatic pulse VESD to the third control terminal CT3, and pulls the voltage level of the second control terminal CT2 to the ground voltage GND. In addition, the first connection terminal TM1 and the second connection terminal TM2 of the protection component 110 respectively receive the electrostatic pulse VESD and the ground voltage GND. Accordingly, as shown in FIG. 2, the N-type transistor MN1 in the protection element 110 will be turned off, and the N-type transistor MN2 will be turned on. Here, as the N-type transistor MN2 is turned on, the P-type well region 152 and the N-type doped region 174 are urged to be biased under forward bias. As a result, the PNPN structure formed by the P-type well region 151, the N-type deep well region 140, the P-type well region 152, and the N-type doped region 174 can be quickly turned on to form a current path. In other words, when an electrostatic discharge event occurs, component controller 120 will turn on an N-type transistor in protection element 110 such that protection element 110 can be turned on quickly and thereby form a current path to discharge the electrostatic pulse.

FIG. 3 is a schematic view showing a state in which the protection element of FIG. 1 is in normal operation of the integrated circuit. Referring to FIG. 1 and FIG. 2 simultaneously, when the integrated circuit is in normal operation, the two operation signals transmitted to the pads 101 and 102 can be, for example, a positive input signal VH (for example, 10 volts) and a reference potential of the system (for example: Ground voltage GND). At this time, the first pad 101 is equivalent to receiving a high level signal (for example, a positive input signal VH), and the first The second pad 102 is equivalent to receiving a low level signal (for example, ground voltage GND). Therefore, the selection circuit 121 outputs the high level signal formed by the positive input signal VH to the first control terminal CT1.

On the other hand, since the positive input signal VH is a low frequency signal, the control circuit 122 transmits the positive input signal VH to the second control terminal CT2, and adjusts the voltage level of the third control terminal CT3 to the ground voltage GND. In addition, the first connection terminal TM1 and the second connection terminal TM2 of the protection component 110 respectively receive the positive input signal VH and the ground voltage GND. Accordingly, as shown in FIG. 3, both of the N-type transistors MN1 and MN2 in the protection element 110 will be in a non-conducting state, thereby causing the protection element 110 to fail to form a current path.

In other words, when the integrated circuit is operating normally, that is, when the two operation signals are respectively supplied to the two pads 101 and 102, the component controller 120 can turn off the two N-type transistors in the protection element 110 according to the two operation signals. MN1 and MN2, so that the protection element 110 cannot form a current path. In addition, the N-type deep well region 140 at this time will be biased at a high level, thereby causing the parasitic diode formed by the N-type deep well region 140 and the P-type substrate 130 in the protection element 110 to be biased under reverse bias. . As such, it will be further ensured that the protective element 110 is in a non-conducting state.

4 is a schematic view showing another state of the protection element of FIG. 1 in the normal operation of the integrated circuit. Referring to FIG. 1 and FIG. 2 simultaneously, when the integrated circuit is in normal operation, the two operation signals transmitted to the two pads 101 and 102 can be, for example, a negative input signal VL (for example, -10 volts) and a reference potential of the system. (Example: Ground voltage GND). At this time, the first pad 101 is equivalent to receiving a low level signal (for example, a negative input signal VL). The second pad 102 is equivalent to receiving a high level signal (for example, ground voltage GND). Therefore, the selection circuit 121 outputs a high level signal composed of the ground voltage GND to the first control terminal CT1.

On the other hand, since the negative input signal VL is a low frequency signal, the control circuit 122 transmits the negative input signal VL to the second control terminal CT2 and adjusts the voltage level of the third control terminal CT3 to the ground voltage GND. In addition, the first connection terminal TM1 and the second connection terminal TM2 of the protection component 110 respectively receive the negative input signal VL and the ground voltage GND. Accordingly, as shown in FIG. 4, both of the N-type transistors MN1 and MN2 in the protection element 110 will be in a non-conducting state, thereby causing the protection element 110 to fail to form a current path. In other words, when the integrated circuit is operating normally, even if the integrated circuit receives the negative input signal through the pad, the component controller 120 still turns off the two N-type transistors MN1 and MN2 in the protection component 110, so that the protection component 110 cannot A current path is formed. In addition, the parasitic diode formed by the N-type deep well region 140 and the P-type substrate 130 at this time will also be biased under reverse bias, thereby ensuring that the protection element 110 is in a non-conducting state.

Figure 5 is a schematic illustration of an electrostatic discharge protection device in accordance with another embodiment of the present invention. Referring to FIG. 1 and FIG. 5 simultaneously, the main difference between the two embodiments is that the control circuit 122 in the embodiment of FIG. 1 is composed of two capacitors C1 and C2 and two resistors R1 and R2, and the embodiment of FIG. 5 The control circuit 122' is composed of two capacitors C3 and C4 and two N-type transistors MN3 and MN4.

As seen from the control circuit 122' in the embodiment of FIG. 5, the first end of the capacitor C3 is electrically connected to the first pad 101, and the second end of the capacitor C3 is electrically connected. Connected to the third control terminal CT3. The first 源/source of the N-type transistor MN3 is electrically connected to the second end of the capacitor C3, the gate of the N-type transistor MN3 is electrically connected to the selection circuit 121, and the second 汲/source of the N-type transistor MN3 The second pad 102 is electrically connected. The first end of the capacitor C4 is electrically connected to the second pad 102, and the second end of the capacitor C4 is electrically connected to the second control terminal CT2. The first 源/source of the N-type transistor MN4 is electrically connected to the second end of the capacitor C4, the gate of the N-type transistor MN4 is electrically connected to the selection circuit 121, and the second 汲/source of the N-type transistor MN4 The first pad 101 is electrically connected.

In operation, selection circuit 121 transmits a high level signal to the gates of N-type transistors MN3 and MN4 to thereby bias N-type transistors MN3 and MN4 in the linear region. As a result, the N-type transistors MN3 and MN4 will be in an on state and have the characteristics of linear resistance. In other words, under the control of the selection circuit 121, the N-type transistors MN3 and MN4 will be equivalent to the two resistors R1 and R2 in the control circuit 122 of FIG. Accordingly, the control circuit 122' of Figure 5 will have the same or similar operational mechanism as the control circuit 122 of Figure 1.

For example, when an electrostatic pulse appears on the first pad 101, the selection circuit 121 turns on the N-type transistors MN3 and MN4 with a high-level signal composed of electrostatic pulses, so that the N-type transistors MN3 and MN4 are biased. Press in the linear zone. Thereby, the electrostatic pulse from the first pad 101 can be transmitted to the third control terminal CT3 through the current loop formed by the capacitor C3 and the N-type transistor MN3. In addition, the voltage level of the second control terminal CT2 will be pulled down to the ground voltage through the current loop formed by the N-type transistor MN4 and the capacitor C4. As for the connection manner and operation mechanism of the remaining members in the embodiment of FIG. 5, etc., it has been included in the above implementations. In the example, it will not be repeated here.

Figure 6 is a schematic illustration of an electrostatic discharge protection device in accordance with yet another embodiment of the present invention. Referring to FIG. 1 and FIG. 6 simultaneously, the main difference between the two embodiments is that the circuit controller 120' in FIG. 6 and the component controller 120 in FIG. 1 have different circuit architectures, but both. The operating mechanism is the same or similar.

As seen in the component controller 120' of Figure 6, the component controller 120' includes a selection circuit 610, a selection circuit 620, and a control circuit 630. The selection circuit 610 includes P-type transistors MP5 to MP8, and the selection circuit 610 has the same circuit configuration as the selection circuit 121 of FIG. In other words, the selection circuit 610 selects a signal having a high level (ie, a high level signal) from the signals from the two pads 101 and 102, and outputs the selected high level signal accordingly. The detailed description of the selection circuit 610 is included in the above embodiment, and therefore will not be described herein.

Selection circuit 620 includes N-type transistors MN5-MN8. The first NMOS/source of the N-type transistor MN5 is electrically connected to the second pad 102, and the gate of the N-type transistor MN5 is electrically connected to the first pad 101. The first 汲/source of the N-type transistor MN6 is electrically connected to the second 汲/source of the N-type transistor MN5, and the gate of the N-type transistor MN6 is electrically connected to the first pad 101, and the N-type transistor The second 源/source of MN6 is electrically coupled to control circuit 630. The first germanium/source of the N-type transistor MN7 is electrically connected to the first pad 101, and the gate of the N-type transistor MN7 is electrically connected to the second pad 102. The first 汲/source of the N-type transistor MN8 is electrically connected to the second 汲/source of the N-type transistor MN7, and the gate of the N-type transistor MN8 is electrically connected to the second pad 102, and the N-type transistor Second 汲/source electrical connection of MN8 Connected to control circuit 630.

In operation, the N-type transistor will be turned on when the gate of the N-type transistor receives a high-level signal. Therefore, when the level of the signal from the first pad 101 is low, that is, when the two pads 101 and 102 respectively receive the low level signal and the high level signal, the two N-type transistors MN7 are connected in series. The MN8 will be turned on, thereby causing the selection circuit 620 to output a low level signal from the first pad 101. In contrast, when the level of the signal from the first pad 101 is higher, that is, when the two pads 101 and 102 respectively receive the high level signal and the low level signal, the two N-type transistors are connected in series. MN5 and MN6 will be turned on, thereby causing selection circuit 620 to output a low level signal from second pad 102. In other words, the selection circuit 620 selects a signal having a low level (ie, a low level signal) from the signals from the two pads 101 and 102, and outputs the selected low level signal accordingly.

Control circuit 630 includes P-type transistors MP9 and MP10 and N-type transistors MN9-MN12. The second 汲/source of the P-type transistor MP9 is electrically connected to the selection circuit 610, and the first 源/source of the P-type transistor MP9 is electrically connected to the second control terminal CT2 and the third control terminal CT3. The first 汲/source of the N-type transistor MN9 is electrically connected to the first 汲/source of the P-type transistor MP9, and the gate of the N-type transistor MN9 is electrically connected to the selection circuit 610. The first 源/source of the N-type transistor MN10 is electrically connected to the second 汲/source of the N-type transistor MN9, the gate of the N-type transistor MN10 receives the power supply voltage VDD, and the second of the N-type transistor MN10 The 汲/source is electrically connected to the selection circuit 620. The second 汲/source of the P-type transistor MP10 is electrically connected to the selection circuit 610, and the gate of the P-type transistor MP10 is electrically The first 汲/source of the P-type transistor MP9 is connected, and the first 源/source of the P-type transistor MP10 is electrically connected to the gate of the P-type transistor MP9. The first 汲/source of the N-type transistor MN11 is electrically connected to the first 汲/source of the P-type transistor MP10, and the gate of the N-type transistor MN11 is electrically connected to the selection circuit 610. The first 源/source of the N-type transistor MN12 is electrically connected to the second 汲/source of the N-type transistor, and the gate of the N-type transistor MN12 is electrically connected to the gate of the P-type transistor MP10, and the N-type The second 汲/source of the transistor MN12 is electrically coupled to the selection circuit 620.

Similarly, for the electrostatic discharge protection device of the embodiment of FIG. 6, in different cases, it may receive an electrostatic pulse, a positive input signal, or a negative input signal from the pad. Therefore, the electrostatic discharge protection device of FIG. 6 will be further described below for the above three cases.

FIG. 7 is a schematic view showing a state of the protection element of FIG. 6 under an electrostatic discharge event. Referring to FIG. 6 and FIG. 7 simultaneously, when the electrostatic pulse VESD appears on the first pad 101, the first pad 101 at this time is equivalent to receiving a high level signal (for example, an electrostatic pulse VESD), and The voltage level of the second pad 102 will approach the ground voltage GND. Therefore, the selection circuit 610 at this time outputs the high level signal composed of the electrostatic pulse VESD to the first control terminal CT1 and the control circuit 630. In addition, the selection circuit 620 outputs a low level signal that is close to the ground voltage GND to the control circuit 630.

For the control circuit 630, the control circuit 630 at this time will not be able to receive the power supply voltage VDD, thereby causing the N-type transistor MN10 to be in a non-conducting state. In addition, electrostatic pulses from the selection circuit 610 The VESD will turn on the N-type transistors MN9 and MN11. Furthermore, the electrostatic pulse VESD is coupled to the gate of the P-type transistor MP10 through the parasitic capacitance of the P-type transistor MP10, thereby turning off the P-type transistor MP10 and turning on the N-type transistor MN12. Thereby, as the N-type transistors MN11 and MN12 are turned on, the gate of the P-type transistor MP9 can receive the low-level signal, thereby turning on the P-type transistor MP9. In this way, the control circuit 630 outputs the electrostatic pulse VESD to the second control terminal CT2 and the third control terminal CT3 through the P-type transistor MP9 that can be turned on. In other words, when the electrostatic pulse VESD appears on the first pad 101, the control circuit 630 outputs the high level signal formed by the electrostatic pulse VESD to the second control terminal CT2 and the third control terminal CT3.

Accordingly, as shown in FIG. 7, the N-type transistor MN1 in the protection element 110 will be turned off, and the N-type transistor MN2 will be turned on. Here, as the N-type transistor MN2 is turned on, the P-type well region 152 and the N-type doped region 174 are urged to be biased under forward bias. As a result, the PNPN structure formed by the P-type well region 151, the N-type deep well region 140, the P-type well region 152, and the N-type doped region 174 can be quickly turned on to form a current path. In other words, when an electrostatic discharge event occurs, component controller 630 will turn on an N-type transistor in protection element 110 such that protection element 110 can be turned on quickly and thereby form a current path to discharge the electrostatic pulse.

FIG. 8 is a schematic view showing a state in which the protection element of FIG. 6 is in normal operation of the integrated circuit. Referring to FIG. 6 and FIG. 8 simultaneously, when the integrated circuit is in normal operation, the two operation signals transmitted to the pads 101 and 102 can be, for example, a positive input signal VH (for example, 10 volts) and a reference potential of the system (for example: Ground voltage GND), and control circuit 630 at this time The power supply voltage VDD will be received. At this time, the first pad 101 is equivalent to receiving a high level signal (for example, the positive input signal VH), and the second pad 102 is equivalent to receiving a low level signal (for example, the ground voltage GND). Therefore, the selection circuit 610 outputs the high level signal formed by the positive input signal VH to the first control terminal CT1 and the control circuit 630. In addition, the selection circuit 620 outputs a low level signal composed of the ground voltage GND to the control circuit 630.

On the other hand, the control circuit 630 will turn on the N-type transistor MN10 with the power supply voltage VDD. In addition, the positive input signal VH from the selection circuit 610 will turn on the N-type transistors MN9 and MN11. Thereby, as the N-type transistors MN9 and MN10 are turned on, the control circuit 630 can output a low-level signal composed of the ground voltage GND to the second control terminal CT2 and the third control terminal CT3. In addition, as the N-type transistors MN9 and MN10 are turned on, the gate of the P-type transistor MP10 will receive a low-level signal composed of the ground voltage GND, and is in an on state, and accordingly the P-type is turned off. Transistor MP9.

As a result, as shown in FIG. 8, both N-type transistors MN1 and MN2 in the protection element 110 will be in a non-conducting state, thereby causing the protection element 110 to fail to form a current path. In other words, when the integrated circuit is operating normally, that is, when the two operation signals are respectively supplied to the two pads 101 and 102, the component controller 630 can turn off the two N-type transistors in the protection element 110 according to the two operation signals. MN1 and MN2, so that the protection element 110 cannot form a current path. In addition, the parasitic diode formed by the N-type deep well region 140 and the P-type substrate 130 at this time will be biased under reverse bias.

FIG. 9 is a schematic view showing another state of the protection element of FIG. 6 in the normal operation of the integrated circuit. Referring to FIG. 6 and FIG. 9 simultaneously, when the integrated circuit is in normal operation, the two operation signals transmitted to the two pads 101 and 102 can be, for example, a negative input signal VL (for example, -10 volts) and a reference potential of the system. (For example: ground voltage GND), and the control circuit 630 at this time will receive the power supply voltage VDD. At this time, the first pad 101 is equivalent to receiving a low level signal (for example, a negative input signal VL), and the second pad 102 is equivalent to receiving a high level signal (for example, a ground voltage GND). Therefore, the selection circuit 610 outputs the high level signal formed by the ground voltage GND to the first control terminal CT1 and the control circuit 630. In addition, the selection circuit 620 outputs a low level signal composed of the negative input signal VL to the control circuit 630.

On the other hand, the control circuit 630 will turn on the N-type transistor MN10 with the power supply voltage VDD. Further, the ground voltage GND from the selection circuit 610 will turn on the N-type transistors MN9 and MN11. Therefore, as the N-type transistors MN9 and MN10 are turned on, the control circuit 630 can output a low-level signal composed of the negative input signal VL to the second control terminal CT2 and the third control terminal CT3. In addition, as the N-type transistors MN9 and MN10 are turned on, the gate of the P-type transistor MP10 will receive a low-level signal composed of the negative input signal VL, and is in a conducting state, and accordingly, the P is turned off. Type transistor MP9.

As a result, as shown in FIG. 9, both N-type transistors MN1 and MN2 in the protection element 110 will be in a non-conducting state, thereby causing the protection element 110 to fail to form a current path. In other words, when the integrated circuit is operating normally, even if the integrated circuit receives negative input through the pad The component controller 630 will still turn off the two N-type transistors MN1 and MN2 in the protection component 110, so that the protection component 110 cannot form a current path. In addition, the parasitic diode formed by the N-type deep well region 140 and the P-type substrate 130 at this time will also be biased under reverse bias.

In summary, the protection element of the present invention has two N-type transistors in addition to the PNPN structure that can be bidirectionally triggered. Thereby, the conduction state of the N-type transistor in the protection element can be controlled by adjusting the voltage level of the control terminal of the protection element, thereby accelerating the conduction speed of the protection element or suppressing the formation of the current path of the protection element. In addition, since the protection element has a better conduction speed, it will contribute to the protection of the electrostatic discharge protection device.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

101‧‧‧First pad

102‧‧‧Second pad

110‧‧‧Protection components

120, 120'‧‧‧ component controller

130‧‧‧P type substrate

140‧‧‧N type deep well area

151, 152‧‧‧P type well area

MN1~MN12‧‧‧N type transistor

161, ‧ ‧ ‧ gate structure

171~174‧‧‧N-doped area

181, 182‧‧‧N type shallow doped area

191, 192‧‧‧P type doping area

121, 610, 620‧‧‧ select circuit

122, 122', 630‧‧‧ control circuit

MP1~MP10‧‧‧P type transistor

C1~C4‧‧‧ capacitor

R1, R2‧‧‧ resistance

VESD‧‧‧Electrostatic pulse

GND‧‧‧ Grounding voltage

VH‧‧‧ is entering the signal

VL‧‧‧ negative input signal

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of an electrostatic discharge protection device in accordance with one embodiment of the present invention.

FIG. 2 is a schematic view showing a state of the protection element of FIG. 1 under an electrostatic discharge event.

FIG. 3 is a schematic view showing a state in which the protection element of FIG. 1 is in normal operation of the integrated circuit.

Figure 4 is a view for explaining the normal operation of the protection element of Figure 1 in the integrated circuit Another state diagram at the time of the work.

Figure 5 is a schematic illustration of an electrostatic discharge protection device in accordance with another embodiment of the present invention.

Figure 6 is a schematic illustration of an electrostatic discharge protection device in accordance with yet another embodiment of the present invention.

FIG. 7 is a schematic view showing a state of the protection element of FIG. 6 under an electrostatic discharge event.

FIG. 8 is a schematic view showing a state in which the protection element of FIG. 6 is in normal operation of the integrated circuit.

FIG. 9 is a schematic view showing another state of the protection element of FIG. 6 in the normal operation of the integrated circuit.

101‧‧‧First pad

102‧‧‧Second pad

110‧‧‧Protection components

120‧‧‧Component Controller

130‧‧‧P type substrate

140‧‧‧N type deep well area

151, 152‧‧‧P type well area

MN1, MN2‧‧‧N type transistor

161, ‧ ‧ ‧ gate structure

171~174‧‧‧N-doped area

181, 182‧‧‧N type shallow doped area

191, 192‧‧‧P type doping area

121‧‧‧Selection circuit

122‧‧‧Control circuit

MP1~MP4‧‧‧P type transistor

C1, C2‧‧‧ capacitor

R1, R2‧‧‧ resistance

Claims (25)

An ESD protection device is electrically connected to a first pad and a second pad, and includes: a protection component having a first connection end, a second connection end, and a first to a third control end The protective component is electrically connected to the first and second pads respectively through the first and second connecting ends, and includes: a P-type substrate, including an N-type deep well region and a first P-type well And a second P-type well region, wherein the first and the second P-type well region are disposed in the N-type deep well region; a first N-type transistor is formed in the N-type deep well region and the first a P-type well region; and a second N-type transistor formed in the N-type deep well region and the second P-type well region, and the first/source of the first and second N-type transistors The first and second N-type transistors are electrically connected to the first and second connection ends, and the first and the second N are electrically connected to the first control terminal. a gate of the type transistor is electrically connected to the second and the third control end respectively; and a component controller electrically connecting the first to the third control end, when an electrostatic When the rushing occurs on the first pad or the second pad, the component controller turns on one of the first and the second N-type transistors to release the static electricity through a current path in the protection component Pulse, when a first and a second operation signal are supplied to the first and second pads, the component controller turns off the first and second N-types according to the first and second operation signals a transistor so that the protective element cannot be formed The current path. The electrostatic discharge protection device of claim 1, wherein when the electrostatic pulse is present on the first pad, the component controller directs the electrostatic pulse to the first control end, and the component controls The transistor turns on the second N-type transistor and turns off the first N-type transistor. The electrostatic discharge protection device of claim 2, wherein the component controller further directs the electrostatic pulse to the third control terminal, and pulls the voltage level of the second control terminal to a ground voltage. The electrostatic discharge protection device of claim 2, wherein the component controller further directs the electrostatic pulse to the second control terminal and the third control terminal. The electrostatic discharge protection device of claim 1, wherein the component controller comprises: a first selection circuit electrically connected to the first pad, the second pad and the first control end, wherein The first selection circuit selects a high level signal from the signals from the first and the second pads, and outputs the high level signal to the first control end; and a first control circuit, electrical Connecting the first pad, the second pad, the second control end and the third control end, wherein the first control circuit adjusts the frequency according to the frequency of the signals from the first and the second pads The voltage level of the second control terminal and the third control terminal. The electrostatic discharge protection device of claim 5, wherein the first selection circuit comprises: a first P-type transistor, the gate electrically connected to the first pad; and a second P-type transistor The gate is electrically connected to the first pad, And the first P-type transistor and the second P-type transistor are connected in series between the second pad and the first control end; a third P-type transistor, the gate is electrically connected to the second a pad; and a fourth P-type transistor, the gate is electrically connected to the second pad, and the third P-type transistor and the fourth P-type transistor are serially connected to the first pad and the Between the first control terminals. The electrostatic discharge protection device of claim 5, wherein the first control circuit comprises: a first capacitor, the first end of which is electrically connected to the first pad, and the second end of the first capacitor is electrically The first resistor is electrically connected to the second end of the first capacitor, and the second end of the first resistor is electrically connected to the second pad; a second capacitor The first end is electrically connected to the second pad, the second end of the second capacitor is electrically connected to the second control end, and a second resistor is electrically connected to the second end of the second capacitor The second end of the second resistor is electrically connected to the first pad. The electrostatic discharge protection device of claim 5, wherein the first control circuit comprises: a third capacitor, the first end of which is electrically connected to the first pad, and the second end of the third capacitor is electrically Connected to the third control terminal; a third N-type transistor, the first 汲/source is electrically connected to the second end of the third capacitor, and the gate of the third N-type transistor is electrically connected to the third a selection circuit, the second 源/source of the third N-type transistor is electrically connected to the second pad; a fourth capacitor, the first end of which is electrically connected to the second pad, the second end of the fourth capacitor is electrically connected to the second control end; and a fourth N-type transistor, the first source/source thereof Electrode is electrically connected to the second end of the fourth capacitor, the gate of the fourth N-type transistor is electrically connected to the first selection circuit, and the second 源/source of the fourth N-type transistor is electrically connected to the First pad. The electrostatic discharge protection device of claim 1, wherein the component controller comprises: a second selection circuit electrically connected to the first pad, the second pad and the first control end, wherein The second selection circuit selects a high level signal from the signals from the first and the second pads, and outputs the high level signal to the first control end; a third selection circuit is electrically connected The first pad and the second pad, wherein the third selection circuit selects a low level signal from the signals from the first and the second pads, and outputs the low level signal; a second control circuit electrically connected to the second selection circuit, the third selection circuit, the second control terminal and the third control terminal, wherein the second control is performed when the electrostatic pulse is present on the first pad The circuit outputs the high level signal formed by the electrostatic pulse to the second and third control terminals, when the first and second operation signals are supplied to the first and second pads, The second control circuit receives a power supply voltage and the low level signal The number is output to the second and the third control end. The electrostatic discharge protection device of claim 9, wherein the second selection circuit comprises: a fifth P-type transistor having a gate electrically connected to the first pad; a sixth P-type transistor having a gate electrically connected to the first pad, and the fifth P-type transistor and the a sixth P-type transistor is serially connected between the second pad and the first control terminal; a seventh P-type transistor having a gate electrically connected to the second pad; and an eighth P-type transistor The gate is electrically connected to the second pad, and the seventh P-type transistor and the eighth P-type transistor are connected in series between the first pad and the first control end. The electrostatic discharge protection device of claim 9, wherein the third selection circuit comprises: a fifth N-type transistor, wherein the first 源/source is electrically connected to the second pad, the fifth The gate of the N-type transistor is electrically connected to the first pad; the sixth N-type transistor has a first 汲/source electrically connected to the second 汲/source of the fifth N-type transistor, The gate of the sixth N-type transistor is electrically connected to the first pad, and the second 源/source of the sixth N-type transistor is electrically connected to the second control circuit; a seventh N-type transistor, The first 汲/source is electrically connected to the first pad, the gate of the seventh N-type transistor is electrically connected to the second pad; and an eighth N-type transistor has a first 汲/source Electrically connecting the second 汲/source of the seventh N-type transistor, the gate of the eighth N-type transistor is electrically connected to the second pad, and the second 汲/source of the eighth N-type transistor The second control circuit is electrically connected to the second control circuit. Such as the electrostatic discharge protection device described in claim 9 The second control circuit includes: a ninth P-type transistor, wherein the first 源/source is electrically connected to the second and the third control end, and the second 汲 of the ninth P-type transistor The source is electrically connected to the second selection circuit; a ninth N-type transistor, the first 源/source is electrically connected to the first 汲/source of the ninth P-type transistor, and the ninth N-type The gate of the crystal is electrically connected to the second selection circuit; a tenth N-type transistor having a first 汲/source electrically connected to the second 汲/source of the ninth N-type transistor, the tenth N The gate of the type transistor receives the power supply voltage, and the second 源/source of the tenth N-type transistor is electrically connected to the third selection circuit; a tenth P-type transistor, the first 源/source is electrically Connected to the gate of the ninth P-type transistor, the gate of the tenth P-type transistor is electrically connected to the first 汲/source of the ninth P-type transistor, and the tenth of the tenth P-type transistor The second 汲/source is electrically connected to the second selection circuit; an eleventh N-type transistor, the first 汲/source is electrically connected to the first 汲/source of the tenth P-type transistor, the first Gate of eleven N-type transistor Connecting the second selection circuit; and a twelfth N-type transistor, wherein the first 源/source is electrically connected to the second 汲/source of the eleventh N-type transistor, the twelfth N-type The gate of the transistor is electrically connected to the gate of the tenth P-type transistor, and the second 汲/source of the twelfth N-type transistor is electrically connected to the third selection circuit. The electrostatic discharge protection device of claim 1, wherein the first N-type transistor comprises: a first gate structure disposed on the first P-type well region, and the a gate of the first N-type transistor is formed by the first gate structure; a first N-type doped region is disposed in the N-type deep well region adjacent to the first P-type well region, and the a first 汲/source of the first N-type transistor is formed by the first N-type doping region; and a second N-type doping region is disposed in the first P-type well region, and the first A second germanium/source of an N-type transistor is formed by the second N-type doped region. The electrostatic discharge protection device of claim 13, wherein the first N-type transistor further comprises: a first N-type shallow doped region, the first P disposed under the first gate structure The well region is surrounded by the circumference of the first N-type doped region. The electrostatic discharge protection device of claim 1, wherein the second N-type transistor comprises: a second gate structure disposed on the second P-type well region, and the second N-type electricity The gate of the crystal is formed by the second gate structure; a third N-type doped region is disposed in the N-type deep well region adjacent to the second P-type well region, and the second N-type electric region a first 汲/source of the crystal is formed by the third N-type doped region; and a fourth N-type doped region is disposed in the second P-type well region, and the second N-type transistor is The second germanium/source is formed by the fourth N-type doped region. The electrostatic discharge protection device of claim 15, wherein the second N-type transistor further comprises: a second N-type shallow doped region, the second P disposed under the second gate structure The well region is surrounded by the circumference of the third N-type doped region. The electrostatic discharge protection device of claim 1, wherein the protection component further comprises: a first P-type doping region disposed in the first P-type well region and electrically connected to the first connection end. The electrostatic discharge protection device of claim 1, wherein the protection component further comprises: a second P-type doping region disposed in the second P-type well region and electrically connected to the second connection end. A protection component comprising: a P-type substrate comprising an N-type deep well region, a first P-type well region and a second P-type well region, wherein the first and the second P-type well region are disposed in the N a deep well region; a first N-type transistor formed in the N-type deep well region and the first P-type well region; and a second N-type transistor formed in the N-type deep well region and the second In the P-type well region, the protection component has a first connection end, a second connection end, and a first to a third control end, and the first and the first N-type transistor are first The first source and the source are electrically connected to the first control terminal, and the first and the second anode/source of the second N-type transistor are electrically connected to the first and the second connection end, respectively, the first and the second The gates of the two N-type transistors are electrically connected to the second and the third control terminals, respectively. The protection component of claim 19, further comprising: a first P-type doping region disposed in the first P-type well region and electrically connected to the first connection terminal. The protection component of claim 19, further comprising: a second P-type doping region disposed in the second P-type well region and electrically connected to the second connection terminal. The protection element of claim 19, wherein the first N-type transistor comprises: a first gate structure disposed on the first P-type well region, and the gate of the first N-type transistor a pole formed by the first gate structure; a first N-type doped region disposed in the N-type deep well region adjacent to the first P-type well region, and the first N-type transistor One 汲/source is formed by the first N-type doping region; and a second N-type doping region is disposed in the first P-type well region, and the second N-type transistor is second The 汲/source is formed by the second N-type doped region. The protection element of claim 22, wherein the first N-type transistor further comprises: a first N-type shallow doped region, the first P-type well region disposed under the first gate structure Inside and surrounding the first N-type doped region. The protection element of claim 19, wherein the second N-type transistor comprises: a second gate structure disposed on the second P-type well region, and the gate of the second N-type transistor a pole formed by the second gate structure; a third N-type doped region disposed in the N-type deep well region adjacent to the second P-type well region, and the second N-type transistor a 汲/source is formed by the third N-type doping region; and a fourth N-type doping region is disposed in the second P-type well region, and The second 汲/source of the second N-type transistor is formed by the fourth N-type doping region. The protection element of claim 24, wherein the second N-type transistor further comprises: a second N-type shallow doped region, the second P-type well region disposed under the second gate structure Inside and surrounding the third N-type doped region.