TWI493688B - Integrated circuit device - Google Patents

Description

Integrated circuit device

The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device having an electrostatic discharge protection circuit.

Electrostatic discharge (ESD) is often the main cause of electrostatic overstress or permanent damage to integrated circuit devices. Therefore, the existing integrated circuit device tends to add an electrostatic discharge protection circuit between the output stage of the internal circuit and the pad to prevent damage from electrostatic discharge.

In addition, under the existing electrostatic discharge protection circuit, the output stage of the internal circuit must still pass through a specific layout structure to prevent damage caused by electrostatic discharge. For example, in the case of the existing integrated circuit device, in addition to the electrostatic discharge protection circuit, the MOS transistor in the output stage must also conform to the ESD design criteria in the circuit layout, in order to increase the MOS transistor. The length of the polar region, in turn, forms a parasitic resistance to prevent electrostatic discharge.

However, this method not only increases the layout area of the output stage, but also leads to an increase in the hardware space and production cost of the integrated circuit device, thereby limiting the miniaturization of the integrated circuit device.

The invention provides an integrated circuit device for protecting electricity through electrostatic discharge The circuit provides a dual discharge path to thereby reduce the hardware space and production cost of the integrated circuit device.

The invention provides an integrated circuit device comprising an internal circuit, an electrostatic discharge protection circuit and a solder pad. The internal circuit is electrically connected to the power supply wiring and the ground wiring. The ESD protection circuit is electrically connected to the internal circuit, the power supply wiring and the grounding wiring, and includes a first protection unit and a second protection unit. The solder pads are electrically connected to the internal circuit through the first protection unit and the second protection unit. Wherein, when the electrostatic signal appears on the solder pad, the ESD protection circuit firstly guides part of the electrostatic signal to the power supply wiring or the ground wiring through the first protection unit, and then passes the remaining electrostatic signal through the second protection unit. Guide to power wiring or ground wiring.

In an embodiment of the invention, the internal circuit is electrically connected to the pad through an output stage, and the output stage includes a first P-type transistor and a first N-type transistor. The first P-type transistor is electrically connected between the power supply wiring and the pad. The first N-type transistor is electrically connected between the pad and the ground wiring.

In an embodiment of the invention, the first protection unit comprises a first diode and a second diode. The cathode of the first diode is electrically connected to the power supply wiring, and the anode of the first diode is electrically connected to the solder pad. The cathode of the second diode is electrically connected to the pad, and the anode of the second diode is electrically connected to the ground wiring.

In an embodiment of the invention, the second protection unit comprises a second P-type transistor, a first resistor, a second N-type transistor and a second resistor. The second P-type transistor includes a first end, a second end, and a control end, wherein the first end of the second P-type transistor is electrically connected to the power supply wiring, and the second P-type electric crystal The second end of the body is electrically connected to the pad. The first end of the first resistor is electrically connected to the power wiring, and the second end of the first resistor is electrically connected to the control end of the second P-type transistor. The second N-type transistor includes a first end, a second end, and a control end, wherein the first end of the second N-type transistor is electrically connected to the pad, and the second end of the second N-type transistor is electrically connected to Ground wiring. The first end of the second resistor is electrically connected to the control end of the second N-type transistor, and the second end of the second resistor is electrically connected to the ground wiring.

In an embodiment of the invention, the second protection unit further includes a first capacitor and a second capacitor. The first end of the first capacitor is electrically connected to the second end of the first resistor, and the second end of the first capacitor is electrically connected to the pad. The first end of the second capacitor is electrically connected to the pad, and the second end of the second capacitor is electrically connected to the first end of the second resistor.

Based on the above, the present invention utilizes the first protection unit and the second protection unit in the electrostatic discharge protection circuit to form a dual discharge path, and thereby directs the electrostatic signal to the power supply wiring and the ground wiring. Thereby, under the arrangement of the electrostatic discharge protection circuit, the integrated circuit device can prevent damage caused by electrostatic discharge without increasing the layout area of the output stage, thereby contributing to reducing the hardware space and production cost of the integrated circuit device. .

The above described features and advantages of the present invention will be more apparent from the following description.

In the following description, in order to present the consistency of the description of the present invention, in different embodiments, if there are components having the same or similar functions and structures, Use the same component symbol and name.

[First Embodiment]

1A is a circuit diagram of an integrated circuit device according to a first embodiment of the present invention. Referring to FIG. 1A, the integrated circuit device 100 includes an internal circuit 110, an electrostatic discharge protection circuit 120, and a pad 130. The internal circuit 110 is electrically connected to the power supply wiring 101 and the ground wiring 102.

In the first embodiment, the internal circuit 110 is electrically connected to the pad 130 through an output stage 111 to thereby transmit an output signal to the pad 130. Further, the output stage 111 includes a P-type transistor 141 and an N-type transistor 142. The P-type transistor 141 is electrically connected between the power supply line 101 and the pad 130 , and the N-type transistor 142 is electrically connected between the pad 130 and the ground line 102 . It is worth mentioning that although the first embodiment exemplifies the connection pattern of the internal circuit 110 and the pad 130, it is not intended to limit the present invention. For example, the internal circuit 110 can also be electrically connected to the pad 130 through an input stage to receive an input signal from the pad 130.

Referring to FIG. 1A , the ESD protection circuit 120 is electrically connected to the internal circuit 110 , the power supply line 101 , and the ground line 102 , and includes a first protection unit 121 and a second protection unit 122 . In operation, when an electrostatic signal is present on the pad 130, the first protection unit 121 first provides a discharge path to guide a portion of the electrostatic signal to the power supply line 101 or the ground line 102. Thereafter, the second protection unit 122 provides another discharge path to guide the remaining electrostatic signals to the power supply wiring 101 or the ground wiring 102. In other words, when an electrostatic discharge event occurs, the ESD protection circuit 120 firstly guides some of the electrostatic signals through the first protection unit 121 to The power supply wiring 101 or the ground wiring is then guided to the power supply wiring 101 or the ground wiring 102 through the second protection unit 122.

In this way, damage to the internal circuit 110 caused by the electrostatic signal can be avoided. In addition, since the first protection unit 121 and the second protection unit 122 provide a dual discharge path to release the electrostatic signal, the output stage 111 in the internal circuit 110 does not need to be increased by the P-type transistor 141 and the N-type transistor 142. The length of the drain region to further prevent electrostatic discharge effects. In other words, under the arrangement of the electrostatic discharge protection circuit 120, the integrated circuit device 100 can prevent damage caused by electrostatic discharge without increasing the layout area of the output stage 111, thereby contributing to reducing the hardware space of the integrated circuit device 100. Cost of production.

Further, the first protection unit 121 includes a diode D11 and a diode D12, and the second protection unit 122 includes a P-type transistor 151, an N-type transistor 152, a resistor R1, and a resistor R2. The cathode of the diode D11 is electrically connected to the power supply wiring 101, and the anode of the diode D11 is electrically connected to the solder pad 130. The cathode of the diode D12 is electrically connected to the pad 130, and the anode of the diode D12 is electrically connected to the ground wiring 102. In addition, the first end of the P-type transistor 151 is electrically connected to the power supply line 101, and the second end of the P-type transistor 151 is electrically connected to the pad 130. The first end of the resistor R1 is electrically connected to the power supply wiring 101, and the second end of the resistor R1 is electrically connected to the control end of the P-type transistor 151. The first end of the N-type transistor 152 is electrically connected to the pad 130, and the second end of the N-type transistor 152 is electrically connected to the ground line 102. The first end of the resistor R2 is electrically connected to the control end of the N-type transistor 152, and the second end of the resistor R2 is electrically connected to the ground wiring 102.

In operation, when the electrostatic signal appears on the pad 130 and the electrostatic signal is a positive pulse signal, the diode D11 in the first protection unit 121 will be turned on to provide a discharge path to guide a portion of the positive pulse signal. Lead to the power supply wiring 101. In addition, the positive pulse signal is coupled to the control terminal of the N-type transistor 152 through the parasitic capacitance of the N-type transistor 152, thereby turning on the N-type transistor 152. Therefore, the N-type transistor 152 in the second guard unit 122 will provide another discharge path to direct the remaining positive pulse signals to the ground wiring 102.

Moreover, when the electrostatic signal appears on the pad 130 and the electrostatic signal is a negative pulse signal, the diode D12 in the first protection unit 121 will be turned on to provide a discharge path to guide part of the negative pulse signal. To the ground wiring 102. In addition, the negative pulse signal is coupled to the control terminal of the P-type transistor 151 through the parasitic capacitance of the P-type transistor 151, thereby turning on the P-type transistor 151. Therefore, the P-type transistor 151 in the second guard unit 122 will provide another discharge path to guide the remaining negative pulse signals to the power supply wiring 101.

On the other hand, when the power supply voltage is supplied to the power supply wiring 101, and the ground voltage is supplied to the ground wiring 102, the internal circuit 110 will operate normally, and an output signal can be transmitted to the pad 130 through the output stage 111. In addition, with the supply of the power supply voltage and the ground voltage, the two diodes D11 and D12 in the first protection unit 121 will operate under reverse bias, and thus cannot be turned on. In addition, the control terminal of the P-type transistor 151 receives the power supply voltage through the resistor R1, and further switches to a non-conducting state. Furthermore, the N-type transistor 152 receives the ground voltage through the resistor R2, and further switches to no. The state of conduction. In other words, when the internal circuit 110 is normally operated, neither the first protection unit 121 nor the second protection unit 122 can generate a discharge path, thereby preventing the electrostatic discharge protection circuit 120 from generating a leakage current.

It is to be noted that, in FIG. 1A, the P-type transistor 151 and the N-type transistor 152 in the second protection unit 122 are respectively composed of a PMOS transistor MP1 and an NMOS transistor MN1. In addition, the first end, the second end, and the control end of the P-type transistor 151 are respectively a source, a drain, and a gate of the PMOS transistor MP1, and the first end and the second end of the N-type transistor 152 are controlled. The terminals are the drain, the source and the gate of the NMOS transistor MN1, respectively.

However, in practical applications, the P-type transistor 151 and the N-type transistor 152 may each be composed of a double-carrier transistor. For example, FIG. 1B is another circuit diagram of an integrated circuit device according to a first embodiment of the present invention. Referring to FIG. 1B, the P-type transistor 151 is composed of a PNP transistor BP1, and the first end, the second end, and the control end of the P-type transistor 151 are an emitter, a collector, and a base, respectively. In addition, the N-type transistor 152 is composed of an NPN transistor BN1, and the first end, the second end, and the control end of the N-type transistor 152 are respectively the collector, the emitter, and the base of the NPN transistor BN1.

2A and FIG. 2B are schematic diagrams showing a layout of an integrated circuit device according to an embodiment of the invention. As shown in FIG. 2A, in the circuit layout, the diode D11 includes a P-type doping region 211 and an N-type well region 212, and the diode D12 includes an N-type doping region 221 and a P-type well region 222. Further, the diode D11 and the diode D12 are disposed under the pad 130 to thereby reduce the layout area. In addition, FIG. 2A only shows the P-type electric crystal of FIG. 1 . The active region (for example, 231 to 234) and the gate (for example, 241 to 244) of the body 141, the P-type transistor 151, the N-type transistor 142, and the N-type transistor 152.

As seen from FIG. 2A, the P-type transistor 151 and the N-type transistor 152 in the second protection unit 122 conform to the design criteria of the ESD. For example, the length WD1 of the drain region of the P-type transistor 151 is greater than that of the source region thereof. Length WS1. In addition, the P-type transistor 141 and the N-type transistor 142 in the output stage 111 do not need to comply with the ESD design criteria. For example, the length WD2 of the drain region of the P-type transistor 141 is approximately equal to the length of the source region WS2. . In other words, under the arrangement of the electrostatic discharge protection circuit 120, the integrated circuit device 100 can suppress the electrostatic discharge effect without increasing the length of the drain region of the MOS transistor in the output stage 111, so that the integrated circuit device 100 can be reduced. Hardware space and production costs.

In addition, in the circuit layout, as shown in FIG. 2A, the P-type transistor 141 and the P-type transistor 151 may be sequentially arranged on one side of the pad 130, and the N-type transistor 142 and the N-type transistor 152 are The other side of the pad 130 may be sequentially arranged. In addition, as shown in FIG. 2B, in another embodiment, the P-type transistor 141, the P-type transistor 151, the N-type transistor 142, and the N-type transistor 152 may also surround the periphery of the pad 130. Although the embodiment of FIGS. 2A and 2B exemplifies the configuration of the P-type transistor 141, the P-type transistor 151, the N-type transistor 142, and the N-type transistor 152, it is not intended to limit the present invention.

[Second embodiment]

3A is a circuit diagram of an integrated circuit device in accordance with a second embodiment of the present invention. Please refer to FIG. 1A and FIG. 3A simultaneously, the two embodiments are the most The difference is that the second protection unit 122 in the integrated circuit device 300 of FIG. 3A further includes an inverter 310 and an inverter 320.

Specifically, in the second embodiment, the input end of the inverter 310 is electrically connected to the ground wiring 102, and the output end of the inverter 310 is electrically connected to the control end of the P-type transistor 151. Furthermore, the input end of the inverter 320 is electrically connected to the power supply wiring 101, and the output end of the inverter 320 is electrically connected to the control end of the N-type transistor 152. Thereby, when the internal circuit 110 operates normally, the inverter 310 will output a high level signal in response to the ground voltage from the ground wiring 102, thereby turning off the P-type transistor 151. In addition, the inverter 320 outputs a low level signal in response to the power supply voltage from the power supply wiring 101, thereby turning off the N-type transistor 152. In other words, when the internal circuit 110 operates normally, neither the first protection unit 121 nor the second protection unit 122 can generate a discharge path.

On the other hand, similar to the first embodiment, when an electrostatic signal is present on the pad 130, one of the diode D11 and the diode D12 will be turned on, thereby providing a discharge path for releasing a portion of the electrostatic signal. In addition, the electrostatic signal is coupled to the control terminal through the parasitic capacitance of the P-type transistor 151 and the N-type transistor 152, thereby turning on one of the P-type transistor 151 and the N-type transistor 152. Thereby, the second protection unit 122 will provide another discharge path to release the remaining electrostatic signals.

Furthermore, in FIG. 3A, the P-type transistor 151 and the N-type transistor 152 in the second guard unit 122 are respectively composed of a PMOS transistor MP1 and an NMOS transistor MN1. However, in practical applications, the P-type transistor 151 and the N-type transistor 152 may also be respectively composed of a double-carrier electron crystal. Body composition. For example, FIG. 3B is another circuit diagram of the integrated circuit device according to the second embodiment of the present invention. Referring to FIG. 3B, the P-type transistor 151 and the N-type transistor 152 are respectively composed of a PNP transistor BP1 and an NPN transistor BN1. The detailed description of the second embodiment illustrated in FIGS. 3A and 3B has been included in the above embodiments, and thus will not be described herein.

[Third embodiment]

4A is a circuit diagram of an integrated circuit device in accordance with a third embodiment of the present invention. Referring to FIG. 1A and FIG. 4A simultaneously, the two embodiments are different in that the second protection unit 122 in the integrated circuit device 400 of FIG. 4A further includes a capacitor C1 and a capacitor C2.

Specifically, in the third embodiment, the first end of the capacitor C1 is electrically connected to the second end of the resistor R1, and the second end of the capacitor C1 is electrically connected to the pad 130. In addition, the first end of the capacitor C2 is electrically connected to the pad 130, and the second end of the capacitor C2 is electrically connected to the first end of the resistor R2. Among them, the impedance of the capacitors C1 and C2 is inversely proportional to the frequency of the signal. That is, capacitors C1 and C2 will approximate an open circuit during low frequency operation, and capacitors C1 and C2 will approximate a short circuit at high frequency operation. Therefore, when the electrostatic signal appears on the pad 130, since the electrostatic signal is a high frequency signal, the capacitors C1 and C2 at this time are approximately short-circuited. Thereby, the electrostatic signal can be directly transmitted through the capacitors C1 and C2 to the control terminals of the P-type transistor 151 and the N-type transistor 152, thereby turning on one of the P-type transistor 151 and the N-type transistor 152.

On the other hand, when the internal circuit 110 operates normally, since the power supply voltage from the power supply wiring 101 and the ground voltage from the ground wiring 102 are both It is a low frequency signal, so the capacitors C1 and C2 at this time are approximately open. Thereby, similar to the first embodiment, the control terminal of the P-type transistor 151 receives the power supply voltage through the resistor R1, thereby switching to the non-conducting state. Further, the N-type transistor 152 receives the ground voltage through the resistor R2 and also switches to the non-conducting state.

Furthermore, in FIG. 4A, the P-type transistor 151 and the N-type transistor 152 in the second guard unit 122 are respectively composed of a PMOS transistor MP1 and an NMOS transistor MN1. However, in practical applications, the P-type transistor 151 and the N-type transistor 152 may each be composed of a double-carrier transistor. For example, FIG. 4B is another circuit diagram of the integrated circuit device according to the third embodiment of the present invention. Referring to FIG. 4B, the P-type transistor 151 and the N-type transistor 152 are respectively composed of a PNP transistor BP1 and an NPN transistor BN1. The detailed description of the third embodiment illustrated in FIGS. 4A and 4B has been included in the above embodiments, and thus will not be described herein.

[Fourth embodiment]

FIG. 5A is a circuit diagram of an integrated circuit device according to a fourth embodiment of the present invention. Referring to FIG. 1A and FIG. 5A simultaneously, the two embodiments are different in that the second protection unit 122 in the integrated circuit device 500 of FIG. 5A includes, in addition to the P-type transistor 151 and the N-type transistor 152, It further includes inverters 510 and 520, resistors R3 and R4, and capacitors C3 and C4.

Specifically, in the fourth embodiment, the first end and the second end of the P-type transistor 151 are electrically connected to the power wiring 101 and the pad 130, respectively, and P The control terminal of the type transistor 151 is electrically connected to the output terminal of the inverter 510. The first end of the capacitor C3 is electrically connected to the power supply line 101, and the second end of the capacitor C3 is electrically connected to the input end of the inverter 510. The first end of the resistor R3 is electrically connected to the second end of the capacitor C3, and the second end of the resistor R3 is electrically connected to the ground wiring 102. The first end and the second end of the N-type transistor 152 are electrically connected to the pad 130 and the ground line 102, respectively, and the control end of the N-type transistor 152 is electrically connected to the output end of the inverter 520. The first end of the resistor R4 is electrically connected to the power supply line 101, and the second end of the resistor R4 is electrically connected to the input end of the inverter 520. The first end of the capacitor C4 is electrically connected to the second end of the resistor R4, and the second end of the capacitor C4 is electrically connected to the ground wiring 102.

In operation, when an electrostatic signal appears on the pad 130 and the electrostatic signal is a positive pulse signal, the positive pulse signal is coupled to the power supply wiring 101 through the parasitic diode in the P-type transistor 151. It is known that the first end of the resistor R4 is electrically connected to the power supply line 101. Therefore, the low-pass filter formed by the resistor R4 and the capacitor C4 can receive the positive pulse signal and generate a low level signal accordingly. In addition, the inverter 520 generates a high level signal in response to the low level signal, thereby turning on the N-type transistor 152.

Moreover, when the electrostatic signal appears on the pad 130 and the electrostatic signal is a negative pulse signal, the negative pulse signal is coupled to the ground wiring 102 through the parasitic diode in the N-type transistor 152. It is known that the second end of the resistor R3 is electrically connected to the ground wiring 102. Therefore, the low-pass filter formed by the resistor R3 and the capacitor C3 can receive the negative pulse signal and generate a high-level signal accordingly. In addition, the inverter 510 generates a low level signal in response to the high level signal, thereby turning on the P type transistor 151.

On the other hand, when the internal circuit 110 operates normally, since the power supply voltage from the power supply wiring 101 and the ground voltage from the ground wiring 102 are both low frequency signals, the capacitances C1 and C2 at this time are approximately open. Thereby, the inverter 510 will generate a high level signal, thereby turning off the P-type transistor 151. In contrast, inverter 520 will generate a low level signal, thereby turning off N-type transistor 152. In other words, when the internal circuit 110 operates normally, the second guard unit 122 cannot generate a discharge path.

Furthermore, in FIG. 5A, the P-type transistor 151 and the N-type transistor 152 in the second guard unit 122 are respectively composed of a PMOS transistor MP1 and an NMOS transistor MN1. However, in practical applications, the P-type transistor 151 and the N-type transistor 152 may each be composed of a double-carrier transistor. For example, FIG. 5B is another circuit diagram of the integrated circuit device according to the fourth embodiment of the present invention. Referring to FIG. 5B, the P-type transistor 151 and the N-type transistor 152 are respectively composed of a PNP transistor BP1 and an NPN transistor BN1. The detailed description of the fourth embodiment illustrated in FIGS. 5A and 5B has been included in the above embodiments, and thus will not be described herein.

In summary, the present invention utilizes the first protection unit and the second protection unit in the electrostatic discharge protection circuit to form a dual discharge path, thereby guiding the electrostatic signal to the power supply wiring and the ground wiring. Thereby, under the arrangement of the electrostatic discharge protection circuit, the integrated circuit device can prevent damage caused by electrostatic discharge without increasing the layout area of the output stage, thereby contributing to reducing the hardware space and production cost of the integrated circuit device. And contribute to the development of integrated circuit devices in miniaturization.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 300, 400, 500‧‧‧ integrated circuit devices

101‧‧‧Power wiring

102‧‧‧ Grounding Wiring

110‧‧‧Internal circuits

111‧‧‧Output level

120‧‧‧Electrostatic discharge protection circuit

121‧‧‧First protection unit

122‧‧‧Second protection unit

130‧‧‧ solder pads

141, 151‧‧‧P type transistor

142, 152‧‧‧N type transistor

R1, R2, R3, R4‧‧‧ resistance

D11, D12‧‧‧ diode

MP1‧‧‧ PMOS transistor

MN1‧‧‧NMOS transistor

BP1‧‧‧PNP transistor

BN1‧‧‧NPN transistor

211‧‧‧P-doped area

212‧‧‧N type well area

221‧‧‧N-doped area

222‧‧‧P type well area

231~234‧‧‧active area

241~244‧‧‧ gate

Length of WD1, WD2‧‧ ‧ bungee zone

Length of WS1, WS2‧‧‧ source region

310, 320, 510, 520‧‧ ‧ inverter

C1, C2, C3, C4‧‧‧ capacitors

1A is a circuit diagram of an integrated circuit device according to a first embodiment of the present invention.

Fig. 1B is another circuit diagram of the integrated circuit device according to the first embodiment of the present invention.

2A and 2B are schematic diagrams showing a layout of an integrated circuit device according to an embodiment of the invention.

3A is a circuit diagram of an integrated circuit device in accordance with a second embodiment of the present invention.

Fig. 3B is another circuit diagram of the integrated circuit device in accordance with the second embodiment of the present invention.

4A is a circuit diagram of an integrated circuit device in accordance with a third embodiment of the present invention.

4B is another circuit diagram of the integrated circuit device according to the third embodiment of the present invention.

FIG. 5A is a circuit diagram of an integrated circuit device according to a fourth embodiment of the present invention.

FIG. 5B is another circuit diagram of the integrated circuit device according to the fourth embodiment of the present invention.

100‧‧‧Integrated circuit device

101‧‧‧Power wiring

102‧‧‧ Grounding Wiring

110‧‧‧Internal circuits

111‧‧‧Output level

120‧‧‧Electrostatic discharge protection circuit

121‧‧‧First protection unit

122‧‧‧Second protection unit

130‧‧‧ solder pads

141, 151‧‧‧P type transistor

142, 152‧‧‧N type transistor

R1, R2‧‧‧ resistance

D11, D12‧‧‧ diode

MP1‧‧‧ PMOS transistor

MN1‧‧‧NMOS transistor

Claims (7)

An integrated circuit device comprising: an internal circuit electrically connected to a power supply wiring and a ground wiring; an electrostatic discharge protection circuit electrically connecting the internal circuit, the power supply wiring and the ground wiring, and including a first protection And a second protection unit; and a solder pad electrically connected to the internal circuit through the first protection unit and the second protection unit, wherein when an electrostatic signal is present on the bonding pad, the static electricity The discharge protection circuit firstly guides a portion of the electrostatic signal to the power supply wiring or the ground wiring through the first protection unit, and then guides the remaining static electricity signal to the power supply wiring or through the second protection unit. The second protection unit includes a first P-type transistor, a first end, a second end, and a control end, wherein the first end of the first P-type transistor is electrically Connecting the power wiring, the second end of the first P-type transistor is electrically connected to the pad; a first resistor is electrically connected to the power terminal, and the second end of the first resistor is electrically connected connection a control terminal of the first P-type transistor; a first N-type transistor comprising a first end, a second end and a control end, wherein the first end of the first N-type transistor is electrically connected to the solder a pad, the second end of the first N-type transistor is electrically connected to the ground wire; and a second resistor electrically connected to the control end of the first N-type transistor, the second resistor The two ends are electrically connected to the ground wiring. The integrated circuit device according to claim 1, wherein The internal circuit is electrically connected to the pad through an output stage, and the output stage includes: a second P-type transistor electrically connected between the power wiring and the pad; and a second N-type A crystal is electrically connected between the pad and the ground wiring. The integrated circuit device of claim 1, wherein the first protection unit comprises: a first diode, the cathode is electrically connected to the power wiring, and the anode of the first diode is electrically connected. The pad; and a second diode, the cathode of the second electrode is electrically connected to the pad, and the anode of the second diode is electrically connected to the ground. The integrated circuit device of claim 1, wherein the first P-type transistor is a PMOS transistor or a PNP transistor, and the first N-type transistor is an NMOS transistor or a NPN transistor. The integrated circuit device of claim 1, wherein the second protection unit further comprises: a first capacitor electrically connected to the second end of the first resistor, the first capacitor The second end is electrically connected to the pad; and a second capacitor is electrically connected to the pad, and the second end of the second capacitor is electrically connected to the first end of the second resistor. An integrated circuit device comprising: an internal circuit electrically connected to a power supply wiring and a grounding wiring; an electrostatic discharge protection circuit electrically connected to the internal circuit, the power supply Wiring and the grounding wiring, and comprising a first protection unit and a second protection unit; and a solder pad electrically connected to the internal circuit through the first protection unit and the second protection unit, wherein When an electrostatic signal is present on the pad, the ESD protection circuit firstly directs the portion of the electrostatic signal to the power wiring or the ground wiring through the first protection unit, and then passes through the second protection unit. The remaining protection signal is directed to the power supply wiring or the grounding wiring, wherein the second protection unit comprises: a P-type transistor, comprising a first end, a second end and a control end, wherein the P The first end of the transistor is electrically connected to the power wiring, the second end of the P-type transistor is electrically connected to the pad; and a first inverter is electrically connected to the ground wiring, the first The output end of the inverter is electrically connected to the control end of the P-type transistor; an N-type transistor includes a first end, a second end and a control end, wherein the first end of the N-type transistor is electrically Sexually connecting the pad, the second of the N-type transistor The terminal is electrically connected to the grounding wire; and a second inverter has an input end electrically connected to the power wiring, and an output end of the second inverter is electrically connected to the control end of the N-type transistor. An integrated circuit device comprising: an internal circuit electrically connected to a power supply wiring and a ground wiring; an electrostatic discharge protection circuit electrically connecting the internal circuit, the power supply wiring and the ground wiring, and including a first protection a unit and a second protection unit; a solder pad is electrically connected to the internal circuit through the first protection unit and the second protection unit, wherein the electrostatic discharge protection circuit first transmits the first protection when an electrostatic signal is present on the bonding pad The unit directs part of the static signal to the power wiring or the ground wiring, and then guides the remaining static signal to the power wiring or the ground wiring through the second protection unit, wherein the The second protection unit includes: a P-type transistor, including a first end, a second end, and a control end, wherein the first end of the P-type transistor is electrically connected to the power wiring, and the P-type transistor is The second end is electrically connected to the pad; a first inverter has an output end electrically connected to the control end of the P-type transistor; and a first capacitor electrically connected to the power line of the first end, the first The second end of the first resistor is electrically connected to the input end of the first inverter; the first end is electrically connected to the second end of the first capacitor, and the second end of the first resistor is electrically connected The grounding wire; an N-type transistor, comprising a first end, a second end and a control end, wherein the first end of the N-type transistor is electrically connected to the pad, the second end of the N-type transistor is electrically connected to the ground wire; and a second inverter is outputted The second end is electrically connected to the control terminal of the N-type transistor; the second end of the second resistor is electrically connected to the power supply wiring, and the second end of the second resistor is electrically connected to the input end of the second inverter; And a second capacitor, the first end of which is electrically connected to the second of the second resistor The second end of the second capacitor is electrically connected to the ground wiring.