TWI518763B - Semiconductor process - Google Patents

Description

Semiconductor process

The present invention relates to a semiconductor process, and more particularly to a semiconductor process that simultaneously grinds a plurality of gate structures of unequal height by varying the polishing selectivity of the CMP process or by adding an etch process.

In today's complementary metal-oxide-semiconductor (CMOS) integrated circuits, as mass production processes progress, component sizes have been reduced to deep-submicron stages to enhance the performance of integrated circuits (ICs). And the speed of operation, but as the size of the component is reduced, there are some reliability problems. In order to solve the problems associated with component shrinkage, attempts have been made in the semiconductor process to incorporate various other processes.

For example, in order to reduce the sheet resistance of the drain and source of the CMOS device and the parasitic resistance of the gate, a so-called self-aligned silicide is developed. , Salicide) process, after forming the gate of the transistor and the source/drain region, covering a metal layer on the desired substrate and gate, and then heating to react to form a metal silicide. The unreacted metal layer is removed again.

In detail, since a salicide is selectively disposed on a portion of the desired substrate and gate, a metal telluride barrier layer must be formed before covering a metal layer (self-aligned). The silicide block (SAB) covers the area of the metal halide to block the metal halide from covering it. Taking a common two-gate structure as an example, when a gate structure needs to cover a metal telluride layer and the other gate structure does not need to be covered, a metal telluride barrier layer is first covered with a metal halide layer. The gate structure. However, after the process is completed, the thickness of the two gate structures is different, so that the interlayer dielectric material subsequently covered thereon remains on the gate structure having a lower thickness even after the polishing process. If the interlayer dielectric layer remaining on the gate structure is completely removed, it may be excessively etched or over-polished such as a gate structure having a relatively high thickness, so that the height of the gate structure is difficult to control and affects its internal structure. Reduce electrical quality.

The present invention provides a semiconductor process that solves the above-mentioned problem that the two gate structures have different height differences, causing the interlayer dielectric layer material to remain on the gate structure, resulting in deterioration of the electrical quality of the gate structure.

The present invention provides a semiconductor process comprising the steps described below. First, a first gate structure and a second gate structure are formed on a substrate, wherein a top portion of the first gate structure includes a cap layer such that a vertical height of the first gate structure is higher than a second gate structure The vertical height. Next, an interlevel dielectric layer is formed on the substrate and covers the first gate structure and the second gate structure. Next, a first chemical mechanical polishing process is performed to polish the interlayer dielectric layer to expose the top surface of the cap layer. Then, a second chemical mechanical polishing process is performed to polish at least the first gate structure and the interlayer dielectric layer to expose the top surface of the second gate structure.

The present invention provides a semiconductor process comprising the steps described below. First, a first gate structure and a second gate structure are formed on a substrate, wherein a top portion of the first gate structure includes a cap layer such that a vertical height of the first gate structure is higher than a second gate structure The vertical height. Next, an interlevel dielectric layer is formed on the substrate and covers the first gate structure and the second gate structure. Next, a first chemical mechanical polishing process is performed to polish the interlayer dielectric layer to expose the top surface of the cap layer. An etch process is then performed to remove the interlayer dielectric layer on the second gate structure. Thereafter, a second CMP process is performed to polish at least the first gate structure and the interlayer dielectric layer to remove the cap layer.

Based on the above, the present invention provides a semiconductor process in which a chemical mechanical polishing process has an approximate polishing selectivity ratio for a cap layer and an interlayer dielectric layer, or an etching process, which first removes a lower vertical height. The interlayer dielectric layer remaining on the gate structure exposes the first gate structure and the second gate structure flatly without any conventional etching or over-grinding of the gate structure.

1-8 are schematic cross-sectional views showing a semiconductor process according to an embodiment of the present invention. As shown in FIG. 1, after forming a first gate structure 110, a second gate structure 120, and corresponding two source/drain regions 130a and 130b, a stress memory technique can be selectively implemented (Stress The Memorization Technique (SMT) improves the carrier mobility by applying stress to the gate channels 140a and 140b under the first gate structure 110 and the second gate structure 120, respectively. The stress memory technology may include forming a strained germanium material (not shown) in the source/drain regions 130a and 130b, for example, forming a germanium epitaxial layer in the PMOS transistor or forming a germanium carbon epitaxial layer in the NMOS transistor. Or directly covering the corresponding stress layer (not shown) on the first gate structure 110 and the second gate structure 120, the invention is not limited thereto. In detail, the first gate structure 110 and the second gate structure 120 may respectively include a buffer layer 112 and 122 on the substrate 10, a gate dielectric layer 114 and 124 on the buffer layers 112 and 122, and a gate. The pole layers 116 and 126 are located on the gate dielectric layers 114 and 124, a cap layer 118 and 128 are located on the gate layers 116 and 126, and a spacer 119 and 129 are located on the buffer layers 112 and 122 and a gate dielectric layer. 114 and 124, a gate layer 116 and 126 and side edges of the cap layers 118 and 128. The material and formation method of the gate structure are well known in the art and will not be described again.

Please continue to refer to FIG. 1 to cover a metal halide barrier layer 20 on the substrate 10, the first gate structure 110 and the second gate structure 120. The metal telluride barrier layer 20 can be, for example, a tantalum nitride layer. In addition, the metal telluride blocking layer 20 may further comprise an oxide layer (not shown) between the substrate 10 and the nitride layer for buffering.

As shown in Figures 2-3, the metal telluride barrier layer 20 is defined such that it is only located in the region A where metal halides are not required to be formed. First, as shown in FIG. 2, a patterned photoresist layer P is formed to cover the metal telluride barrier layer 20a of the region A where metal halide does not need to be formed, and the metal telluride barrier layer 20b is exposed. It is located in the region B where metal halides are to be formed. Next, as shown in FIG. 3, an etching process is performed to remove the metal halide barrier layer 20b. Thereafter, the patterned photoresist layer P is removed leaving the patterned metal halide barrier layer 20a.

As shown in FIG. 4, a metal layer 60 is deposited on the substrate 10 in a comprehensive manner, and covers the metal telluride barrier layer 20a of the region A and the second gate structure 120 and the source/drain region 130b of the region B, and then proceeds. A rapid thermal anneal (RTA) is used to react the metal layer 60 with the substrate in direct contact with the enamel to form a self-aligned metal salicide, that is, a source/drain region 130b is formed. The metal halide 150 is finally removed from the unreacted metal layer 60. The material of the metal layer 60 may include nickel, cobalt, titanium, etc., and the metal halide 150 formed by reacting with the ruthenium substrate may be a nickel ruthenium compound or a titanium ruthenium compound, but the invention is not limited thereto. In addition, after the metal layer 60 is removed, the present embodiment can also selectively perform another rapid heating annealing (RTA) to lower the resistance value of the metal germanide 150.

As shown in FIG. 5, after the metal halide 150 is formed, the metal halide barrier layer 20a is removed. Since the metal telluride blocking layer 20a is usually a nitride layer, the cap layer 128 and the spacer 129 in the second gate structure 120 are also nitrided while removing the metal telluride blocking layer 20a. It will also be removed. It should be noted that since the cap layer 128 and the spacer 129 in the second gate structure 120 have been removed, the vertical height of the first gate structure 110 on the substrate 10 is higher than the second gate. The vertical height of the structure 120. In other words, since the first gate structure 110 has a cap layer 118 more than the second gate structure 120, the thickness t1 of the first gate structure 110 is greater than the thickness t2 of the second gate structure 120, so the first gate structure The horizontal plane of the top surface S1 of 110 is higher than the thickness t3 of the surface plane S2 of the second gate structure 120 by about several hundred angstroms. In the present embodiment, the first gate structure 110 and the second gate structure 120 having different heights are formed by the above method. However, in other embodiments, the first gate structure 110 having different heights may be formed in other manners. The second gate structure 120. Moreover, the formed gate structures having different heights are not limited to two, and may include more numbers, and the invention is not limited thereto.

As shown in FIG. 6, the substrate 10, the first gate structure 110, and the second gate structure 120 may be selectively covered by a contact Etching Stop Layer (CESL) 160, wherein the contact hole is etched. Layer 160 can be, for example, a nitride layer, and it can be re-incorporated with other impurities to have the function of a stress layer to apply pressure to the underlying gate channels 140a and 140b. Then, an interlayer dielectric layer 170 is formed on the substrate 10 and covers the first gate structure 110 and the second gate structure 120. In the present embodiment, the interlayer dielectric layer 170 is an oxide layer, but the invention is not limited thereto.

As shown in FIG. 7, a first chemical mechanical polishing process C1 is performed to polish the interlayer dielectric layer 170 to expose the contact hole etch stop layer 160 of the region A. In one embodiment, if the contact hole etch stop layer 160 is not covered, the top surface S1 of the cap layer 118 is directly exposed. As can be seen from the figure, since the first gate structure 110 and the second gate structure 120 have different heights (more specifically, the top of the first gate structure 110 further includes the cap layer 118), After the chemical mechanical polishing process C1, a portion of the interlayer dielectric layer 170 is left on the second gate structure 120.

As shown in FIG. 8, a second chemical mechanical polishing process C2 is performed to at least polish the first gate structure 110 and the interlayer dielectric layer 170 to expose the top surface S2 of the second gate structure 120. As shown in FIG. 7, since a portion of the interlayer dielectric layer 170 is left on the second gate structure 120, and the cap layer 118 and the interlayer dielectric layer 170 have different materials, the present invention is particularly In the second chemical mechanical polishing process C2, a polishing slurry is selected, and the polishing cover layer 118 and the interlayer dielectric layer 170 have a polishing selection ratio of between 1.2 and 0.8, preferably about 1, so that the cover can be removed at the same time. The layer 118 and the interlayer dielectric layer 170 are not conventionally known because the cap layer 118 is removed too quickly, resulting in the phenomenon that the first gate structure 110 is excessively ground. In a preferred embodiment, the second CMP process C2 comprises a CMP process in which the polishing ratio is selected, that is, the polishing rate of the slurry to the oxide is equal to the polishing rate of the nitride, so that The polishing rates of the cap layer 118 and the interlayer dielectric layer 170 are substantially equal. In this embodiment, the cap layer 118 is a nitride layer, and the interlayer dielectric layer 170 is an oxide layer. The slurry of the second chemical mechanical polishing process may include an oxygen inhibitor, and the concentration thereof is more general. The abrasive slurry used in the industry has fewer oxygen inhibitors, and the polishing rate of the interlayer dielectric layer 170 relative to the cap layer 118 can be accelerated, so that the cap layer 128 and the interlayer dielectric layer 170 can be simultaneously planarly moved. In addition, the gate layers 116 and 126 of the first gate structure 110 and the second gate structure 120 are stopped.

Further, since the second chemical mechanical polishing process C2 has the same polishing rate of oxide and nitride, the second chemical mechanical polishing process C2 first removes the contact hole located in the first gate structure 110 in the region A. Etching the stop layer 160 and the interlayer dielectric layer 170 of the region B, and then the first gate structure 110 is higher than the portion of the second gate structure 120 as the cap layer 118, and is the second chemical mechanical polishing process C2 polishing region. While the contact hole of B etches the stop layer 160 to expose the top surface S2 of the second gate structure 120, the cap layer 118 of the region A will be completely removed. At this time, when the cap layer 118 is removed, the contact hole etch stop layer 160 on the second gate structure 120 is also removed at the same time. Moreover, after the cap layer 118 is completely removed, and simultaneously exposing the gate layers 116 and 126 in the first gate structure 110 and the second gate structure 120. In other embodiments, depending on the needs of the process and the method of the process, the heights of the first gate structure and the second gate structure and the relative positions of the internal structures may be different, and the present invention is not illustrated by the embodiment. The first gate structure 110 and the second gate structure 120 are limited.

In addition, the present invention also proposes another similar process method to achieve the functionality of the present invention. 9-10 are schematic cross-sectional views showing a semiconductor process according to another embodiment of the present invention. First, as shown in FIGS. 1-7, the first gate structure 110 and the second gate structure 120 are formed on the substrate 10. The top of the first gate structure 110 includes a cap layer 118, so that the first gate The vertical height of the pole structure 110 (the same thickness t1 in this embodiment) is higher than the vertical height of the second gate structure 120 (the same thickness t2 in this embodiment). An interlayer dielectric layer 170 is formed on the substrate 10 and covers the first gate structure 110 and the second gate structure 120. A first chemical mechanical polishing process C1 is performed to polish the interlayer dielectric layer 170 to expose the top surface S1 of the cap layer 118. The detailed formation method has been described in the previous embodiment, and therefore will not be described again.

Next, as shown in FIG. 9, an etching process E is performed to remove the interlayer dielectric layer 170 on the second gate structure 120. The etching process E may include a dry etching process or a wet etching process, and the wet etching process may be, for example, an etching process of a hydrofluoric acid-containing etching solution, but the invention is not limited thereto. In this embodiment, if the cap layer 118 is a nitride layer and the interlayer dielectric layer 170 is an oxide layer, the etching process E may include an oxide etching process. In a preferred embodiment, the etching solution of the etching process E can only etch the interlayer dielectric layer 170, thereby not damaging the cap layer 118 of the first gate structure 110 (if another contact hole etch stop layer 160 is covered) A contact structure etch stop layer 160 is not damaged on a gate structure 110. In other words, the etching process E performed by the present invention merely removes the interlayer dielectric layer 170 separately to expose the first gate structure 110 and the second gate structure 120 (or expose the contact hole etch stop layer 160).

Finally, as shown in FIG. 10, a second CMP process C3 is performed to at least polish the first gate structure 110 and the interlayer dielectric layer 170 to remove the cap layer 118. If the contact hole etch stop layer 160 is further removed, the contact hole etch stop layer 160 on the top surfaces S1 and S2 of the first gate structure 110 and the second gate structure 120 is removed. In one embodiment, since the etching process E has removed the interlayer dielectric layer 170 on the second gate structure 120, the second CMP process C3 preferably has a higher polishing rate for the cap layer 118 than The polishing rate of the interlayer dielectric layer 170, that is, the polishing slurry having a high nitride to oxide polishing rate. In this way, the interlayer dielectric layer 170 located between the first gate structure 110 and the second gate structure 120 is not dented by excessive grinding.

Further, in this embodiment, if the contact hole etch stop layer 160 covers the first gate structure 110, the second gate structure 120, and the substrate 10, the second CMP process C3 is first removed. The contact hole on the first gate structure 110 etches the stop layer 160, and then the portion of the first gate structure 110 that is higher than the second gate structure 120 is the cap layer 118, which is grounded by the second chemical mechanical polishing process C3. The cover layer 118 will be completely removed while exposing the top surface S2 of the second gate structure 120. At this time, while the cap layer 118 is removed, the contact hole etch stop layer 160 on the second gate structure 120 is also removed. Moreover, after the cap layer 118 is completely removed, the gate layers 116 and 126 in the first gate structure 110 and the second gate structure 120 are simultaneously exposed. In other embodiments, the heights of the first gate structure and the second gate structure and the relative positions of the internal structures may be different according to the needs of the process and the process. The present invention is not illustrated by the embodiment. The first gate structure 110 and the second gate structure 120 are limited.

In addition, after exposing the gate structures 116 and 126 in the first gate structure 110 and the second gate structure 120, the present invention can continue with other semiconductor processes, such as metal gates.

In summary, the present invention provides a semiconductor process in which a chemical mechanical polishing process has an approximate polishing selectivity ratio for a cap layer and an interlayer dielectric layer, or an etching process, which has a lower removal first. An interlayer dielectric layer remaining on the gate structure of the vertical height to expose the first gate structure and the second gate structure in a flat manner (in more detail, the first gate structure and the first gate structure may be exposed uniformly The gate layer in the second gate structure) does not have the phenomenon of over-etching or over-grinding of the conventional gate structure. Therefore, the semiconductor process of the present invention can improve the electrical quality of the gate structure.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . Base

20, 20a, 20b. . . Metal telluride barrier

60. . . Metal layer

110. . . First gate structure

112, 122. . . The buffer layer

114, 124. . . Gate dielectric layer

116, 126. . . Gate layer

118, 128. . . Cover

119, 129. . . Clearance wall

120. . . Second gate structure

130a, 130b. . . Source/bungee area

140a, 140b. . . Gate channel

150. . . Metal telluride

160. . . Contact hole etch stop layer

170. . . Interlayer dielectric layer

A, B. . . region

C1. . . First chemical mechanical polishing process

C2, C3. . . Second chemical mechanical polishing process

E. . . Etching process

P. . . Photoresist layer

S1, S2. . . Top surface

T1, t2, t3. . . thickness

1-8 are schematic cross-sectional views showing a semiconductor process according to an embodiment of the present invention.

9-10 are schematic cross-sectional views showing a semiconductor process according to an embodiment of the present invention.

10. . . Base

110. . . First gate structure

112, 122. . . The buffer layer

114, 124. . . Gate dielectric layer

116, 126. . . Gate layer

119. . . Clearance wall

120. . . Second gate structure

130a, 130b. . . Source/bungee area

140a, 140b. . . Gate channel

150. . . Metal telluride

160. . . Contact hole etch stop layer

170. . . Interlayer dielectric layer

A, B. . . region

C2. . . Second chemical mechanical polishing process

S2. . . Top surface

Claims (20)

A semiconductor process includes: forming a first gate structure and a second gate structure on a substrate, wherein a top portion of the first gate structure includes a cap layer such that a vertical height of the first gate structure Higher than the vertical height of the second gate structure; forming an interlayer dielectric layer on the substrate and covering the first gate structure and the second gate structure; performing a first chemical mechanical polishing process to polish the interlayer a dielectric layer to expose a top surface of the cap layer; and performing a second CMP process to at least partially polish the first gate structure and the interlayer dielectric layer to expose the second gate structure Top surface. The semiconductor process of claim 1, wherein the cap layer and the interlayer dielectric layer comprise different materials. The semiconductor process of claim 2, wherein the cap layer comprises a nitride layer, the interlayer dielectric layer comprising an oxide layer. The semiconductor process of claim 3, wherein the slurry of the second CMP process comprises an oxygen inhibitor. The semiconductor process of claim 1, wherein the second CMP process polishes the cap layer and the interlayer dielectric layer has a polishing selectivity ratio between 1.2 and 0.8. The semiconductor process of claim 5, wherein the second chemical mechanical polishing process comprises a chemical mechanical polishing process of a first polishing selectivity, wherein the polishing rate of the cap layer and the interlayer dielectric layer is substantially equal . The semiconductor process of claim 1, wherein the second CMP process completely removes the cap layer while exposing the top surface of the second gate structure. The semiconductor process of claim 1, wherein the second CMP process exposes the first gate structure and a gate layer of the second gate structure. The semiconductor process of claim 1, further comprising forming a contact etch stop layer covering the first gate structure, the second gate structure, and the substrate. The semiconductor process of claim 8, wherein the second CMP process removes the cap layer and a portion of the contact hole etch stop layer. A semiconductor process includes: forming a first gate structure and a second gate structure on a substrate, wherein a top portion of the first gate structure includes a cap layer such that a vertical height of the first gate structure Higher than the vertical height of the second gate structure; forming an interlayer dielectric layer on the substrate and covering the first gate structure and the second gate structure; performing a first chemical mechanical polishing process to polish the interlayer a dielectric layer to expose a top surface of the cap layer; performing an etching process to remove the interlayer dielectric layer on the second gate structure; and performing a second chemical mechanical polishing process, at least a grinding portion The first gate structure and the interlayer dielectric layer are used to remove the cap layer. The semiconductor process of claim 11, wherein the cap layer and the interlayer dielectric layer comprise different materials. The semiconductor process of claim 12, wherein the cap layer comprises a nitride layer, the interlayer dielectric layer comprising an oxide layer. The semiconductor process of claim 13, wherein the etching process comprises an oxygen etching process. The semiconductor process of claim 11, wherein the etching process of the etching process etches only the interlayer dielectric layer. The semiconductor process of claim 11, wherein the etching process comprises a dry etching process or a wet etching process. The semiconductor process of claim 16, wherein the wet etching process comprises an etching process of a hydrofluoric acid-containing etching solution. The semiconductor process of claim 11, wherein the second CMP process has a higher polishing rate for the cap layer than for the interlayer dielectric layer. The semiconductor process of claim 11, further comprising forming a contact hole etch stop layer covering the first gate structure, the second gate structure and the substrate, and the second CMP process, shifting In addition to the cap layer and a portion of the contact hole etch stop layer. The semiconductor process of claim 11, wherein the second CMP process exposes one of the first gate structure and the second gate structure.