TWI517161B - Supply voltage generation circuit, and operation method of a supply voltage generation circuit used for a memory array - Google Patents

Description

Power supply voltage generating circuit and power supply voltage generating circuit for memory array Method of operation

The present invention relates to the field of data storage technology, and more particularly to a method of operating a power supply voltage generating circuit and a power supply voltage generating circuit for a memory array.

A non-volatile memory is a type of memory that retains stored data even when it is not powered by an external power source. Since the memory itself does not need to waste power on the memory of the data, it is particularly suitable for use on a portable device.

Non-volatile memory has three modes of operation: read, write, and erase. Among them, the write operation is a so-called program operation. In general, non-volatile memory requires different voltages to perform these three operations. Since the non-volatile memory requires more and more stringent precision for the stylized voltages required to perform the stylized operation, the required stylized voltage must be very accurate.

The present invention provides a power supply voltage generating circuit that is suitable for use in a memory array. This supply voltage generation circuit provides a more accurate supply voltage for use as a stylized voltage.

The present invention further provides an operation corresponding to the above-described power supply voltage generating circuit method.

The present invention further provides a memory in which a power supply voltage is generated as a stylized voltage, and the memory improves the temperature of the component on the transmission path of the stylized voltage, and the variation of the process to the programmed voltage influences.

The present invention provides a power supply voltage generating circuit suitable for use in a memory array wherein the memory array includes a plurality of memory cells. The power voltage generating circuit includes a comparing unit, a voltage level control unit and a voltage stabilizing circuit. The comparing unit is configured to compare an input data of the memory array with an output data to generate a comparison result, wherein the output data is in a memory array and has been subjected to a stylized operation according to the input data. A stored data stored in the memory unit, and the comparison result shows that the output data is different from the number of bits of the input data. The voltage level control unit is configured to generate a control signal according to the comparison result. The voltage stabilizing circuit is configured to provide a power supply voltage required by the memory array, and change the power supply voltage according to the control signal.

The present invention further provides an operational method for a power supply voltage generating circuit of a memory array. The memory array includes a plurality of memory units, and the memory array is electrically coupled to a decoder. The decoder includes an input end and a plurality of output ends, and each output end is electrically coupled to a part of the memory unit. The operation method includes the following steps: providing a power voltage to an input end of the decoder according to one of the input data of the memory array; comparing the input data with an output data of the memory array to generate a comparison result The output data is a stored data stored in a plurality of memory cells of the memory array that have been subjected to a stylized operation according to the input data, and the comparison result shows how much of the output data is relative to the input data. The information of one bit is different; and when the comparison shows at least one bit of data When it is different, the power supply voltage is changed according to the comparison result.

The invention further provides a memory comprising a memory array, a decoder and a voltage stabilizing circuit. The memory array includes a plurality of source lines and a plurality of memory cells, and each of the source lines is electrically coupled to a portion of the memory cells. The decoder includes an input end and a plurality of output ends, and the output ends of the decoder are electrically coupled to the source lines respectively. The voltage stabilizing circuit is configured to provide a power supply voltage to the input end of the decoder, and the voltage stabilizing circuit is electrically coupled to the output ends of the decoder to output signals according to one of the output ends of the decoder. A control signal is correspondingly generated to generate a feedback signal, and the size of the power supply voltage is changed according to the feedback signal.

In the method for operating the power supply voltage generating circuit and the power supply voltage generating circuit of the present invention, an input data of the memory array is first compared with an output data to generate a comparison result, and the output data is in the memory array. The input data carries a stored data stored in a plurality of memory units of a stylized operation, and the comparison result indicates that the output data has different data relative to the input data. Therefore, when the comparison result shows that the data of at least one bit is different, the magnitude of the power supply voltage can be changed according to the comparison result. Accordingly, the method of operating the power supply voltage generating circuit and the power supply voltage generating circuit of the present invention can provide a relatively accurate power supply voltage for use as a stylized voltage.

Further, in the memory of the present invention, the power supply voltage generated by the voltage stabilizing circuit can be used as a stylized voltage. The voltage-stabilizing circuit is electrically coupled to the plurality of outputs of the decoder, and the voltage-stabilizing circuit can generate a feedback signal according to the signal outputted by one of the output ends of the decoder and a control signal. And further changing the magnitude of the power supply voltage according to the feedback signal, so the memory improves the temperature and process variation of the component on the transmission path of the stylized voltage. The effect of the voltage.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1 is a schematic diagram of a memory device in accordance with an embodiment of the invention, showing only the circuit architecture associated with the present invention in memory. Referring to FIG. 1 , the memory 100 includes a data input/output interface 110 , a power voltage generating circuit 120 , a power voltage switching switch 160 , a decoder 170 , and a memory array 180 . The memory array 180 includes a plurality of source lines (as indicated by the numeral 181) and a plurality of memory cells (shown by the numeral 182), and each of the source lines 181 is electrically coupled to the memory units 182. Part of it. The decoder 170 includes an input 171 and a plurality of outputs (as indicated by reference numeral 172). In this example, the output terminals 172 of the decoder 170 are electrically coupled to the source lines 181 of the memory array 180, respectively. As can be seen from the above description, the decoder 170 is a source line decoder.

The power supply voltage switching switch 160 is electrically coupled between the output end of the power supply voltage generating circuit 120 and the input end 171 of the decoder 170, and is configured to receive the power supply voltage PV1 and the preset voltage PV2, and then select the output power according to the control command CM. The voltage PV1 or the preset voltage PV2 is input to the input terminal 171 of the decoder 170. In this example, the supply voltage PV1 is used as a stylized voltage, and the preset voltage PV2 is used, for example, as a read voltage.

The power supply voltage generating circuit 120 includes a comparing unit 130, a voltage level control unit 140, and a voltage stabilizing circuit 150. The comparing unit 130 is configured to compare an input data of the memory array 180 with an output data to generate a comparison result CR. The above output data is stored in the memory array 180 according to the above input data. A stored data stored in the plurality of memory units 182 of a stylized operation, and the comparison result CR indicates that the output data is different from the number of bits of the input data. In addition, the voltage level control unit 140 is configured to generate the control signal CS according to the comparison result CR. The voltage stabilizing circuit 150 is configured to provide a power supply voltage PV1 required by the memory array 180, and change the magnitude of the power supply voltage PV1 according to the control signal CS.

In addition, in order to obtain the input data and the output data, the comparison unit 130 is further electrically coupled to the data input/output interface 110 to receive the input data and the output data transmitted by the data input/output interface 110. The data input/output interface 110 is also used to latch the input data. In this example, the data input/output interface 110 further includes an input data transmission unit 112 and an output data transmission unit 114, wherein the input data transmission unit 112 is configured to transmit and latch the input data, and the output data transmission unit 114 To transmit the above output data.

An actual operation mode of one of the power supply voltage generating circuits 120 will be described below, and an example of the stylization operation of the four memory cells 182 will be described. Please continue to refer to Figure 1. The power supply voltage generating circuit 120 may first supply the power supply voltage PV1 according to one of the input data of the memory array 180 to transmit the power supply voltage PV1 as a stylized voltage to the input terminal 171 of the decoder 170. Therefore, the four memory cells 182 in the memory array 180 can perform a stylization operation according to the size of the stylized voltage at this time, thereby storing one bit of data respectively. Then, the memory 100 can transfer a stored data (including four-bit data) stored in the four memory units 182 that have been subjected to a stylization operation according to the input data to the data input/output. The interface 110 outputs data as one of the memory arrays 180.

Therefore, the power supply voltage generating circuit 120 can be accessed from the data input/output interface. 110 obtains the previously latched input data and the output data transmitted to the data input/output interface 110, and compares the obtained input data with the output data to generate a comparison result CR. When the comparison result CR indicates that the data of the output data is different from the input data by at least one bit, the power supply voltage generating circuit 120 changes the magnitude of the power supply voltage PV1 according to the comparison result CR. This is because the stylized voltage levels required for the four or fewer (excluding four) memory cells 182 are different from the stylized voltage levels required for the four memory cells 182.

Assuming that the comparison result CR shows that the data of the output data has two bits relative to the input data, the power supply voltage generating circuit 120 lowers the power supply voltage PV1 to lower the power supply voltage PV1. The size can match the stylized voltage required by the two memory cells 182. Therefore, the two memory cells 182 that are incorrectly stored can perform a stylization operation again according to the size of the stylized voltage at this time to store the correct data. In other words, the more the bit data is different, the larger the power supply voltage PV1; and the less the bit data is different, the smaller the power supply voltage PV1. Of course, the comparison operation of the above input data and output data can be repeated until the input data and the output data match. Further, the voltage level control unit 140 is not limited to receiving the comparison result CR generated by the comparison unit 130, and may also directly receive the comparison result CR' from the outside of the memory 100. That is, the comparison result CR' is from the outside of the memory 100 to which the memory array 180 belongs.

As apparent from the above description, the power supply voltage generating circuit 120 can dynamically adjust the magnitude of the power supply voltage PV1 in accordance with the magnitude of the load (i.e., the number of memory cells 182 to be driven). Therefore, the power supply voltage generating circuit 120 can provide a more accurate power supply voltage PV1 for use as a stylized voltage.

The actual design of each component in the power supply voltage generating circuit 120 will be further explained below. The comparing unit 130 in FIG. 1 can compare the input data and the output data by using a digital data comparison method, an analog current comparison method or an analog voltage comparison method. In the digital data comparison manner, the comparison unit 130 may adopt the design shown in FIG. 2.

2 is a circuit diagram of one of the comparison units of FIG. 1. Referring to FIG. 2, the comparison unit 130 includes a plurality of reverse gates (as indicated by the numeral 132), a plurality of inverse gates (as indicated by the numeral 134), and a plurality of D-type flip-flops (as indicated by the numeral 136). The inputs of the reverse gates 132 are electrically coupled to each other and are used to receive input data DIN[0:N] of the memory array 180, where N is a natural number. One of the inputs of each of the anti-gates 134 is configured to receive an output signal of one of the anti-gates 132, and the other input of each of the anti-gates 134 is electrically coupled to the other input of the other of the anti-gates 134. Connected and used to receive the output data DOUT[0:N] of the memory array 180.

Each D-type flip-flop 136 has a data input terminal D, a clock signal input terminal CLK, a reset signal input terminal R and a data output terminal Q. The data input terminal D of each D-type flip-flop 136 is configured to receive an output signal of one of the anti-gates 134. The clock signal input terminals CLK of the D-type flip-flops 136 are used to receive a clock signal CK, and the pulse signal CK is generated when the input data and the output data need to be compared. . In addition, the reset signal input terminals R of the D-type flip-flops 136 are used to receive a reset signal RS. The data output terminal Q of each D-type flip-flop 136 is used to provide an output signal (as shown by signals Q1 to Q4), and the output signals of the D-type flip-flops 136 are used to form a comparison result CR. As can be seen from FIG. 2, the comparison unit 130 is presented in a multi-stage circuit. Each stage of the circuit can include a reverse gate 132, a reverse gate 134 and a D-type flip-flop 136.

In addition, the voltage level control unit 140 in FIG. 1 may store a control. table. This comparison table records the correspondence between the number of memory cells 182 to be programmed and the magnitude of the power supply voltage PV1 to be supplied. In this way, the voltage level control unit 140 can search the comparison table according to the comparison result CR output by the comparison unit 130 to generate the control signal CS according to a search result.

As for the voltage stabilizing circuit 150 of FIG. 1, it can be implemented by a Low Dropout Regulator. FIG. 3 is one of the circuit architectures of the voltage regulator circuit of FIG. 1. Referring to FIG. 3, the voltage stabilizing circuit 150 includes a P-type transistor 151, a voltage dividing circuit 152, a plurality of switches (as indicated by reference numeral 153), a switch control circuit 154, and a voltage comparator 155. One source/drain of the P-type transistor 151 is electrically coupled to operate the power supply VDD, and the other source/drain is used to supply the power supply voltage PV1. The voltage divider circuit 152 has a plurality of resistors in series (as indicated by reference numeral 152-1). One end of the voltage dividing circuit 152 is electrically coupled to another source/drain of the P-type transistor 151, and the other end of the voltage dividing circuit 152 is electrically coupled to a reference voltage, for example, A ground voltage GND.

In addition, each switch 153 has a first end (as indicated by reference numeral 153-1), a second end (as indicated by reference numeral 153-2) and a control end (as indicated by reference numeral 153-3). The first end 153-1 and the second end 153-2 of each switch 153 are electrically coupled to the two ends of one of the resistors 152-1 of the voltage dividing circuit 152, and each switch 153 is based on its control end 153- 3 received signals to determine whether to turn on. The switch control circuit 154 is electrically coupled to the control terminals 153-3 of the switches 153, and is configured to determine which switches 153 to be turned on according to the control signal CS output by the voltage level control unit 140. As for the voltage comparator 155, it has a positive input terminal (indicated by a + sign), a negative input terminal (indicated by a - sign), and an output terminal. The positive input terminal of the voltage comparator 155 is configured to receive another reference voltage VREF, and the negative input terminal of the voltage comparator 155 is electrically coupled to the mutual electrical coupling of the two resistors 152-1 of the voltage dividing circuit 152. The mutual electrical coupling is used to provide a feedback signal FB, and The output of the voltage comparator 155 is electrically coupled to the gate of the P-type transistor 151.

In addition, in order to improve the influence of the temperature of the components on the transmission path of the stylized voltage and the variation of the process on the stylized voltage, the voltage regulator circuit in the power supply voltage generating circuit can adopt different feedback methods, for example, as shown in FIG. 4 or 6 is designed to be designed. Please refer to FIG. 4, which is a schematic diagram of a memory according to another embodiment of the present invention, and only shows the circuit architecture related to the present invention in the memory. The memory 400 differs from the memory 100 in that the voltage regulator circuit 450 in the power voltage generating circuit 420 of the memory 400 is more electrically coupled to the input terminal 171 included in the decoder 170, and is stable. The voltage circuit 450 is further configured to generate a feedback signal according to the signal received by the input terminal 171 and the control signal CS, and then change the magnitude of the power supply voltage PV1 according to the feedback signal.

FIG. 5 depicts one of the circuit architectures of the voltage regulator circuit of FIG. Referring to FIG. 5, the voltage stabilizing circuit 450 includes a P-type transistor 451, a voltage dividing circuit 452, a plurality of switches (as indicated by reference numeral 453), a switch control circuit 454, and a voltage comparator 455. One of the source/drain electrodes of the P-type transistor 451 is electrically coupled to operate the power supply VDD, and the other source/drain is used to supply the power supply voltage PV1. Voltage divider circuit 452 has a plurality of resistors in series (as indicated by reference 452-1). One end of the voltage dividing circuit 452 is electrically coupled to the input end 171 of the decoder 170, and the other end of the voltage dividing circuit 452 is electrically coupled to a reference voltage, such as a ground voltage GND.

In addition, each switch 453 has a first end (as indicated by the reference 453-1), a second end (as indicated by the reference 453-2) and a control end (as indicated by the reference 453-3), and each switch 453 The first end 453-1 and the second end 453-2 are electrically coupled to the two ends of one of the resistors 452-1 of the voltage dividing circuit 452, respectively. The switch control circuit 454 is electrically coupled to the control terminals 453-3 of the switches 453, and is configured to determine which switches to be turned on according to the control signal CS output by the voltage level control unit 140. 453. As for the voltage comparator 455, it has a positive input terminal (indicated by a + sign), a negative input terminal (indicated by a - sign), and an output terminal. The positive input terminal of the voltage comparator 455 is configured to receive another reference voltage VREF, and the negative input terminal of the voltage comparator 455 is electrically coupled to the mutual electrical coupling of the two resistors 452-1 of the voltage dividing circuit 452. The electrical coupling is used to provide the aforementioned feedback signal (indicated by FB), and the output of the voltage comparator 455 is electrically coupled to the gate of the P-type transistor 451.

FIG. 6 is a schematic diagram of a memory according to still another embodiment of the present invention, and only shows a circuit architecture related to the present invention in a memory. The difference between the memory 600 and the memory 100 is that the voltage regulator circuit 650 in the power voltage generating circuit 620 of the memory 600 is more electrically coupled to the plurality of outputs 172 included in the decoder 170. Each of the output terminals 172 is configured to generate a feedback signal according to the signal outputted by one of the output terminals 172 and the control signal CS, and then change the magnitude of the power supply voltage PV1 according to the feedback signal.

FIG. 7 is a circuit diagram of one of the voltage regulator circuits of FIG. Referring to FIG. 7, the voltage stabilizing circuit 650 includes a P-type transistor 651, a voltage dividing circuit 652, a plurality of switches (as indicated by reference numeral 653), a switch control circuit 654, a voltage comparator 655, and a selection circuit 656. One of the source/drain electrodes of the P-type transistor 651 is electrically coupled to operate the power supply VDD, and the other source/drain is used to supply the power supply voltage PV1. Selection circuit 656 has a plurality of inputs (as indicated by reference 656-1) and an output 656-2. The input terminals 656-1 of the selection circuit 656 are electrically coupled to the output terminals 172 of the decoder 170, respectively, and the selection circuit 656 is configured to select one of the input terminals 656-1 according to the selection signal SL. The signal received by the selected input terminal 656-1 is output from the output terminal 656-2 of the selection circuit 656.

In addition, the voltage dividing circuit 652 has a plurality of resistors connected in series (eg, 652-1) Shown). One end of the voltage dividing circuit 652 is electrically coupled to the output end 656-2 of the selecting circuit 656, and the other end of the voltage dividing circuit 656 is electrically coupled to a reference voltage, such as a ground voltage. GND. Each switch 653 has a first end (as indicated by reference 653-1), a second end (as indicated by reference 653-2) and a control end (as indicated by reference 653-3), and each switch 653 The one end 653-1 and the second end 653-2 are electrically coupled to the two ends of one of the resistors 652-1 of the voltage dividing circuit 652, respectively. The switch control circuit 654 is electrically coupled to the control terminals 653-3 of the switches 653 and configured to determine which switches 653 to be turned on according to the control signal CS.

As for the voltage comparator 655, it has a positive input terminal (indicated by a + sign), a negative input terminal (indicated by a - sign), and an output terminal. The positive input terminal of the voltage comparator 655 is configured to receive another reference voltage VREF, and the negative input terminal of the voltage comparator 655 is electrically coupled to the mutual electrical coupling of the two resistors 652-1 of the voltage dividing circuit 652. The electrical coupling is used to provide the aforementioned feedback signal (indicated by FB), and the output of the voltage comparator 655 is electrically coupled to the gate of the P-type transistor 651.

According to the teachings of the above embodiments, those skilled in the art can generalize the basic operation modes of the foregoing power supply voltage generating circuits, and the first step is as shown in FIG. FIG. 8 is a flow chart showing an operation method of a power supply voltage generating circuit for a memory array in accordance with an embodiment of the present invention. The memory array includes a plurality of memory units, and the memory array is electrically coupled to a decoder. The decoder includes an input end and a plurality of output ends, and each of the output ends is electrically coupled to a portion of the memory unit. The method includes the following steps: providing a power voltage to the input end of the decoder according to one of the input data of the memory array (as shown in step S802); comparing the input data with the output data of one of the memory arrays, Generating a comparison result, wherein the output data is a plurality of memory cells in the memory array that have been subjected to a stylization operation according to the input data a stored data stored, and the comparison result shows that the output data is different from the number of bits of the input data (as shown in step S804); and when the comparison result shows at least one bit When the data of the meta is different, the magnitude of the power supply voltage is changed according to the comparison result (as shown in step S806).

In summary, in the operating method of the power supply voltage generating circuit and the power supply voltage generating circuit of the present invention, an input data of the memory array is first compared with an output data to generate a comparison result, and the output data is a stored data stored in a plurality of memory cells of the memory array that have been subjected to a stylized operation according to the input data, and the comparison result shows how many bits of the output data are relative to the input data. It is different. Therefore, when the comparison result shows that the data of at least one bit is different, the magnitude of the power supply voltage can be changed according to the comparison result. Accordingly, the method of operating the power supply voltage generating circuit and the power supply voltage generating circuit of the present invention can provide a relatively accurate power supply voltage for use as a stylized voltage.

Further, in the memory of the present invention, the power supply voltage generated by the voltage stabilizing circuit can be used as a stylized voltage. The voltage-stabilizing circuit is electrically coupled to the plurality of outputs of the decoder, and the voltage-stabilizing circuit can generate a feedback signal according to the signal outputted by one of the output ends of the decoder and a control signal. Then, according to the feedback signal, the magnitude of the power supply voltage is changed. Therefore, the memory improves the influence of the temperature of the component on the transmission path of the stylized voltage and the variation of the process on the stylized voltage.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100, 400, 600‧‧‧ memory

110‧‧‧Data input/output interface

112‧‧‧Input data transmission unit

114‧‧‧Output data transmission unit

120, 420, 620‧‧‧ power supply voltage generating circuit

130‧‧‧Comparative unit

132‧‧‧Backgate

134‧‧‧Anti-gate

136‧‧‧D type flip-flop

140‧‧‧Voltage level control unit

150, 450, 650‧‧‧ voltage regulator circuit

151, 451, 651‧‧‧P type transistor

152, 452, 652‧‧ ‧ voltage divider circuit

152-1, 452-1, 652-1‧‧‧ resistance

153, 453, 653‧ ‧ switch

153-1, 453-1, 653-1‧‧‧ first end

153-2, 453-2, 653-2‧‧‧ second end

153-3, 453-3, 653-3‧‧‧ control terminal

154, 454, 654‧‧ ‧ switch control circuit

155, 455, 655‧‧‧ voltage comparator

160‧‧‧Power supply voltage switch

170‧‧‧Decoder

171,656-1‧‧‧ input

172, 656-2‧‧‧ output

180‧‧‧ memory array

181‧‧‧ source line

182‧‧‧ memory unit

656‧‧‧Selection circuit

CK‧‧‧ clock signal

CLK‧‧‧ clock signal input

CM‧‧‧ control order

CR‧‧‧ comparison results

CR’‧‧‧ comparison results

CS‧‧‧Control signal

D‧‧‧ data input

DIN[0:N]‧‧‧ Input data

DOUT[0:N]‧‧‧Output data

FB‧‧‧ feedback signal

GND‧‧‧ Grounding voltage

PV1‧‧‧Power supply voltage

PV2‧‧‧Preset voltage

Q‧‧‧ data output

Q1~Q4‧‧‧ output signal

R‧‧‧Reset signal input

RS‧‧‧Reset signal

SL‧‧‧Select signal

VDD‧‧‧Operating power supply

VREF‧‧‧reference voltage

S802~S806‧‧‧Steps

+‧‧‧正Input

-‧‧‧negative input

1 is a schematic diagram of a memory array in accordance with an embodiment of the present invention.

2 is a circuit diagram of one of the comparison units of FIG. 1.

FIG. 3 is one of the circuit architectures of the voltage regulator circuit of FIG. 1.

4 is a schematic diagram of a memory array in accordance with another embodiment of the present invention.

FIG. 5 depicts one of the circuit architectures of the voltage regulator circuit of FIG.

6 is a schematic diagram of a memory array in accordance with still another embodiment of the present invention.

Figure 7 depicts one of the circuit architectures of the voltage regulator circuit of Figure 6.

FIG. 8 is a flow chart showing an operation method of a power supply voltage generating circuit for a memory array in accordance with an embodiment of the present invention.

S802~S806‧‧‧Steps

Claims (17)

A power supply voltage generating circuit is applicable to a memory array, wherein the memory array includes a plurality of memory cells, and the power voltage generating circuit includes: a comparing unit for comparing an input data of the memory array with an output data For generating a comparison result, wherein the output data is a stored data stored in a plurality of memory cells of the memory array that have been subjected to a program operation according to the input data, and the comparison result indicates that the output data is relatively How many bits of data are different in the input data; a voltage level control unit for generating a control signal according to the comparison result; and a voltage stabilizing circuit for providing one of the required memory arrays The power supply voltage changes the size of the power supply voltage according to the control signal. The power supply voltage generating circuit of claim 1, wherein the comparing unit compares the input data and the output data by a digital data comparison method, an analog current comparison method or an analog voltage comparison method. . The power supply voltage generating circuit of claim 2, wherein the comparison result is from outside the memory to which the memory array belongs. The power supply voltage generating circuit of claim 1, wherein the voltage stabilizing circuit comprises: a P-type transistor having a first source/drain, a second source/drain, and a gate, The first source/drain is electrically coupled to an operating power source, and the second source/drain is configured to provide the power voltage; a voltage dividing circuit having a plurality of resistors connected in series, one end of the voltage dividing circuit is electrically coupled to the second source/drain, and the other end of the voltage dividing circuit is electrically coupled a first reference voltage; a plurality of switches, each switch having a first end, a second end, and a control end, and the first end and the second end of each switch are electrically coupled to the branch a second end of one of the resistors of the voltage circuit; a switch control circuit electrically coupled to the control terminals of the switches, and configured to determine which switches to be turned on according to the control signal; and a voltage comparator having a positive input terminal, a negative input terminal and an output terminal, the positive input terminal is configured to receive a second reference voltage, and the negative input terminal is electrically coupled to the mutual electrical property of the two resistors of the voltage dividing circuit The coupling is electrically coupled to the gate of the voltage comparator. The power supply voltage generating circuit of claim 1, wherein the voltage stabilizing circuit is further electrically coupled to an input end of the decoder of the memory array, and configured to receive the signal according to the input end. The control signal generates a feedback signal corresponding to the size of the power supply voltage according to the feedback signal. The power supply voltage generating circuit of claim 5, wherein the decoder comprises a source line decoder. The power supply voltage generating circuit of claim 5, wherein the voltage stabilizing circuit comprises: a P-type transistor having a first source/drain, a second source/drain and a gate, The first source/drain is electrically coupled to an operating power source, and the second source/ a drain voltage is used to provide the power supply voltage; a voltage dividing circuit has a plurality of resistors connected in series, and one end of the voltage dividing circuit is electrically coupled to the input end of the decoder, and the voltage dividing circuit The other end is electrically coupled to a first reference voltage; the plurality of switches each having a first end, a second end, and a control end, and the first end of the switch and the first end The two ends are respectively electrically coupled to the two ends of one of the resistors of the voltage dividing circuit; a switch control circuit is electrically coupled to the control terminals of the switches, and is configured to determine which switches to be turned on according to the control signal And a voltage comparator having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is configured to receive a second reference voltage, and the negative input terminal is electrically coupled to the voltage dividing circuit The two electrical resistors are electrically coupled to each other, and the electrical coupling is electrically coupled to the feedback signal, and the output of the voltage comparator is electrically coupled to the gate. The power supply voltage generating circuit of claim 1, wherein the voltage stabilizing circuit is electrically coupled to the plurality of outputs of the decoder of the memory array, and is configured to output according to one of the outputs The signal corresponding to the control signal generates a feedback signal, and the size of the power supply voltage is changed according to the feedback signal. The power supply voltage generating circuit of claim 8, wherein the decoder comprises a source line decoder. The power supply voltage generating circuit of claim 8, wherein the voltage stabilizing circuit comprises: a P-type transistor having a first source/drain, a second source/drain and a gate, the first source/drain for electrically coupling an operating power source, and the second source/ a drain circuit for providing the power supply voltage; a selection circuit having a plurality of input terminals and an output terminal, wherein the input terminals of the selection circuit are electrically coupled to the output terminals of the decoder, respectively, and the selection circuit is used Selecting one of the input terminals according to a selection signal to output the signal received by the input terminal from the output end of the selection circuit; a voltage dividing circuit having a plurality of resistors connected in series; One end of the voltage dividing circuit is electrically coupled to the output end of the selection circuit, and the other end of the voltage dividing circuit is electrically coupled to a first reference voltage; The switch has a first end, a second end and a control end, and the first end and the second end of each switch are respectively electrically coupled to the two ends of one of the resistors of the voltage dividing circuit; a control circuit electrically coupled to the control terminals of the switches and used to control the signals according to the control signals Which switches are to be turned on; and a voltage comparator having a positive input terminal, a negative input terminal and an output terminal, the positive input terminal for receiving a second reference voltage, the negative input terminal being electrically coupled to The two resistors of the voltage dividing circuit are electrically coupled to each other, and the electrical coupling is electrically coupled to provide the feedback signal, and the output of the voltage comparator is electrically coupled to the Gate. The power supply voltage generating circuit of claim 1, wherein the comparing unit is further electrically coupled to a data input/output interface for receiving the input data and the output data transmitted by the data input/output interface, The data input/output interface is further used to latch the input data. The power supply voltage generating circuit of claim 11, wherein the data input/output interface further comprises an input data transmission unit and an output data transmission unit, wherein the input data transmission unit is configured to transmit and latch the input data. And the output data transmission unit is configured to transmit the output data. The power supply voltage generating circuit of claim 1, wherein the voltage stabilizing circuit is implemented by a low dropout voltage regulator. The power supply voltage generating circuit of claim 1, wherein the voltage level control unit further stores a lookup table for recording the number of memory cells to be programmed and the power supply voltage to be supplied. Corresponding relationship between the sizes, and the voltage level control unit searches the comparison table according to the comparison result to generate the control signal according to a search result. An operation method for a power supply voltage generating circuit of a memory array, wherein the memory array includes a plurality of memory units, the memory array is electrically coupled to a decoder, and the decoder includes an input end and a plurality of output ends. And each output end is electrically coupled to a part of the memory units, the method comprising: providing a power voltage to the input end of the decoder according to one input data of the memory array; Comparing the output data of one of the memory arrays to generate a comparison result, wherein the output data is a stored data stored in the plurality of memory cells of the memory array that have been subjected to a program operation according to the input data, and the comparison is performed The result shows that the output data is different from the number of bits of the input data; and when the comparison shows that the data of at least one bit is different Then, the magnitude of the power supply voltage is changed according to the comparison result. The method of operation of claim 15, wherein the decoder comprises a source line decoder. For example, in the operation method described in claim 15, the input data and the output data are compared by a digital data comparison method, an analog current comparison method or an analog voltage comparison method.