JP2012244577A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that allows the performance test of a ZQ calibration circuit without preparing an external resistive element for the performance test.SOLUTION: A semiconductor device comprises: an external terminal; a calibration circuit that is connected to the external terminal and performs calibration using an external resistive element connected to the external terminal; an internal resistive element; and a switch that is provided between the internal resistive element and the external terminal. The switch is in conduction state, and then the internal resistive element is electrically connected to a ZQ terminal in the state that the external resistive element is not connected to the external terminal. Consequently, the calibration can be performed using the internal resistive element instead of the external resistive element.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a ZQ calibration circuit.

  The characteristics of electric / electronic elements included in a semiconductor device depend on the manufacturing process, power supply voltage, ambient temperature, and the like. If the impedance of the output driver of the semiconductor device is an inappropriate value, the signal output from the output driver to the outside via the output terminal is partially reflected at the output terminal and distorted in the waveform of the signal output subsequently. Give rise to As a result, high-speed transmission of signals output from the semiconductor device to the outside becomes impossible.

  Therefore, in a related semiconductor device, an external terminal called a ZQ terminal and an impedance adjustment circuit called a ZQ calibration circuit connected thereto are provided, and an external resistance element having a predetermined resistance value connected to the ZQ terminal is used. Thus, the impedance of the output driver can be adjusted (see, for example, Patent Document 1).

JP 2008-218655

  The related semiconductor device is configured such that when mounted on a circuit board or the like, a resistance element mounted on the circuit board is connected to the ZQ terminal. Therefore, there is a problem that an external resistance element for an operation test must be prepared in order to perform a confirmation test of the operation of the ZQ calibration circuit at the time of manufacture.

  An object of the present invention is to provide a semiconductor device capable of performing an operation test of a ZQ calibration circuit without preparing an external resistance element for an operation test.

  A semiconductor device according to an embodiment of the present invention includes an external terminal, a calibration circuit that is connected to the external terminal and performs calibration using an external resistance element connected to the external terminal, and an internal resistance element And a switch provided between the internal resistance element and the external terminal, and when the external resistance element is not connected to the external terminal, the switch is turned on to switch the internal resistance element The calibration is performed by using the internal resistance element instead of the external resistance element by being electrically connected to the ZQ terminal.

  According to the present invention, the semiconductor device that performs calibration using the external resistance element connected to the external terminal is provided with the internal resistance element that is connected to the external terminal via the switch. Even if the resistance element is not connected, calibration can be performed using the internal resistance element.

1 is a block diagram showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a block diagram showing an internal configuration of a ZQ calibration circuit included in the semiconductor device of FIG. 1. FIG. 3 is a circuit diagram showing a detailed configuration of a part of an internal resistance circuit and a first pull-up circuit included in the ZQ calibration circuit of FIG. 2. FIG. 6 is a circuit diagram showing a detailed configuration of part of a ZQ calibration circuit included in a semiconductor device according to a second embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a schematic configuration of a semiconductor device according to the first embodiment of the present invention. Here, a DRAM (Dynamic Random Access Memory) is taken as an example of the semiconductor device, but the present invention is applicable to all semiconductor devices having a calibration circuit for adjusting the impedance of the output driver. Semiconductor devices to which the present invention is applicable include, for example, SRAM (Static RAM), PRAM (Phase change type RAM), and flash memory.

  The semiconductor device 10 in FIG. 1 includes a plurality of external connection terminals. These external connection terminals include, for example, power supply terminals (VDD, VSS), clock terminals (CK, / CK), command terminals (/ RAS, / CAS, / WE), address terminals (ADD), data input / output terminals ( DQ) and ZQ terminal (ZQ).

  Further, the semiconductor device 10 includes an internal voltage generation circuit 11, a clock input circuit 12, a command input circuit 13, an address input circuit 14, a command decoder 15, an address latch circuit 16, a memory array 17, a column decoder 18, a row decoder 19, An output circuit 20, a test control circuit 21, and a ZQ calibration circuit 22 are included.

  The internal voltage generation circuit 11 generates various internal voltages such as a boosted voltage VODPP, a peripheral circuit internal voltage VPERI, and the like from an external power supply voltage supplied to power supply terminals (VDD, VSS). The generated internal voltage is supplied to each unit according to the voltage level.

  The clock input circuit 12 generates an internal clock from an external clock supplied to the clock terminals (CK, / CK) and supplies it to each unit.

  The command input circuit 13 receives an external command signal supplied to the command terminals (/ RAS, / CAS, / WE), generates an internal command signal, and outputs it to the command decoder 15.

  The address input circuit 14 receives an external address signal supplied to the address terminal (ADD), generates an internal address signal, and outputs it to the address latch circuit 16.

  The command decoder 15 decodes the internal command signal from the command input circuit and supplies the decoded command to each unit.

  The address latch circuit 16 outputs an internal address signal from the address input circuit 14 or an internally generated address signal generated as necessary to the column decoder 18, the row decoder 19, and the test control circuit 21.

  The memory array 17 has a large number of memory cells (not shown) arranged in an array. These memory cells are arranged so as to correspond to intersections between a plurality of bit lines formed along a predetermined direction and a plurality of word lines formed along a direction intersecting them. Each memory cell is connected to one bit line and one word line.

  The column decoder 18 selects a bit line based on the command from the command decoder 15 and the address signal from the address latch circuit 16.

  Similarly, the row decoder 19 selects a word line based on a command from the command decoder 15 and an address signal from the address latch circuit 16.

  Data is written to or read from one or more memory cells connected to the bit line selected by the column decoder 18 and the word line selected by the row decoder.

  The input / output circuit 20 supplies write data input from the outside to the DQ terminal to the memory array 17. Further, the input / output circuit 20 outputs read data read from the memory array 17 to the DQ terminal. The input / output circuit 20 includes an output driver that outputs read data to the DQ terminal. The impedance of the output driver is adjusted by calibration by the ZQ calibration circuit 22 as will be described later.

  The test control circuit 21 generates control signals for performing various tests based on the command from the command decoder 15 and the address signal from the address latch circuit 16. Since the present invention particularly relates to the ZQ calibration circuit 22, only the control signal to the ZQ calibration circuit 22 is shown in FIG. However, the test control circuit 21 supplies a control signal corresponding to the test content to each unit.

  The ZQ calibration circuit 22 performs ZQ calibration according to the command from the command decoder 15 and the control signal from the test control circuit 21. ZQ calibration refers to impedance adjustment of an output driver in the input / output circuit 20. The internal configuration and operation of the ZQ calibration circuit 22 will be described in detail later.

  The normal operation of the semiconductor device 10 is the same as that of a known semiconductor device. That is, the write data input to the data input / output terminal is written to the memory array 17 according to the external command signal and the external address signal. Data read from the memory array 17 is output to the data input / output terminal in response to the external command signal and the external address signal. In addition, a refresh operation and the like necessary for normally performing these operations are performed in the same manner as a known semiconductor device.

  Next, the ZQ calibration circuit 22 will be described in detail.

  The ZQ calibration circuit 22 is configured as shown in FIG. 2, for example. That is, the ZQ calibration circuit 22 includes a reference voltage generator 221, first and second comparators 222 and 223, first and second counters 224 and 225, and first and second pull-up circuits. 226, 227, a pull-down circuit 228, and an internal resistance circuit 229.

  The reference voltage generator 221 generates a voltage that is ½ of the high-potential-side internal power supply voltage VDDCA for the ZQ calibration circuit 22 as a reference voltage, and is applied to one input terminal of each of the first and second comparators. Supply.

  The first comparator 222 compares the reference voltage from the reference voltage generator 221 with the voltage appearing at the ZQ terminal, and outputs the comparison result to the first counter.

  The second comparator 223 compares the reference voltage from the reference voltage generator 221 with the voltage appearing at the connection point N between the second pull-up circuit 227 and the pull-down circuit 228, and compares the comparison result with the second counter. Output to.

  The first counter 224 performs a count-up or count-down operation based on the comparison result from the first comparator 222, and the second counter 225 performs a count-up or count-down operation based on the comparison result from the second comparator 223, respectively. . The count value of the first counter 224 is supplied to the first and second pull-up circuits 226 and 227 and also to the input / output circuit. The count value of the second counter 225 is supplied to the pull-down circuit 228 and also to the input / output circuit 20.

  The first and second pull-up circuits 226 and 227 are configured the same as the pull-up circuit of the output driver included in the input / output circuit 20, and the pull-down circuit 228 is configured the same as the pull-down circuit of the output driver.

  Each of the first pull-up circuit 226 and the second pull-up circuit includes a plurality of P-channel transistors (hereinafter referred to as PTR) connected in parallel between the internal power supply voltage VDDCA and the ZQ terminal (see FIG. 3). These PTRs may be, for example, P-channel MOS (Metal Oxide Semiconductor) transistors.

  In each of the first pull-up circuit 226 and the second pull-up circuit, the plurality of PTRs are turned on / off according to the count value of the first counter 224 (PUC [1] to [n] in FIG. 3). Be controlled. That is, in each of the first and second pull-up circuits 226 and 227, the number of PTRs corresponding to the count value of the first counter 224 among a plurality of PTRs is turned on. The voltage appearing at the ZQ terminal varies depending on the number of PTRs that are turned on in the first pull-up circuit 226. The first pull-up circuit 226 is controlled so that the voltage appearing at the ZQ terminal becomes equal to the reference voltage from the reference voltage generator 221. Further, the second pull-up circuit 227 is controlled so as to be in the same state as the first pull-up circuit 226.

  The pull-down circuit 228 includes a plurality of N-channel transistors (hereinafter referred to as “N-channel transistors”) connected in parallel between the connection point N with the second pull-up circuit and the low-potential side internal power supply voltage (or external power supply voltage VSS (ground potential)). , NTR). These NTRs may be, for example, P-channel MOS (Metal Oxide Semiconductor) transistors.

  The plurality of NTRs of the pull-down circuit 228 are on / off controlled according to the count value of the second counter 225. That is, in the pull-down circuit 228, the number of NTRs corresponding to the count value of the second counter 225 is turned on among the plurality of NTRs. The voltage at the node N varies depending on the number of PTRs turned on in the second pull-up circuit 227 and the number of NTRs turned on in the pull-down circuit 228. The pull-down circuit 228 is controlled so that the voltage appearing at the connection point N becomes equal to the reference voltage from the reference voltage generator 221.

  The internal resistance circuit 229 has an internal resistance element and a switch connected between the internal resistance element and the ZQ terminal. Details of the internal resistance circuit 229 will be described later.

  In the above configuration, it is assumed that the switch of the internal resistance circuit 229 is in an off state (non-conducting state), and an external resistance element (reference resistance element, for example, 240 ohm) is connected to the ZQ terminal. explain.

  First, the first counter 224 is activated by a command from the command decoder 15 or a control signal from the test control circuit 21. The first counter 224 performs a count-up or count-down operation based on the comparison result from the first comparator 222 and outputs a count value to the first pull-up circuit 226.

  The first pull-up circuit 226 controls the number of PTRs that are turned on according to the count value from the first counter 224. The voltage appearing at the ZQ terminal changes according to the number of PTRs that are turned on.

  The first comparator 222 compares the reference voltage from the reference voltage generator 221 with the voltage appearing at the ZQ terminal, and outputs the comparison result to the first counter.

  Through the above feedback control, the first pull-up circuit 226 is controlled to have an impedance (resistance value) equal to the resistance value of the external resistance element.

  Since the output of the first counter 224 is also supplied to the second pull-up circuit 227, the second pull-up circuit 227 has the same impedance (resistance value) as the first pull-up circuit 226.

  Next, the second counter 225 is activated by a command from the command decoder 15 or a control signal from the test control circuit 21. The second counter 225 performs a count up or count down operation based on the comparison result from the second comparator 223 and outputs the count value to the pull down circuit 228. The pull-down circuit 228 controls the number of NNRs that are turned on according to the count value of the second counter 225. The voltage appearing at the connection point N changes according to the number of NTRs that are turned on.

  The second comparator 223 compares the reference voltage from the reference voltage generator 221 with the voltage appearing at the connection point N, and outputs the comparison result to the second counter 225.

  With the above feedback control, the pull-down circuit 228 is controlled to have a resistance value equal to the resistance value of the second pull-up circuit 227 (that is, the resistance value of the external resistance element).

  The count values of the first and second counters 224 and 225 are supplied to the input / output circuit 20 and controlled so that the impedance (resistance value) of the pull-up circuit and pull-down circuit of the output driver becomes equal to the external resistance (ZQ calibration). )

  Next, the internal resistance circuit 229 will be described in detail.

  As shown in FIG. 3, the internal resistance circuit 229 includes an internal resistance element Rin and a switch SW connected between the internal resistance element Rin and the ZQ terminal. The internal resistance element Rin has the same resistance value (for example, 240Ω) as the external resistance element connected to the ZQ terminal. The switch SW is configured using, for example, a low threshold value NTR. Note that the low threshold means a lower one of thresholds included in a plurality of NTRs included in the semiconductor device 10.

  In the configuration of FIG. 3, when the switch SW is turned on, a state in which the external resistance element is electrically connected to the ZQ terminal can be realized without using the external resistance element. That is, the above-described ZQ calibration can be executed without using an external resistance element.

  In order to make the switch SW conductive, a ZQ calibration self test mode (ZQ CAL Self Test Mode) is defined. When entry to the ZQ calibration self-test mode is instructed by the external command signal, a command instructing entry to the mode is output from the command decoder 15 to each related unit. The test control circuit 21 outputs a test mode signal TMR (high level) in response to a command from the command decode 15. Thereby, the internal resistance element Rin is electrically connected to the ZQ terminal.

  Further, when execution of ZQ calibration is instructed by an external command signal (ZQ CAL command), ZQ calibration is executed in the ZQ calibration circuit 22 in the same manner as when an external resistance element is connected.

  In addition, the test control circuit 21 checks the operation state of the ZQ calibration circuit 22 by monitoring the count values from the first and second counters 224 and 225, for example.

  As described above, in the semiconductor device 10 according to the present embodiment, the operation test of the ZQ calibration circuit 22 can be performed without using an external resistance element. Therefore, it is possible to use a test board on which an external resistance element is not mounted in a test during or after manufacturing of the semiconductor device 10.

  Note that an external resistance element connected to the ZQ terminal is usually mounted on a circuit board or the like on which the semiconductor device 10 is mounted, but an internal resistance element may be used instead of the external resistance element. . Thereby, the number of parts mounted on a circuit board etc. can be reduced.

  Next, a semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. The overall configuration of the semiconductor device according to the present embodiment is the same as that according to the first embodiment.

  As shown in FIG. 4, the semiconductor device according to the present embodiment is provided between the internal power supply voltage VDDCA and the ZQ terminal, and between the ZQ terminal and the low potential internal power supply voltage (or the external power supply voltage VSS (ground potential)). , N-channel transistors NTR1 and NTR2 are provided as short-circuit switches, respectively.

  When entry to the ZQ BIST (Built In Self Test) test mode is instructed by an external command, the test control circuit 21 outputs one of the test mode signals TM1 and TM2 (sets it to high level).

  Test mode signals TM1 and TM2 cause transistors NTR1 and NTR2 to transition to a conductive state. When the transistor NTR1 is turned on, the voltage appearing at the ZQ terminal becomes equal to the internal power supply voltage VDDCA. Further, when the transistor NTR2 is turned on, the voltage appearing at the ZQ terminal becomes equal to the low potential side internal power supply voltage.

  In response to the external ZQ calibration command and the mode register setting command, the test control circuit 21 checks whether the voltage appearing at the ZQ terminal is equal to the internal power supply voltage VDDCA or the low potential side internal power supply voltage. To do. Thereby, the test control circuit 21 can test whether or not the malfunction of the ZQ calibration circuit 22 can be detected correctly (confirms a BIST (built in self test) operation). If the above-described calibration test is performed after this test is performed, it is possible to distinguish between a malfunction of the test control circuit 21 and a malfunction of the ZQ calibration circuit 22.

  As described above, the present invention has been described with reference to the representative embodiments. However, the present invention is not limited to the above-described embodiments, and various changes and modifications can be made. For example, although the DRAM is exemplified in the above embodiment, the present invention is applicable to various semiconductor devices including a ZQ calibration circuit that adjusts the impedance of the output driver.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Internal voltage generation circuit 12 Clock input circuit 13 Command input circuit 14 Address input circuit 15 Command decoder 16 Address latch circuit 17 Memory array 18 Column decoder 19 Row decoder 20 Input / output circuit 21 Test control circuit 22 ZQ calibration circuit 221 Reference voltage generator 222 First comparator 223 Second comparator 224 First counter 225 Second counter 226 First pull-up circuit 227 Second pull-up circuit 228 Pull-down circuit 229 Internal resistance circuit

Claims (5)

An external terminal,
A calibration circuit connected to the external terminal and performing calibration using an external resistance element connected to the external terminal;
An internal resistance element;
A switch provided between the internal resistance element and the external terminal,
In a state where the external resistance element is not connected to the external terminal, the internal resistance element is substituted for the external resistance element by electrically connecting the internal resistance element to the ZQ terminal by setting the switch to a conductive state. A semiconductor device characterized in that the calibration can be performed using an element. A test control circuit for generating a test mode signal based on an input command;
The semiconductor device according to claim 1, wherein the switch is controlled to be in the conductive state by the test mode signal.   3. The semiconductor according to claim 2, further comprising: a command input circuit that receives an external command signal and outputs an internal command signal; and a command decoder that decodes the internal command signal and generates the command. apparatus.   The semiconductor device according to claim 1, wherein the switch is a transistor switch.   A first short-circuiting switch connected between the external terminal and the high-potential-side power supply; and a second short-circuiting switch connected between the external terminal and the low-potential-side power supply. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.

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