JP2012104201A - Semiconductor device and semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device provided with a reset circuit for generating a reset signal of an internal circuit.SOLUTION: The semiconductor device includes: a first reset signal generation circuit (RSTC1) for generating a first reset signal POR1 in accordance with first power supply voltage; a second reset signal generation circuit (RSTC2) operated by second power supply voltage to execute a reset operation in response to a control signal, and transit a second reset signal POR2 from an active level to an inactive level in accordance with the completion of the reset operation; a third reset signal generation circuit (RSTC3) for generating a third reset signal POR3 of the active level when at least one between two signals of the first reset signal POR1 and the second reset signal POR2 is at an active level, and a third reset signal POR3 of the inactive level when both the two signals are at an inactive level, and supplying the third reset signal POR3 as a control signal to the second reset circuit (RSTC2); and an internal circuit CKT for executing a reset operation when the third reset signal POR3 is at an active level.

Description

  The present invention relates to a semiconductor device and a semiconductor memory device including a power-on reset circuit.

  With the miniaturization of semiconductor elements, the electrical characteristics of the semiconductor elements greatly fluctuate due to manufacturing variations in processing dimensions, and the operating characteristics of the semiconductor device are easily affected by manufacturing variations. Therefore, there is an increasing need to generate a test signal by a test circuit provided in the semiconductor device and perform an operation test on an internal circuit included in the semiconductor device. Therefore, in order to generate a test signal by the test circuit and test the operation margin of the internal circuit, the semiconductor device has a small operation margin by making the malfunction of the semiconductor device obvious by changing the internal power supply voltage and the internal signal timing. Deteriorating is performed.

  For example, a semiconductor device vendor supplies a control signal from a semiconductor test apparatus (tester) to a semiconductor device in a screening test for determining whether the manufactured semiconductor device is a non-defective product or a defective product. The test circuit is operated by shifting to a different test operation mode. The command data for shifting the semiconductor device to the test operation mode is composed of a combination of logics of a plurality of control signals that are normally not disclosed to a user who uses the semiconductor device. However, there is a case where a user who uses the semiconductor device supplies command data that is mistakenly disclosed and shifts the semiconductor device to a test operation mode. Patent Document 1 discloses a semiconductor memory device that can cope with an erroneous entry to a test operation mode by supplying command data that is not disclosed.

Japanese Patent Laid-Open No. 2001-243796

The semiconductor memory device disclosed in Patent Document 1 is a user who uses a semiconductor memory device by making the output of the input / output circuit high impedance and disabling the data input / output operation when erroneously entering the test operation mode. This is a semiconductor memory device that makes an erroneous entry recognized.
However, Patent Document 1 describes a case where a semiconductor storage device erroneously enters command data that is not disclosed when the power is turned on (power-on) and erroneously enters the test operation mode. Absent. As a result, the semiconductor memory device described in Patent Document 1 executes a test operation mode unintended by the user due to an erroneous entry to the test operation mode at power-on.

  For this reason, as a configuration for preventing erroneous entry into the test operation mode at power-on, in recent semiconductor memory devices, when the power is turned on, the power-on level of the active level is increased as the power supply voltage level is increased. There is a semiconductor memory device having a power-on reset circuit that internally generates a reset signal. This power-on reset circuit supplies a power-on reset signal to an internal circuit, for example, a test mode latch circuit (hereinafter referred to as a test latch circuit section) that sets a test operation mode in a plurality of control circuits in the semiconductor memory device when the power is turned on. To do. When the power-on reset signal is supplied, the test latch circuit unit executes a reset operation for returning the output of the internal flip-flop to a predetermined initial level. When the test latch circuit unit performs the reset operation, the plurality of control circuits prevent the semiconductor memory device from erroneously entering the test operation mode without setting the test operation mode.

However, the power-on reset signal corresponds to the ambient temperature at which the power-on reset signal generation circuit operates, or to element variations caused by the manufacturing process of transistors, resistors, etc. that constitute the power-on reset signal generation circuit, and the pulse width is It will change.
When the pulse width of the power-on reset signal is shortened, that is, when the period during which the power-on reset signal is at the active level is shortened, the period during which the test latch circuit unit to which the power-on reset signal is input performs the reset operation There is a problem that the test latch circuit unit is not reset normally.

  In addition, when the test latch circuit unit is not normally reset, the data held in the flip-flop by the test latch circuit unit becomes indefinite data different from the reset state, and the control unit performs a test operation mode corresponding to the indefinite data. May be set, and the semiconductor memory device may enter a test operation mode. When the semiconductor memory device erroneously enters the test operation mode at the time of power-on, there is a problem that it cannot move to the normal operation mode unless the reset command is input and cannot operate normally.

  The present invention is a first reset signal generation circuit that generates a first reset signal in response to a first power supply voltage, and a circuit that operates at a second power supply voltage and generates a second reset signal. A second reset signal generation circuit that executes its own reset operation in response to a control signal and transitions the second reset signal from an active level to an inactive level in response to completion of the reset operation; A third reset signal generation circuit for generating a third reset signal from the first reset signal and the second reset signal, wherein at least one of the first reset signal and the second reset signal When the first reset signal and the second reset signal are both at the inactive level, the third reset signal is at the active level. The third reset signal generating circuit that is inactivated and supplies the third reset signal as the control signal to the second reset circuit; receives the third reset signal; and receives the third reset signal And an internal circuit that executes its own reset operation when the signal is at the active level.

  The present invention also provides a read / write control unit for controlling the operation of the memory cell array according to a plurality of control test signals, and an operation designation command for setting an operation mode supplied from the outside of the semiconductor memory device. A test latch that outputs the plurality of control test signals according to a test code signal supplied from the outside when setting the operation mode, and sets the test operation mode in the control circuit in the read / write control unit A power-on reset signal generation circuit, wherein the power-on reset signal generation circuit generates a first reset signal in response to a first power supply voltage; 2 is a circuit that operates with a power supply voltage of 2 and generates a second reset signal, and executes its own reset operation in response to a control signal. A second reset signal generating circuit that transitions the second reset signal from an active level to an inactive level in response to the completion of the set operation, the first reset signal, and the second reset signal; A third reset signal generating circuit for generating a third reset signal, wherein when at least one of the first reset signal and the second reset signal is at an active level, the third reset signal is set at an active level; When the first reset signal and the second reset signal are both in an inactive level, the third reset signal is set to an inactive level, and the third reset signal is sent to the second reset circuit. A third reset signal generation circuit that supplies the control signal, and the test latch circuit unit receives the third reset signal and receives the third reset signal. A semiconductor memory device, characterized in that the reset signal is to perform its reset operation when the activity level.

According to the present invention, the second reset signal generation circuit executes the reset operation when the control signal output from the third reset signal generation circuit is input, and the second reset signal generation circuit receives the second reset signal in response to the completion of the reset operation. The reset signal is deactivated. Further, the third reset signal generation circuit generates the third reset signal having the active level until the second reset signal becomes the inactive level even when the first reset signal becomes the inactive level. That is, the third reset circuit outputs the third reset signal at the active level while the second reset signal does not become the inactive level by the second reset circuit. Thereby, the reset period of the internal circuit to which the third reset signal is input can be extended as compared with the reset period of the internal circuit when only the first reset signal is input. Therefore, when the third reset signal is input to the internal circuit in the semiconductor device, the problem that the internal circuit is not reset by the reset signal can be reduced compared to the case where the first reset signal is input to the internal circuit. .
In addition, the period during which the reset signal is at the active level is short, the internal circuit (for example, the test latch unit in the semiconductor memory device) cannot perform the reset operation, outputs the test signal for controlling the activation level, and the semiconductor memory device It is possible to prevent erroneous entry to the test operation mode at power-on.

It is a figure for demonstrating the technical idea of this invention. 2 is a block diagram showing a circuit configuration of a semiconductor memory device 100. FIG. 3 is a block diagram showing a circuit configuration of a test latch circuit unit 107. FIG. 3 is a block diagram showing a circuit configuration of a power-on reset signal generation circuit 109. FIG. It is a block diagram which shows the circuit structure of power supply level monitor RSTC1 (1st reset circuit). It is an operation timing chart at the time of power-on of the power supply level monitor RSTC1. It is a block diagram which shows the circuit structure of FF circuit reset monitor RSTC2 (2nd reset circuit). 6 is an operation timing chart when the power-on reset signal generation circuit 109 is powered on. 6 is an operation timing chart at power-on when the power-on reset signal generation circuit 109 does not include the FF circuit reset monitor RSTC2. It is a block diagram which shows the circuit structure of FF circuit reset monitor RSTC2a (modified example of a 2nd reset circuit).

A typical example of the technical idea for solving the problems of the present invention will be described below with reference to FIG. However, it goes without saying that the claimed contents of the present invention are not limited to this technical idea, but are the contents described in the claims of the present invention.
FIG. 1 is a diagram for explaining the technical idea of the present invention, and shows the configuration of a power-on reset signal generation circuit 109 (semiconductor device) in an embodiment of the present invention. In FIG. 1, a circuit portion related to power-on reset signal generation is extracted from a semiconductor memory device 100 described later, and a power-on reset signal generation circuit 109 and an internal circuit CKT are shown.

The internal circuit CKT is, for example, the above-described test latch circuit unit, and generates a test signal to read out the operation mode of the control unit to a circuit in the control unit that controls the memory cell array constituting the semiconductor memory device 100. This is a circuit for setting a test operation mode different from the normal operation mode such as writing.
The power-on reset signal generation circuit 109 also supplies a power supply voltage supplied from an externally supplied first power supply or a second power supply generated from the first power supply inside the semiconductor memory device 100 when the power is turned on. The third reset signal POR3 at the active level is output to the internal circuit CKT until the power supply voltage becomes a predetermined voltage (a value determined by design).

  The internal circuit CKT to which the third reset signal POR3 is input performs a reset operation while the third reset signal POR3 is at the active level, and initializes the output of the internal circuit CKT. For example, when the test signal generated by the internal circuit CKT becomes an active level (for example, H level), the test operation mode is set in the control unit. Therefore, the internal circuit CKT initializes the output signal to an inactive level (for example, L level) while the third reset signal POR3 is at an active level at power-on.

The power-on reset signal generation circuit 109 includes a first reset signal generation circuit (power supply level monitor RSTC1 described later), a second reset signal generation circuit (FF circuit reset monitor RSTC2 described later), and a third reset signal generation circuit. (A logic circuit RSTC3 described later).
The first reset signal generation circuit monitors at least a rise in the voltage level of the first power supply voltage at the time of power-on, and keeps the first power supply voltage supplied from the first power supply at the active level until the power supply voltage reaches a predetermined voltage. 1 reset signal POR1 is generated. Conventionally, the internal circuit CKT has been initialized by the first reset signal POR1 at this active level. However, elements such as transistors and resistors that constitute the first reset circuit are subject to manufacturing variations at the time of manufacturing, and the threshold voltage is changed in the case of a transistor, and the resistance value is changed in the case of a resistor. In some cases, the first reset signal POR1 having a short period in the active level is generated. When the period of the activation level of the first reset signal POR1 is short and the initialization operation of the internal circuit CKT is not sufficiently performed, the internal circuit CKT generates an activation level test signal and the test operation mode is set in the control unit. End up.

In order for the power-on reset signal generation circuit 109 to generate the power-on reset signal POR3 at the active level during a period when the initialization operation of the internal circuit CKT is sufficiently performed, the power-on reset signal generation circuit 109 of the present application The circuit includes a circuit, a second reset circuit, and a third reset circuit.
When the second reset circuit generates the second reset signal POR2 at the active level at the time of power-on, the third reset signal POR3 at the active level generated by the third reset circuit is input as a control signal. Then, the reset operation is executed, and the second reset signal POR2 as an output is deactivated.

The third reset circuit receives the first reset signal POR1 and the second reset signal POR2, and generates the third reset signal POR3.
The third reset circuit is a third reset which is a power-on reset signal input to the internal circuit CKT when at least one of the first reset signal POR1 and the second reset signal POR2 is at an active level. When the signal POR3 is set to the active level and both the first reset signal POR1 and the second reset signal POR2 are set to the inactive level, the third reset signal POR3 is set to the inactive level.

With the above configuration, the power-on reset signal generation circuit 109 of the present application resets the internal circuit CKT to which only the first reset signal POR1 is input during the reset period of the internal circuit CKT to which the third reset signal POR3 is input. It can be extended compared to the period. Therefore, when the third reset signal POR3 is input to the internal circuit CKT, the problem that the internal circuit CKT is not reset by the reset signal is compared to the case where the first reset signal POR1 is input to the internal circuit CKT. Can be reduced.
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS.

FIG. 2 is a block diagram showing a circuit configuration of the semiconductor memory device 100 including the power-on reset signal generation circuit 109.
The semiconductor memory device 100 includes a clock generation circuit 101, a command input circuit 1021, a command decoder 102, a memory cell array 103, a read / write control unit 104, an address input circuit 1051, and an address latch unit 105.
The semiconductor memory device 100 also includes a test decoder 106, a test latch circuit unit 107, an internal voltage generation circuit 108, and a power-on reset signal generation circuit 109.

The clock generation circuit 101 determines whether the clock signal CK, the inverted clock signal / CK that is a complementary signal of the clock signal CK, and the input clock signal CK and the inverted clock signal / CK are valid from the outside of the semiconductor memory device 100. A clock enable signal CKE indicating whether or not. In addition, the clock generation circuit 101 sends an external clock signal to the read / write control unit 104 or the like, which is an internal circuit of the semiconductor memory device 100, in accordance with the input clock signal CK, inverted clock signal / CK, and clock enable signal CKE. An internal clock signal ICLK synchronized with CK is supplied. The clock generation circuit 101 supplies the internal clock signal ICLK synchronized with the external clock signal CK to the command input circuit 1021, the address input circuit 1051, and the test latch circuit unit 107.
In this specification, a signal having “/” at the head of a signal name indicates an inverted signal of the corresponding signal or a low active signal.

The command input circuit 1021 receives a command signal input from the outside of the semiconductor memory device 100 (for example, when the semiconductor memory device is a DRAM, a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, The write enable signal / WE) is latched in synchronization with the internal clock signal ICLK.
The command decoder 102 receives the command signal latched by the command input circuit 1021, decodes the latched command signal, and controls to instruct the read / write control unit 104 to operate according to the decoding result. A signal (internal command signal ICOM) is output. When the command decoder 102 determines that the decoding result is a test command (a command indicating setting of the test operation mode), the command decoder 102 outputs an internal command signal ICOM to the address latch unit 105.

Address input circuit 1051 takes in an address signal (a signal indicating the position of the memory cell in the memory cell array) input from the outside of semiconductor memory device 100 in synchronization with internal clock signal ICLK output from clock generation circuit 101, and addresses Output to the latch unit 105.
The address latch unit 105 latches the address signal output from the address input circuit 1051 according to the internal command signal ICOM, and supplies the latched internal address signal to the test decoder 106 or the read / write control unit 104.
When the decoding result in the command decoder 102 determines that a test command (a command indicating setting of the test operation mode) is input, the address latch unit 105 performs a test using the internal address signal as a test address signal in accordance with the internal command signal ICOM. Output to the decoder.

The memory cell array 103 is configured by arranging a plurality of memory mats including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells provided at intersections of the plurality of word lines and the plurality of bits.
The memory cell array 103 includes a plurality of sense amplifiers that perform operations such as amplifying data read from the memory cells to the bit lines, a plurality of word drivers that drive the plurality of word lines, a bit line, and an IO line. Are provided with a plurality of Y switches. The sense amplifier is a circuit that amplifies a weak data signal from a memory cell appearing on a bit line in a read operation. Further, in the write operation, it is a circuit for writing data to the memory cell via the bit line. The operation timing of the sense amplifier is controlled by a sense amplifier drive signal output from an X decoder and an X timing circuit described later.

  The Y switch controls the opening and closing timing by a Y decoder and a Y timing circuit described later. In the read operation, when the Y switch is opened in the read operation, the data from the bit line is read, and this data is transferred to the read / write control unit 104 arranged outside the memory cell array 103. Further, the IO line transfers write data from the read / write control unit 104 to the bit line in the write operation.

The read / write control unit 104 is a control unit that controls the operation of the memory cell array 103, and includes an X decoder, an X timing circuit, a Y decoder / Y timing circuit, and the like.
The X decoder and the X timing circuit decode the row address (internal address signal) input from the address latch unit 105, and select the memory cell of the memory cell array 103 using the word line according to the decoding result. The X decoder and the X timing circuit control the operation timing of the sense amplifier that amplifies the difference potential between the bit lines.
The Y decoder and the Y timing circuit decode the column address (internal address signal) input from the address latch unit 105, and select the Y switch interposed between the bit line and the IO line according to the decoding result. Control and so on.

  In addition, the Y decoder and the Y timing circuit synchronize with the internal clock signal ICLK input from the clock generation circuit 101 in accordance with the internal command signal ICOM input from the command decoder 102, and connect the IO line from the selected memory cell. The operation of reading data via the I / O or the operation of writing data to the selected memory cell via the IO line is controlled. The Y decoder and the Y timing circuit output the memory cell data to the outside of the semiconductor memory device 100 as DQ signals (DQ0 to n). In addition, the Y decoder and the Y timing circuit write the DQ signal input from the outside of the semiconductor memory device 100 to the memory cell as data. These read and write operations are also performed in synchronization with the internal clock signal ICLK.

  As described above, the read / write control unit 104 includes an X decoder and an X timing circuit, a Y decoder and a Y timing circuit. These X decoder and X timing circuit, Y decoder and Y timing circuit further have the following control circuit, and control the operation of the memory cell array 103. The control circuit includes a circuit for changing timing (for example, a circuit for increasing or decreasing the drive timing of the sense amplifier by the test mode signal TMS, or a delay circuit embedded in advance in a signal control system used for control for writing and reading. There is a delay circuit activated by the test mode signal TMS).

  In addition, the control circuit includes a circuit that changes the voltage level of the internally generated power supply circuit (for example, a circuit that can switch the input reference voltage input to the internally generated power supply circuit to a high voltage or a low voltage by the test mode signal TMS. ) The control circuit also includes a circuit that changes the circuit operation by enabling or disabling the control signal (the circuit that was originally inactivated can be activated by the test mode signal TMS, or vice versa. There is a circuit that can inactivate the circuit that has been activated by the test mode signal TMS).

The test decoder 106 is generally composed of an AND circuit, receives the test address signal output from the address latch unit 105, decodes the input test address signal, and outputs the code address DTA in various tests to the test latch circuit unit. It outputs to 107.
When in the test operation mode, test latch circuit unit 107 (internal circuit) latches code address DTA input from test decoder 106, and activates test mode signal TMS (control circuit connected to the internal circuit). As a control signal or a test signal for test control input to the control circuit in the read / write control unit 104), the control signal is supplied to the corresponding control circuit in the read / write control unit 104. The configuration of the test latch circuit unit 107 will be described later.

The internal voltage generation circuit 108 is a circuit that generates an internal power supply voltage VINT that is different from the external power supply voltage VDD and the ground power supply voltage VSS supplied from the outside of the semiconductor memory device 100. To supply.
The power-on reset signal generation circuit 109 generates a reset signal POR3 from the external power supply voltage VDD and the ground power supply voltage VSS supplied from the outside of the semiconductor memory device 100 and the internal power supply voltage VINT. The power-on reset signal generation circuit 109 outputs the reset signal POR3 to the internal circuit CKT that needs to reset the output level of the circuit to an inactive level when the test latch circuit unit 107 and the like are powered on. The configuration of the power-on reset signal generation circuit 109 will be described later.

FIG. 3 is a block diagram showing a circuit configuration of the test latch circuit unit 107.
The test latch circuit unit 107 includes a plurality of test latches TFF0 to TFFn and an inverter inv41 respectively corresponding to the plurality of code addresses DTA0 to code addresses DTAn input from the test decoder 106.
Although the test latches TFF0 to TFF are different in input and output, but have the same circuit configuration, the circuit configuration of the test latch TFF0 will be described below.
The test latch TFF0 includes an inverter inv42, a P-channel MOS transistor M41, an inverter inv43, an N-channel MOS transistor M42, a P-channel MOS transistor M43, an inverter inv44, and an inverter inv45.

The inverter inv42 has an input connected to the clock generation circuit 101, receives the internal clock signal ICLK, logically inverts the internal clock signal ICLK, and outputs it to the gate terminal of the P-channel MOS transistor M41.
The gate terminal of the P-channel MOS transistor M41 is connected to the output of the inverter inv42, and the logical inversion signal of the internal clock signal ICLK is input.
The P-channel MOS transistor M41 has a source terminal connected to the internal power supply line, supplied with the internal power supply voltage VINT, and a drain terminal connected to the source terminal of the P-channel MOS transistor constituting the inverter inv43. .

The gate terminal of the P-channel MOS transistor constituting the inverter inv43 is connected to the test decoder 106, the code address DTA0 is input, and the drain terminal is connected to the internal node node41.
The drain terminal of the N channel type MOS transistor constituting the inverter inv43 is connected to the internal node node 41 together with the drain terminal of the P channel type MOS transistor constituting the inverter inv43. The gate terminal of the N-channel MOS transistor constituting the inverter inv43 is connected to the test decoder 106, the code address DTA0 is input, and the source terminal is connected to the drain terminal of the N-channel MOS transistor M42.

The N-channel MOS transistor M42 has a drain terminal connected to the source terminal of the N-channel MOS transistor constituting the inverter inv43, a source terminal connected to the power supply line, and a ground power supply voltage VSS.
The N-channel MOS transistor M42 has a gate terminal connected to the clock generation circuit 101 and receives the internal clock signal ICLK.

  With the above connection, the P-channel MOS transistor M41, the inverter inv43, and the N-channel MOS transistor M42 constitute a clocked inverter. When the internal clock signal ICLK is at the active level (H level), the code address DTA0 is fetched. The code address DTA0 is logically inverted and output to the internal node node41.

The inverter inv44 and the inverter inv45 constitute a flip-flop (first flip-flop), the input of the flip-flop is connected to the internal node node 41, the logic of the internal node node 41 is inverted, and the test mode signal TMS0 is output as an output signal. Output. The inverter inv44 and the inverter inv45 are arranged at the final stage of the test latch TFF0. When the code address DTA0 is at the H level in the test operation mode period, the test mode signal TMS0 is set to the active level (H level), and the semiconductor memory device 100 The active level is maintained during the test operation mode.
In addition, the control circuit in the read / write control unit 104 to which the active mode test mode signal TMS0 is input is set in the read / write control unit 104 while the test operation mode is set and the semiconductor memory device 100 is in the test operation mode. Performs operation adjustment such as timing adjustment.

  Each of the test latches TFF1 to TFFn has a circuit configuration similar to that of the test latch TFF0, and when the input code address DTA1 to code address DTAn is at the H level, the corresponding test mode signal TMS1 to test mode signal TMSn is The active level is maintained (H level), and the active level is maintained while the semiconductor memory device 100 is in the test operation mode. In addition, each of the control circuits in the read and write control unit 104 to which the active mode test mode signals TMS1 to TMSn are input is set in the test operation mode and read during the period in which the semiconductor memory device 100 is in the test operation mode. The write control unit 104 performs operation adjustment such as timing adjustment.

The flip-flops constituting the final stage of each of the test latches TFF0 to TFFn are supplied with test mode signals TMS0 to TMS0 so that the test operation mode is not set in the corresponding control circuit in the read / write control unit 104 at power-on. It is necessary to set TMSn to the inactive level (L level).
Therefore, a P-channel MOS transistor M43 is connected to the input (internal node node 41) of the flip-flop that forms the final stage of each of the test latches TFF0 to TFFn.

In the P-channel MOS transistor M43, the source terminal is connected to the internal power supply line, the internal power supply voltage VINT is supplied, and the drain terminal is connected to the internal node node41. The P-channel MOS transistor M43 has a gate terminal connected to the output of the inverter inv41.
The inverter inv41 is a logic inversion circuit provided in common to the test latches TFF0 to TFFn, and has an input connected to the output of the power-on reset signal generation circuit 109 and receives the reset signal POR3. The inverter inv41 logically inverts the reset signal POR3 and outputs it to the gate terminal of the P-channel MOS transistor M43.

  As the voltage level of the internal power supply voltage VINT increases, the voltage level of the reset signal POR3 increases, that is, the reset signal POR3 becomes an activation level (H level) that is the same voltage level as the internal power supply voltage VINT. Thus, the gate terminal connected to the inverter inv41 becomes the voltage level of the ground power supply voltage VSS. As a result, the P-channel MOS transistor M43 in each test latch TFF is turned on to charge the internal node node 41 to the H level. Each test latch TFF sets the test mode signal TMS to an inactive level (L level) by a flip-flop connected to the internal node node 41 in the final stage.

  When the power-on reset signal generation circuit 109 sets the reset signal POR3 to an inactive level (L level), the inverter inv41 outputs an H level, and the P-channel MOS transistor M43 is turned off. The flip-flops in each test latch TFF maintain the internal node node 41 at the H level and maintain the test mode signal TMS at the inactive level (L level) until the clocked inverter is turned on thereafter in the test operation mode. That is, when the power is turned on, the test operation mode is not set in the corresponding control circuit in the test mode signal TMS read / write control unit 104, and the control circuit operates in the normal operation mode.

FIG. 4 is a block diagram showing a circuit configuration of the power-on reset signal generation circuit 109 that generates the reset signal POR3 input to the test latch circuit unit 107. Hereinafter, the power-on reset will be described with reference to FIGS. The operation of the signal generation circuit when the power is turned on will be described.
As shown in FIG. 4, the power-on reset signal generation circuit 109 includes a power supply level monitor RSTC1 (first reset circuit), an FF circuit reset monitor RSTC2 (second reset circuit), and a logic circuit RSTC3 (third reset circuit). Circuit).
The power supply level monitor RSTC1 (first reset circuit) monitors the rise of the voltage levels of the external power supply voltage VDD and the internal power supply voltage VINT when the semiconductor memory device 100 is powered on, and each power supply level becomes a predetermined voltage level. Until it reaches the reset signal POR1, the active level (H level) is output. The power supply level monitor RSTC1 outputs an inactive level (L level) reset signal POR1 when both the external power supply voltage VDD and the internal power supply voltage VINT reach the set voltage levels. The detailed circuit configuration and operation of the power supply level monitor RSTC 1 will be described later with reference to FIGS.

  The FF circuit reset monitor RSTC2 (second reset circuit) performs a reset operation of the built-in FF circuit (flip-flop) according to the reset signal POR3 when the semiconductor memory device 100 is powered on, and the reset operation is completed. Until then, the reset signal POR2 of the active level (H level) is output. The FF circuit reset monitor RSTC2 outputs an inactive level (L level) reset signal POR2 when the reset operation of the built-in FF circuit is completed. The detailed circuit configuration and operation of the FF circuit reset monitor RSTC2 will be described later with reference to FIG.

As shown in FIG. 4, the logic circuit RSTC3 (third reset circuit) includes an inverter inv61, an inverter inv62, and a NAND circuit nand61.
The inverter inv61 has an input connected to the output of the power supply level monitor RSTC1, receives a reset signal POR1 (first reset signal), logically inverts the reset signal POR1, and outputs it to one input of the NAND circuit nand61. To do.
Further, the inverter inv62 has an input connected to the output of the FF circuit reset monitor RSTC2, receives a reset signal POR2 (second reset signal), logically inverts the reset signal POR2, and inputs it to the other input of the NAND circuit NAND61. Output.
The NAND circuit nand61 is a two-input one-output NAND circuit, and one input of two inputs is connected to the output of the inverter inv61, and the other input of two inputs is connected to the output of the inverter inv62. A reset signal POR3 is output.

With the above configuration, the logic circuit RSTC3 has an active level (H level) when at least one of the reset signal POR1 (first reset signal) and the reset signal POR2 (second reset signal) is at the active level (H level). Reset signal POR3 (third reset signal) is generated. The logic circuit RSTC3 generates the inactive level (L level) reset signal POR3 when both the reset signal POR1 and the reset signal POR2 are at the inactive level (L level).
When the reset signal POR3 is input and the reset signal POR3 is at the active level (H level), the FF circuit reset monitor RSTC2 and the test latch circuit unit 107 set the input of the flip-flop inside each of the flip-flops to the H level. Is set to the inactive level (L level).

FIG. 5 is a block diagram showing a circuit configuration of the power supply level monitor RSTC1 (first reset circuit), and FIG. 6 is a timing chart showing an operation of the power supply level monitor RSTC1 when the power is turned on. Hereinafter, the operation of the power supply level monitor RSTC1 when the semiconductor memory device 100 is powered on will be described with reference to FIGS.
The power supply level monitor RSTC1 includes a level monitor RSTC11, a level monitor RSTC12, and a NAND circuit nand21.

The level monitor RSTC11 includes a resistor R21, a resistor R22, a resistor R23, an N-channel MOS transistor M21, and an inverter inv21.
The resistor R21 has one end of the resistor connected to the power supply line, supplied with the external power supply voltage VDD, and the other end of the resistor connected to one end of the resistor R22 and the gate terminal of the N-channel MOS transistor M21.
The resistor R22 has one end of the resistor connected to the other end of the resistor R21 and the gate terminal of the N-channel MOS transistor M21, the other end of the resistor connected to the power supply line, and supplied with the ground power supply voltage VSS.
The resistor R23 has one end of the resistor connected to the power supply line, supplied with the external power supply voltage VDD, and the other end connected to the drain terminal of the N-channel MOS transistor M21 and the input of the inverter inv21.

The N-channel MOS transistor M21 has a drain terminal connected to the other end of the resistor R23 and the input of the inverter inv21, a source terminal connected to the power supply line, and a ground power supply voltage VSS.
The other end of the resistor R23, the drain terminal of the N-channel MOS transistor M21, and the input of the inverter inv21 are connected in common, and this connection point is defined as an internal node node21.
The inverter inv21 has an input connected to the internal node node21, logically inverts the logic level of the internal node node21, and outputs a reset signal PrePOR11 from the output.

The level monitor RSTC12 includes a resistor R24, a resistor R25, a resistor R26, an N-channel MOS transistor M22, and an inverter inv22.
The resistor R24 has one end of the resistor connected to the internal power supply line, supplied with the internal power supply voltage VINT, and the other end of the resistor connected to one end of the resistor R25 and the gate terminal of the N-channel MOS transistor M22.
The resistor R25 has one end of the resistor connected to the other end of the resistor R24 and the gate terminal of the N-channel MOS transistor M22, the other end of the resistor connected to the power supply line, and supplied with the ground power supply voltage VSS.
The resistor R26 has one end of the resistor connected to the power supply line, supplied with the external power supply voltage VDD, and the other end connected to the drain terminal of the N-channel MOS transistor M22 and the input of the inverter inv22.

The N-channel MOS transistor M22 has a drain terminal connected to the other end of the resistor R26 and the input of the inverter inv22, a source terminal connected to the power supply line, and a ground power supply voltage VSS.
The other end of the resistor R26, the drain terminal of the N-channel MOS transistor M22, and the input of the inverter inv22 are connected in common, and this connection point is defined as an internal node node22.
The inverter inv22 has an input connected to the internal node node22, logically inverts the logical level of the internal node node22, and outputs a reset signal PrePOR12 from the output.

  The NAND circuit nand21 is a NAND circuit with two inputs and one output. One input of two inputs is connected to the output of the inverter inv21, and the other input of two inputs is connected to the output of the inverter inv22. A reset signal POR1 is output.

The resistors R21 and R22 in the level monitor RSTC11 divide the voltage level of the external power supply voltage VDD, but since the resistance value is set large from the standpoint of reducing the standby current, the voltage dividing point (the common connection of the resistor R21 and the resistor R22) The voltage level of point) rises more slowly than the rise of the external power supply voltage VDD.
The resistance value of the resistor R23 is set smaller than the resistors R21 and R22 so that the voltage level of the internal node node21 follows the rise of the external power supply voltage VDD.
Therefore, the voltage level of the internal node node21 is as shown in FIG. 6 until the voltage level at the voltage dividing point (common connection point of the resistor R21 and the resistor R22) rises and the N-channel MOS transistor M21 is turned on. Rises with the external power supply voltage VDD.

  When the voltage level of the external power supply voltage VDD reaches the voltage level VDDa, the voltage level at the voltage dividing point exceeds the threshold voltage of the N-channel MOS transistor M21, the N-channel MOS transistor M21 starts to turn on, and the internal node node21 The voltage level drops (time t1). When the voltage level at the voltage dividing point further increases, the on-resistance value of the N-channel MOS transistor M21 becomes sufficiently smaller than the resistance value of the resistor R23, and the voltage level of the internal node node21 becomes L level. The inverter inv21 inverts the logic level of the internal node node21 and outputs an H level reset signal PrePOR11.

  Thus, the level monitor RSTC 11 monitors the rise of the external power supply voltage VDD when the semiconductor memory device 100 is powered on, and keeps the reset signal PrePOR11 at the active level (until the voltage level of the external power supply voltage VDD reaches the voltage level VDDa). When the voltage level of the external power supply voltage VDD reaches the voltage level VDDa, the reset signal PrePOR11 is set to an inactive level (H level).

  The level monitor RSTC 12 performs the same operation as the level monitor RSTC 11, but the internal power supply voltage VINT is generated by the internal voltage generation circuit 108 according to the external power supply voltage VDD. Therefore, the increase in the voltage level of the internal power supply voltage VINT is more gradual than the increase in the voltage level of the external power supply voltage VDD, and the increase in the voltage level at the voltage dividing point (common connection point of the resistor R24 and the resistor R25) Compared to the increase in the voltage level of the corresponding voltage dividing point of the level monitor RSTC 11, it is gradual.

  When the voltage level of the internal power supply voltage VINT reaches the voltage level VINTa, the voltage level at the voltage dividing point exceeds the threshold voltage of the N-channel MOS transistor M22, the N-channel MOS transistor M22 starts to turn on, and the internal node node22 The voltage level drops (time t2). When the voltage level at the voltage dividing point further increases, the on-resistance value of the N-channel MOS transistor M22 becomes sufficiently smaller than the resistance value of the resistor R26, and the voltage level of the internal node node22 becomes L level. The inverter inv22 inverts the logic level of the internal node node22 and outputs an H level reset signal PrePOR12.

  As described above, the level monitor RSTC 12 monitors the rise of the internal power supply voltage VINT when the semiconductor memory device 100 is powered on, and keeps the reset signal PrePOR12 at the active level (until the voltage level of the internal power supply voltage VINT reaches the voltage level VINTa). When the voltage level of the internal power supply voltage VINT reaches the voltage level VINTa, the reset signal PrePOR12 is set to an inactive level (H level).

The NAND circuit nand21 changes the reset signal POR1 from the active level (H level) to the inactive level (L level) when any of the input reset signals PrePOR11 and PrePOR12 becomes inactive level (H level). (Time t3).
As described above, the power supply level monitor RSTC1 (first reset circuit) monitors the increase of the voltage levels of the external power supply voltage VDD and the internal power supply voltage VINT when the semiconductor memory device 100 is powered on, and each power supply level is predetermined. Until this voltage level is reached, the active level (H level) reset signal POR1 is output. The power supply level monitor RSTC1 outputs an inactive level (L level) reset signal POR1 when both the external power supply voltage VDD and the internal power supply voltage VINT reach the set voltage levels.

FIG. 7 is a block diagram showing a circuit configuration of the FF circuit reset monitor RSTC2 (second reset circuit). Hereinafter, the operation of the FF circuit reset monitor RSTC2 when the semiconductor memory device 100 is powered on will be described with reference to FIG.
The FF circuit reset monitor RSTC2 includes an inverter inv71, a P-channel MOS transistor M71, an inverter inv72, and an inverter inv73.

The inverter inv71 is connected to the output of the logic circuit RSTC3, receives the reset signal POR3, logically inverts the reset signal POR3, and outputs it to the gate terminal of the P-channel MOS transistor M71.
In the P-channel MOS transistor M71, the source terminal is connected to the internal power supply line, the internal power supply voltage VINT is supplied, and the drain terminal is connected to the internal node node 71.
The final stage of the FF circuit reset monitor RSTC2 includes a flip-flop (second flip-flop) including an inverter inv72 and an inverter inv73.
The input of the flip-flop (the input of the inverter inv72 and the output of the inverter inv73) is connected to the internal node node 71, and the reset signal POR2 is output from the output of the flip-flop (the output of the inverter inv72 and the input of the inverter inv73). To do.

The FF circuit reset monitor RSTC2 has the same circuit configuration as each test latch TFF in the test latch circuit unit 107 described above, and performs the same reset operation.
That is, the inverter inv71 corresponds to the inverter inv41 provided in common to each latch in the test latch circuit unit 107, and the P-channel MOS transistor M71 is a P-channel MOS provided in each latch in the test latch circuit unit 107. This corresponds to the transistor M43. The flip-flop composed of the inverter inv72 and the inverter inv73 corresponds to the flip-flop composed of the inverter inv44 and the inverter inv45 provided in the output unit of each latch in the test latch circuit unit 107.

Thus, the FF circuit reset monitor RSTC2 performs the same reset operation as each test latch TFF in the test latch circuit unit 107 by adopting the same circuit configuration as each test latch TFF in the test latch circuit unit 107.
That is, as the voltage level of the internal power supply voltage VINT increases, the voltage level of the reset signal POR3 increases, that is, the activation level (H level) at which the reset signal POR3 is the same voltage level as the internal power supply voltage VINT. Thus, the gate terminal connected to the inverter inv71 becomes the voltage level of the ground power supply voltage VSS.

  As a result, the P-channel MOS transistor M71 in the FF circuit reset monitor RSTC2 is turned on to charge the internal node node 71 to the H level. The FF circuit reset monitor RSTC2 sets the reset signal POR2 to the inactive level (L level) by the flip-flop connected to the internal node node 71 in the final stage.

In the FF circuit reset monitor RSTC2, it is necessary to output an activation level (H level) reset signal POR2 as the voltage level of the internal power supply voltage VINT increases. That is, at the time of power-on, it is necessary to make it easy for the output of the flip-flop to shift in the opposite direction to the reset state, that is, to the H level that is the active level. Therefore, the transistors and the like of each circuit in the FF circuit reset monitor RSTC2 are set as follows, for example.
First, in order to make the voltage level of the internal node node 71 easily become L level at power-on, for example, the drive capability of the P-channel MOS transistor M71 is set smaller than the drive capability of the N-channel MOS transistor constituting the inverter inv73. Is done.

  Further, in order to make the reset signal POR2 easily become H level at power-on, for example, the parasitic capacitance of the internal node node 71 (the gate capacitance of the transistor constituting the inverter inv72, etc.) is connected to the signal line that voltage the reset signal POR2. The drive capacity of the inverter inv72 is set to be greater than the drive capacity of the inverter inv73 after the capacity is made larger.

With the configuration described above, the power-on reset signal generation circuit 109 executes the reset operation of the test latch circuit unit 107 (internal circuit) at power-on. The reset operation of the power-on reset signal generation circuit 109 will be described below with reference to FIGS.
FIG. 8 is an operation timing chart of the power-on reset signal generation circuit 109 when the power is turned on. FIG. 8A shows an activation level (H level) of the power supply level monitor RSTC1 without being affected by temperature and process variations. The main signal and internal node voltage waveforms when the reset signal POR1 having a sufficiently long period is output. FIG. 8B shows the main signal and the internal node when the power supply level monitor RSTC1 outputs a reset signal POR1 having an insufficient active level (H level) period due to temperature and process variations. The voltage waveform of is shown. FIG. 9 shows voltage waveforms of main signals and internal nodes when the power-on reset signal generation circuit 109 does not have the FF circuit reset monitor RSTC2, that is, when the reset signal POR1 becomes the reset signal POR3.

As shown in FIG. 8A and FIG. 8B, the FF circuit reset monitor RSTC2 is a signal whose voltage level increases as the voltage level of the internal power supply voltage VINT increases, that is, the voltage level of the internal power supply voltage VINT. The reset signal POR2 having the same active level (H level) is output.
Accordingly, when the reset signal POR2 is at the active level (H level), the logic circuit RSTC3 to which the reset signal POR2 is input has one input level of the NAND circuit nand61 attains the L level by the inverter inv61.

  Therefore, as shown in FIG. 8 (b), the power supply level monitor RSTC1 has received the reset signal POR1 already inactive level (L level) due to temperature and process variations, and the other input level is set to H by the inverter inv61. Even at the level, the FF circuit reset monitor RSTC2 continues to output the reset signal POR3 at the active level (H level).

  In the test latch circuit unit 107 to which the active level (H level) reset signal POR3 is input, each test latch TFF executes a reset operation. That is, each test latch TFF in the test latch circuit unit 107 precharges the internal node node 41 that is the input of the flip-flop to H level when the P-channel MOS transistor M43 is turned on, and deactivates the test mode signal TMS. Set to level (L level).

Further, in the FF circuit reset monitor RSTC2, when the reset signal POR3 exceeds a predetermined voltage (the logic threshold voltage of the inverter inv71) as the voltage level of the internal power supply voltage VINT increases, the inverter inv71 outputs an L level signal to the P channel type. Output to the MOS transistor M43. In the FF circuit reset monitor RSTC2, the P-channel MOS transistor M71 is turned on, charges the internal node node 71 to H level, inverts the flip-flop, and outputs an inactive level (L level) reset signal POR2.
Accordingly, in the logic circuit RSTC3 to which the reset signal POR2 is input, one input level of the NAND circuit nand61 becomes the H level.

  Therefore, as shown in FIG. 8A, if the power supply level monitor RSTC1 outputs the reset signal POR1 of the inactive level (L level) and the other input level becomes H level by the inverter inv61, the logic circuit RSTC3 Inactive level (L level) reset signal POR3 is output. Further, as shown in FIG. 8B, the power supply level monitor RSTC1 has already received the reset signal POR1 at the inactive level (L level) due to temperature and process variations, and the other input level is set to H by the inverter inv61. Even in the case of the level, the logic circuit RSTC3 outputs the inactive level (L level) reset signal POR3.

  In the test latch circuit unit 107 to which the reset signal POR3 is input, each test latch TFF ends the reset operation. That is, each test latch TFF in the test latch circuit unit 107 finishes precharging the internal node node 41 that is the input of the flip-flop to the H level when the P-channel MOS transistor M43 is turned off. After completion of precharging of internal node node 41, the flip-flop maintains test mode signal TMS at an inactive level (L level).

  The FF circuit reset monitor RSTC2 also ends the reset operation when the input reset signal POR3 becomes inactive level (L level). That is, the FF circuit reset monitor RSTC2 finishes precharging the internal node node 71, which is the input of the flip-flop, to the H level when the P-channel MOS transistor M71 is turned off. After the precharge of internal node node 71 is completed, the flip-flop maintains reset signal POR2 at the inactive level (L level).

  A case where the power-on reset signal generation circuit 109 does not have the FF circuit reset monitor RSTC2 and the power supply level monitor RSTC1 receives temperature and process variations will be described. In this case, as shown in FIG. 9, the power-on reset signal generation circuit 109 receives the reset signal POR3 (corresponding to the reset signal POR1 shown in FIG. 8B) having a short period of the activation level (H level). Output. Therefore, as shown in FIG. 9, the internal node that is the input of each test latch TFF in the test latch circuit unit 107 to which the reset signal POR3 is input is not charged to the H level, and the test mode signal TMS is set to the inactive level (L The active level (H level) is maintained. That is, at the time of power-on, the reset operation of the test latch circuit unit 107 is not completed, and the semiconductor memory device 100 continues to power-on while the test operation mode is set in the control circuit in the read / write control unit 104. For example, the operation mode is shifted to the normal operation mode.

  On the other hand, since the power-on reset signal generation circuit 109 of the present invention has the FF circuit reset monitor RSTC2, the power supply level monitor RSTC1 receives temperature and process variations and has an insufficient active level (H level) period. Even when the reset signal POR1 is output (shown in FIG. 8B), the reset operation of the test latch circuit unit 107 (operation for setting the test mode signal TMS to the inactive level (L level)) can be performed. . Therefore, it is possible to prevent the test operation mode from being set in the control circuit in the read / write control unit 104 at power-on.

As described above, the semiconductor device (power-on reset signal generation circuit 109) according to the present embodiment outputs the first reset signal (reset signal POR1) according to the first power supply voltage (at least according to the external power supply voltage VDD). A first reset signal generation circuit is provided.
The power-on reset signal generation circuit 109 is a circuit that operates with the second power supply voltage (internal power supply voltage VINT) and generates a second reset signal (reset signal POR2), and is a control signal (reset signal POR3). ) And the second reset signal is changed from the active level (H level in the above embodiment) to the inactive level (L level) in response to the completion of the reset operation. A second reset signal generation circuit (FF circuit reset monitor RSTC2) is provided.
The power-on reset signal generation circuit 109 generates a third reset signal (reset signal POR3) from the first reset signal (reset signal POR1) and the second reset signal (reset signal POR2). A third reset signal generation circuit (logic circuit RSTC3), wherein the third reset signal is generated when at least one of the first reset signal and the second reset signal is at an active level (H level in the embodiment). When the signal (reset signal POR3) is at the active level (H level) and both the first reset signal and the second reset signal are at the inactive level (L level), the third reset signal is inactivated. Level (L level), and the third reset signal is sent to the second reset circuit (FF circuit reset monitor RSTC2). Comprising said supplied as control signal a third reset signal generating circuit (logic circuit RSTC3).
Further, the power-on reset signal generation circuit 109 receives the third reset signal, and performs its own reset operation (test) when the third reset signal is at the active level (H level in the embodiment). Latch circuit portion 107).

  According to the present invention, the second reset signal generation circuit (FF circuit reset monitor RSTC2) receives the control signal (reset signal POR3) output from the third reset signal generation circuit (logic circuit RSTC3). A reset operation is executed, and the second reset signal (reset signal POR2) is deactivated (L level) in response to the completion of the reset operation. In addition, the third reset signal generation circuit (logic circuit RSTC3) has a second reset signal inactive level (reset signal) even if the first reset signal is inactive level (reset signal POR3 is L level). An active level third reset signal (H level reset signal POR3) is generated until POR2 becomes L level.

  That is, the third reset circuit (logic circuit RSTC3) is activated while the second reset circuit (FF circuit reset monitor RSTC2) does not set the second reset signal to the inactive level (the reset signal POR2 is at the L level). A third level reset signal (H level reset signal POR3) is output. Thus, the reset period of the internal circuit (test latch circuit unit 107) to which the third reset signal is input is compared with the reset period of the internal circuit when only the first reset signal (reset signal POR3) is input. Can be extended. Therefore, when the third reset signal (reset signal POR3) is input to the internal circuit (test latch circuit unit 107), the internal circuit is not reset by the reset signal. This can be reduced compared to the case where the reset signal POR1) is input.

  Further, the period during which the reset signal is at the active level is short, and the internal circuit (the test latch circuit unit 107 in the semiconductor memory device) cannot execute the reset operation, and outputs an activation level control test signal (test mode signal TMS). Thus, it is possible to prevent the semiconductor memory device from erroneously entering the test operation mode when the power is turned on.

The basic technical idea of the present application is not limited to this, and a semiconductor chip having the functions of the present application can be applied to semiconductor devices such as SOC, SIP, and POP (package on package). The function of the semiconductor chip having the function of the present application can be applied to a semiconductor device such as a CPU, MCU, DSP, or memory.
The transistors constituting the logic circuit may be field effect transistors (FETs), and other than MOS (Metal Oxide Semiconductor), MIS (Metal-Insulator Semiconductor), TFT (Thin Film Transistor), etc. Applicable to various FETs. It can be applied to various FETs such as transistors. A bipolar transistor may be used. Transistors other than FETs may be used.
Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various modifications and corrections that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

For example, in the description of the embodiment, the FF circuit reset monitor RSTC2 has been described as the second logic circuit. However, the second logic circuit may be the latch circuit reset monitor RSTC2a illustrated in FIG.
FIG. 10 is a block diagram showing a circuit configuration of the latch circuit reset monitor RSTC2a (second logic circuit). The latch circuit reset monitor RSTC2a includes an inverter inv91, a P-channel MOS transistor M91, an inverter inv92, and an inverter inv93. The inverter inv91, the P channel type MOS transistor M91, the inverter inv92, and the inverter inv93 respectively correspond to the inverter inv71, the P channel type MOS transistor M71, the inverter inv72, and the inverter inv73 in the FF circuit reset monitor RSTC2. The portions corresponding to the FF circuit reset monitor RSTC2 perform the same reset operation as that of the FF circuit reset monitor RSTC2 when the power is turned on, and thus the description thereof is omitted.

In the FF circuit reset monitor RSTC2, as described above, when the power is turned on, the output of the flip-flop needs to easily shift in the direction opposite to the reset state, that is, the H level which is the active level. In other words, the output of the second logic circuit is easier to shift in the direction opposite to the reset state than any other flip-flop with reset in the semiconductor memory device 100 (if the reset state of the output is L level, the H level is high). Need to be).
Specifically, in the latch circuit reset monitor RSTC2a, the internal node node 91 needs to be easily at the L level and the internal node node 92 is likely to be at the H level (active level). However, the power-on state of the internal node node 91 and the internal node node 92 includes not only the strength relationship of the driving capability between the P-channel MOS transistor M91 and the inverter inv93 but also each element (P-channel MOS transistor M91, inverter inv92, And the off-leakage characteristic of the inverter inv93) and the parasitic capacitance formed between the internal power supply voltage VINT and the internal wiring for supplying the ground power supply voltage VSS.

  Therefore, in addition to setting the drive capability relationship between the P-channel MOS transistor M91 and the inverter inv93 in advance, as shown in FIG. 10, the capacitor C91, the capacitor C92, the leak element M92, and the leak element M93 are used as the input / output of the flip-flop. By adding to the corresponding internal node, the output of the flip-flop is easily determined in the opposite direction to the reset state.

One end of the capacitor C91 is connected to the internal node node91, the other end is connected to the external power supply line, and the ground power supply voltage VSS is supplied. The leak element M92 is, for example, an N-channel MOS transistor, the drain terminal is connected to the internal node node 91, the gate terminal and the source terminal are connected to the external power supply line, and the ground power supply voltage VSS is supplied.
The capacitor C91 is provided to make it difficult to charge the internal node node 91 to the H level even when the P-channel MOS transistor M91 is turned on at the time of power-on, or a power supply line that supplies the ground power supply voltage VSS The internal node node 91 operates to be at the L level due to the coupling between the two nodes.
In addition, leak element M92 causes internal node node 91 to be at L level at power-on by off-leakage Ioff (GIDL (Gate-Induced Drain Leakage) when the gate-source voltage of the N-channel MOS transistor is 0 V). To work.

One end of the capacitor C92 is connected to the internal node node92, the other end is connected to the internal power supply line, and the internal power supply voltage VINT is supplied. The leak element M93 is, for example, a P-channel MOS transistor, the drain terminal is connected to the internal node node 92, the source terminal and the gate terminal are connected to the internal power supply line, and the internal power supply voltage VINT is supplied.
Capacitor C92 operates to set internal node node 91 to the H level by coupling with internal power supply line supplying internal power supply voltage VINT when power is turned on.
Further, the leak element M93 operates to set the internal node node 92 to the H level at the time of power-on due to off-leakage Ioff (GIDL when the gate-source voltage of the P-channel MOS transistor is 0V).

  As described above, the latch circuit reset monitor RSTC2a makes it easy to shift the internal node node 91 to the L level and the internal node node 92 to the H level by adding a leak element and a capacitor to the input and output of the flip-flop, and power-on. Sometimes, the reset signal POR2 at the active level (H level) can be output more reliably than the FF circuit reset monitor RSTC2.

  Further, the latch circuit reset monitor RSTC2a may be configured as follows in order to output the reset signal POR2 at the active level (H level) at the time of power-on. An N-channel MOS transistor (reset transistor) to which the drain terminal is connected to the internal node node 91, the source terminal is connected to the external power supply line, and the ground power supply voltage VSS is supplied is provided. Further, a logic inversion signal of a reset signal PrePOR11 that is an output of the level monitor RSTC11 (a voltage level signal corresponding to the internal node node21 of the level monitor RSTC11, which is referred to as a reset signal / PrePOR11) is supplied to the gate terminal of the reset transistor. And

  In this way, at the time of power-on, while the reset signal / PrePOR11 is at the active level (H level), the internal node node 91 is fixed at the L level, and the latch circuit reset monitor RSTC2a is reset at the active level (H level). POR2 can be output. Further, since the reset signal / PrePOR11 becomes inactive level (L level) earlier than the reset signal POR1, both the P-channel MOS transistor M91 and the reset transistor in the latch circuit reset monitor RSTC2a are turned on. And the increase in current consumption due to the current passing through both transistors can be reduced.

  Note that in the case where the reset transistor is provided, the drive capability of the reset operation reset transistor is set smaller than the drive capability of the P-channel MOS transistor M91. Thus, the reset operation (the operation of setting the internal node node 91 to the H level and outputting the inactive level reset signal POR2) in the latch circuit reset monitor RSTC2a is not hindered.

  DESCRIPTION OF SYMBOLS 100 ... Semiconductor memory device, 101 ... Clock generation circuit, 1021 ... Command input circuit, 102 ... Command decoder, 103 ... Memory cell array, 104 ... Read / write control part, 1051 ... Address input circuit, 105 ... Address latch part, 106 ... Test decoder 107, test latch circuit unit, TFF, TFF0, TFF1, TFFn, test latch, 108, internal voltage generation circuit, 109, power-on reset signal generation circuit, RSTC1, power supply level monitor, RSTC11, RSTC12, level monitor, RSTC2 ... FF circuit reset monitor, RSTC2a ... latch circuit reset monitor, RSTC3 ... logic circuit, CKT ... internal circuit, POR1, POR2, POR3, PrePOR11, PrePOR12 ... reset signal, VDD ... Power supply voltage, VINT ... internal power supply voltage, VSS ... ground power supply voltage, inv41, inv42, inv43, inv44, inv45, inv61, inv62, inv21, inv22, inv71, inv72, inv73, inv91, inv92, inv93 ... inverter, M41, M43, M71, M91 ... P-channel MOS transistor, M42, M21, M22 ... N-channel MOS transistor, node41, node21, node22, node71, node91, node92 ... internal node, NAND21, NAND61 ... NAND circuit, R21, R22, R23, R24, R25, R26 ... resistor, M92, M93 ... leakage element, C91, C92 ... capacitance, ICLK ... internal clock signal, ICOM ... internal command signal DTA, DTA0, DTA1, DTAn ... code address, TMS, TMS0, TMS1, TMSn ... test mode signal

Claims (9)

A first reset signal generating circuit for generating a first reset signal in response to a first power supply voltage;
A circuit that operates with a second power supply voltage and generates a second reset signal, executes its own reset operation in response to a control signal, and performs the second reset in response to completion of the reset operation. A second reset signal generating circuit for transitioning the signal from the active level to the inactive level;
A third reset signal generating circuit for generating a third reset signal from the first reset signal and the second reset signal, wherein at least one of the first reset signal and the second reset signal; When one is at an active level, the third reset signal is set at an active level, and when both the first reset signal and the second reset signal are at an inactive level, the third reset signal is set at an inactive level. And the third reset signal generating circuit for supplying the third reset signal to the second reset circuit as the control signal;
An internal circuit that receives the third reset signal and executes its own reset operation when the third reset signal is at an active level;
A semiconductor device comprising: The internal circuit has a first flip-flop that outputs an activation control signal that activates another internal circuit connected to the internal circuit;
2. The semiconductor according to claim 1, wherein when the third reset signal is at an active level, the first flip-flop executes its own reset operation and sets the activation control signal to an inactive level. apparatus. The second reset signal generation circuit includes a second flip-flop that outputs the second reset signal;
2. The second flip-flop according to claim 1, wherein when the third reset signal is at an active level, the second flip-flop performs its own reset operation and sets the second reset signal to an inactive level. Item 3. The semiconductor device according to Item 2. The second flip-flop
A first leakage element and a first capacitance element connected to the input; a second leakage element and a second capacitance element connected to the output;
The first leakage element is connected between the input and a power supply wiring having the same voltage level as the inactive level of the second reset signal,
The first capacitive element has one end connected to the input and the other end connected to a power supply wiring having the same voltage level as the inactive level of the second reset signal.
The second leak element is connected between the output and a power supply wiring having the same voltage level as the voltage level of the activation level of the second reset signal,
The second capacitor element has one end connected to the output and the other end connected to a power supply wiring having the same voltage level as the active reset voltage level of the second reset signal.
4. The semiconductor device according to claim 3, wherein the second flip-flop sets the second reset signal to an active level when the power of the semiconductor device is turned on. A read and write controller that controls the operation of the memory cell array in response to a plurality of control test signals;
When the operation designation command indicating the setting of the operation mode supplied from the outside of the semiconductor memory device indicates the setting of the test operation mode, the plurality of control test signals are set according to the test code signal supplied from the outside. A test latch circuit unit that outputs and sets a test operation mode in a control circuit in the read and write control unit;
A power-on reset signal generation circuit,
The power-on reset signal generating circuit is
A first reset signal generating circuit for generating a first reset signal in response to a first power supply voltage;
A circuit that operates with a second power supply voltage and generates a second reset signal, executes its own reset operation in response to a control signal, and performs the second reset in response to completion of the reset operation. A second reset signal generating circuit for transitioning the signal from the active level to the inactive level;
A third reset signal generating circuit for generating a third reset signal from the first reset signal and the second reset signal, wherein at least one of the first reset signal and the second reset signal; When one is at an active level, the third reset signal is set at an active level, and when both the first reset signal and the second reset signal are at an inactive level, the third reset signal is set at an inactive level. And the third reset signal generating circuit for supplying the third reset signal to the second reset circuit as the control signal;
Have
The test latch circuit section receives the third reset signal and executes its own reset operation when the third reset signal is at an active level. The test latch circuit unit includes a first flip-flop that outputs the control test signal,
6. The first flip-flop according to claim 5, wherein when the third reset signal is at an active level, the first flip-flop executes its own reset operation and sets the control test signal to an inactive level. Semiconductor memory device. The second reset signal generation circuit includes a second flip-flop that outputs the second reset signal;
7. The second flip-flop performs a reset operation when the third reset signal is at an active level, and sets the second reset signal to an inactive level. The semiconductor memory device described in 1. The second flip-flop
A first leakage element and a first capacitance element connected to the input; a second leakage element and a second capacitance element connected to the output;
The first leakage element is connected between the input and a power supply wiring having the same voltage level as the inactive level of the second reset signal,
The first capacitive element has one end connected to the input and the other end connected to a power supply wiring having the same voltage level as the inactive level of the second reset signal.
The second leak element is connected between the output and a power supply wiring having the same voltage level as the voltage level of the activation level of the second reset signal,
The second capacitor element has one end connected to the output and the other end connected to a power supply wiring having the same voltage level as the active reset voltage level of the second reset signal.
8. The semiconductor memory device according to claim 7, wherein the second flip-flop sets the second reset signal to an active level when the power of the semiconductor memory device is turned on. A power-on reset circuit that generates a power-on reset signal in the internal circuit of the semiconductor device when the power of the semiconductor device is turned on,
The internal circuit performs its own reset operation when the power-on reset signal is at an active level,
The power-on reset circuit performs its own reset operation when the power-on reset signal is at an active level, and sets the power-on reset signal to an inactive level when the reset operation is completed. apparatus.

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