JP4405215B2 - Memory device - Google Patents

Description

  The present invention relates to a memory device having multiple ports, and more particularly to a memory device that can reduce cross-coupling noise between signals of multiple ports.

  Conventionally, there is a register file used for a CPU or the like as a memory device having multiple ports. A register file generally has a write port and a read port. In particular, register files having a plurality of read ports and write ports are frequently used so that they can be used for various purposes.

  FIG. 27 is a circuit diagram showing a configuration example of a memory cell of a conventional register file having a write 2 port and a read 3 port. In FIG. 27, the memory cell is composed of transfer gates 1 and 2 for inputting write data, a memory element composed of inverters 3 and 4 for storing data, and NMOS transistors 5 to 10 for reading data from the memory element. .

  Further, as signal lines for controlling the writing and reading of the memory cells, the write word lines 11 and 12 for the two ports, the write bit lines 13 and 14 for the respective ports, and the read word lines 15 to 17 for the respective three ports, Port read bit lines 18 to 20 are provided.

  FIG. 28 is a block diagram illustrating a configuration example of a register file including memory cells configured as shown in FIG. 28, the register file includes a memory cell array 200 in which memory cells are arranged in a 32-entry 32-bit configuration, an address decoder 210 that generates an address of the memory cell, a read data holding circuit 220 that holds read data from the memory cell, a memory It has a write data holding circuit 230 and a control circuit 240 that hold write data to the cell.

  From the outside, a 4-bit address for each of the write 2 ports and a 5-bit address for each of the 3 read ports are given to the register file. The address decoder 210 decodes a given address, and is connected to the memory cell array 200 by 64 write word lines with 32 entries and 2 ports and 96 read word lines with 32 entries and 3 ports. The read data holding circuit 220 and the memory cell array 200 are connected by a 32-bit read bit line for each of three ports, and the write data holding circuit 230 and the memory cell array 200 are connected by a 32-bit write bit line for each of two ports.

  FIG. 29 is a timing chart for explaining the operation of the register file shown in FIG. 26 and FIG. The register file operates in synchronization with the clock signal CLK, and is read at the H level of the clock signal CLK and written at the L level.

  In FIG. 29, when the clock signal CLK is at L level, the write word line specified by the write address of the selected port is at H level. If the port number is 0 and the word number is 1, the transfer gate 1 in FIG. Is turned on. As a result, the data of the write bit line 13 of port number 0 is stored in the storage element of word number 1 through the transfer gate 1.

  When the clock signal CLK is at the H level, the read word line specified by the read address of the selected port is at the H level, and the transistor 5 is turned on in FIG. . As a result, the data stored in the memory element having the word number 1 is read out to the read bit line 18 having the port number 0 through the transistor 6.

  The semiconductor integrated circuit has been continually improved in semiconductor technology in response to the ever-increasing demand for higher integration, and further miniaturization has progressed in semiconductor processing. Along with the miniaturization of semiconductor processing, the problem of malfunction caused by cross coupling noise between adjacent bit lines and word lines has become more serious.

  In addition, along with miniaturization, it is necessary to reduce drain leakage when performing a write operation to a memory cell by lowering the power supply voltage. However, if the drain leakage is reduced, the threshold value of the transistor increases, so Therefore, there is a problem that it is difficult to reduce the power supply voltage because ideal scaling according to the trend cannot be achieved.

  Further, in order to perform fine processing, the exposure wavelength is shortened in the manufacturing process. In order to realize the functional characteristics of the memory cell, it is desirable to optimize the mask data of the transistor in accordance with the shortening of the wavelength or to individually perform optical phase correction at the time of exposure. However, optimization of mask data requires an enormous amount of man-hours, and partial optical phase correction is difficult because exposure is performed on the entire wafer. Therefore, there is a problem that a memory cell must be designed on the assumption that mask data that can be compromised to some extent is used.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a memory device that can reduce cross-coupling noise of bit lines and word lines caused by fine processing of semiconductors.

  It is another object of the present invention to provide a memory device that can reduce the power supply voltage even in a microfabricated memory device. It is another object of the present invention to provide a memory device that can share the physical shape of transistors and prevent performance degradation even when mask data that can be compromised to some extent is used.

  In order to solve the above problems, a memory device according to claim 1 of the present invention corresponds to one or more read control signal lines (read word lines) for transmitting a read control signal to the memory cells, and each of the read word lines. In response to the activation of the read control signal, one or more read signal lines (read bit lines) for transmitting the memory cell information to the outside and one or more write control signal lines (for transmitting the write control signal to the memory cells) A write word line) and one or more write signal lines (write bit lines) corresponding to the write word lines and transmitting external information to the memory cells in response to activation of the write control signal. The read bit line and the write bit line are alternately arranged, and the read control signal and the write control signal There are those controlled so as not to be activated simultaneously.

  According to the above configuration, since the read word line and the write word line for the memory cell array are controlled so as not to be activated at the same time, the read bit line and the write bit line do not operate simultaneously, and the layout portion of the memory cell Since one of the bit lines serves as a shield, the bit lines do not interfere with each other, preventing read bit line malfunctions and write bit line malfunctions. be able to.

  A memory device according to a second aspect of the present invention is the memory device according to the first aspect, wherein the write control signal is transmitted to the outside in response to activation of the read control signal. It is activated after detection.

  According to the above configuration, since the write control signal is activated after detecting that the information of the memory cell is read to the read bit line, the operation control of the post-read write to the memory cell array can be made autonomous. Control can be ensured such that the read word line and the write word line are not activated simultaneously.

  According to a third aspect of the present invention, in the memory device according to the first or second aspect, the information of the memory cell is transmitted to the outside in response to the activation of the read control signal. It is inactivated after detecting this.

  According to the above configuration, since the read control signal is inactivated after detecting that the memory cell information is read to the read bit line, the read operation control for the memory cell array can be made autonomous. The read cycle can be shortened.

  A memory device according to a fourth aspect of the present invention is the memory device according to the second or third aspect, wherein a dummy memory cell is formed using a semiconductor element having the same shape as the semiconductor element forming the memory cell, and a read word line When the dummy memory cell circuit is configured to include a dummy read word line and a dummy read bit line having the same load characteristics as the read bit line, and the dummy memory cell is activated by the read control signal The fixed storage value is output to the dummy read bit line, and the detection of the memory cell information according to claim 2 or 3 is detected by detecting the fixed storage value in the dummy read bit line.

  According to the above configuration, by forming a dummy memory cell using transistors having the same shape as the memory cell, and by configuring the circuit so that the load characteristics of each signal line for controlling reading are the same, process variations and temperature 4. The information of the memory cell according to claim 2 or 3 is transmitted to the outside because the operating characteristic of each signal line in the dummy memory cell can be made coincident with the operating characteristic of the memory cell without depending on fluctuations or voltage fluctuations. Can be reliably detected.

  A memory device according to a fifth aspect of the present invention is the memory device according to the fourth aspect, wherein a dummy memory cell is formed using a semiconductor element having the same shape as the semiconductor element forming the memory cell, and the same as the write word line. A first dummy write word line having a load characteristic and receiving a read control signal, a second dummy write word line having the same load characteristic as the write word line and receiving a write control signal, and the same as the write bit line A dummy memory cell circuit is configured to include a dummy write bit line having a load characteristic and a dummy write value and a dummy write detection signal line having the same load characteristic as the read bit line, and the read control signal is activated. The dummy write value is written to the dummy memory cell according to the conversion, and the written dummy write value is By inverting the dummy write value when it is detected that the output to the over write detection signal line, in which writing dummy write value which is inverted in response to activation of the write control signal to the dummy memory cell.

  According to the above configuration, by forming a dummy memory cell using transistors having the same shape as the memory cell and configuring the circuit so that the load characteristic of each signal line for controlling writing is the same, process variations and temperature Because the operating characteristics of each signal line in the dummy memory cell can be made to match the operating characteristics of the memory cell without depending on fluctuations or voltage fluctuations, detection of dummy write values on the dummy write detection signal lines and inversion of dummy write values A series of operations for rewriting to the dummy memory cell can be ensured in accordance with the write cycle after reading, and the dummy memory cell can be initialized.

  According to a sixth aspect of the present invention, in the memory device according to the fifth aspect, the write control signal is output after detecting that the dummy write value written in the dummy memory cell is output to the dummy write detection signal line. Inactivate.

  According to the above configuration, since the write control signal is deactivated after detecting that the dummy write value is output from the dummy memory cell to the dummy write detection signal line, the write operation control to the memory cell array is made autonomous. And the write cycle can be shortened.

  According to a seventh aspect of the present invention, there is provided a memory device according to the sixth aspect, wherein a dummy write value is activated by activating a read control signal after giving a dummy write value in synchronization with a clock signal. Write to the cell, read the fixed memory value from the dummy memory cell, deactivate the read control signal, activate the write control signal, detect the dummy write value output by detecting the output of the dummy write value written to the dummy memory cell A series of operations consisting of inversion, writing of the inverted dummy write value to the dummy memory cell, and inactivation of the write control signal are repeated.

  According to the above configuration, since a series of post-read write operations are performed autonomously by activating the read control signal after giving a dummy write value in synchronization with the clock signal, process variations, temperature fluctuations, or voltage fluctuations It is possible to form the most efficient post-read / write cycle synchronized with the clock signal without depending on the clock signal, and since the series of operations does not depend on the clock duty ratio, there is no need to guarantee the clock duty. There is an effect.

  According to an eighth aspect of the present invention, in the memory device according to the first aspect, the read control signal is that external information is transmitted to the memory cell in response to activation of the write control signal. It is activated after detection.

  According to the above configuration, since the read control signal is activated after detecting that the information of the write bit line is written in the memory cell, the post-write read operation control with respect to the memory cell array can be made autonomous. Control to prevent the word line and the write word line from being activated simultaneously can be ensured.

  The memory device according to claim 9 of the present invention is the memory device according to claim 1 or 8, wherein external information is transmitted to the memory cell in response to the activation of the write control signal. It is inactivated after detecting this.

  According to the above configuration, since the write control signal is deactivated after detecting that the information of the write bit line is written in the memory cell, the write operation control to the memory cell array can be made autonomous. The cycle can be shortened.

  A memory device according to claim 10 of the present invention is the memory device according to claim 8 or 9, wherein a dummy memory cell is formed using a semiconductor element having the same shape as the semiconductor element forming the memory cell, and a write word line A first dummy write word line having the same load characteristics and a read control signal applied thereto, a second dummy write word line having the same load characteristics as the write word lines and provided with a write control signal, and a write bit line The dummy memory cell circuit is configured to include a dummy write bit line having the same load characteristics and a dummy write value and a dummy write detection signal line having the same load characteristics as the read bit line, and a write control signal The dummy write value is written to the dummy memory cell in response to the activation of the dummy write detection signal line. The detection of the dummy write value written to the dummy memory cells force in which external information according to claim 8 or 9, wherein the detection is performed that is transmitted to the memory cell.

  According to the above configuration, by forming a dummy memory cell using transistors having the same shape as the memory cell and configuring the circuit so that the load characteristic of each signal line for controlling writing is the same, process variations and temperature 10. The external information according to claim 8 or 9 is transmitted to the memory cell because the operating characteristic of each signal line in the dummy memory cell can be matched with the operating characteristic of the memory cell without depending on fluctuations or voltage fluctuations. Can be reliably detected.

  According to an eleventh aspect of the present invention, in the memory device according to the tenth aspect, the dummy write value is detected by detecting that the dummy write value written in the dummy memory cell is output to the dummy write detection signal line. The dummy write value that is inverted and inverted according to the activation of the read control signal is written to the dummy memory cell.

  According to the above configuration, the dummy write value is inverted by detecting the dummy write value in the dummy write detection signal line, and the dummy memory cell is rewritten in the read cycle. The operation can be ensured, and the dummy memory cell can be initialized.

  A memory device according to a twelfth aspect of the present invention is the memory device according to the tenth or eleventh aspect, wherein a dummy memory cell is formed using a semiconductor element having the same shape as the semiconductor element forming the memory cell, and the read word The dummy memory cell circuit is configured to have a dummy read word line and a dummy read bit line having the same load characteristics as the read line and the read bit line, and the dummy memory cell is activated by a read control signal. In this case, the fixed storage value is output to the dummy read bit line, and the read control signal is inactivated by detecting the fixed storage value in the dummy read bit line.

  According to the above configuration, by forming a dummy memory cell using transistors having the same shape as the memory cell, and by configuring the circuit so that the load characteristics of each signal line for controlling reading are the same, process variations and temperature Because the operating characteristics of each signal line in the dummy memory cell can be matched with the operating characteristics of the memory cell without depending on fluctuations or voltage fluctuations, the read control signal is inactivated by detecting the fixed storage value in the dummy read bit line. Thus, the read operation control for the memory cell array can be made autonomous, and the read cycle can be shortened.

  According to a thirteenth aspect of the present invention, there is provided a memory device according to the twelfth aspect, wherein a dummy write value is activated by activating a write control signal after giving a dummy write value in synchronization with a clock signal. Write to cell, inversion of dummy write value by detection of dummy write value written at output of dummy memory cell, inactivation of write control signal, activation of read control signal, dummy memory with inverted dummy write value A series of operations consisting of writing to a cell, reading a fixed storage value from a dummy memory cell, and inactivating a read control signal are repeated.

  According to the above configuration, since a series of post-write read operations are performed autonomously by activating the write control signal after giving a dummy write value in synchronization with the clock signal, process variations, temperature fluctuations, or voltage fluctuations It is possible to form the most efficient post-write and read cycle synchronized with the clock signal without depending on the clock signal, and it is not necessary to guarantee the duty of the clock because the series of operations does not depend on the clock duty ratio. There is an effect.

  A memory device according to a fourteenth aspect of the present invention is the memory device according to any one of the first to thirteenth aspects, wherein the read word lines and the write word lines are alternately arranged as much as possible. .

  According to the above configuration, in the memory device according to any one of claims 1 to 13, since the read word line and the write word line for the memory cell array are controlled not to be activated simultaneously, the read word line and the write By physically arranging the word lines alternately, one of the word lines serves as a shield, and an effect of preventing cross coupling noise between the word lines can be obtained.

  A memory device according to a fifteenth aspect of the present invention is the memory device according to any one of the first to fourteenth aspects, wherein the substrate voltage of the MOSFET constituting the memory element in the memory cell is activated when the read control signal is activated. The absolute value is set higher than the absolute value of the signal voltage applied to the storage element.

  According to the above configuration, by making the absolute value of the substrate voltage of the MOSFET constituting the storage element higher than the absolute value of the signal voltage applied to the storage element, the absolute value of the threshold can be increased. As a result, the noise resistance is increased, and when the voltage drop due to the cross-coupling effect occurs in the write word line due to the fall of the read word line, the write malfunction is less likely to occur. That is, the current between the source and drain of the MOSFET is reduced.

  The memory device according to claim 16 of the present invention is the memory device according to any one of claims 1 to 14, wherein an absolute value of a substrate voltage of a transfer gate in the memory cell when the read control signal is activated. Is made higher than the absolute value of the signal voltage applied to the storage element.

  According to the above configuration, even if it is difficult to boost only the substrate voltage of the MOSFET for layout reasons, it is possible to increase the glitch (when the write word line is not selected, the write word line by boosting the substrate voltage of the transfer gate in the memory cell). If the line is “H”, even if a voltage drop occurs in the write word line), it is possible to obtain an effect that it is difficult for a write malfunction to occur.

  A memory device according to a seventeenth aspect of the present invention is the memory device according to the sixteenth aspect, wherein the substrate voltage of the P-channel MOSFET of the transfer gate is increased.

  According to the above configuration, the decrease in the speed of the readout system can be minimized by boosting the substrate voltage of the P-channel MOSFET of the transfer gate.

  A memory device according to an eighteenth aspect of the present invention is the memory device according to any one of the first to seventeenth aspects, wherein an inversion logic controlled by a write control signal is applied to a write control circuit that writes information into a memory cell. A transfer gate switch including a circuit includes a MOSFET having a gate connected to an output of an inverting logic circuit, a drain connected to a write word line, and a source connected to a power supply or a ground.

  According to the above configuration, the impedance of the write word line is reduced due to the current path generated in the write word line when the read word line falls due to the MOSFET, so the ratio of the coupling capacitance with the read word line is small. Thus, the effect of being hardly affected by the cross coupling noise can be obtained.

  A memory device according to a nineteenth aspect of the present invention is the memory device according to any one of the first to eighteenth aspects, wherein the gate is connected to an input of an inverting logic gate that drives the read word line, and the source is a write control signal. Is connected to the output of the normal logic gate to which is inputted, and the MOSFET whose drain is connected to the write word line is provided as the drive source of the write word line.

  According to the above configuration, the MOSFET causes the impedance of the write word line to be higher than when connected to the power supply, and the transient response speed of the power supply voltage drop due to the coupling caused by the fall of the read word line is reduced. The voltage value of the write word line can be kept high and the power supply voltage drop can be absorbed.

  A memory device according to a twentieth aspect of the present invention is the memory device according to any one of the first to nineteenth aspects, wherein the gate is connected to the output of the inverting logic gate that inputs the read control signal, and the source is the write control signal. Is connected to the output of the normal logic gate, and the MOSFET has a drain connected to the write word line at the middle or end of the write word line.

  According to the above configuration, even if the read word line falls, the voltage of the write word line can be maintained at the power supply voltage for the time corresponding to the delay of the normal logic gate, so that the read word line cross-couples to the write word line Noise is less likely to occur and erroneous writing can be prevented.

  In a memory device according to a twenty-first aspect of the present invention, a memory element in a memory cell is composed of first and second inversion logic gates, and a reset signal line is provided as a first source of the first inversion logic gate. The reset signal applied to the reset signal line is fixed to be inactive during memory cell read and write operations, and the reset signal is activated at other times than the read and write operations to change the state of the storage element to a desired value. It is to make.

  A memory device according to a twenty-second aspect of the present invention is the memory device according to the twenty-first aspect, wherein a first source of the first inversion logic gate and a first source of the second inversion logic gate in the first source of the first inversion logic gate. When the source and the second source are made to correspond to each other, an inverted reset signal line for applying an inverted signal of the reset signal to the second source of the second inverted logic gate is connected.

  According to a twenty-third aspect of the present invention, in the memory device of the twenty-first or twenty-second aspect, the reset signal is activated by a signal indicating completion of writing to the memory cell.

  According to the above configuration, the memory element in the memory cell can be initialized within one cycle even when the write word line is inactive by adopting a circuit configuration in which the reset signal is supplied to the memory element in the memory cell. it can. By adopting such a structure, the physical shape of the transistor can be shared with other memory cells, and performance degradation can be prevented even with mask data that can be compromised to some extent.

  According to a twenty-fourth aspect of the present invention, in the memory device, the storage element in the memory cell is composed of first and second inversion logic gates, and the first source of the transistor constituting the first inversion logic gate Is connected to a negative signal of the logical product of the write control signal and the write signal, and a logical product signal of the write control signal and the inverted write signal is connected to the second source of the transistor constituting the first inverted logic gate. A negative signal of the logical product of the write control signal and the inverted write signal is connected to the first source of the transistor that constitutes the second inverted logic gate, and the second source of the transistor that constitutes the second inverted logic gate. The source of this is connected to the logical product signal of the write control signal and the write signal.

  According to the above configuration, with respect to the two inverted logic gates constituting the storage element in the memory cell, the sources of the transistors constituting the respective inverted logic gates are set by the write signal and its inverted signal according to the write control signal. By controlling, it is possible to release the feedback strength of the feedback inverter inside the memory cell, so that writing is easy even if the power supply voltage is lowered, and the voltage of the memory device can be reduced.

  A memory device according to a twenty-fifth aspect of the present invention is the memory device according to the twenty-fourth aspect, comprising a combination of a plurality of the write control signals and the write signals, wherein the memory element in the memory cell includes the write control signal and The same number and combination of two inverted logic gates associated with the write control signal are used, and the corresponding points of the gates and drains of the transistors constituting the respective inverted logic gates are connected in parallel. The sources of the transistors constituting the inverting logic gate are connected to the write control signal and the signal generated by the write signal associated with each inverting logic gate.

  According to the above configuration, a plurality of sets of inversion logic gates can be connected in parallel accordingly, so that a memory element circuit capable of obtaining the same effect as the memory device according to claim 22 can be configured. Also in the memory device, the voltage of the memory device can be reduced.

  As described above, according to the present invention, it is possible to avoid simultaneous operation of the read bit line and the write bit line by controlling the read word line and the write word line for the memory cell array so as not to be activated at the same time. By alternately arranging read word lines and write word lines in the cell layout portion, the bit lines can serve as a shield, and malfunctions of the read bit lines due to cross-coupling noise between the bit lines can be achieved. An excellent effect is obtained that the malfunction of the write bit line can be prevented.

  Furthermore, according to the present invention, by forming a dummy memory cell using transistors having the same shape as the memory cell and making the circuit so that the load characteristics of each signal line are the same, process variations, temperature fluctuations or voltage Since the operation characteristics of each signal line in the dummy memory cell can be matched with the operation characteristics of the memory cell without depending on the fluctuation, the memory device can be obtained by configuring a read and write control system using the dummy memory cell. An excellent effect can be obtained that the operation can be performed autonomously and efficiently in synchronization with the clock signal, and the control for preventing the read word line and the write word line from being simultaneously activated can be ensured.

  Furthermore, according to the present invention, the write word by the fall of the read word line is controlled by controlling the threshold value by increasing the substrate voltage of the MOSFET constituting the memory element in the memory cell or by controlling the impedance of the write control signal. Since the cross coupling noise to the line can be reduced, an excellent effect of preventing erroneous writing can be obtained.

  Furthermore, according to the present invention, the memory element in the memory cell can be initialized within one cycle even when the write word line is inactive by adopting a circuit configuration that applies a reset signal to the memory element in the memory cell. By adopting such a structure, the physical shape of the transistor can be shared with other memory cells, and an excellent effect can be obtained that performance degradation can be prevented even with mask data that can be compromised to some extent.

  Furthermore, according to the present invention, the source voltage is controlled by controlling the source of each of the two inverted logic gate transistors constituting the memory element in the memory cell with the write signal and its inverted signal according to the write control signal. Even if it is lowered, writing becomes easier and the voltage of the memory device can be reduced. Furthermore, by forming a similar circuit by connecting a plurality of sets of inversion logic gates in parallel, an excellent effect is obtained that the voltage of the memory device can be reduced even in a memory device having multiple ports. .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing a configuration example of a memory device according to Embodiment 1 of the present invention. FIG. 1A is a circuit diagram showing a configuration example of a memory cell of a register file having two write ports and three read ports as the memory device of this embodiment, and FIG. 1B is a circuit diagram of FIG. It is a figure which shows the physical arrangement | positioning of the write bit line and read bit line of a memory cell.

  In FIG. 1A, the same components as those in the configuration example of the conventional memory device shown in FIG. That is, the memory cell includes transfer gates 1 and 2 for inputting write data, a storage element including inverters 3 and 4 for storing data, and NMOS transistors 5 to 10 for reading data from the storage element. Furthermore, the configuration shown in FIGS. 1C and 1D may be used.

  Further, as signal lines for controlling the writing and reading of the memory cells, the write word lines 11 and 12 for the two ports, the write bit lines 13 and 14 for the respective ports, and the read word lines 15 to 17 for the respective three ports, Port read bit lines 18 to 20 are provided.

  Of these signal lines, the write bit lines and the read bit lines are physically arranged alternately in the layout portion 21 of the memory cell as shown in FIG. In other words, the bit line 13 of the write port 0 is between the bit line 18 of the read port 0 and the bit line 19 of the read port 1, and the bit line 14 of the write port 1 is the bit line 19 of the read port 1 and the bit of the read port 2. Arranged between the lines 20.

  As described above, in the memory device of this embodiment, when the number of write ports and the number of read ports is the same, the write bit lines and the read bit lines can be alternately arranged at all bit positions. If the number of ports is different, arrange them as much as possible. For example, in the case of a memory cell having one write port and three read ports, it is inevitable that two read bit lines are adjacent to each other. Further, in a two-column configuration, when the ports to be read are different between the odd period and the even period of the clock, the read ports may be adjacent to each other.

  FIG. 2 shows an example of the layout layout of each port under the condition that there are four read ports and two write ports, of which read bits rd data0 to rd data2 and read bit rd data3 are read at different periods. .

  FIG. 3 is a block diagram illustrating a configuration example of a register file including memory cells configured as shown in FIG. In FIG. 3, the register file includes a memory cell array 201 in which memory cells are arranged in a 33-entry 33-bit configuration, an address decoder 211 that generates an address of the memory cell, a read data holding circuit 221 that holds read data from the memory cell, A write data holding circuit 231 and a control circuit 241 for holding write data to the memory cell are provided.

  Here, the memory cell array 201 has a configuration in which one dummy entry and one dummy bit are added to a normal 32 entry 32-bit memory cell array. Therefore, in comparison with the memory cell array 200 of FIG. 28, the memory cell array 201 has a dummy memory cell A having 1 dummy entry and 1 dummy bit structure, a dummy memory cell B having 1 dummy entry and a 32 bit structure, and a dummy having 32 entry and 1 dummy bit structure. A memory cell C is added.

  Here, the dummy memory cell A outputs a fixed storage value to the dummy read bit line in the reading regardless of the writing. Further, in writing, in order to detect that a dummy write value is written, a dummy write detection signal line for outputting the written value to the outside is provided.

  The dummy memory cell B and the dummy memory cell C are memory cells having a 32-entry 32-bit configuration in which the load characteristic of each signal line of the dummy memory cell A stores original data when the dummy memory cell A is added. The circuit structure is added so as to be the same as the load characteristic of each signal line. In the dummy memory cell B, the capacity of the read word line and the write word line is equivalent to that of a normal memory cell, and in the dummy memory cell C, the capacity of the read bit line and the write bit line is equivalent to that of a normal memory cell. I have to.

  Further, as an alternative configuration of the register file including the memory cells, it is preferable to use a dummy memory cell layout as shown in FIG. In this layout, in addition to the dummy cell located on the left side of FIG. 3, the dummy cell located in the center and the dummy cell located on the right side are arranged symmetrically from the center line of the memory cell array. By balancing the dummy memory cells in this way, the operation can be made more stable. By configuring these dummy memory cells using transistors having the same shape as the memory cell shown in FIG. 1, the load characteristic of each signal line can be made the same as that of the memory cell array 301, and an inverter or the like can be used instead. Compared with the case where the delay characteristic is approximated, it is possible to approximate the load characteristic including process variation, temperature variation or voltage variation.

  A 5-bit address for each of the write 2 ports, a 5-bit address for each of the 3 read ports, a clock signal CLK, and a select signal for selecting this register file are given to the register file from the outside. Each port is interfaced with the 32-bit data input / output signal.

  The address decoder 211 decodes a given address, and the memory cell array 201 includes a read word for the dummy memory cell A in addition to 64 write word lines with 32 entries and 2 ports and 96 read word lines with 32 entries and 3 ports. A line and a write word line are added and connected. The read data holding circuit 221, the write data holding circuit 231 and the memory cell array 201 include a dummy read bit line and a dummy write bit line in addition to a 32-bit read bit line for each of the three ports and a 32-bit write bit line for each of the two ports. The dummy write detection signal line is added and connected.

  In the memory device configured as described above, according to the present invention, the read word line and the write word line are controlled so as not to be activated simultaneously. FIG. 5 is a circuit diagram showing a detailed circuit configuration example for controlling writing and reading of the register file having the above configuration. FIG. 5 also shows a circuit configuration example of the dummy memory cell A. An example of the circuit configuration of the dummy memory cell B is shown in FIG. 6, and an example of the circuit configuration of the dummy memory cell C is shown in FIG.

  5, the memory cell array 201 includes a memory cell array 301 having a 32-entry 32-bit configuration, a dummy memory cell A302 having a 1-dummy entry 1-dummy bit configuration, and dummy memory cells B303, 32 having a 1-dummy entry 32-bit configuration, as described above. The dummy memory cell C304 has an entry 1 dummy bit configuration. A word line control block 305 controls activation of the write word line and the read word line.

  In FIG. 5, 311, 312, and 313 are flip-flops, 321 is a read row decoder that activates a read word line of the memory cell array 301, 322 is a write row decoder that activates a write word line of the memory cell array 301, Is a read dummy row decoder for activating the read word line of the dummy memory cell A, 324 is a first write dummy row decoder for activating the first dummy write word line of the dummy memory cell A, and 325 is a dummy memory cell A This is a second write dummy row decoder for activating the second dummy write word line.

  Further, in FIG. 5, 331 is a clock signal, 332 is a select signal, 333 is a dummy write bit line for giving a dummy write value to the dummy memory cell A, 334 is an output of the flip-flop 312 for giving a read control signal, 335 is a dummy A dummy read bit line from which a fixed storage value is read from the memory cell A, 336 is an output of the flip-flop 313 that gives a write control signal, and 337 is a dummy write detection signal line for reading the dummy write value written in the dummy memory cell A.

  Further, FIG. 8 is a timing chart for explaining the operation of the control circuit shown in FIG. The operation of a register file composed of multi-port memory cells by the memory device of this embodiment will be described below with reference to FIGS. In FIGS. 7 and 4, the correspondence between the signal timing and the operation circuit is indicated by a number in the circle. In the following explanation, it is written as (○ number).

  First, in the initial state, when the select signal changes from the L level to the H level, the flip-flops 311, 312, and 313 are in the reset state, and the Q output is at the L level. Next, when the clock signal CLK is input, the flip-flop 311 changes from L level to H level (（1). As a result, the flip-flop 312 is changed from the L level to the H level (○ 2), and the read row decoder 321, the read dummy decoder 323, and the first write dummy row decoder 324 are activated.

  In response to this, the dummy write value given from the output of the flip-flop 311 on the dummy write bit line 333 is written to the dummy memory cell A, and the fixed storage value is output from the dummy memory cell A to the dummy read bit line 335. (○ 3). By this fixed storage value, the flip-flop 312 is reset and the Q output changes to the L level, the read row decoder 321 and the read dummy decoder 323 become inactive (（3), and the read cycle ends.

  Next, since the clock input of the flip-flop 313 becomes H level by the fixed storage value read to the dummy read bit line 335, the Q output of the flip-flop 313 becomes H level, and the write row decoder 322 and the second write The dummy row decoder 325 is activated (○ 4).

  Further, the flip-flop 311 is reset by the dummy write value read to the dummy write detection signal line 337 (（5), and the dummy write bit line is inverted to the L level. Data is written in the memory cell A. At the same time, the flip-flop 313 is reset, the write row decoder 322 and the second write dummy row decoder 325 become inactive (○ 6), and the write cycle is completed. Note that when writing 0 or 1, it is important to use a dummy configuration in which the write period is delayed as the write word line activation period.

  Thus, the operation of one cycle of writing after reading is completed. As described above, since the read cycle and the write cycle are generated using the flip-flops 311, 312, and 313 with reset, the read cycle and the write cycle do not depend on the duty ratio of the clock as compared with the case where the inverted edge of the clock signal is used. There is an effect that it is not necessary to guarantee the duty of the clock. Further, since each of the read operation and the write operation does not depend on the duty ratio, there is an effect that it is possible to prevent a speed change due to clock system factors (jitter, change in duty ratio due to process variation).

  The activation period of the word line guarantees the minimum time for reading and writing from the memory cell, so if there is a cell with a current capability inferior to that of the dummy memory cell, it will be rejected in the initial test. The configuration of the form is a very excellent configuration in terms of quality assurance against aging. If the dummy memory cell itself is defective, the dummy memory cell does not operate at a specified frequency, and is therefore rejected in the initial test.

  As described above, since the read word line and the write word line for the memory cell array 310 are controlled so as not to be activated at the same time, the read bit line and the write bit line do not operate simultaneously, and the memory cell Since the physical layout is alternately arranged in the layout section, either bit line serves as a shield, so there is no interference between the bit lines, preventing malfunction of the read bit line and malfunction of the write bit line. There is an effect. In the present embodiment, two write row decoders for dummy memory cells are prepared, and each is activated by activation of the read row decoder and activation of the write row decoder. However, information stored in the dummy memory cell A Can be initialized within one cycle, the number of write row decoders for dummy memory cells may be one. Moreover, although the case where one port of the dummy cell is used for detection is shown, a plurality of dummy cells may be used, or detection may be performed from information of multiple ports. In that case, the accuracy is further increased.

  FIG. 16 is a circuit diagram showing a circuit configuration example for initializing the inside of the dummy memory cell. In FIG. 16, reference numerals 31 and 32 denote first and second inverters constituting the storage element in the dummy memory cell, 33 denotes a first source of the first inverter serving as a reset terminal, and 34 denotes a power source. The second source of the first inverter, 35 is the first source of the second inverter that is grounded, and 36 is the second source of the second inverter that becomes the inverting reset terminal.

  Here, by connecting the Q output of the flip-flop 311 to the reset terminal 33 and inputting the inversion information of the Q output of the flip-flop 311 to the inversion reset terminal 36, even if the write word line is inactive, within one cycle It is initialized to. Further, by adopting such a structure, it is possible to reset the dummy memory cell without inserting a special transistor and without changing the physical shape of the transistor constituting the circuit. By doing so, the physical shape of the transistor can be shared with other memory cells, and performance degradation can be prevented.

  In addition, it is necessary to lower the power supply voltage along with the fine processing, but also in this case, the writing operation to the memory cell must be guaranteed. FIGS. 17A and 17B are circuit diagrams showing a basic configuration of a memory cell capable of writing operation at a low voltage according to the present invention. In FIG. 17A, reference numerals 37 and 38 respectively denote first and second inverters constituting the memory element in the memory cell. In FIG. 17B, reference numerals 39 to 42 denote a write word line and a write bit line. It is a logic circuit that generates a signal that is input and applied to the sources of the transistors constituting the first and second inverters.

  Specifically, when the signal of the write word line is WE and the signal of the write bit line is WD, the logic circuit 39 applies a logical product of WE and WD to the first source IN1 of the transistor constituting the first inverter. A negative signal is given, and a logical product signal of WE and inverted WD is given by the logic circuit 40 to the second source IN2 of the transistor constituting the first inverter, and the first source IN3 of the transistor constituting the second inverter is given. The logic circuit 41 gives a negative signal of the logical product of WE and inverted WD, and the logical circuit 42 gives a logical product signal of WE and WD to the second source IN4 of the transistor constituting the second inverter. By doing so, the strength of feedback of the feedback inverter in the memory cell can be released, so that writing is easy even if the power supply voltage is lowered.

  Further, regarding the signal levels of Sn1, Sn2, Sn3, and Sn4 as shown in FIG. 16 (a), where VDD is a power supply voltage and VSS is a ground voltage, the signal levels are VDD or VSS. The voltage fluctuates +/− 0.4V from either voltage value. By varying the substrate voltage in this way, a lower write voltage can be more easily achieved.

  FIG. 18 is a circuit diagram showing a basic configuration of a write 2-port memory cell capable of a write operation at a low voltage according to the present invention, as an application example of this type of multi-port memory cell. In FIG. 18, the memory cell corresponding to write port 0 is constituted by inverters 43 and 45, the memory cell corresponding to write port 1 is constituted by inverters 44 and 46, and the gates of the transistors constituting inverter 43 and inverter 44 Are connected in parallel, and the gates and drains of the transistors constituting the inverter 45 and the inverter 46 are connected in parallel. In this way, the inverters 43 and 44 and the inverters 45 and 46 are respectively the first and second inverters constituting the memory element of the write 2-port memory cell.

  Here, with respect to the sources WR0IN1, WR0IN2, WR0IN3, and WR0IN4 of the transistors constituting the inverters 43 and 45 corresponding to the write port 0, the write word line signal and the write bit line signal corresponding to the write port 0 are shown in FIG. To the source WR1IN1, WR1IN2, WR1IN3, WR1IN4 of the transistors constituting the inverters 44 and 46 corresponding to the write port 1, and the signal of the write word line corresponding to the write port 1 is applied. A signal generated by a logic circuit similar to that of FIG. 17 is given from the signal and the signal of the write bit line.

  By doing so, the same method as the circuit method shown in FIG. 17 can be realized in the multi-port memory cell, so that the feedback strength of the feedback inverter in the multi-port memory cell can be released. Writing is easy even if the power supply voltage is lowered.

  If it is clear that the write bit line is not critical in the operation of the register file of this embodiment, that is, if the bit line is clearly determined rather than the write word line being activated, FIG. The circuit configuration shown in (1) can be simplified. 24 is a circuit diagram showing an example of a simplified circuit configuration for controlling writing and reading of the register file configured as shown in FIGS. 1 and 3, and FIG. 26 is an operation of the control circuit shown in FIG. It is a timing chart explaining these.

  In FIG. 24, the same components as those in the circuit configuration example of FIG. In addition, a component having the same reference numeral with a suffix a indicates that the dummy memory cell A of 302a has the same role but has a different circuit configuration, and has the same role in the flip-flop 312a and the first write dummy row decoder 324a. However, the connection relationship is changed. In this case, since the write bit line is not critical, the flip-flop 311 in FIG. 5 is not necessary, and the write bit line of the dummy memory cell A has the first write data as the power supply and the second write data in the memory cell. Is connected to ground. Further, there are a reading circuit and a writing circuit. The read circuit includes a circuit that is switched by a control signal that is shifted in the same sequence as the read address enable signal. These may be FIG. 25 (a), or FIG. 25 (b) for higher speed. Thereby, when the address enable signal becomes “L”, the output of the read data does not change even if the read bit line is precharged.

  Simultaneously with the activation of the clock signal CLK, the flip-flop 312a is activated, and the read row decoder 321 and the read dummy decoder 323 are activated (○ 2). When a fixed storage value is output from the dummy memory cell A to the dummy read bit line 335 (◯ 3), the flip-flop 312 is reset and the flip-flop 313 is set, whereby the read cycle is completed and the write cycle is completed. Started (○ 4).

  On the other hand, the first write dummy row decoder 324a is activated by an inverted signal of the Q output of the flip-flop 313 during the read cycle, and the write value of the dummy memory cell A is initialized by writing from the power source inside the dummy memory cell A. When the write cycle is started, the second write dummy row decoder 325 is activated by the Q output of the flip-flop 313, the write is performed from the ground inside the dummy memory cell A, and this change is detected by the dummy write detection signal line 337. By detecting it, the writing cycle is terminated (○ 6).

  If it is clear that the write bit line is not critical in this way, the circuit configuration can be simplified by taking this into consideration, so that the area and power consumption of the semiconductor integrated circuit chip can be reduced. There is an effect that can be.

  In the first embodiment, a method of performing writing after reading in one cycle operation in synchronization with the clock signal has been described. Similarly, reading after writing may be performed in one cycle operation in synchronization with the clock signal. it can. FIG. 9 is a circuit diagram showing a detailed circuit configuration example for controlling writing and reading according to the second embodiment of the register file configured as shown in FIGS. Furthermore, when the write input data is transmitted to the write bit line in the multi-port memory, when the transition overlaps the read bit line transition, between the flip-flop receiving the write input data and the write bit line, A switch controlled by a signal line that transitions in the same sequence as the write address enable signal may be inserted. This slightly increases the write cycle time, but avoids interference between the read and write bit lines. FIG. 10 shows a circuit diagram thereof.

  With respect to the circuit of FIG. 10, each write dummy cell is directly connected to ground or a power supply. However, it is also possible to change the direct connection in this way by placing a resistor between the ground and the power source. The resistance value at this time is the same as the resistance value of the writing circuit.

  In addition, in order to speed up read access, an example in which a dynamic decoder as shown in FIGS. 11A and 11B is used for a row decoder is shown. Since this row decoder does not need to receive an input address by a flip-flop or a latch, the address setup and hold time is shortened accordingly. If the failure of the interface between the multi-port memory and another block for which an address is generated is observed, a flip-flop that operates as a shift register may be placed in the failure diagnosis. Further, since the operation time of the read data and the write data is different in this multi-port memory, as shown in FIGS. 12 (a) and 12 (b), the final decoded portion of the address is written and shared by the read word line. It is also possible to reduce the area of the address decoder by switching with the address enable signal in the last part.

  FIG. 13 shows an example of a hierarchical memory in which the memory cell array is divided into two in the row direction (Bank 1 and Bank 2). In this case, the write bit lines are not hierarchized, and the read bit lines are hierarchized. FIG. 14 shows the arrangement of dummy memory cells in such a case. The dummy memory cell A1 is for read system delay compensation, and the dummy memory cell A is a write time compensation circuit. For the write detection signal, no wiring is specified, but it is desirable that the write bit line, the word line, the read local bit line, the read global line, and the word line have the same structure as that of the original memory cell.

  In FIG. 9, the same components as those in the circuit configuration example of FIG. In addition, the constituent elements having the same symbol and the subscript b have the same role, but the connection relationship is changed. That is, FIG. 9 differs from FIG. 5 in that the clock input of the flip-flop 313b is directly connected to the clock signal 331, and the flip-flop 312b is set by the reset signal of the flip-flop 313b.

  FIG. 15 is a timing chart for explaining the operation of the control circuit shown in FIG. The operation of the register file composed of multi-port memory cells by the memory device of the present embodiment will be described below with reference to FIGS. In FIG. 8 and FIG. 14, the correspondence relationship between the signal timing and the operation circuit is indicated by numerals in the circles, and the following description is the same as in the first embodiment in that it is described as (circle numerals).

  First, in the initial state, when the select signal changes from the L level to the H level, the flip-flops 311, 312 b and 313 b are in the reset state, and the Q output is at the L level. Next, when the clock signal CLK is input, the flip-flop 311 and the flip-flop 313b change from L level to H level (レ ベ ル 1). As a result, the write row decoder 322 and the second write dummy row decoder 325 are activated (○ 2).

  In response to this, the dummy write value on the dummy write bit line 333 is written into the dummy memory cell A. Next, when the dummy write value is read to the dummy write detection signal line 337 (◯ 3), the flip-flop 311 and the flip-flop 313b are thereby reset, and the write row decoder 322 and the second write dummy row decoder 325 It becomes inactive and the write cycle ends (◯ 4).

  At the same time, the flip-flop 312b is set (○ 5), the read row decoder 321, the read dummy decoder 323, and the first write dummy row decoder 324 are activated to start a read cycle. Here, since the flip-flop 311 is reset, the inverted dummy write value is written into the dummy memory cell A, whereby the write value of the dummy memory cell A is initialized.

  Next, when a fixed storage value is output from the dummy memory cell A to the dummy read bit line 335 (○ 6), the flip-flop 312b is reset by this fixed storage value, and the read row decoder 321 and the read dummy decoder 323 are not activated. It becomes active and the read cycle ends.

  Thus, the operation of one cycle of reading after writing is completed. As described above, since the read word line and the write word line for the memory cell array 301 are controlled so as not to be activated at the same time, the read bit line and the write bit line do not operate simultaneously, and the memory cell Since the physical layout is alternately arranged in the layout section, one of the bit lines serves as a shield, there is no interference between the bit lines, and malfunction of the read bit line or malfunction of the write bit line can occur. There is an effect to be prevented.

  In the present embodiment, a write operation is possible even with a memory cell having a circuit configuration for initializing the dummy memory cell shown in FIG. 16 or with a low voltage shown in FIGS. 17 (a), 17 (b) and 17. Even if the memory cell is used, the same effect as that of the first embodiment is exhibited.

  In the first and second embodiments described above, the read word lines and the write word lines are alternately physically arranged in the memory cell layout portion and controlled so as not to be activated at the same time. Although the effect of preventing malfunction due to cross coupling noise has been described, a circuit configuration for enhancing noise resistance in the memory device according to the present invention will be described below.

  19 (a) and 19 (b) are diagrams showing a configuration example of a memory device for controlling the substrate voltage of the MOSFET according to the embodiment of the present invention. FIG. 19A is a circuit diagram showing a configuration example of a memory cell of a register file having two write ports and three read ports as a memory device, and FIG. 19B is a write word of the memory cell of FIG. It is a figure which shows the physical arrangement | positioning of a line and a read word line line.

  19A and 19B, the same components as those in the circuit configuration example of the memory device illustrated in FIGS. 1A to 1D are denoted by the same reference numerals. That is, the memory cell includes transfer gates 1 and 2 for inputting write data, a storage element including inverters 3 and 4 for storing data, and NMOS transistors 5 to 10 for reading data from the storage element. Read word lines 11 and 12, and 3 port read word lines 15 to 17, and a P-channel NWELL 22 constituting a memory cell is provided with a signal input line NW.

  Here, in the first and second embodiments, the read word line and the write word line for the memory cell array are controlled so as not to be activated at the same time. Therefore, the read word lines 15 to 17 and the write word lines 11 and 12 are controlled. Since one of the word lines serves as a shield, the effect of preventing cross coupling noise between the word lines can be obtained.

  FIG. 20 is a timing chart for explaining the operation of the register file using the memory cell shown in FIG. In FIG. 20, while the read word line is activated, the substrate voltage of the MOSFET applied to the signal input line NW is boosted higher than the power supply voltage. As a result, the threshold value of the P-channel MOSFET becomes a value (−Vth−δV) lower than the normal value. Normally, a voltage drop due to the cross coupling effect is observed on the write word line due to the fall of the read word line. However, according to the embodiment of FIG. 19, the threshold value is lowered by −δV. Compared to the case where there is no noise, the noise resistance is increased by −δV, and even if a glitch is applied, an effect that a write malfunction hardly occurs can be obtained. For the sake of layout, only the transfer gate may be set higher than the substrate voltage. In this case, it is preferable for maintaining the speed that the substrate voltage of the N-channel MOSFET constituting the read port is not boosted.

  FIG. 21 is a circuit diagram showing a configuration example of a memory cell having a write 2 port and a read 3 port as a memory device for controlling the impedance of the control signal according to the embodiment of the present invention.

  In FIG. 21, the same components as those in the circuit configuration example of the memory device shown in FIG. That is, the memory cell includes transfer gates 1 and 2 for inputting write data, a storage element including inverters 3 and 4 for storing data, and NMOS transistors 5 to 10 for reading data from the storage element. Read word lines 11 and 12, and 3 port read word lines 15 to 17, and further, a drain and a gate are connected to the write word line for controlling the transfer gate and its inverted logic circuit output, respectively, and the source to the power supply A connected P-channel MOSFET 23 is provided.

  This P-channel MOSFET 23 reduces the impedance of the write word line by causing a current path other than the P-channel MOSFET of the inverter at the final stage of the write row decoder when the read word line falls. As a result, the ratio of the coupling capacitance is reduced, and the effect of being hardly affected by the cross coupling noise can be obtained.

  FIG. 22 is a circuit diagram showing a configuration example of a cross coupling noise removing circuit in the memory device according to the embodiment of the present invention. The cross coupling noise elimination circuit of FIG. 22 is arranged at the word line drive source. In FIG. 22, the input of a buffer for driving a read word line RWD is connected to the gate of a P-channel MOSFET 24, the output of a two-stage inverter for inputting the write word line WWD is connected to the source, and the write word is connected to the drain. Line WWD is connected.

  By connecting the output of the two-stage inverter that inputs the write word line WWD to the source of the P-channel MOSFET 24, the impedance becomes higher than when connected to the power supply, and the word line generated by the fall of the read word line RWD The transient response speed of the power supply voltage drop due to the coupling with the power supply line becomes slow. Therefore, the voltage value of the source of the P-channel MOSFET 24 can be maintained higher, and the power supply voltage drop of the drive capability of the P-channel MOSFET 24 can be absorbed. Further, since it can also be used as an inverting logic circuit for driving the read word line, the area of the semiconductor integrated circuit chip can be reduced.

  FIG. 23 is a circuit diagram showing another configuration example of the cross coupling noise removing circuit in the memory device according to the embodiment of the present invention. The cross coupling noise elimination circuit of FIG. 23 is arranged at the middle or end point of the word line. In FIG. 23, the output of the inverter that inputs the read word line RWD is connected to the gate of the P-channel MOSFET 25, the output of the two-stage inverter that inputs the write word line WWD is connected to the source, and the write word is connected to the drain. Line WWD is connected.

  By arranging this circuit in the middle or end point of the word line, even when the read word line falls, WWD is maintained at VDD for the time of the delay of the inverter, and the write word line to the write word line by the read word line RWD is maintained. Cross coupling noise hardly occurs, and erroneous writing can be prevented.

  A memory device according to the present invention avoids simultaneous operation of a read bit line and a write bit line by controlling so that a read word line and a write word line for a memory cell array are not activated simultaneously, and a memory cell layout unit By alternately arranging the read word line and the write word line in FIG. 1, the bit line can serve as a shield, and malfunction of the read bit line due to cross coupling noise between the bit lines and the write bit line This has the effect of preventing malfunction and is useful for a memory device having multiple ports.

FIGS. 3A to 3D are diagrams showing a configuration example of a memory device according to Embodiment 1 of the present invention. FIGS. The figure which shows the layout arrangement | positioning of 2 column structure by the memory device which concerns on Embodiment 1 of this invention. 1 is a block diagram showing a configuration example of a register file by a memory device according to Embodiment 1 of the present invention. The block diagram which shows the structural example which changed the register file by the memory device which concerns on Embodiment 1 of this invention. FIG. 3 is a circuit diagram showing a detailed circuit configuration example for controlling a register file by the memory device according to the first embodiment of the present invention. FIG. 3 is a circuit diagram showing a circuit configuration example of a dummy memory cell B. FIG. 3 is a circuit diagram showing a circuit configuration example of a dummy memory cell C. 4 is a timing chart for explaining the operation of the register file by the memory device according to the first embodiment of the present invention. The circuit diagram which shows the detailed circuit structural example which controls the register file by the memory device which concerns on Embodiment 2 of this invention. The circuit diagram which shows the detailed circuit structural example which controls the register file by the memory device which concerns on Embodiment 2 of this invention. (A) And (b) is a circuit diagram which shows the structure of the row decoder in the register file by the memory device based on Embodiment 2 of this invention. (A) And (b) is a circuit diagram which shows the structure of the row decoder in the register file by the memory device based on Embodiment 2 of this invention. FIG. 5 is a circuit diagram showing an example of a hierarchical memory in which a memory cell array in a register file by a memory device according to a second embodiment of the present invention is divided into two in the row direction. The figure which shows arrangement | positioning of the dummy cell in the register file by the memory device concerning Embodiment 2 of this invention. 9 is a timing chart for explaining the operation of a register file by the memory device according to the second embodiment of the present invention. The circuit diagram which shows the circuit structural example which initializes the inside of a dummy memory cell. (A) And (b) is a circuit diagram which shows the basic composition of the memory cell which can write-in by the low voltage based on embodiment of this invention. 1 is a circuit diagram showing a basic configuration of a multi-port memory cell capable of performing a write operation at a low voltage according to an embodiment of the present invention. (A) And (b) is a figure which shows the structural example of the memory device which controls the board | substrate voltage of MOSFET which concerns on embodiment of this invention. 6 is a timing chart for explaining the operation of a register file using the memory device for controlling the substrate voltage of the MOSFET according to the embodiment of the present invention. FIG. 3 is a circuit diagram showing a configuration example of a memory device that controls the impedance of a control signal according to an embodiment of the present invention. FIG. 3 is a circuit diagram showing a configuration example of a cross coupling noise removing circuit in the memory device according to the embodiment of the present invention. FIG. 3 is a circuit diagram showing a configuration example of a cross coupling noise removing circuit in the memory device according to the embodiment of the present invention. FIG. 3 is a circuit diagram showing a simplified circuit configuration example for controlling a register file by the memory device according to the first embodiment of the present invention. FIGS. 4A and 4B are circuit diagrams showing a configuration of a read data holding circuit in a simplified circuit configuration example for controlling a register file by the memory device according to the first embodiment of the present invention. 6 is a timing chart for explaining the operation of a simplified circuit configuration example for controlling a register file by the memory device according to the first embodiment of the present invention; The circuit diagram which shows the structural example of the memory cell of the conventional register file. The block diagram which shows the structural example of the register file using the conventional memory cell. 9 is a timing chart for explaining the operation of a register file using a conventional memory cell.

Explanation of symbols

1, 2 Transfer gate 3, 4 Inverter 5, 6, 7, 8, 9, 10 NMOS transistor 11, 12 Write word line 13, 14 Write bit line 15, 16, 17 Read word line 18, 19, 20 Read bit line 21 Memory Cell Layout 22 P-Channel NWELL
23, 24, 25 P-channel MOSFET
31, 32, 37, 38, 43, 44, 45, 46 Inverter 33, 34, 35, 36 Source 39, 40, 41, 42 Logic circuit 200, 201 Memory cell array 210, 211 Address decoder 220, 221 Read data holding circuit 230, 231 Write data holding circuit 240, 241 Control circuit 301 Memory cell array 301
302, 302a Dummy memory cell A
303 Dummy memory cell B
304 Dummy memory cell C
305 Word line control block 311, 312, 313 Flip flop 312 a, 312 b, 313 b Flip flop 321 Read row decoder 322 Write row decoder 323 Read dummy row decoder 324, 324 a First write dummy row decoder 325 Second write dummy row decoder 331 Clock signal 332 Select signal 333 Dummy write bit line 334 Read control signal 335 Dummy read bit line 336 Write control signal 337 Dummy write detection signal line

Claims (5)

The memory element in the dummy memory cell is composed of first and second inverted logic gates, a reset signal line is connected to the first source of the first inverted logic gate, and the dummy memory cell is read and During the write operation, the reset signal applied to the reset signal line is fixed inactive,
The reset signal is activated to set the state of the memory element to a desired value except during the read and write operations.
Dummy memory cell initialization circuit . When the first source and the second source of the second inversion logic gate correspond to the first source and the second source of the first inversion logic gate, respectively, The inversion reset signal line which gives the inversion signal of the said reset signal to a 2nd source is connected.
Dummy memory cell initialization circuit . 2. The reset signal is activated by a signal indicating completion of writing to the dummy memory cell.
Dummy memory cell initialization circuit . A memory element in the memory cell is composed of two first and second inverted logic gates, and a first source of a transistor constituting the first inverted logic gate has a logical product of a write control signal and a write signal. A negative signal is connected, and a logical product signal of a write control signal and an inverted write signal is connected to the second source of the transistor constituting the first inverted logic gate,
The first source of the transistor constituting the second inverted logic gate is connected to a negative signal of the logical product of the write control signal and the inverted write signal, and the second source of the transistor constituting the second inverted logic gate is connected. A logical product signal of a write control signal and a write signal is connected to the source
A memory device comprising the memory cell .   A plurality of combinations of the write control signal and the write signal are provided, and the storage element in the memory cell uses a combination of two inverted logic gates that is the same number as the write control signal and is associated with the write control signal. The gates and drains of the transistors constituting the respective inversion logic gates are respectively connected at corresponding points in parallel, and the sources of the transistors constituting the respective inversion logic gates are associated with the respective inversion logic gates. 5. The memory device according to claim 4, wherein the memory device is connected to a write control signal and a signal generated by the write signal.

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