TWI516777B - Chip testing method - Google Patents
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- TWI516777B TWI516777B TW103107504A TW103107504A TWI516777B TW I516777 B TWI516777 B TW I516777B TW 103107504 A TW103107504 A TW 103107504A TW 103107504 A TW103107504 A TW 103107504A TW I516777 B TWI516777 B TW I516777B
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Description
本發明係關於一種晶粒測試方法,尤指一種可測試非完整晶圓狀態之晶粒測試方法。 The present invention relates to a grain test method, and more particularly to a die test method capable of testing a non-complete wafer state.
在晶片生產與製造流程中,當晶片出貨後才被發現問題而遭客戶退貨(簡稱客退)時,客戶通常是退回單顆晶粒或一晶粒承載盤中的所有晶粒。此時,因相關於該晶片之晶圓已經過切割,故僅能針對單顆晶粒的故障模式(IC Failure mode)作確認,而無法針對大量的退貨晶片來進行重新測試。此外,當任何產品之晶圓(Wafer)經過切割(Die Saw)後或未完全切割時,若發生前製程(Circuit Probe)的測試異常,將無法回溯完整晶圓的狀態以晶圓偵測機(Prober)重新作測試,整片晶圓只能以報廢處理。非以晶粒方式出貨的產品可在完成封裝後進入最後測試階段進行晶片測試,以區分晶粒的良莠。由於封裝的成本通常佔單顆晶片的30%以上,若該產品在完成封裝後的測試才被發現良率偏低,撿出不良品,則產品的成本將大幅的提高。 In the wafer production and manufacturing process, when the wafer is shipped and the problem is discovered and returned by the customer (referred to as customer return), the customer usually returns all the grains in a single die or a die carrier. At this time, since the wafer related to the wafer has been cut, it can only be confirmed for the IC Failure mode of the single die, and cannot be retested for a large number of returned wafers. In addition, when the wafer of any product (Wafer) is cut (Die Saw) or not completely cut, if the circuit probe test abnormality occurs, the state of the complete wafer cannot be traced back to the wafer inspection machine. (Prober) re-tested, the entire wafer can only be disposed of. Products that are not shipped in a die can be wafer tested after the final package is completed to differentiate the grain. Since the cost of the package usually accounts for more than 30% of the single wafer, if the product is found to have a low yield after the completion of the package, the cost of the product will be greatly increased.
於習知技術中,當晶片被客退而需進行測試以找出故障原因時,一種方法是以手動的方式將欲測試的單顆晶粒擺放在一未切割的完整晶圓上,以晶圓偵測機重新作測試。如第1圖所示,該方法將一未切割的完整晶圓10的中間部分割開,形成一槽口12,並將待測的單顆晶粒14與晶圓10 中的其他晶粒16對齊,以騙過晶圓偵測機正常執行晶圓測試的功能。然而,設置一顆晶粒約需30分鐘,故此方法非常耗時費工。另一種方法(如中華民國專利編號M358303)使用具有長孔之鐵片設置晶粒,藉由鐵片的滑移,將不同尺寸之晶粒以夾具固定於長孔側緣及水平、垂直定位肋,以利於晶圓偵測機進行逐一檢測,因此可用來測試多量的晶粒。然而,若晶片的大小不一致,則需要設計不同的夾具,且對於具有較大長寬比的驅動晶片(Driver IC)而言,此方法的效果不佳。此外,如第2圖所示,小方塊代表一晶粒,習知的晶圓偵測機只能對晶圓進行如第2圖中區域200的區塊式(Block-level)調校,或進行如第2圖中區域202的行列式(Row-level)調校,無法針對單一晶粒進行調校,故只適用於測試以晶圓級尺寸封裝(Wafer-Level Chip Scale Packaging,WLCSP)或四方平面無引腳封裝(Quad Flat No-Lead Packaging,QFN Packaging)等的晶圓。 In the prior art, when the wafer is thrown away and needs to be tested to find the cause of the failure, one method is to manually place the single die to be tested on an uncut complete wafer. The wafer inspection machine was retested. As shown in FIG. 1, the method divides the middle portion of an uncut complete wafer 10 to form a notch 12, and the single die 14 to be tested and the wafer 10 The other dies 16 are aligned to fool the wafer inspection machine from performing wafer testing. However, it takes about 30 minutes to set up a die, so this method is very time consuming and labor intensive. Another method (such as the Republic of China Patent No. M358303) uses a piece of iron with long holes to set the die. By sliding the iron piece, the different sizes of the die are fixed to the long hole side edge and the horizontal and vertical positioning ribs by clamps. In order to facilitate the wafer detector to perform one-by-one detection, it can be used to test a large number of grains. However, if the sizes of the wafers are inconsistent, it is necessary to design different jigs, and this method is not effective for a driver IC having a large aspect ratio. In addition, as shown in FIG. 2, the small squares represent a die, and the conventional wafer inspection machine can only perform a block-level adjustment on the wafer as in the area 200 in FIG. 2, or Performing the Row-level adjustment of the area 202 in Figure 2 cannot be calibrated for a single die, so it is only suitable for testing Wafer-Level Chip Scale Packaging (WLCSP) or Wafers such as Quad Flat No-Lead Packaging (QFN Packaging).
因此,如何對切割後的非完整晶圓或單一晶片進行快速的測試,且可不受限於晶片的尺寸大小,實為本領域的重要課題之一。 Therefore, how to perform rapid testing on a cut non-complete wafer or a single wafer, and is not limited to the size of the wafer, is one of the important topics in the field.
本發明的目的之一即在於提供一種晶粒測試方法,其可測試切割後的非完整晶圓及單一晶粒,且不受限於晶粒的尺寸大小及排列整齊與否,以迅速而有效地找出客退晶片的故障原因,進而針對故障問題進行規格調校。 One of the objects of the present invention is to provide a die test method capable of testing a cut non-complete wafer and a single die without being limited to the size and arrangement of the die, so as to be fast and effective. Find out the cause of the failure of the customer to retreat the wafer, and then adjust the specifications for the problem.
本發明揭露一種晶粒測試方法,用來測試一晶圓之複數個晶粒。該晶粒測試方法包含有將該複數個晶粒放置於一承載盤(Chip Tray)上;將該複數個晶粒藉由一挑揀機(Place and Pick)由該承載盤挑揀至一晶圓框(Wafer Frame)上;透過一晶圓偵測機(Prober)對該複數個晶粒進行驗證作業,以產生一驗證結果;以及根據該驗證結果,將該複數個晶粒之部分晶 粒挑揀至該承載盤中。 The present invention discloses a die test method for testing a plurality of dies of a wafer. The die test method includes placing the plurality of dies on a chip tray (Phip Tray); picking the plurality of dies from the carrier tray to a wafer frame by a pick and placer (Place and Pick) (Wafer Frame); verifying the plurality of crystal grains through a wafer inspection machine (Prober) to generate a verification result; and, according to the verification result, partially crystallizing the plurality of crystal grains The grain is picked into the carrier tray.
10‧‧‧晶圓 10‧‧‧ wafer
12‧‧‧槽口 12‧‧‧ notch
14、16、402、502、602‧‧‧晶粒 14, 16, 402, 502, 602‧‧ ‧ grains
200、202‧‧‧區域 200, 202‧‧‧ area
30‧‧‧流程 30‧‧‧Process
300~310‧‧‧步驟 300~310‧‧‧Steps
40‧‧‧待測元件 40‧‧‧Device under test
400‧‧‧晶圓框 400‧‧‧ Wafer Frame
4002‧‧‧框架 4002‧‧‧Frame
4004‧‧‧膠帶 4004‧‧‧ Tape
500、600‧‧‧承載盤 500, 600‧‧‧ carrier tray
6002‧‧‧承載環 6002‧‧‧ Carrying ring
6004‧‧‧具黏性膠帶 6004‧‧‧Adhesive tape
θ1、θ2、θ3‧‧‧角度 θ 1 , θ 2 , θ 3 ‧‧‧ angle
第1圖為使用習知一晶粒測試方法之待測晶圓及晶粒之示意圖。 Figure 1 is a schematic diagram of a wafer and die to be tested using a conventional die test method.
第2圖為習知一晶圓偵測機每次測試的區域範圍之示意圖。 Figure 2 is a schematic diagram of the area range of each test of a conventional wafer inspection machine.
第3圖為本發明實施例一晶粒測試流程之示意圖。 FIG. 3 is a schematic diagram of a die test flow according to an embodiment of the present invention.
第4圖為使用本發明晶粒測試流程之一待測元件之示意圖。 Figure 4 is a schematic illustration of one of the components to be tested using the die test procedure of the present invention.
第5圖為本發明實施例之一承載盤及其中複數個晶粒之示意圖。 FIG. 5 is a schematic diagram of a carrier disk and a plurality of crystal grains thereof according to an embodiment of the present invention.
第6圖為本發明實施例一承載盤及其中複數個晶粒之示意圖。 FIG. 6 is a schematic diagram of a carrier disk and a plurality of crystal grains thereof according to an embodiment of the present invention.
第7圖為每一晶粒之Theta角度偏移量之示意圖。 Figure 7 is a graphical representation of the Theta angular offset for each die.
請參考第3圖,第3圖為本發明實施例一晶粒測試流程30之示意圖。晶粒測試流程30用來測試一晶圓之複數個晶粒,特別是可針對非完整晶圓狀態之晶圓或單一晶粒進行測試驗證。晶粒測試流程30可應用於各種尺寸大小的晶粒,因此對於長寬比大於10的平面顯示器驅動晶片(LCD Driver IC),也能有良好的測試結果。此外,不論是晶片出貨前或出貨後均可利用晶粒測試流程30作測試。晶粒測試流程30包含有以下步驟:步驟300:開始。 Please refer to FIG. 3 , which is a schematic diagram of a die test flow 30 according to an embodiment of the present invention. The die test flow 30 is used to test a plurality of dies of a wafer, particularly for wafers or single dies of non-complete wafer states. The die test flow 30 can be applied to die of various sizes, so that a good test result can be obtained for a flat panel display driver (LCD Driver IC) having an aspect ratio of more than 10. In addition, the die test flow 30 can be tested before or after the wafer is shipped. The die test flow 30 includes the following steps: Step 300: Start.
步驟302:將該複數個晶粒放置於一承載盤(Chip Tray)上。 Step 302: Place the plurality of dies on a carrier tray (Chip Tray).
步驟304:將該複數個晶粒藉由一挑揀機(Place and Pick)由該承載盤挑揀至一晶圓框(Wafer Frame)上。 Step 304: Picking the plurality of dies from the carrier to a Wafer Frame by a pick and place.
步驟306:透過一晶圓偵測機(Prober)對該複數個晶粒進行驗證作業,以產生一驗證結果。 Step 306: Perform verification operations on the plurality of dies through a wafer detector (Prober) to generate a verification result.
步驟308:根據該驗證結果,將該複數個晶粒之部分晶粒挑揀至 該承載盤中。 Step 308: According to the verification result, select a part of the plurality of crystal grains to In the carrier tray.
步驟310:結束。 Step 310: End.
根據晶粒測試流程30,首先利用挑揀機將置於承載盤上的晶粒由承載盤反向挑揀至晶圓框中。一般挑揀機的正常運作模式係將晶圓框中的晶粒挑揀至承載盤中。於晶粒測試流程30中,挑揀機需進行反向挑揀的運作模式,即將置於承載盤上的晶粒由承載盤挑揀至晶圓框中。請參考第4圖,第4圖為使用本發明晶粒測試流程30之一待測元件40之示意圖。步驟304的挑揀完成後,於晶圓框上的複數個晶粒即為晶圓偵測機的待測元件40。待測元件40包含有晶圓框(Wafer Frame)400及複數個晶粒402。晶圓框400包含有一框架4002及一膠帶(Tape)4004,膠帶4004貼合於框架4002上,複數個晶粒402之背面設置並黏貼於膠帶4004上,使探針卡偵測晶粒402時,晶粒402不至於滑動。接著,利用晶圓偵測機,將設置於晶圓框400中的複數個晶粒402一一進行測試與驗證,以產生一驗證結果。驗證結果可以是具有表格型式的電子檔,以另儲存於電子設備中,但不限於此。驗證結果另可輸入挑揀機,以根據驗證結果,將適當的晶粒(如驗證結果顯示為良品(Pass Die)的晶粒),挑揀至承載盤中。完成挑揀的良品晶粒如第5圖所示,第5圖為本發明實施例之一承載盤500及其中的良品晶粒502,可用來準備出貨。 According to the die test procedure 30, the die placed on the carrier disk is first picked up by the picker from the carrier tray to the wafer frame. The normal mode of operation of the general picker is to pick the die in the wafer frame into the carrier. In the die test flow 30, the picker needs to perform a reverse picking operation mode in which the die placed on the carrier tray is picked up by the carrier tray into the wafer frame. Please refer to FIG. 4, which is a schematic diagram of an element 40 to be tested using the die test flow 30 of the present invention. After the picking of step 304 is completed, the plurality of dies on the wafer frame are the components 40 to be tested of the wafer detector. The device under test 40 includes a wafer frame 400 and a plurality of crystal grains 402. The wafer frame 400 includes a frame 4002 and a tape 4004. The tape 4004 is attached to the frame 4002. The back surface of the plurality of die 402 is disposed on the tape 4004, so that the probe card detects the die 402. The die 402 does not slip. Then, using the wafer inspection machine, the plurality of crystal grains 402 disposed in the wafer frame 400 are tested and verified one by one to generate a verification result. The verification result may be an electronic file having a form type, but is additionally stored in the electronic device, but is not limited thereto. The verification results can also be input to the picker to pick the appropriate die (such as the die of the Pass Die) and pick it into the carrier according to the verification result. As shown in FIG. 5, FIG. 5 is a carrier disk 500 and a good die 502 thereof in the embodiment of the present invention, which can be used for shipment.
一般而言,晶圓生產完成後需經過晶背研磨、切割、挑揀、置入晶粒承載盤等程序,才可將晶片產品送至客戶手上。習知的晶圓偵測機及晶圓測試流程只能對未研磨及未切割或已研磨但未切割的晶圓進行測試。相較之下,本發明實施例之晶粒測試流程30可針對已開始切割但未切割完成的晶圓、已切割完成但未經挑揀的晶圓,以及已切割完成並已挑揀至晶粒承載盤的晶粒(即非完整晶圓狀態之晶圓或單一晶粒)進行測試驗證。針對已開始切割但未切割完成的晶圓,可將該晶圓切割完成以分離複數個晶粒,再將複 數個晶粒放置於承載盤上,然後接至步驟304以完成晶粒測試流程30,而達到利用晶圓偵測機測試客退晶片的目的。針對已切割完成但未經挑揀的晶圓,可直接進行晶粒測試流程30。針對已切割完成並已挑揀至晶粒承載盤的晶粒,亦可直接進行晶粒測試流程30。因此,本發明不限於晶圓的狀態,並且可迅速而有效地找出客退晶片的故障原因。 In general, after wafer production is completed, the wafer backing, cutting, picking, and placement of the die carrier tray are required to deliver the wafer product to the customer. Conventional wafer inspection and wafer testing processes can only test unpolished and uncut or ground but uncut wafers. In contrast, the die test flow 30 of the embodiment of the present invention may be directed to a wafer that has been cut but not cut, a wafer that has been cut but not picked, and that has been cut and has been picked to the grain carrier. The die of the disk (ie, a wafer or a single die in a non-complete wafer state) is tested and verified. For a wafer that has been cut but not cut, the wafer can be cut to separate a plurality of grains, and then A plurality of dies are placed on the carrier, and then connected to step 304 to complete the die test process 30, thereby achieving the purpose of testing the die-back wafer using the wafer inspection machine. The die test procedure 30 can be performed directly on wafers that have been cut but not picked. The die test procedure 30 can also be performed directly on the die that has been cut and picked to the die carrier. Therefore, the present invention is not limited to the state of the wafer, and the cause of the failure of the guest wafer can be quickly and efficiently found.
需注意的是,本發明將晶粒放置於承載盤,經過反向挑揀的步驟將晶粒設置於晶圓框中,以透過晶圓偵測機的測試並從複數個晶粒中挑出良品。本領域具通常知識者當可據以做不同之修飾,而不限於此。舉例來說,找出良品並將其挑揀至承載盤後,可將承載盤透過一自動光學檢查(automated optical inspection,AOI)機台,檢查該承載盤中之晶粒是否符合一出貨規範,以進一步對產品的品質進行把關。 It should be noted that the present invention places the die on the carrier, and in the reverse picking step, the die is placed in the bezel to pass the test of the wafer inspection machine and pick out the plurality of crystal grains. . Those skilled in the art will be able to make various modifications, and are not limited thereto. For example, after finding a good product and picking it to the carrier tray, the carrier disk can be passed through an automated optical inspection (AOI) machine to check whether the die in the carrier disk meets a shipping specification. To further check the quality of the product.
用於步驟302中承載晶粒的承載盤可以是一般由塑膠成形的承載盤,但不限於此。舉例來說,如第6圖所示,第6圖為本發明實施例一承載盤600及其中複數個晶粒602之示意圖。承載盤600由一承載環6002及一具黏性膠帶6004構成的承載裝置,具黏性膠帶6004設置在承載環6002的中央,用來固定並承載切割完的複數個晶粒602。 The carrier tray used to carry the die in step 302 may be a carrier disk generally formed of plastic, but is not limited thereto. For example, as shown in FIG. 6, FIG. 6 is a schematic diagram of a carrier disk 600 and a plurality of die 602 thereof according to an embodiment of the present invention. The carrier tray 600 is composed of a carrier ring 6002 and a carrier tape 6004. The adhesive tape 6004 is disposed at the center of the carrier ring 6002 for fixing and carrying the cut plurality of crystal grains 602.
另外,由於晶片挑揀機是進行反向挑揀的運作,受限於儀器的精確度,於晶圓框中挑揀完成的晶粒可能排列不整齊。因此,本發明可利用軟體的方式,對每一晶粒分別校正其Theta角度偏移量(如第7圖之角度θ1、θ2、θ3),而產生一校正結果。接著,將校正結果反饋至晶圓偵測機的驗證模組中,以根據該校正結果,調整晶圓偵測機中晶粒的影像、定位肋、探針卡等的位置及角度,以得到精確的晶粒驗證結果。 In addition, since the wafer picker is performing reverse picking operations, the accuracy of the instrument is limited, and the crystal grains picked up in the wafer frame may be arranged irregularly. Therefore, the present invention can correct the Theta angular offset (such as the angles θ 1 , θ 2 , θ 3 of FIG. 7 ) for each crystal grain by means of a soft body to generate a correction result. Then, the calibration result is fed back to the verification module of the wafer inspection machine to adjust the position and angle of the image, positioning rib, probe card, etc. of the die in the wafer inspection machine according to the calibration result. Accurate grain verification results.
綜上所述,本發明之晶粒測試流程可測試切割後的非完整晶圓及單一晶粒,且不受限於晶粒的尺寸大小及排列整齊與否,即使是長寬比大於10的平面顯示器驅動晶片(LCD Driver IC)亦能有效地利用晶粒測試流程進行測試與驗證。因此,當晶片被客退而需進行測試以找出故障原因時,可依據本發明之流程及實施例迅速而有效地找出客退晶片的故障原因,進而針對故障問題進行修復,可大幅減少人力、物力及時間,不需報廢晶片、重新製作晶片,故可幫助提升產品的競爭力。 In summary, the die test process of the present invention can test the cut non-complete wafer and a single die without being limited to the size and arrangement of the die, even if the aspect ratio is greater than 10. The flat panel driver IC (LCD Driver IC) can also effectively use the die test process for testing and verification. Therefore, when the wafer is retired and needs to be tested to find the cause of the failure, the cause of the failure of the customer rewinding wafer can be quickly and effectively found according to the flow and embodiment of the present invention, and the failure problem can be repaired, which can be greatly reduced. Manpower, material resources and time, no need to scrap wafers, re-production of wafers, it can help improve the competitiveness of products.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
30‧‧‧流程 30‧‧‧Process
300~310‧‧‧步驟 300~310‧‧‧Steps
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