TWI509996B - Successive-approximation-register analog-to-digital converter (sar adc) with programmable gain of amplitude of input signal and method therefor - Google Patents

Description

Programmable amplified input signal amplitude gradually approximating analog digital converter (SAR ADC) and method thereof

The present invention relates to a progressive-approximation-register analog-to-digital converter (SAR ADC), and more particularly to a SAR ADC and method for amplifying an input signal amplitude.

Analog-to-digital converters (ADCs) have a variety of architectures, such as: flash ADC, pipelined ADC, successive-approximation-register (SAR) ADC, etc. . Each of these architectures has its own advantages and is usually chosen for different application needs. Among them, SAR ADC consumes lower power, smaller area and lower cost than other architectures.

The operation of the SAR ADC begins in the sampling phase. During the sampling phase, the sample and hold circuit samples and accesses the analog input signal. The SAR ADC then enters the bit-cycling phase to determine the conversion output of the digital code.

An N-bit SAR ADC typically includes a sample-and-hold (S/H) circuit, an N-bit digital-to-analog converter (DAC), a voltage comparator, and a SAR control circuit. .

The input voltage provides a regulated voltage to the voltage comparator via the sample and hold circuit, and the voltage comparator compares this regulated voltage to the output voltage of the N-bit DAC. The SAR control circuit uses a binary search algorithm to control the output of the N-bit DAC.

Among them, the sample and hold circuit and the N-bit DAC are generally implemented by a capacitive DAC composed of a capacitor array. The SAR control circuit adjusts the output of the N-bit DAC by controlling the switching of the switching elements in the capacitive DAC.

To suppress power noise and common mode noise, common SAR ADCs use a fully differential architecture. There are two main types of SAR ADCs with common fully differential structures: one with upper plate sampling and one with lower plate sampling. That is, during the sampling phase, the upper plate of the capacitor array is coupled to the input signal or the lower plate of the capacitor array is coupled to the input signal to sample the input signal.

Due to the limitation of the capacitive sampling noise (KT/C noise), the sampling capacitance of the SAR ADC is usually inversely proportional to the square of the amplitude of the input signal. Therefore, if the amplitude of the input signal can be increased, the size of the sampling capacitor can be greatly reduced. The prior art mainly uses a programmable gain amplifier (PGA) to amplify the amplitude of the input signal, but the PGA itself consumes the chip area and brings additional noise.

In an embodiment, a progressive approximation analog-to-digital converter having a programmable amplified input signal amplitude includes a first end point, a second end point, a third end point, a fourth end point, and a fifth end A point, a comparator, a SAR control circuit, a selection module, and a capacitor module. The selection module includes a plurality of first switching units UA1, UA2~UA(N-1), a plurality of second switching units UB1, UB2~UB(N-1), a first switch SW1 and a second switch SW2. . The capacitor module 170 includes a plurality of first capacitors CA1, CA2~CA(N-1) and a plurality of second capacitors CB1, CB2~CB(N-1).

The first end is configured to receive one of the differential input signals, the second end is configured to receive the other of the differential input signals, the third end is configured to receive the positive phase reference voltage, and the fourth end The point is for receiving the inverted reference voltage, and the fifth terminal is for receiving the common mode voltage.

The SAR control circuit is coupled to the output of the comparator and generates a first control signal, a second control signal, and a digital signal according to the output of the comparator. Here, the first switching unit is controlled by the first control signal, and the second switching unit is controlled by the second control signal.

The first switch is coupled between the first input of the comparator and the first end, and the second switch is coupled between the second input and the second end of the comparator.

The first capacitors respectively correspond to the first switching unit, and are coupled between the first input end of the comparator and the corresponding first switching unit. The first capacitors are coupled to the third endpoint via the corresponding first switching unit, The fourth end point and the fifth end point, and the at least one first capacitor is further coupled to the second end point via the corresponding first switching unit.

The second capacitors respectively correspond to the second switching unit, and are coupled between the second input end of the comparator and the corresponding second switching unit. The second capacitors are coupled to the third endpoint, the fourth endpoint, and the fifth endpoint via the corresponding second switching unit.

In one embodiment, a SAR analog-to-digital conversion method for programmable amplification of an input signal amplitude includes: sequentially performing one sampling phase, one holding phase, and one bit cycle phase.

The step of the sampling phase includes: sampling one of the differential input signals by using the upper plates of the plurality of first capacitors in the capacitor module, and utilizing the lower pole of the at least one of the first capacitors The board samples the other of the differential input signals and samples the other of the differential input signals using an upper plate of the plurality of second capacitors in the capacitive module. The second capacitors respectively correspond to the first capacitors.

The step during the hold phase includes disconnecting the upper plate of the first capacitor and the second capacitor from the differential input signal, and setting the lower plate of the first capacitor to electrically connect a common mode voltage.

The step during the bit cycle phase includes: comparing a terminal voltage of the upper plate of the first capacitor with a terminal voltage of the upper plate of the second capacitor by using a comparator, sequentially, according to an output of the comparator, a first capacitor The lower plate of the lower plate and the corresponding second capacitor are electrically connected to the common mode voltage to be respectively electrically connected to the differential reference voltage, and after each switching, the comparator is used to compare the upper plate of the first capacitor. Terminal voltage and the end of the second capacitor The voltage, and a digital signal is generated based on the output of the comparator.

In some embodiments, during the sampling phase, the method further includes sampling the one of the differential input signals with a lower plate of at least one of the second capacitors. Moreover, during the maintaining phase, the method further includes: setting the lower plates of the second capacitors to electrically connect the common mode voltage.

In summary, the progressive approximation analog-to-digital converter of the amplitude of the programmable amplified input signal according to the present invention and the method thereof use the upper and lower plates of the capacitor to simultaneously sample, thereby simultaneously amplifying the amplitude of the input signal so as to be at the same level of noise. The sampling capacitance required will be smaller, or the noise will be smaller for the same sampling capacitor. Moreover, for the pseudo-differential input signal, after the sampling, the pseudo-differential input signal is automatically converted into a fully differential input signal, thereby suppressing power noise and common mode noise.

10‧‧‧Frequent approximation analog digital converter

110‧‧‧ comparator

130‧‧‧SAR control circuit

150‧‧‧Capacitor Module

170‧‧‧Selection module

N1‧‧‧ first endpoint

N2‧‧‧ second endpoint

N3‧‧‧ third endpoint

N4‧‧‧ fourth endpoint

N5‧‧‧ fifth endpoint

UA1~UA(N-1)‧‧‧ first switching unit

UB1~UB(N-1)‧‧‧Second switching unit

SW1‧‧‧ first switch

SW2‧‧‧second switch

CA1~CA(N-1)‧‧‧first capacitor

CB1~CB(N-1)‧‧‧second capacitor

CKin‧‧‧ clock signal

IN1‧‧‧ first input

IN2‧‧‧ second input

OUT‧‧‧ output

ScA0~ScA(N-1)‧‧‧ first control signal

ScB0~ScB(N-1)‧‧‧second control signal

B1~BN‧‧‧digit code

Vip‧‧ positive input signal

Vin‧‧‧Inverting input signal

Vrp‧‧‧ positive phase reference voltage

Vrn‧‧‧inverted reference voltage

Vcm‧‧‧ Common mode voltage

CAN‧‧‧ third capacitor

CBN‧‧‧fourth capacitor

VA‧‧‧ terminal voltage

VB‧‧‧ terminal voltage

C‧‧‧ capacitor

SW3‧‧‧ switch

SW4‧‧‧ switch

SW5‧‧‧ switch

SW6‧‧‧ switch

1 is a schematic diagram showing a progressive approximation analog-to-digital converter (SAR ADC) of a programmable amplified input signal amplitude in accordance with an embodiment of the present invention.

Figure 2 is a schematic illustration of an exemplary state of a SAR ADC of the programmable amplified input signal amplitude in Figure 1 during the sampling phase.

Figure 3 is a diagram showing an exemplary state of a SAR ADC of the programmable amplified input signal amplitude in Figure 1 during the first comparison period of the hold phase and the bit cycle phase.

Figure 4 is the first comparison period in the first cycle of the bit cycle. A schematic diagram of an exemplary state of a SAR ADC that can amplify an input signal amplitude.

Figure 5 is a diagram showing another exemplary state of the SAR ADC of the programmable amplified input signal amplitude in Figure 1 during the second comparison period of the bit cycle phase.

Figure 6 is a partial schematic diagram of an exemplary state of a SAR ADC of the programmable amplified input signal amplitude in Figure 1 during the third comparison period of the bit cycle phase.

Figure 7 is a partial schematic diagram of another exemplary state of the SAR ADC of the programmable amplified input signal amplitude in Figure 1 during the third comparison period of the bit cycle phase.

Figure 8 is a partial schematic diagram of a SAR ADC that can amplify the amplitude of an input signal in accordance with another embodiment of the present invention.

Figure 9 is a partial schematic diagram of an exemplary state of a SAR ADC of the programmable amplified input signal amplitude in Figure 8 during the sampling phase.

Figure 10 is a partial schematic diagram of an exemplary state of a SAR ADC of the programmable amplified input signal amplitude in Figure 8 during the first comparison period of the hold phase and the bit cycle phase.

Figure 11 is a schematic diagram of an exemplary structure of the switching unit.

Fig. 12 is a schematic diagram showing another exemplary structure of the switching unit.

In the following terms, "first", "second" and the like, are used to distinguish the elements that are referred to, and are not intended to limit or limit the differences of the elements referred to, and are not intended to limit the scope of the present invention. .

Referring to FIG. 1, a progressive-approximation-register analog-to-digital converter (SAR ADC) 10 includes a first endpoint N1 and a second endpoint N2. A third endpoint N3, a fourth endpoint N4, a fifth endpoint N5, a comparator 110, a SAR control circuit 130, a selection module 170, and a capacitor module 150.

The selection module 170 includes a plurality of switching units (hereinafter referred to as first switching units UA1, UA2 UA UA (N-1) and second switching units UB1, UB2 UB UB(N-1)) and two input switches (below) It is referred to as a first switch SW1 and a second switch SW2). The capacitor module 150 includes a plurality of capacitors (hereinafter referred to as first capacitors CA1, CA2 to CA(N-1) and second capacitors CB1, CB2 to CB(N-1)). Here, the first capacitors CA1, CA2~CA(N-1) correspond to the first switching units UA1, UA2~UA(N-1), respectively, and the second capacitors CB1, CB2~CB(N-1) respectively correspond to The second switching unit UB1, UB2~UB(N-1). Where N is a positive integer greater than one. In some embodiments, the switching units and capacitors form a switched-capacitor array (SCA).

The lower plates of the first capacitors CA1, CA2~CA(N-1) are coupled to the second end point N2 and the third end point N3 via the corresponding first switching units UA1, UA2~UA(N-1), The fourth endpoint N4 and the fifth endpoint N5. For example, the lower plate of the first capacitor CA1 is coupled to the second end point N2, the third end point N3, the fourth end point N4, and the fifth end point N5 via the corresponding first switching unit UA1. That is, the first switching unit UA1 is coupled between the lower plate of the first capacitor CA1 and the second end point N2 at the lower plate of the first capacitor CA1. Between the third terminal N3, between the lower plate and the fourth end point N4 of the first capacitor CA1, and between the lower plate and the fifth end point N5 of the first capacitor CA1. Similarly, the lower plate of the first capacitor CA2 is coupled to the second end point N2, the third end point N3, the fourth end point N4, and the fifth end point N5 via the corresponding first switching unit UA2. And so on, the lower plate of the first capacitor CA(N-1) is coupled to the second end point N2, the third end point N3, and the fourth end point via the corresponding first switching unit UA(N-1) N4 and fifth endpoint N5.

The lower plates of the second capacitors CB1, CB2~CB(N-1) are coupled to the first end point N1 and the third end point N3 via the corresponding second switching units UB1, UB2 UB UB(N-1), The fourth endpoint N4 and the fifth endpoint N5. For example, the lower plate of the second capacitor CB1 is coupled to the first end point N1, the third end point N3, the fourth end point N4, and the fifth end point N5 via the corresponding second switching unit UB1. That is, the second switching unit UB1 is coupled between the lower plate of the second capacitor CB1 and the first terminal N1, between the lower plate and the third terminal N3 of the second capacitor CB1, and at the second capacitor CB1. Between the lower plate and the fourth end point N4, and between the lower plate and the fifth end point N5 of the second capacitor CB1. Similarly, the lower plate of the second capacitor CB2 is coupled to the first end point N1, the third end point N3, the fourth end point N4, and the fifth end point N5 via the corresponding second switching unit UA2. And so on, the lower plate of the second capacitor CB(N-1) is coupled to the first end point N1, the third end point N3, and the fourth end point via the corresponding second switching unit UB(N-1) N4 and fifth endpoint N5.

In some embodiments, the first capacitors CA1, CA2~CA(N-1) correspond to the second capacitors CB1, CB2~CB(N-1), respectively, in terms of capacitance. That is, the capacitance of the first capacitor CAj is equal to the second capacitor CBj's capacitance. Furthermore, the capacitance of the first capacitor CAj is equal to twice the capacitance of the first capacitor CA(j+1), and the capacitance of the second capacitor CBj is equal to twice the capacitance of the second capacitor CB(j+1) capacity. Among them, j=1~N-2.

The first input terminal IN1 of the comparator 110 is electrically coupled to one end of the first switch SW1 and the upper plate of the first capacitors CA1, CA2~CA(N-1). The second input terminal IN2 of the comparator 110 is electrically coupled to one end of the second switch SW2 and the upper plate of the second capacitors CB1, CB2 C CB (N-1). The output terminal OUT of the comparator 110 is electrically coupled to the SAR control circuit 130. The other end of the first switch SW1 is electrically coupled to the first end point N1, and the other end of the second switch SW2 is electrically coupled to the second end point N2. In other words, the first switch SW1 is coupled between the first input terminal IN1 of the comparator 110 and the first terminal N1, and the second switch SW2 is coupled to the second input terminal IN2 and the second terminal end N2 of the comparator 110. between.

The SAR control circuit 130 is coupled between the output terminal OUT of the comparator 110 and the control terminal of the selection module 170, and generates a first control signal ScA0~ScA according to the output of the comparator 130 under the control of the clock signal CKin. -1), second control signals ScB0~ScB(N-1) and digital signals (ie, digital code B1~BN).

Here, the first end point N1 is for receiving the normal phase input signal Vip, the second end point N2 is for receiving the inverting input signal Vin, the third end point N3 is for receiving the positive phase reference voltage Vrp, and the fourth end point N4 And receiving the inverted reference voltage Vrn and the fifth terminal N5 for receiving the common mode voltage Vcm. The positive phase input signal Vin and the inverted input signal Vip are a differential input signal (Vi). Positive phase reference voltage Vrp and inverting reference voltage Vrn is a differential reference voltage (Vref).

In some embodiments, the capacitor module 150 further has a third capacitor CAN and a fourth capacitor CBN. The third capacitor CAN is coupled between the first input terminal IN1 and the fifth terminal end N5 of the comparator 110. The fourth capacitor CBN is coupled between the second input terminal IN2 of the comparator 110 and the fifth terminal end N5.

In some embodiments, the third capacitor CAN corresponds to the fourth capacitor CBN in terms of capacitance. That is, the capacitance of the third capacitor CAN is equal to the capacitance of the fourth capacitor CBN. Furthermore, the capacitance of the third capacitor CAN is equal to the capacitance of the first capacitor CA(N-1), and the capacitance of the fourth capacitor CBN is equal to the capacitance of the second capacitor CB(N-1).

In operation, the SAR ADC 10 first enters a sampling phase. Referring to FIG. 2, during the sampling phase, the SAR control circuit 130 outputs the first control signals ScA1~ScA(N-1) to the control terminals of all the first switching units UA1, UA2~UA(N-1), so as to cause A switching unit UA1, UA2~UA(N-1) electrically connects the lower plates of the first capacitors CA1, CA2~CA(N-1) to the first control signals ScA1~ScA(N-1), respectively. The second endpoint N2.

The SAR control circuit 130 outputs the second control signals ScB1 SScB(N-1) to the control terminals of all the second switching units UB1, UB2 UB UB(N-1) to cause the second switching units UB1, UB2 UB UB (N -1) Electrically connecting the lower plates of the second capacitors CB1, CB2~CB(N-1) to the first terminal N1 in response to the second control signals ScB1 to ScB(N-1), respectively.

And, the SAR control circuit 130 outputs the first control signal respectively. No. ScA0 and the second control signal ScB0 to the control ends of the first switch SW1 and the second switch SW2, so that the first switch SW1 responds to the first control signal ScA0 to the first capacitors CA1, CA2~CA(N-1) The plate is electrically connected to the first end point N1, and the second switch SW2 is electrically connected to the second end point N2 of the second capacitor CB1, CB2~CB(N-1) in response to the second control signal ScB0.

At this time, the upper plates of the first capacitors CA1, CA2~CA(N-1) and the lower plates of the second capacitors CB1, CB2~CB(N-1) receive the positive phase input signal Vip via the first terminal N1. The positive phase input signal Vip is sampled. The lower plates of the first capacitors CA1, CA2~CA(N-1) and the upper plates of the second capacitors CB1, CB2~CB(N-1) receive the inverted input signal Vin via the second terminal N2 and counter The phase input signal Vin is sampled.

The SAR ADC 10 then enters a hold phase from the sampling phase. Referring to FIG. 3, during the hold phase, the SAR control circuit 130 outputs the first control signals ScA1~ScA(N-1) to the control terminals of all the first switching units UA1, UA2~UA(N-1), so as to cause A switching unit UA1, UA2~UA(N-1) electrically connects the lower plates of the first capacitors CA1, CA2~CA(N-1) in response to the first control signals ScA1~ScA(N-1), respectively. The second endpoint N2 is switched to electrically connect to the fifth endpoint N5.

The SAR control circuit 130 outputs the second control signals ScB1 SScB(N-1) to the control terminals of all the second switching units UB1, UB2 UB UB(N-1) to cause the second switching units UB1, UB2 UB UB (N -1) switching the lower plates of the second capacitors CB1, CB2~CB(N-1) from the electrically connected first terminal N1 to the electrical respectively in response to the second control signals ScB1~ScB(N-1) The fifth terminal N5 is connected sexually.

Moreover, the SAR control circuit 130 outputs the first control signal ScA0 and the second control signal ScB0 to the control ends of the first switch SW1 and the second switch SW2, respectively, to cause the first switch SW1 to pass the first capacitor CA1 in response to the first control signal ScA0. The upper plate of CA2~CA(N-1) is disconnected from the first terminal N1, and the second switch SW2 is responsive to the second control signal ScB0 to the upper pole of the second capacitor CB1, CB2~CB(N-1) The board is disconnected from the second end point N2.

The SAR ADC 10 then enters the bit cycle phase from the hold phase. During the bit cycle phase, comparator 110 begins the first comparison. At this time, the comparator 110 compares the terminal voltage VA of the upper plate of the first capacitors CA1, CA2~CA(N-1) (that is, the voltage received by the first input terminal IN1) and the second capacitors CB1, CB2~. The terminal voltage VB of the upper plate of CB(N-1) (ie, the voltage received by the second input terminal IN2).

Next, the SAR control circuit 130 sets the digital code B1 of the first bit of the digital signal to be output according to the output of the comparator 110 (ie, the first comparison result of the terminal voltage VA and the terminal voltage VB), and according to the comparator The output of 110 generates first control signals ScA1~ScA(N-1) to the control terminals of the first switching units UA1, UA2~UA(N-1) and generates second control signals ScB1~ScB(N-1) to The switching ends of the switching units UB1, UB2 UB UB(N-1) are such that the first switching unit UA1 responds to the first control signal ScA1 with the maximum capacitance of the first capacitors CA1, CA2~CA(N-1) (ie The lower plate of the first capacitor CA1) is switched from the electrically connected common mode voltage Vcm to one of the positive phase reference voltage Vrp and the inverted reference voltage Vrn. The second switching unit UB1 responds to the second control signal ScB1 with the lower plate of the second capacitor CB1, CB2~CB(N-1) corresponding to the first capacitor CA1 (ie, the largest second capacitor CB1). The electrical connection common mode voltage Vcm is switched to electrically connect the other of the positive phase reference voltage Vrp and the inverted reference voltage Vrn. At this time, the lower plates of the remaining capacitors (the first capacitors CA2~CA(N-1) and the second capacitors CB2~CB(N-1)) remain unchanged, that is, the common mode voltage Vcm is electrically connected.

For example, referring to FIG. 4, when the terminal voltage VA is greater than the terminal voltage VB, the SAR control circuit 130 sets the digital code B1 of the first bit of the digital signal to be output to "1", and controls the first switching. The unit UA1 electrically connects the lower plate of the first capacitor CA1 to the inverted reference voltage Vrn and controls the second switching unit UB1 to electrically connect the lower plate of the second capacitor CB1 to the positive phase reference voltage Vrp. Moreover, the electrical connection relationship of the lower plates of the remaining capacitors remains unchanged.

Referring to FIG. 5, when the terminal voltage VA is not greater than the terminal voltage VB, the SAR control circuit 130 sets the digital code B1 of the first bit of the digital signal to be output to "0", and controls the first switching unit UA1 to The lower plate of the first capacitor CA1 is electrically connected to the positive phase reference voltage Vrp and the second switching unit UB1 is electrically connected to the lower plate of the second capacitor CB1 to the inverted reference voltage Vrn. Moreover, the electrical connection relationship of the lower plates of the remaining capacitors remains unchanged.

Then, the comparator 110 compares the terminal voltage VA of the upper plate of the first capacitors CA1, CA2~CA(N-1) and the terminal voltage VB of the upper plate of the second capacitors CB1, CB2~CB(N-1) again. (ie, the second ratio More).

Then, the SAR control circuit 130 further sets the digital code B2 of the second bit of the digital signal to be output according to the output of the comparator 110 (ie, the second comparison result of the terminal voltage VA and the terminal voltage VB), and according to the comparison. The output of the device 110 generates first control signals ScA1~ScA(N-1) to the control terminals of the first switching units UA1, UA2~UA(N-1) and generates second control signals ScB1~ScB(N-1) to a control end of the second switching unit UB1, UB2~UB(N-1) such that the first switching unit UA2 sends the second of the first capacitors CA1, CA2~CA(N-1) in response to the first control signal ScA2 The lower plate of the first capacitor CA2 is switched from the electrically connected common mode voltage Vcm to one of the positive phase reference voltage Vrp and the inverted reference voltage Vrn, and the second switching unit UB2 is responsive to the second control signal ScB2. The lower plate of the second capacitor CB1, CB2~CB(N-1) corresponding to the first capacitor CA2 (ie, the second largest capacitor CB2) is switched from the electrically connected common mode voltage Vcm to the electrical connection. The other of the phase reference voltage Vrp and the inverted reference voltage Vrn. At this time, the lower plates of the remaining capacitors (the first capacitors CA1, CA3~CA(N-1) and the second capacitors CB1, CB3~CB(N-1)) remain unchanged, that is, the first capacitor CA1 and the first capacitor The two capacitors CB1 are electrically connected to the positive phase reference voltage Vrp and the inverted reference voltage Vrn, respectively, and the first capacitors CA3~CA(N-1) and the second capacitors CB3~CB(N-1) are electrically connected to the common mode. Voltage Vcm.

Here, similarly, referring to FIG. 6 (here, assuming that the first comparison result is that the terminal voltage VA is greater than the terminal voltage VB), when the terminal voltage VA is greater than the terminal voltage VB, the SAR control circuit 130 will output the digital signal to be output. The digit code B2 of the second bit in the middle is set to "1", and the first slice is controlled. The switching unit UA2 electrically connects the lower plate of the first capacitor CA2 to the inverted reference voltage Vrn and controls the second switching unit UB2 to electrically connect the lower plate of the second capacitor CB2 to the positive phase reference voltage Vrp. Moreover, the electrical connection relationship of the lower plates of the remaining capacitors remains unchanged.

Referring to FIG. 7 (here, assuming that the first comparison result is that the terminal voltage VA is greater than the terminal voltage VB), when the terminal voltage VA is not greater than the terminal voltage VB, the SAR control circuit 130 will be the second bit of the digital signal to be output. The digit code B2 of the element is set to "0", and the first switching unit UA2 is controlled to electrically connect the lower plate of the first capacitor CA2 to the positive phase reference voltage Vrp and control the second switching unit UB2 to lower the second capacitor CB2. The plate is electrically connected to the inverting reference voltage Vrn. Moreover, the electrical connection relationship of the lower plates of the remaining capacitors remains unchanged.

In other words, each comparison result sequentially corresponds to a first capacitor, sequentially corresponds to a second capacitor, and sequentially corresponds to a bit of the digit signal. Therefore, after each comparison, the SAR control circuit 130 sets the value of the digital code of the corresponding bit in the digital signal according to the output of the comparator 110 and controls the voltage level of the lower plate corresponding to the first capacitor and the corresponding second capacitor. Bit (ie, electrical connection relationship). By repeating comparison, setting and control until the last digit of the digit code BN is set.

After the setting of the last bit digital code BN is completed, the SAR control circuit 130 outputs the digital signal (i.e., all the digital code B1~BN set) to the next stage.

In these embodiments, after the sampling is completed, the SAR ADC 10 has a voltage difference of 2 (Vip-Vin) at the input of the comparator 130, so the input The amplitude of the signal to the comparator 130 is twice the amplitude of the differential input signal (Vi). In other words, the SAR ADC 10 compares the input signal (Vi) by a factor of two. Furthermore, in the SAR ADC 10 according to the present invention, for the pseudo differential input signal, the pseudo differential input signal is automatically converted into a fully differential input signal after being sampled. For example, in the pseudo differential input signal (the positive phase input signal Vip and the inverted input signal Vin), the inverted input signal Vin is always Vcmin, and the positive phase input signal Vip is Vcmin + ΔV. After the sampling is completed, the input voltage (terminal voltage VA) of the first input terminal IN1 of the comparator 130 is Vcm + ΔV, and the input voltage (terminal voltage VB) of the second input terminal IN2 of the comparator 130 is Vcm - ΔV. .

Furthermore, the magnification of the amplitude of the differential input signal (Vi) (between 1 and 2 times) can be determined by electrically connecting the input signal to the lower plate that provides only a portion of the capacitance.

In some embodiments, referring to FIG. 8, the lower plates of the first capacitors CA1, CA2~CA(N-1) are coupled to the first switching unit UA1, UA2~UA(N-1) to the first The three endpoints N3, the fourth endpoint N4, and the fifth endpoint N5. The lower plates of the second capacitors CB1, CB2~CB(N-1) are coupled to the third end point N3 and the fourth end point N4 via the corresponding second switching units UB1, UB2 UB UB(N-1) and The fifth endpoint N5.

The lower plate of at least one of the first capacitors CA1, CA2~CA(N-1) is further coupled to the second end point N2 via the corresponding first switching unit, and the remaining first capacitors are corresponding to The first switching unit is not coupled to the second endpoint N2.

In some embodiments, the second capacitor CB1, CB2~CB(N-1) The lower plate of at least one of the second switching units is coupled to the first end point N1 via the corresponding second switching unit, and the second switching unit corresponding to the remaining second capacitor is not coupled to the first end point N1.

For example, in the structure of the SAR ADC 10 shown in FIG. 8, only the two first capacitors CA1 and CA3 are coupled to the second terminal N2 and the second capacitor CB1 via the corresponding first switching units UA1 and UA3. The CB3 is coupled to the first endpoint N1 via the corresponding second switching unit UB1, UB3. The switching units corresponding to the remaining capacitors are not coupled to the first terminal N1 and the second terminal N2.

Here, referring to FIG. 9, during the sampling phase, the SAR control circuit 130 outputs the first control signals ScA1 to ScA(N-1) to the control terminals of all the first switching units UA1, UA2 to UA(N-1). So that the first switching unit UA1, UA3 electrically connects the lower plates of the first capacitors CA1, CA3 to the second end point N2 in response to the first control signals ScA1, ScA3, respectively, and the first switching unit UA2, UA4~UA (N-1) electrically connecting the lower plates of the first capacitors CA2, CA4~CA(N-1) to the fifth terminal N5 in response to the first control signals ScA2, ScA4~ScA(N-1), respectively. .

At the same time, the SAR control circuit 130 outputs the second control signals ScB1~ScB(N-1) to the control terminals of all the second switching units UB1, UB2~UB(N-1), so that the second switching units UB1, UB3 respectively respond The second control signals ScB1, ScB3 electrically connect the lower plates of the second capacitors CB1, CB3 to the first end point N1, and the second switching units UB2, UB4~UB(N-1) respectively respond to the second control Signals ScB2, ScB4~ScB(N-1) and the lower plates of the second capacitors CB2, CB4~CB(N-1) Electrically connected to the fifth terminal N5.

Moreover, the SAR control circuit 130 outputs the first control signal ScA0 and the second control signal ScB0 to the control ends of the first switch SW1 and the second switch SW2, respectively, to cause the first switch SW1 to pass the first capacitor CA1 in response to the first control signal ScA0. The upper plate of CA2~CA(N-1) is electrically connected to the first end point N1, and the second switch SW2 is connected to the upper end of the second capacitor CB1, CB2~CB(N-1) in response to the second control signal ScB0. The board is electrically connected to the second end point N2.

At this time, the upper plates of the first capacitors CA1, CA2 to CA(N-1) receive the positive phase input signal Vip and sample the normal phase input signal Vip. The upper plates of the second capacitors CB1, CB2 to CB(N-1) receive the inverted input signal Vin via the second terminal N2 and sample the inverted input signal Vin. Only the lower plates of the first capacitors CA1, CA3 receive the inverted input signal Vin and sample the inverted input signal Vin via the second terminal N2, and the lower plates of the second capacitors CB1, CB3 pass through the first terminal N1 receives the positive phase input signal Vip and samples the positive phase input signal Vip. The lower plates of the remaining capacitors (the first capacitors CA2, CA4~CA(N-1) and the second capacitors CB2, CB4~CB(N-1)) do not have an input signal (positive phase input signal Vip or inverted input signal). Vin) for sampling.

After the sampling is completed, referring to FIG. 10, during the holding phase, under the control of the SAR control circuit 130, all the capacitors (the first capacitor CA1~CA(N-1) and the second capacitor CB1~CB(N-1) The lower plates are all set to be electrically connected to the fifth terminal N5, and the upper plates of all the capacitors are disconnected from the differential input signal (the positive phase input signal Vip or the inverted input signal Vin).

During the bit cycle phase, the operation of the SAR ADC 10 is the same as that of the above embodiment, and therefore will not be described again.

Under this architecture, after the sampling is completed, the voltage difference at the input of the comparator 130 is M (Vip-Vin), that is, the amplitude of the differential input signal of the SAR ADC 10 is amplified by M times. Among them, M is between 1 and 2.

In this case, although the corresponding first capacitor and the second capacitor simultaneously sample the input signal with the lower plate thereof, the present invention is not limited thereto, that is, the corresponding first capacitor and second capacitor may be only included therein. The lower plate of one samples the input signal.

In other words, the position and number of capacitors that can sample the input signal by adjusting the lower plate can produce amplitudes of the differential input signal (Vi) at different magnifications.

In some embodiments, each of the first switching units UA1, UA2 UA UA (N-1) and the second switching units UB1, UB2 UB UB(N-1) (hereinafter collectively referred to as switching unit UB) is plural The switch is composed of.

Referring to FIG. 11, a capacitor C (ie, one of the first capacitors CA1 to CA(N-1) and the second capacitors CB1 to CB(N-1)) for sampling the input signal of the lower plate, The corresponding switching unit UB may include four switches SW3, SW4, SW5, SW6.

The switch SW3 is coupled between the fifth terminal N5 and the lower plate of the capacitor C. The switch SW4 is coupled between the fourth terminal N4 and the lower plate of the capacitor C. The switch SW5 is coupled between the third terminal N3 and the lower plate of the capacitor C. The switch SW6 is coupled between the first terminal N1 or the second terminal N2 and the lower plate of the capacitor C.

The control terminals of the switches SW3, SW4, SW5, and SW6 are coupled to the SAR control circuit 130. In other words, the switches (ON/OFF) of the switches SW3, SW4, SW5, and SW6 to which each capacitor is coupled are controlled by corresponding signals (ie, the first control signals ScA1~ScA(N-1) and the second Controlled by one of the control signals ScB1 to ScB(N-1).

Referring to FIG. 12, for the lower plate, the capacitor C (ie, one of the first capacitors CA1 to CA(N-1) and the second capacitors CB1 to CB(N-1)) is not required to sample the input signal, The corresponding switching unit UB does not need the switch SW6, that is, only three switches SW3, SW4, SW5 are included.

In some embodiments, the first control signals scA0~ScA(N-1) may be implemented as a single signal or as multiple signals. Similarly, the second control signals ScB0~ScB(N-1) may be implemented as a single signal or as multiple signals.

Since the structure and operation principle of the SAR control circuit 130 are well known to those skilled in the art, no further details are provided herein.

In summary, a progressive approximation analog-to-digital converter of a programmable amplified input signal amplitude and method thereof according to the present invention electrically connects a lower plate of at least one capacitor in a capacitor array to an input signal during a sampling phase to be used by a capacitor array The input signal is sampled and amplified to reduce the required sampling capacitance or to reduce noise generation. In other words, the progressive approximation analog-to-digital converter of the amplitude of the programmable amplified input signal according to the present invention and the method thereof use the upper and lower plates of the capacitor to simultaneously sample, thereby simultaneously amplifying the amplitude of the input signal so as to be at the same level of noise. Consider that the required sampling capacitance will be smaller, or, for the same sampling capacitor, The noise will be smaller. Moreover, for the pseudo-differential input signal, after the sampling, the pseudo-differential input signal is automatically converted into a fully differential input signal, thereby suppressing power noise and common mode noise.

While the present invention has been described above in the foregoing embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of patent protection shall be subject to the definition of the scope of the patent application attached to this specification.

10‧‧‧Frequent approximation analog digital converter

110‧‧‧ comparator

130‧‧‧SAR control circuit

150‧‧‧Capacitor Module

170‧‧‧Selection module

N1‧‧‧ first endpoint

N2‧‧‧ second endpoint

N3‧‧‧ third endpoint

N4‧‧‧ fourth endpoint

N5‧‧‧ fifth endpoint

UA1~UA(N-1)‧‧‧ first switching unit

UB1~UB(N-1)‧‧‧Second switching unit

SW1‧‧‧ first switch

SW2‧‧‧second switch

CA1~CA(N-1)‧‧‧first capacitor

CB1~CB(N-1)‧‧‧second capacitor

CKin‧‧‧ clock signal

IN1‧‧‧ first input

IN2‧‧‧ second input

OUT‧‧‧ output

ScA0~ScA(N-1)‧‧‧ first control signal

ScB0~ScB(N-1)‧‧‧second control signal

B1~BN‧‧‧digit code

Vip‧‧ positive input signal

Vin‧‧‧Inverting input signal

Vrp‧‧‧ positive phase reference voltage

Vrn‧‧‧inverted reference voltage

Vcm‧‧‧ Common mode voltage

CAN‧‧‧ third capacitor

CBN‧‧‧fourth capacitor

VA‧‧‧ terminal voltage

VB‧‧‧ terminal voltage

Claims (17)

A progressive approximation (SAR) analog-to-digital converter capable of amplifying an input signal amplitude, comprising: a first end point for receiving one of a differential input signal; and a second end point for receiving the The other of the differential input signals; a third terminal for receiving a positive phase reference voltage; a fourth terminal for receiving an inverted reference voltage; and a fifth terminal for receiving a total of a comparator having a first input terminal, a second input terminal, and an output terminal; a SAR control circuit coupled to the output terminal for generating a first control signal according to an output of the comparator a second control signal and a digital signal; a selection module comprising: a plurality of first switching units controlled by the first control signal; a plurality of second switching units controlled by the second control signal; a switch coupled between the first input end and the first end point; and a second switch coupled between the second input end and the second end point; and a capacitor module including : a plurality of first capacitors respectively corresponding to the first switching unit, coupled between the first input end and the corresponding first switching unit, wherein each of the first capacitors is coupled via the corresponding first switching unit Up to the third end point, the fourth end point, and the fifth end point, and at least one of the first capacitors is coupled to the second end point via the corresponding first switching unit; a second capacitor, corresponding to the second switching unit, coupled between the second input terminal and the corresponding second switching unit, wherein each of the second capacitors is coupled to the second switching unit via the corresponding second switching unit The third endpoint, the fourth endpoint, and the fifth endpoint. The SAR analog-to-digital converter of the programmable amplifying input signal amplitude of claim 1, wherein the first capacitors are coupled to the first end point via the corresponding first switching unit. The SAR analog-to-digital converter of the programmable amplified input signal amplitude of claim 2, wherein during the sampling phase, the upper plates of the first capacitors sample the one of the differential input signals, and the A lower plate of a capacitor samples the other of the differential input signals. The SAR analog-to-digital converter of the programmable amplifying input signal amplitude of claim 1 or 2, wherein the second capacitors are coupled to the second end point via the corresponding second switching unit. The SAR analog-to-digital converter of the programmable amplified input signal amplitude of claim 4, wherein during the sampling phase, the upper plates of the second capacitors sample the other of the differential input signals, and The lower plates of the second capacitors sample the one of the differential input signals. The SAR analog-to-digital converter of the programmable amplifying input signal amplitude according to claim 1 or 2, wherein at least one of the second capacitors is further coupled to the first end point via the corresponding second switching unit The SAR analog-to-digital converter of the programmable amplified input signal amplitude of claim 6, wherein during the sampling phase, the upper plates of the second capacitors sample the other of the differential input signals, A lower plate of the at least one of the second capacitors samples the one of the differential input signals and the lower plate of the remaining ones of the second capacitors receives the common mode voltage. The SAR analog-to-digital converter of claim 1, wherein the capacitor module further includes: a third capacitor coupled between the first input end and the fifth end point; And a fourth capacitor coupled between the second input terminal and the fifth terminal end. The SAR analog-to-digital converter of the programmable amplified input signal amplitude as claimed in claim 1, wherein each of the first switching unit and the second switching units is composed of a plurality of switches. The SAR analog-to-digital converter of the programmable amplified input signal amplitude according to claim 1, wherein during the sampling phase, the upper plates of the first capacitors sample the one of the differential input signals, the first A lower plate of at least one of the capacitors samples the other of the differential input signals, and a lower plate of the remaining ones of the first capacitors receives the common mode voltage. SAR analog digital conversion method for programmable amplification of input signal amplitude The method includes: sampling, during a sampling phase, one of a differential input signal by using an upper plate of the plurality of first capacitors in the capacitor module; utilizing at least one of the first capacitors The lower plate samples the other of the differential input signals; and samples the other of the differential input signals by using an upper plate of the plurality of second capacitors in the capacitor module, wherein the second The capacitors respectively correspond to the first capacitors; and the sampling phase enters a holding phase, during which the first plates of the first capacitors are disconnected from the differential input signal; Setting the lower plates of the first capacitors to be electrically connected to a common mode voltage; and disconnecting the upper plates of the second capacitors from the other of the differential input signals; And entering, by the holding phase, a one-bit looping phase, during which the comparing, by using a comparator, the terminal voltages of the upper plates of the first capacitors and the second capacitors The terminal voltage of the plate; in accordance with the comparator The more that the lower plate of the first one of the plurality of capacitors and a second capacitance corresponding to those of The lower plate is electrically connected to the common mode voltage to be electrically connected to a differential reference voltage, and is used again to compare the terminal voltages of the upper plates of the first capacitors after each switching. And the terminal voltages of the upper plates of the second capacitors; and generating a digital signal according to the outputs of the comparators. The SAR analog-to-digital conversion method of the programmable amplified input signal amplitude according to claim 11, wherein the step of sampling the other of the differential input signals by using a lower plate of at least one of the first capacitors The method further includes: electrically connecting the lower plates of the at least one of the first capacitors to the other one of the differential input signals; and lowering the rest of the first capacitors The plates are electrically connected to the common mode voltage. The SAR analog-to-digital conversion method of the programmable amplified input signal amplitude according to claim 11, wherein the step of sampling the other of the differential input signals by using a lower plate of at least one of the first capacitors The method includes: electrically connecting the lower plates of the first capacitors to the other one of the differential input signals. The SAR analog-to-digital conversion method of the programmable amplified input signal amplitude of any one of claims 11 to 13, wherein the sampling phase further comprises: utilizing a lower pole of at least one of the second capacitors The board samples the one of the differential input signals; and wherein during the maintaining phase, the method further includes: setting the lower plates of the second capacitors to electrical Connect the common mode voltage. The SAR analog-to-digital conversion method of the programmable amplified input signal amplitude of claim 14, wherein the step of sampling the differential input signal by using a lower plate of at least one of the second capacitors comprises: And electrically connecting the lower plates of the at least one of the second capacitors to the one of the differential input signals; and electrically charging the lower plates of the remaining of the second capacitors Connected to the common mode voltage. The SAR analog-to-digital conversion method of the programmable amplified input signal amplitude of claim 14, wherein the step of sampling the differential input signal by using a lower plate of at least one of the second capacitors comprises: And electrically connecting the lower plates of the second capacitors to the one of the differential input signals. The method of claim 11, wherein the capacitor module further comprises a third capacitor coupled between the first input end of the comparator and the common mode voltage. And a fourth capacitor coupled between the second input of the comparator and the common mode voltage.