TW202218343A - Multiplying digital-to-analog converter with pre-sampling and associated pipelined analog-to-digital converter - Google Patents

Abstract

A multiplying digital-to-analog converter includes an operational amplifier, a sampling capacitor circuit, a pre-sampling capacitor circuit, and a switch circuit. During a sampling cycle, the switch circuit connects a pre-defined voltage and reference voltages to the pre-sampling capacitor circuit, disconnects the pre-sampling capacitor circuit from an input port of the operational amplifier and the sampling capacitor circuit, disconnects an output port of the operational amplifier from the sampling capacitor circuit, and connects a voltage input to the sampling capacitor circuit. During a conversion cycle, the switch circuit connects the pre-sampling capacitor circuit to the sampling capacitor circuit, disconnects the pre-defined voltage and the reference voltages from the pre-sampling capacitor circuit, connects the pre-sampling capacitor circuit to the input port of the operational amplifier, connects the output port of the operational amplifier to the sampling capacitor circuit, and disconnects the voltage input from the sampling capacitor circuit.

Description

Multiplying digital-to-analog converters with pre-sampling and associated pipelined analog-to-digital converters

The present invention relates to conversion between analog and digital signals, and more particularly, to a multiplying digital-to-analog converter (MDAC) with pre-sampling and an associated pipelined analog-to-digital converter (analog-to-digital converter, ADC).

Analog-to-digital converters (ADCs) are used in various electronic systems. Such systems require cost-effective ADCs that can efficiently convert analog input signals to digital output signals over a wide frequency range and signal amplitude while minimizing noise and distortion.

The ADC typically converts the analog signal to a digital signal by sampling the analog signal at predetermined sampling intervals and generating a binary digital sequence via a quantizer, where the binary digital sequence is a digital representation of the sampled analog signal. Some common types of ADCs include flash memory ADCs, pipeline ADCs, successive approximation register (SAR) ADCs, and more. Of these different types, pipelined ADCs are particularly popular in applications that require higher resolution. Typical pipelined ADCs use switched capacitor circuits to increase or decrease charge and active circuits such as op amps for multiplication, they are very susceptible to component mismatch (such as capacitor mismatch) and circuit defects (such as limited amplifier gain) Influence. Additionally, a typical pipelined ADC may employ high gain and high speed op amps, which have high power consumption and require background calibration. Therefore, there is a need for an innovative low-power pipelined ADC that does not require background calibration.

It is an object of the present invention to provide a multiplying digital-to-analog converter (MDAC) with pre-sampling and an associated pipelined analog-to-digital converter (ADC).

According to a first aspect of the present invention, an exemplary multiplying digital-to-analog converter (MDAC) is disclosed. An exemplary MDAC includes an operational amplifier, a sampling capacitor circuit, a pre-sampling capacitor circuit, and a switching circuit. Wherein, the operational amplifier has an input port and an output port; the switch circuit is used to control the interconnection between the operational amplifier, the sampling capacitor circuit and the pre-sampling capacitor circuit; wherein, in the sampling period of the MDAC During the period, the switch circuit is configured to connect a predefined voltage to the pre-sampling capacitor circuit, connect a plurality of reference voltages to the pre-sampling capacitor circuit, disconnect the pre-sampling capacitor circuit from the input of the operational amplifier port, disconnect the pre-sampling capacitor circuit and the sampling capacitor circuit, disconnect the output port of the operational amplifier from the sampling capacitor circuit, connect the voltage input of the MDAC to the a sampling capacitor circuit; and wherein, during a conversion cycle of the MDAC, the switch circuit is used to connect the pre-sampling capacitor circuit to the sampling capacitor circuit, wherein the pre-sampling capacitor circuit is connected to the sampling capacitor circuit The connection configuration between the voltage inputs depends on the quantization result of the voltage input, further disconnecting the predefined voltage from the pre-sampling capacitor circuit, disconnecting the plurality of reference voltages from the pre-sampling capacitor circuit, The pre-sampling capacitor circuit is connected to the input of the operational amplifier, the output of the operational amplifier is connected to the sampling capacitor circuit, and the voltage input is disconnected from the sampling capacitor circuit.

Wherein, connecting a predefined voltage to the pre-sampling capacitor circuit means providing a predefined voltage to the pre-sampling capacitor circuit; connecting a plurality of reference voltages to the pre-sampling capacitor circuit means providing a plurality of reference voltages to the pre-sampling capacitor circuit ; connecting the voltage input of the MDAC to the sampling capacitor circuit means supplying the voltage input of the MDAC to the sampling capacitor circuit; disconnecting the predefined voltage from the pre-sampling capacitor circuit means not supplying the predefined voltage to the pre-sampling capacitor circuit ; Disconnecting the plurality of reference voltages from the pre-sampling capacitor circuit means not supplying the plurality of reference voltages to the pre-sampling capacitor circuit; Disconnecting the voltage input from the sampling capacitor circuit means not supplying the voltage input to the sampling capacitor circuit .

According to a second aspect of the present invention, an exemplary pipelined analog-to-digital converter (ADC) is disclosed. An exemplary pipelined ADC includes multiple stages and combinational circuits. The stages are arranged to produce a plurality of digital outputs, respectively. A combining circuit is arranged to combine the plurality of digital outputs. At least one of the plurality of stages includes a quantization circuit and a multiplying digital-to-analog converter (MDAC). A quantization circuit is arranged to generate a quantized result of the voltage input of the at least one of the plurality of stages, wherein the digital output of the at least one of the plurality of stages is dependent on the quantized result of the voltage input. The MDAC includes an operational amplifier, a sampling capacitor circuit, a pre-sampling capacitor circuit and a switch circuit. The operational amplifier has an input port and an output port. The switch circuit is used to control the interconnection between the operational amplifier, the sampling capacitor circuit and the pre-sampling capacitor circuit. wherein, during a sampling period of the MDAC, the switching circuit is configured to connect a predefined voltage to the pre-sampling capacitor circuit, connect a plurality of reference voltages to the pre-sampling capacitor circuit, and disconnect the pre-sampling The capacitor circuit is connected to the input port of the operational amplifier, the connection between the pre-sampling capacitor circuit and the sampling capacitor circuit is disconnected, the connection between the output port of the operational amplifier and the sampling capacitor circuit is disconnected, and the a voltage input of the MDAC is connected to the sampling capacitor circuit; and wherein, during a conversion period of the MDAC, the switching circuit is used to connect the pre-sampling capacitor circuit to the sampling capacitor circuit, wherein the pre-sampling capacitor circuit is The connection configuration between the sampling capacitor circuit and the sampling capacitor circuit depends on the quantization result of the voltage input, further disconnecting the predefined voltage from the pre-sampling capacitor circuit, and connecting the plurality of reference voltages with all the reference voltages. the pre-sampling capacitor circuit is disconnected, the pre-sampling capacitor circuit is connected to the input of the operational amplifier, the output of the operational amplifier is connected to the sampling capacitor circuit, and the voltage input is connected to the The sampling capacitor circuit is disconnected.

According to a third aspect of the present invention, there is provided an MDAC comprising: an operational amplifier; a sampling capacitor circuit; and a pre-sampling capacitor circuit; wherein, during a sampling period of the MDAC, the pre-sampling capacitor circuit samples and holds a plurality of pre-sampling capacitor circuits sampling a reference voltage, the sampling capacitor circuit sampling the voltage input of the MDAC; wherein, during a conversion period of the MDAC, the pre-sampling capacitor circuit is coupled to the sampling capacitor circuit, the operational amplifier according to the voltage The input and one of the plurality of pre-sampling reference voltages set the voltage output of the output port of the operational amplifier; the connection configuration between the pre-sampling capacitor circuit and the sampling capacitor circuit depends on the quantization result of the voltage input, so The voltage output is obtained from a combination of voltages based on the voltage input and one of the plurality of pre-sampled reference voltages.

According to a fourth aspect of the present invention, there is provided a pipelined analog-to-digital converter ADC comprising a plurality of stages connected in a pipelined manner and arranged to respectively generate a plurality of digital outputs; and a combining circuit for combining the plurality of digital outputs output; wherein at least one of the plurality of stages includes: a quantization circuit and the above-mentioned MDAC.

The multiplying digital-to-analog converter MDAC and the pipeline ADC provided by the embodiments of the present invention can reduce the power consumed by the operational amplifier.

These and other objects of the present invention will no doubt become apparent to those of ordinary skill in the art after reading the various drawings and the following detailed description of the preferred embodiments shown in the accompanying drawings.

Certain terms are used in the following descriptions and claims to refer to specific components. Those of ordinary skill in the art will understand that electronic equipment manufacturers may refer to components by different names. This application does not intend to distinguish between components that have different names but have the same function. In the following description and claims, the terms "including" and "comprising" are used in an open-ended fashion and should therefore be interpreted as "including but not limited to...". Furthermore, the term "coupled" is intended to mean an indirect or direct electrical connection. Thus, if one device is coupled to another device, the connection may be through a direct electrical connection, or through an indirect electrical connection via the other device and connection.

FIG. 1 is a block diagram illustrating a multiplying digital-to-analog converter (MDAC) with pre-sampling in accordance with an embodiment of the present invention. The MDAC 100 includes an operational amplifier 102 , a switching circuit 104 , and a plurality of capacitive circuits including a pre-sampling capacitor circuit 106 and a sampling capacitor circuit 108 . The operational amplifier 102 has an input port 112 and an output port 114 . For example, input port 112 may include a non-inverting input node (+) and an inverting input node (-), and output port 114 may include a non-inverting output node (+) and an inverting output node (-). Since MDAC 100 is a switched capacitor circuit, switching circuit 104 is arranged to control the interconnection between operational amplifier 102 , sampling capacitor circuit 108 and pre-sampling capacitor circuit 106 .

The operation of the DAC-subtract-gain function performed by the MDAC 100 may be divided into a sampling period and a conversion period following the sampling period. During a sampling period of the MDAC 100, the switch circuit 104 is set to connect the predefined voltage Vpd to the pre-sampling capacitor circuit 106, connecting a plurality of reference voltages (eg, Vrefn, Vcm, and Vrefp, where Vrefp > Vcm > Vrefn and Vcm=Vrefp +Vrefn=0V) to the pre-sampling capacitor circuit 106, disconnect the pre-sampling capacitor circuit 106 from the input port 112 of the operational amplifier 102, disconnect the pre-sampling capacitor circuit 106 from the sampling capacitor circuit 108, connect the The output port 114 is disconnected from the sampling capacitor circuit 108 and connects the voltage input V_IN of the MDAC 100 to the sampling capacitor circuit 108 . For example, the voltage input V_IN may be a differential input that includes a positive signal Vip and a negative signal Vin (ie, V_IN=Vip-Vin).

During the conversion cycle of the MDAC 100, the switching circuit 104 is used to connect the pre-sampling capacitor circuit 106 to the sampling capacitor circuit 108, wherein the connection configuration between the pre-sampling capacitor circuit 106 and the sampling capacitor circuit 108 depends on the quantization of the voltage input V_IN ( quantization) results, while the switch circuit 104 is also used to disconnect the predefined voltage Vpd from the pre-sampling capacitor circuit 106, disconnect the reference voltages (eg, Vrefn, Vcm, and Vrefp) from the pre-sampling capacitor circuit 106, connect the The pre-sampling capacitor circuit 106 is connected to the input port 112 of the operational amplifier 102, the output port 114 of the operational amplifier 102 is connected to the sampling capacitor circuit 108, and the sampling capacitor circuit 108 is disconnected from the voltage input V_IN. Using the pre-sampling capacitor circuit 106 can relax the power requirements of the operational amplifier as well as the power requirements of the reference buffer.

FIG. 2 is a circuit diagram of an MDAC with pre-sampling in accordance with an embodiment of the present invention. The MDAC 100 shown in FIG. 1 can be implemented by the MDAC 200 shown in FIG. 2 . The MDAC 200 includes an operational amplifier OPAMP, a plurality of pre-sampling capacitors Cps1, Cps0, Cps-1, C'ps1, C'ps0, C'ps-1, a plurality of sampling capacitors Csam, C'sam, and a plurality of switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW9, SW10, SW11, SW'1, SW'2, SW'3, SW'4, SW'5, SW'6, SW'7, SW' 8. SW'9, SW'10, SW'11. The operational amplifier 102 shown in Figure 1 can be implemented using the operational amplifier OPAMP shown in Figure 2, where the operational amplifier OPAMP is a differential amplifier whose input ports include a non-inverting input node (+) and an inverting input node (-) , the output port includes an inverting output node (-) and a non-inverting output node (+). The pre-sampling capacitor circuit 106 shown in FIG. 1 can be implemented using the pre-sampling capacitors Cps1 , Cps0 , Cps−1 , C′ps1 , C′ps0 , and C′ps−1 shown in FIG. 2 . The sampling capacitor circuit 108 shown in FIG. 1 can be realized using the sampling capacitors Csam and C'sam shown in FIG. 2 . The switch circuit 104 shown in FIG. 1 can be realized using switches SW1 to SW11 and SW′ 1 to SW′ 11 shown in FIG. 2 .

Pre-sampling capacitors Cpsl, Cps0, Cps-1, C'psl, C'ps0, C'ps-1 are used to pre-sample Vref, 0V and -Vref, where Vrefp-Vrefn=Vref, Vrefn-Vrefp=-Vref , Vcm=0V. The sampling capacitors Csam and C'sam are used to sample a voltage input (Vip-Vin), which is a differential input including a positive signal Vip and a negative signal Vin. The principle of the proposed MDAC design with pre-sampling is to combine the voltage difference held by the capacitor to achieve reference voltage subtraction and input voltage amplification. Figure 3 is a schematic diagram illustrating the principle of the proposed MDAC design with pre-sampling according to an embodiment of the present invention. Assume that a voltage difference ΔV1 is maintained between the top and bottom plates of capacitor C1, and another voltage difference ΔV2 is maintained between the top and bottom plates of capacitor C2. When capacitors C1 and C2 are in series, the voltage across the series-connected capacitors C1 and C2 is equal to ΔV1 + ΔV2. For MDAC200, the voltage output V_OUT is the MDAC output, and is determined by △V1=2*(Vip-Vin) and △V2=Dout*Vref, that is, V_OUT = 2*(Vip-Vin) + Dout*Vref. The voltage 2*(Vip-Vin) is obtained through the sampling capacitor. The voltage Dout*Vref is achieved by the selection of the pre-sampling capacitor. FIG. 4 is a schematic diagram showing a transfer curve of the MDAC 200 shown in FIG. 2 . If (Vip-Vin) > Vref/4, then Dout=-1 and V_OUT=2*(Vip-Vin)+Vref. If -Vref/4 ≦ (Vip-Vin) ≦ Vref/4, then Dout=0 and V_OUT=2*(Vip-Vin). When (Vip-Vin) < -Vref/4, Dout=+1 and V_OUT=2*(Vip-Vin)-Vref. Further details of the proposed MDAC 200 with pre-sampling are described below.

As described above, the operation of the DAC-subtract-gain function performed by the MDAC 200 is divided into a sampling period and a conversion period following the sampling period. For example, the sampling period is enabled by the first clock, and the conversion period is enabled by the second clock, wherein the first clock and the second clock are non-overlapping clocks, and the on-off state of the switch can be enabled by the first clock and the second clock. control. One node of the switch SW1 is coupled to a predefined voltage (eg, the bias voltage Vbias of the operational amplifier OPAMP), and the other node is coupled to one plate of each of the pre-sampling capacitors Cps1, Cps0, Cps-1. In this embodiment, Vpd=Vbias. One node of the switch SW'1 is coupled to a predefined voltage (eg, the bias voltage Vbias of the operational amplifier OPAMP) and the other node is coupled to each of the pre-sampling capacitors C'ps1, C'ps0, C'ps-1. one plate of each. One node of the switch SW5 is coupled to the non-inverting input node (+) of the operational amplifier OPAMP, and the other node is coupled to one plate of each of the pre-sampling capacitors Cps1, Cps0, Cps-1. One node of the switch SW'5 is coupled to the inverting input node (-) of the operational amplifier OPAMP, and the other node is coupled to one pole of each of the pre-sampling capacitors C'ps1, C'ps0, C'ps-1 board. One node of the switch SW9 is coupled to the inverting output node (-) of the operational amplifier OPAMP, and the other node is coupled to one plate of the sampling capacitor Csam. One node of the switch SW'9 is coupled to the non-inverting output node (+) of the operational amplifier OPAMP, and the other node is coupled to one plate of the sampling capacitor C'sam.

One node of the switch SW2 is coupled to the reference voltage Vrefp, and the other node is coupled to the other plate of the pre-sampling capacitor Cps1. One node of the switch SW'2 is coupled to the reference voltage Vrefn, and the other node is coupled to the other plate of the pre-sampling capacitor C'ps1. One node of the switch SW3 is coupled to the reference voltage Vcm, and the other node is coupled to the other plate of the pre-sampling capacitor Cps0. One node of the switch SW'3 is coupled to the reference voltage Vcm, and the other node is coupled to the other plate of the pre-sampling capacitor C'ps0. One node of the switch SW4 is coupled to the reference voltage Vrefn, and the other node is coupled to the other plate of the pre-sampling capacitor Cps-1. One node of the switch SW'4 is coupled to the reference voltage Vrefp, and the other node is coupled to the other plate of the pre-sampling capacitor C'ps-1. When a pair of pre-sampling capacitors Cps1 and C'ps1 are selected for providing the pre-sampling reference voltage Vref according to the quantization result of the voltage input, the pair of pre-sampling capacitors Cps0 and C'ps0 and the pair of pre-sampling capacitors Cps-1 and C' are not selected ps-1.

One node of the switch SW6 is coupled to the other plate of the pre-sampling capacitor Cps1, and the other node of the switch SW6 is coupled to the other plate of the sampling capacitor Csam. One node of switch SW7 is coupled to the other plate of the pre-sampling capacitor Cps0 and the other node is coupled to the other plate of the sampling capacitor Csam. One node of the switch SW8 is coupled to the other plate of the pre-sampling capacitor Cps-1, and the other node of the switch SW8 is coupled to the other plate of the sampling capacitor Csam. One node of switch SW'6 is coupled to the other plate of the pre-sampling capacitor C'ps1 and the other node is coupled to the other plate of the sampling capacitor C'sam. One node of switch SW'7 is coupled to the other plate of the pre-sampling capacitor C'ps0 and the other node is coupled to the other plate of the sampling capacitor C'sam. One node of switch SW'8 is coupled to the other plate of the pre-sampling capacitor C'ps-1 and the other node is coupled to the other plate of the sampling capacitor C'sam.

The switch SW10 has one node coupled to the other plate of the sampling capacitor Csam and another node coupled to the negative signal Vin of the differential voltage input. One node of the switch SW11 is coupled to one plate of the sampling capacitor Csam, and the other node is coupled to the positive signal Vip of the differential voltage input. One node of the switch SW'10 is coupled to the other plate of the sampling capacitor C'sam, and the other node is coupled to the positive signal Vip of the differential voltage input. One node of the switch SW'11 is coupled to one plate of the sampling capacitor C'sam, and the other node is coupled to the negative signal Vin of the differential voltage input.

During the sampling period, each of the switches SW1, SW2, SW3, SW4, SW10, SW11, SW'1, SW2', SW'3, SW'4, SW'10, SW'11 is turned on, and the switches Each of SW5, SW6, SW7, SW8, SW9, SW'5, SW'6, SW'7, SW'8, SW'9 is turned off. FIG. 5 is an equivalent circuit diagram showing MDAC 200 operating during a sampling period. For a period of time, the voltage difference (Vrefp-Vbias) remains between the two plates of the pre-sampling capacitor Cps1. During a period of time, the voltage difference (Vcm-Vbias) remains between the two plates of the pre-sampling capacitor Cps0. During a period of time, the voltage difference (Vrefn-Vbias) remains between the two plates of the pre-sampling capacitor Cps-1. For a period of time, the voltage difference (Vrefn-Vbias) remains between the two plates of the pre-sampling capacitor C'ps1. During a period of time, the voltage difference (Vcm-Vbias) remains between the two plates of the pre-sampling capacitor C'ps0. For a period of time, the voltage difference (Vrefp-Vbias) remains between the two plates of the pre-sampling capacitor C'ps-1. During a period of time, the voltage difference (Vin-Vip) is maintained between the two plates of the sampling capacitor Csam. The voltage difference (Vip-Vin) is maintained between the two plates of the sampling capacitor C'sam.

During the switching period, each of the switches SW1, SW2, SW3, SW4, SW10, SW11, SW'1, SW2', SW'3, SW'4, SW'10, SW'11 is opened, and the switches Each of SW5, SW9, SW'5, SW'9 is turned on. Each of the switches SW6, SW7, SW8, SW'6, SW'7, SW'8 is selectively turned on in response to a quantized result of the voltage input (Vip-Vin). When the pre-sampling capacitor pair Cps1 and C'ps1 is selected to provide the pre-sampling reference voltage Vref (ie Vrefp-Vrefn) according to the quantization result of the voltage input (Vip-Vin), the pre-sampling capacitor pair Cps0 and C'ps0 and the pre-sampling capacitor No selection was made for Cps-1 and C'ps-1. When the pre-sampling capacitor pair Cps0 and C'ps0 is selected to provide the pre-sampling reference voltage 0V (ie Vcm-Vcm) according to the quantization result of the voltage input (Vip-Vin), the pre-sampling capacitor pair Cps1 and C'ps1 and the pre-sampling capacitor pair Cps-1 and C'ps-1 were not selected. When the pre-sampling capacitor pair Cps-1 and C'ps-1 is selected to provide the pre-sampling reference voltage -Vref (ie Vrefn-Vrefp) according to the quantization result of the voltage input (Vip-Vin), the pre-sampling capacitor pair Cps0 and C'ps0 And the pre-sampling capacitor pair Cps1 and C'ps1 is not selected.

For example, when (Vip-Vin) is greater than Vref/4, the quantization result of the voltage input (Vip-Vin) can generate a 2-bit digital output "11", and the decision circuit can refer to the quantization result to switch on (switch on) ) switches SW8 and SW'8, switch off switches SW6, SW6 ' , SW7 and SW'7 . FIG. 6 is an equivalent circuit diagram of the MDAC 200 under the condition (Vip-Vin)>Vref/4 during the conversion cycle. As shown in Figure 6, the pre-sampling capacitor Cps-1 and the sampling capacitor Csam are connected in series, the pre-sampling capacitor C'ps -1 and the sampling capacitor C'sam are connected in series, and one plate of the pre-sampling capacitor Cps-1 is connected to the operational amplifier OPAMP The virtual ground (floating ground) of the pre-sampling capacitor C ' ps-1 is connected to the virtual ground (floating ground) of the operational amplifier OPAMP. The voltage difference between the inverting output node (-) and the non-inverting input node (+) of the operational amplifier OPAMP is equal to (Vip-Vin)+(Vrefn-Vbias). The voltage difference between the non-inverting output node (+) and the inverting input node (-) of the operational amplifier OPAMP is equal to (Vin-Vip)+(Vrefp-Vbias). Therefore, the voltage output V_OUT can be represented as follows:

V_OUT= (Vip-Vin)+(Vrefn-Vbias)-[(Vin-Vip)+(Vrefp-Vbias)]

=2*(Vip-Vin)+(Vrefn-Vrefp)

=2*(Vip-Vin)-Vref

For another example, when (Vip-Vin) is not greater than Vref/4 and not less than -Vref/4, the quantization result of the voltage input (Vip-Vin) can generate a 2-bit digital output "01", and the decision circuit can refer to the quantization result to turn on the switches SW7 and SW'7, and turn off the switches SW6, SW6', SW8 and SW'8. FIG. 7 is an equivalent circuit diagram illustrating the MDAC 200 operating under the condition of -Vref/4≦(Vip-Vin)≦Vref/4 during the conversion period. As shown in Figure 7, the pre-sampling capacitor Cps0 is connected in series with the sampling capacitor Csam, the pre-sampling capacitor C'ps0 is connected in series with the sampling capacitor C'sam, and one plate of the pre-sampling capacitor Cps0 is connected to the virtual (virtual) of the operational amplifier OPAMP. Ground (floating), one plate of the pre-sampling capacitor C'ps0 is connected to the virtual ground (floating) of the operational amplifier OPAMP. The voltage difference between the inverting output node (-) and the non-inverting input node (+) of the operational amplifier OPAMP is equal to (Vip-Vin)+(Vcm-Vbias). The voltage difference between the non-inverting output node (+) and the inverting input node (-) of the operational amplifier OPAMP is equal to (Vin-Vip)+(Vcm-Vbias). Therefore, the voltage output V_OUT can be represented as follows:

V_OUT= (Vip-Vin)+(Vcm-Vbias)-[(Vin-Vip)+(Vcm-Vbias)]

=2*(Vip-Vin)

For another example, when (Vip-Vin) is less than -Vref/4, the quantization result of the voltage input (Vip-Vin) can generate a 2-bit digital output "00", and the decision circuit can refer to the quantization result to turn on the switches SW6 and SW '6, open switches SW7, SW7', SW8 and SW'8. FIG. 8 is an equivalent circuit diagram illustrating the MDAC 200 operating under the condition (Vip-Vin)<-Vref/4 during the conversion period. As shown in Figure 8, the pre-sampling capacitor Cps1 is connected in series with the sampling capacitor Csam, the pre-sampling capacitor C'ps1 is connected in series with the sampling capacitor C'sam, and one plate of the pre-sampling capacitor Cps1 is connected to the virtual ground (floating ground) of the operational amplifier OPAMP. ), one plate of the pre-sampling capacitor C'ps1 is connected to the virtual ground (floating ground) of the operational amplifier OPAMP. The voltage difference between the inverting output node (-) and the non-inverting input node (+) of the operational amplifier OPAMP is equal to (Vip-Vin)+(Vrefp-Vbias). The voltage difference between the non-inverting output node (+) and the inverting input node (-) of the operational amplifier OPAMP is equal to (Vin-Vip)+(Vrefn-Vbias). Therefore, the voltage output V_OUT can be represented as follows:

V_OUT= (Vip-Vin)+(Vrefp-Vbias)-[(Vin-Vip)+(Vrefn-Vbias)]

=2*(Vip-Vin)+(Vrefp-Vrefn)

=2*(Vip-Vin)+Vref

Since one plate of the selected pre-sampling capacitor that receives Vbias during the sampling period is floated during the conversion period, the OPAMP does not need to consume power to drive any capacitive load during the conversion period, so the OPAMP Has relaxed power requirements. Furthermore, as can be seen in Figures 6-8, the voltage output V_OUT is derived by combining the voltage across the selected pre-sampling capacitor and the voltage across the sampling capacitor. Therefore, the operational amplifier OPAMP has a feedback factor (β) equal to one. Compared with the operational amplifier with β<1, the operational amplifier OPAMP can have wider bandwidth or lower power consumption. Additionally, since no charge flows between the selected precharge capacitors Cps1/Cps0/Cps-1/C'ps1/C'ps0/C'ps-1 and the sampling capacitors Csam/C'sam during the conversion cycle, the selected receiver There is no voltage change on one plate of the precharge capacitors Cps1/Cps0/Cps-1/C'ps1/C'ps0/C'ps-1 of the reference voltage Vrefp/Vcm/Vrefn provided by the external reference buffer. Since the reference buffer does not consume additional power to maintain the reference voltage Vrefp/Vcm/Vrefn during the conversion cycle, the power requirement of the reference buffer is relaxed.

As mentioned above, the voltage output V_OUT is derived by combining the voltage across the selected pre-sampling capacitor (also called the cross-voltage of the pre-sampling capacitor) with the voltage across the sampling capacitor (also called the cross-voltage of the sampling capacitor) , where one plate of the selected precharge capacitor receives a reference voltage from an external reference buffer. The output common-mode voltage is not determined by the input common-mode voltage. Therefore, the proposed MDAC 200 with pre-sampling can reject the input common mode offset. FIG. 9 is a schematic diagram of common mode rejection achieved by the proposed MDAC 200 with pre-sampling according to an embodiment of the present invention. Assuming that the positive signal Vip of the differential voltage input has a common mode offset (eg 10mV), the negative signal Vin of the differential voltage input also has a common mode offset (eg 10mV). During the sampling period, a fixed common-mode voltage appears on the pre-sampling capacitor. During the conversion period, the pre-sampling capacitor and the sampling capacitor are connected in series, and the voltage across the series-connected pre-sampling and sampling capacitors is equal to the sum of the voltage across the pre-sampling capacitor and the voltage across the sampling capacitor. Therefore, the output common-mode voltage is determined by the fixed common-mode voltage provided by the pre-sampling capacitor, independent of the input common-mode offset (eg, 10mV).

Conventional differential amplifiers can provide tail current sources as an effective technique for solving problems associated with common-mode offset. However, conventional differential amplifiers with tail current sources often sacrifice speed to address issues related to common-mode offset. Since the proposed MDAC 200 with pre-sampling suppresses the input common-mode offset, the operational amplifier OPAMP can be implemented by a differential amplifier without a tail current source, as shown in Figure 10. For example, the operational amplifier OPAMP may be a telescopic differential amplifier without a tail current source. Since the operational amplifier OPAMP does not use a tail current source, the output current is no longer limited by the tail current source. In this way, the operational amplifier OPAMP can operate at a higher speed to respond according to the differential amplifier input (eg {OP _in1 , OP _ip1 } and {OP _in0 , OP _ip0 } received by the telescopic differential amplifier shown in FIG. 10 ]. ) to set the differential amplifier output (OPout from the telescopic differential amplifier shown in Figure 10). Furthermore, since the proposed MDAC 200 with pre-sampling can suppress the input common-mode offset, the common-mode feedback circuit can be omitted from the operational amplifier OPAMP.

Compared to the conventional MDAC without pre-sampling, the proposed MDAC 200 with pre-sampling selects one of -Vref, 0V and Vref by pre-sampling capacitor selection to achieve 2X voltage by sampling the voltage input only at the sampling capacitor Amplification, same kT/C noise performance as using smaller sampling capacitor, using op amp with β=1, lower finite gain error and lower power dissipation, and can use no tail current source and relaxes the power requirements of the reference buffers used to provide the reference voltages Vrefp, Vcm and Vrefn. Furthermore, since the voltage output V_OUT is obtained by combining the voltage across the selected pre-sampling capacitor with the voltage across the sampling capacitor, the proposed MDAC 200 with pre-sampling does not require background calibration.

Compared with multi-stage op amps, single-stage op amps have lower power consumption and smaller output swing. When the operational amplifier OPAMP is implemented by a single stage operational amplifier, the MDAC 200 with pre-sampling can benefit from the low power consumption of the operational amplifier OPAMP. As mentioned above, the proposed MDAC 200 with pre-sampling can reject the input common-mode offset, and the operational amplifier OPAMP can be implemented by a differential amplifier without a tail current source. The operational amplifier OPAMP employed by the proposed MDAC 200 with pre-sampling may be a single stage differential amplifier without a tail current source. A single stage differential amplifier without a tail current source can provide the output swing required by the proposed MDAC 200 with pre-sampling due to the removal of the tail current source that affects the output swing.

In some embodiments of the invention, correlated-level-shifting (CLS) auxiliary op amps may be used in MDACs with pre-sampling to address the output swing problems encountered with single-stage op amps. It should be noted that the use of a CLS auxiliary op amp with/without tail current in an MDAC with pre-sampling is optional. Virtually any MDAC design using the proposed pre-sampling technique falls within the scope of the present invention.

11 is a circuit diagram of an MDAC with pre-sampling and CLS auxiliary op amps according to an embodiment of the present invention. The MDAC 100 shown in FIG. 1 can be implemented by the MDAC 1100 shown in FIG. 11 . In this embodiment, the operational amplifier OPAMP can be implemented by a single-stage differential amplifier with a tail current source or a single-stage differential amplifier without a tail current source. The main difference between MDAC200 and 1100 is that MDAC1100 also includes multiple CLS capacitors C _CLS , C ' _CLS and multiple switches SW12 , SW'12 , SW13 . One plate of CLS capacitor C _CLS is coupled to one plate of sampling capacitor Csam. CLS Capacitor C' One plate of _CLS is coupled to one plate of sampling capacitor C'sam. The switch SW13 is a reset switch, one node of which is coupled to the other plate of the CLS capacitor C _CLS and the other node is coupled to the other plate of the CLS capacitor C ′ _CLS . One node of the switch SW12 is coupled to the inverting output node (-) of the operational amplifier OPAMP, and the other node is coupled to one node of the switch SW13. One node of the switch SW'12 is coupled to the non-inverting output node (+) of the operational amplifier OPAMP, and the other node is coupled to the other node of the switch SW13.

During the sampling period, each of the switches SW1, SW2, SW3, SW4, SW10, SW11, SW'1, SW2', SW'3, SW'4, SW'10, SW'11 is turned on, and the switches Each of SW5, SW6, SW7, SW8, SW9, SW12, SW13, SW'5, SW'6, SW'7, SW'8, SW'9, SW'12 is turned off. During the switching cycle, each of the switches SW1, SW2, SW3, SW4, SW10, SW11, SW'1, SW2', SW'3, SW'4, SW'10, SW'11 is opened, and the switches Each of SW5, SW'5, SW9, SW'9 is turned on. Regarding each of the switches SW6, SW7, SW8, SW'6, SW'7 and SW'8, it is selectively turned on in response to the quantization result of the voltage input (Vip-Vin). Since the MDACs 200 and 1100 control the above switches during the sampling period and the conversion period are the same, for the sake of brevity, the details are not repeated here.

In contrast to MDAC 200, which has an amplifier output that acts directly as the MDAC output (ie, V_OUT), MDAC 1100 does not use the amplifier output OP_OUT as the MDAC output (ie, V_OUT). Specifically, the conversion cycle is divided into a first stage Amp1 and a second stage Amp2 following the first stage Amp1. In addition, the second stage Amp2 includes a start period in which a reset (RST) operation occurs to quickly reset the amplifier output OP_OUT. FIG. 12 is a schematic diagram illustrating the operation of the DAC gain reduction function performed by the MDAC 1100, including a sampling period, a first stage Amp1 of a conversion period, and a second stage Amp2 of the conversion period, where the second stage Amp2 includes a reset (RST) operate.

Referring to FIG. 11 in conjunction with FIG. 13 , FIG. 13 is a schematic diagram illustrating the voltage level of the amplifier output OP_OUT and the voltage level of the MDAC output (ie, V_OUT) during a conversion cycle of the MDAC 1100 . During the first phase Amp1 of the switching cycle, each of switch SW9 and switch SW'9 is turned on, and each of switches SW12, SW'12 , SW13 is turned off. FIG. 14 is an equivalent circuit diagram showing the MDAC 1100 operating during the first phase Ampl of the conversion cycle. Since the MDAC output terminal is coupled to the amplifier output terminal through switches SW9 and SW'9 , the voltage level of the amplifier output terminal OP_OUT is substantially the same as the voltage level of the MDAC output terminal (ie, V_OUT), as shown in FIG. 13 .

During the start period of the second phase Amp2 of the conversion cycle, each of the switches SW9 and SW'9 is turned off, and each of the switches SW12, SW'12 , SW13 is turned on. FIG. 15 is an equivalent circuit diagram showing the MDAC 1100 operating during the start period of the second phase Amp2 of the conversion cycle. As shown in Figure 13, the voltage level of the MDAC output (ie, _{V_OUT} ) is maintained by the _CLS capacitors C'CLS and C'CLS , while the voltage level of the amplifier output OP_OUT is reset to a common-mode voltage (eg, 0V).

During the remainder of the second phase Amp2 of the switching cycle, each of the switches SW9, SW'9 , SW13 is turned off, and each of the switches SW12, SW'12 is turned on. FIG. 16 is an equivalent circuit diagram illustrating the MDAC 1100 operating during the remainder of the second phase Amp2 of the conversion cycle. As shown in FIG. 13 , the operational amplifier OPAMP continuously adjusts the amplifier output OP_OUT, so that the voltage level of the MDAC output (ie V_OUT) is further adjusted by the voltage level of the amplifier output OP_OUT through capacitive coupling. As can be seen from Figure 13, the amplification operation of the operational amplifier OPAMP is divided into two stages Amp1 and Amp2. After the operational amplifier output OP_OUT is reset, the output swing required to operate the operational amplifier OPAMP in the second stage Amp2 is reduced. In this way, an MDAC output with a larger swing (ie, V_OUT) can be successfully obtained by using a CLS auxiliary single-stage amplifier with a smaller output swing. Furthermore, with the help of CLS capacitors and two-step amplification, the finite gain error of the operational amplifier OPAMP (ie, CLS auxiliary single-stage amplifier) can be greatly reduced.

The proposed MDAC with pre-sampling (or the proposed MDAC with pre-sampling and CLS auxiliary op amp) can be used by analog-to-digital converters (ADCs) such as pipelined ADCs or time-interleaved ADCs using pipelined ADCs . FIG. 17 is a schematic diagram of a pipelined ADC according to an embodiment of the present invention. The pipelined ADC 1700 includes a plurality of stages 1702_1 - 1702_N and a combining circuit 1704 . Stages 1702_1-1702_N are pipelined and arranged to produce a plurality of digital outputs D_1-D_N. Combining circuit 1704 is used to combine the digital outputs D_1-D_N to produce the final digital output. Stage 1702_N is a terminal ADC. For example, the end ADC can be implemented by a SAR ADC. In this embodiment, each of stages 1702_1-1702_(N-1) may employ the proposed MDAC with pre-sampling (or the proposed MDAC with pre-sampling and a CLS auxiliary op amp). Taking stage 1702_1 as an example, it includes a quantization circuit (QTZ) 1712 , a decision circuit 1714 and an MDAC 1716 . The quantization circuit 1712 produces a quantized result of the voltage input of stage 1702_1, wherein the digital output D_1 of the stage 1702_1 depends on the quantized result of the voltage input of the stage 1702_1. MDAC 1716 may be implemented by MDAC 200/1100. The decision circuit 1714 is configured to select one of the pre-sampling capacitors Cps1 , Cps0 , Cps-1 to be connected in series to one sampling capacitor Csam during the conversion period, and further to select one of the pre-sampling capacitors C to be connected in series to the other sampling capacitor C during the conversion period One of ' sam's pre-sampling capacitors C'ps1 , C'ps0 , C'ps -1. For example, decision circuit 1714 refers to the quantization result of the voltage input (eg, digital output D_1) to determine Dout*Vref to be combined with 2*(Vip-Vin), where if (Vip-Vin) < -Vref/4, then Dout =+1; if -Vref/4 ≦ (Vip-Vin) ≦ Vref/4, then Dout=0, if (Vip-Vin) > Vref/4, then Dout=-1.

Regarding the pipelined ADC 1700, the stage with the MDAC implemented by the MDAC 200/1100 has a 1.5-bit/stage structure. However, this is for illustrative purposes only, and is not meant to limit the present invention. With appropriate modifications to the MDAC 200/1100, a stage with a modified MDAC may have a 2.5 bits/stage structure or a 3.5 bits/stage structure. FIG. 18 is a circuit diagram illustrating another MDAC with pre-sampling according to an embodiment of the present invention. Regarding the pipelined ADC 1700, a stage with an MDAC implemented by the MDAC 1800 has a 2.5 bit/stage structure. The main difference between MDAC 200 and 1800 is that MDAC 1800 includes four sampling capacitors Csam1, Csam2, C'sam1 , C'sam2 and additional switches SW14 and SW'14 . Each of the switches SW10, SW11, SW14, SW'10, SW'11 , SW'14 is turned on during the sampling period and turned off during the conversion period. Since the details and benefits of the pre-sampling technique employed by MDAC 1800 can be readily understood by those skilled in the relevant art after reading the paragraphs above for MDAC 200, further description is omitted here for brevity.

In the above-described embodiments shown in Figures 2, 11 and 18, the predefined voltage V _pd is set by the bias voltage V _bias of the operational amplifier OPAMP. However, these are for illustrative purposes only, and are not meant to limit the present invention. Alternatively, the embodiments shown in Figures 2, 11 and 18 may be modified to have a predefined voltage _Vpd set by a different voltage such as a common mode voltage (eg, 0V). 19 is a circuit diagram of an MDAC with pre-sampling using a common-mode voltage as a predefined voltage, according to an embodiment of the present invention. The main difference between MDAC 200 and 1900 is that one node of switch SW1 is arranged to receive a reference voltage V _CM while one node of switch SW ′ 1 is arranged to receive a reference voltage V _CM , where the reference voltage V _CM is a common mode voltage (eg, 0V ).

In the above-described embodiments shown in Figures 2, 11 and 18, the arrangement of switches SW1, SW'1 , SW5, SW'5 controls the pre-sampling capacitors Cps1, Cps0, Cps-1, One plate of each of C'ps1 , C'ps0 , C'ps -1 is connected to a predefined voltage (eg, _Vpd = _Vbias ) and disconnected from the input port of the operational amplifier OPAMP, during conversion One plate of each of the pre-sampling capacitors Cps1, _Cps0 , Cps-1, C'ps1 , C'ps0 , C'ps -1 is controlled to be disconnected from a predefined voltage (eg, _Vpd =Vbias) during the cycle , and connect to the input port of the operational amplifier OPAMP. However, these are for illustrative purposes only, and are not meant to limit the present invention. Alternatively, the embodiments shown in Figures 2, 11 and 18 can be modified to have a different switch arrangement, which can achieve the same purpose of being arranged to make the pre-sampling capacitors Cps1, Cps0, Cps- during the sampling period 1. One plate of each of _C'ps1 , C'ps0 , C'ps - 1 is connected to a predefined voltage (eg, _Vpd = _Vbias or Vpd= _Vcm ) and is connected to the input port of the operational amplifier OPAMP Disconnect and connect one plate of the pre-sampling capacitors Cps1, _Cps0 , Cps-1, C'ps1 , C'ps0 , C'ps -1 to a predefined voltage (eg, _Vpd =Vbias) during the conversion cycle or V _pd =V _cm ) is disconnected and connected to the input port of the operational amplifier OPAMP.

20 is a circuit diagram of an MDAC with pre-sampling utilizing different switch arrangements, according to an embodiment of the present invention. The main difference between MDACs 200 and 2000 is that switch SW1 is replaced by switch group SG1 comprising a plurality of switches, switch SW'1 is replaced by switch group SG'1 comprising a plurality of switches, and switch SW5 is replaced by a switch group SG'1 comprising a plurality of switches The switch group SG5 is replaced, and the switch SW'5 is replaced by a switch group SG'5 comprising a plurality of switches.

Switch group SG1 has a switch, another switch, and yet another switch, the one switch having a first node coupled to a predefined voltage _Vpd (eg, _Vpd = _Vbias or _Vpd = _Vcm ) and a node coupled to The second node of one plate of the pre-sampling capacitor Cpsl, the other switch having a first node coupled to a predefined voltage Vpd (eg, Vpd=Vbias or Vpd=Vcm) and one coupled to the pre-sampling capacitor Cps0 The second node of the plate, the further switch has a first node coupled to a predefined voltage Vpd (eg, Vpd=Vbias or Vpd=Vcm) and a second node of one of the plates coupled to the pre-sampling capacitor Cps-1 two nodes.

Switch group SG'1 has one switch, another switch, and yet another switch, the one switch having a first node coupled to a predefined voltage Vpd (eg, Vpd=Vbias or Vpd=Vcm) and coupled to a pre-sampling capacitor A second node of one plate of C'ps1 , the other switch having a first node coupled to a predefined voltage Vpd (eg, Vpd=Vbias or Vpd=Vcm) and a pre-sampling capacitor C'ps0 A second node of one plate, the further switch has a first node coupled to a predefined voltage Vpd (eg, Vpd=Vbias or Vpd=Vcm) and a pole coupled to a pre-sampling capacitor C'ps -1 The second node of the board.

switch bank SG5 has a switch, another switch and yet another switch, the one switch having a first node coupled to the non-inverting input node of the operational amplifier OPAMP and a second node coupled to one plate of the pre-sampling capacitor Cps1, The other switch has a first node coupled to the non-inverting input node of the operational amplifier OPAMP and a second node coupled to one plate of the pre-sampling capacitor Cps0, the further switch has a non-inverting input coupled to the operational amplifier OPAMP A first node of the nodes and a second node coupled to one plate of the pre-sampling capacitor Cps-1.

Switch bank SG'5 has a switch, another switch, and yet another switch, the one switch having a first node coupled to the inverting input node of the operational amplifier OPAMP and one plate coupled to the pre-sampling capacitor C'ps1 The second node of the other switch has a first node coupled to the inverting input node of the operational amplifier OPAMP and a second node coupled to one plate of the pre-sampling capacitor C ' ps0 , the further switch has a second node coupled to A first node to the inverting input node of the operational amplifier OPAMP and a second node coupled to one plate of the pre-sampling capacitor C'ps -1.

During the sampling period of MDAC 2000, all switches contained in switch groups SG1 and SG'1 are turned on, and all switches contained in switch groups SG5 and SG'5 are turned off. During a conversion cycle of MDAC 2000, all switches contained in switch groups SG1 and SG'1 are turned off, while all switches contained in switch groups SG5 and SG'5 are turned on.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be subject to the appended claims.

100: MDAC 102: Operational Amplifier 112: input port 114: output port 104: switch circuit 106: Pre-sampling capacitor circuit 108: Sampling capacitor circuit 200, 1100: MDAC 1700: Pipeline ADC 1702_1-1702_N: level 1712: Quantization Circuits 1714: Decision Circuit 1716: MDAC 1704: Combinational Circuits 1800, 1900, 2000: MDAC

Figure 1 is a block diagram illustrating a multiplying digital-to-analog converter (MDAC) with pre-sampling in accordance with an embodiment of the present invention. FIG. 2 is a circuit diagram of an MDAC with pre-sampling in accordance with an embodiment of the present invention. Figure 3 is a schematic diagram illustrating the principle of the proposed MDAC design with pre-sampling according to an embodiment of the present invention. FIG. 4 is a graph showing the transfer curve of the MDAC shown in FIG. 2 . FIG. 5 is an equivalent circuit diagram showing the MDAC shown in FIG. 2 operating during the sampling period. FIG. 6 is an equivalent circuit diagram showing the MDAC shown in FIG. 2 operating under the condition of (Vip-Vin) > Vref/4 during the conversion cycle shown in FIG. 2 . FIG. 7 is an equivalent circuit diagram showing the MDAC operating under the condition of -Vref/4≦(Vip-Vin)≦Vref/4 during the conversion period shown in FIG. 2 , where ≦ denotes less than or equal to. Figure 8 is an equivalent circuit diagram showing the MDAC shown in Figure 2 operating under the condition (Vip-Vin) <-Vref/4 during the conversion cycle shown in Figure 2. Figure 9 is a schematic diagram illustrating common mode rejection achieved by the proposed MDAC with pre-sampling according to an embodiment of the present invention. FIG. 10 is a schematic diagram illustrating a differential amplifier without a tail current source according to an embodiment of the present invention. FIG. 11 is a circuit diagram of an MDAC with pre-sampling and a CLS-assisted operational amplifier according to an embodiment of the present invention. FIG. 12 is a schematic diagram showing the operation of the DAC-subtract-gain function performed by the MDAC shown in FIG. 11, where the MDAC includes a sampling period, a first stage of a conversion period, and a conversion The second phase of the cycle, where the second phase includes a reset (RST) operation. FIG. 13 is a schematic diagram showing the voltage level of the amplifier output and the voltage level of the MDAC output during the conversion period of the MDAC shown in FIG. 11 . FIG. 14 is an equivalent circuit diagram showing the MDAC shown in FIG. 11 operating in the first stage of the conversion cycle. FIG. 15 is an equivalent circuit diagram showing the MDAC shown in FIG. 11 operating during the start period of the second phase of the conversion cycle. FIG. 16 is an equivalent circuit diagram illustrating the MDAC shown in FIG. 11 operating during the remainder of the second phase of the conversion cycle. FIG. 17 is a schematic diagram illustrating a pipelined ADC according to an embodiment of the present invention. FIG. 18 is a circuit diagram illustrating another MDAC with pre-sampling according to an embodiment of the present invention. 19 is a circuit diagram of an MDAC with pre-sampling using a common-mode voltage as a predefined voltage, according to an embodiment of the present invention. 20 is a circuit diagram of an MDAC with pre-sampling utilizing different switch arrangements, according to an embodiment of the present invention.

200: MDAC

Claims (26)

A multiplying digital-to-analog converter MDAC, comprising: Operational amplifier, with input port and output port; sampling capacitor circuit; a pre-sampling capacitor circuit; and a switch circuit for controlling interconnection between the operational amplifier, the sampling capacitor circuit and the pre-sampling capacitor circuit; wherein, during a sampling period of the MDAC, the switching circuit is configured to connect a predefined voltage to the pre-sampling capacitor circuit, connect a plurality of reference voltages to the pre-sampling capacitor circuit, and disconnect the pre-sampling The capacitor is connected to the input port of the operational amplifier, the connection between the pre-sampling capacitor circuit and the sampling capacitor circuit is disconnected, the connection between the output port of the operational amplifier and the sampling capacitor circuit is disconnected, and the The voltage input of the MDAC is connected to the sampling capacitor circuit; and wherein the switching circuit is configured to connect the pre-sampling capacitor circuit to the sampling capacitor circuit during a conversion period of the MDAC, wherein the connection between the pre-sampling capacitor circuit and the sampling capacitor circuit is configured further disconnecting the predefined voltage from the pre-sampling capacitor circuit, disconnecting the plurality of reference voltages from the pre-sampling capacitor circuit, disconnecting the pre-sampling capacitor circuit depending on the quantization result of the voltage input A circuit is connected to the input of the operational amplifier, the output of the operational amplifier is connected to the sampling capacitor circuit, and the voltage input is disconnected from the sampling capacitor circuit. The MDAC of claim 1, wherein the pre-sampling capacitor circuit includes a first pre-sampling capacitor, a second pre-sampling capacitor, a third pre-sampling capacitor, a fourth pre-sampling capacitor, a fifth pre-sampling capacitor, and a six pre-sampling capacitors; and the switching circuit includes: a first switch having a first node coupled to the predefined voltage, and a first switch coupled to each of the first pre-sampling capacitor, the second pre-sampling capacitor, and the third pre-sampling capacitor a second node of a plate, wherein the first switch is on during the sampling period and the first switch is off during the conversion period; and A second switch having a first node coupled to the predefined voltage and coupled to one of each of the fourth pre-sampling capacitor, the fifth pre-sampling capacitor, and the sixth pre-sampling capacitor a second node of the plate, wherein the second switch is on during the sampling period and the second switch is off during the conversion period. The MDAC of claim 1, wherein the pre-sampling capacitor circuit includes a first pre-sampling capacitor, a second pre-sampling capacitor, a third pre-sampling capacitor, a fourth pre-sampling capacitor, a fifth pre-sampling capacitor, and a sixth pre-sampling capacitor A pre-sampling capacitor; the switch circuit includes: a first switch bank having one switch, another switch, and yet another switch; the one switch having a first node coupled to the predefined voltage, and a plate coupled to the first pre-sampling capacitor a second node of , the further switch has a first node coupled to the predefined voltage and a second node coupled to one plate of the second pre-sampling capacitor, the further switch has a coupled a first node coupled to the predefined voltage and a second node coupled to one plate of the third pre-sampling capacitor; and A second switch bank having one switch, another switch, and yet another switch; the one switch having a first node coupled to the predefined voltage, and a plate coupled to the fourth pre-sampling capacitor a second node of , the further switch has a first node coupled to the predefined voltage and a second node coupled to one plate of the fifth pre-sampling capacitor, the further switch has a coupled a first node coupled to the predefined voltage and a second node coupled to one plate of the sixth pre-sampling capacitor; Wherein, all switches included in the first switch group and the second switch group are turned on during the sampling period and turned off during the conversion period. The MDAC of claim 1, wherein the input port of the operational amplifier includes a non-inverting input node and an inverting input node; the pre-sampling capacitor circuit includes a first pre-sampling capacitor, a second pre-sampling capacitor, a third pre-sampling capacitor a sampling capacitor, a fourth pre-sampling capacitor, a fifth pre-sampling capacitor and a sixth pre-sampling capacitor; the switch circuit includes: a first switch having a first node coupled to a non-inverting input node of the operational amplifier and coupled to each of the first pre-sampling capacitor, the second pre-sampling capacitor, and the third pre-sampling capacitor a second node of one plate; wherein the first switch is turned off during the sampling period and turned on during the conversion period; A second switch having a first node coupled to an inverting input node of the operational amplifier and coupled to one of the fourth pre-sampling capacitor, the fifth pre-sampling capacitor, and the sixth pre-sampling capacitor A second node of one plate of each, wherein the second switch is turned off during the sampling period and turned on during the conversion period. The MDAC of claim 1, wherein the input port of the operational amplifier includes a non-inverting input node and an inverting input node; the pre-sampling capacitor circuit includes a first pre-sampling capacitor, a second pre-sampling capacitor, a third pre-sampling capacitor a sampling capacitor, a fourth pre-sampling capacitor, a fifth pre-sampling capacitor, and a sixth pre-sampling capacitor; and the switching circuit includes: a first switch bank having one switch, another switch and yet another switch; the one switch having a first node coupled to a non-inverting input node of the operational amplifier and one coupled to the first pre-sampling capacitor a second node of the plate, the other switch having a first node coupled to a non-inverting input node of the operational amplifier and a second node of one plate coupled to the second pre-sampling capacitor, the yet another switch has a first node coupled to a non-inverting input node of the operational amplifier and a second node coupled to one plate of the third pre-sampling capacitor; and A second switch bank having one switch, another switch and yet another switch; the one switch having a first node coupled to an inverting input node of the operational amplifier and a second switch coupled to the fourth pre-sampling capacitor a second node of one plate, the other switch having a first node coupled to the inverting input node of the operational amplifier and a second node of the one plate coupled to the fifth pre-sampling capacitor, and the further switch has a first node coupled to an inverting input node of the operational amplifier and a second node coupled to one plate of the sixth pre-sampling capacitor; Wherein, all switches included in the first switch group and the second switch group are turned off during the sampling period and turned on during the conversion period. The MDAC of claim 1, wherein the plurality of reference voltages comprise a first reference voltage, a second reference voltage and a third reference voltage; the pre-sampling capacitor circuit comprises a first pre-sampling capacitor, a second pre-sampling capacitors, a third pre-sampling capacitor, a fourth pre-sampling capacitor, a fifth pre-sampling capacitor, and a sixth pre-sampling capacitor, wherein the first plate of the first pre-sampling capacitor, the first plate of the second pre-sampling capacitor The plate and the first plate of the third pre-sampling capacitor are coupled to each other, and the first plate of the fourth pre-sampling capacitor, the first plate of the fifth pre-sampling capacitor, and the sixth The first plates of the pre-sampling capacitors are coupled to each other; and the switch circuit includes: a first switch having a first node coupled to the first reference voltage and a second node coupled to a second plate of the first pre-sampling capacitor, wherein the first switch is in the sampling period turned on during the conversion period and turned off during the conversion cycle; a second switch having a first node coupled to the second reference voltage and a second node coupled to a second plate of the second pre-sampling capacitor, wherein the second switch is in the sampling period turned on during the conversion period and turned off during the conversion cycle; a third switch having a first node coupled to the third reference voltage and a second node coupled to a second plate of the third pre-sampling capacitor, wherein the third switch is in the sampling period turned on during the conversion period and turned off during the conversion cycle; a fourth switch having a first node coupled to the third reference voltage and a second node coupled to a second plate of the fourth pre-sampling capacitor, wherein the fourth switch is in the sampling period turned on during the conversion period and turned off during the conversion cycle; a fifth switch having a first node coupled to the second reference voltage and a second node coupled to a second plate of the fifth pre-sampling capacitor, wherein the fifth switch is in the sampling period turned on during the conversion period and turned off during the conversion period; and a sixth switch having a first node coupled to the first reference voltage and a second node coupled to a second plate of the sixth pre-sampling capacitor, wherein the sixth switch is in the sampling period on during the transition period and off during the transition period. The MDAC of claim 1, wherein the sampling capacitor circuit includes a first sampling capacitor and a second sampling capacitor; the pre-sampling capacitor circuit includes a first pre-sampling capacitor, a second pre-sampling capacitor, a third pre-sampling capacitor capacitors, a fourth pre-sampling capacitor, a fifth pre-sampling capacitor, and a sixth pre-sampling capacitor, wherein the first plates of the first pre-sampling capacitor, the second pre-sampling capacitor, and the third pre-sampling capacitor are each other coupled, and the first plates of the fourth pre-sampling capacitor, the fifth pre-sampling capacitor, and the sixth pre-sampling capacitor are coupled to each other; and the switch circuit includes: a first switch having a first node coupled to a second plate of the first pre-sampling capacitor and a second node coupled to one plate of the first sampling capacitor, wherein the first switch is at turned off during the sampling period and selectively turned on during the conversion period in response to a quantized result of the voltage input; A second switch having a first node coupled to a second plate of the second pre-sampling capacitor and a second node coupled to the one plate of the first sampling capacitor, wherein the second a switch is turned off during the sampling period and selectively turned on during the conversion period in response to the quantized result of the voltage input; A third switch having a first node coupled to a second plate of the third pre-sampling capacitor and a second node coupled to the one plate of the first sampling capacitor, wherein the third a switch is turned off during the sampling period and selectively turned on during the conversion period in response to the quantized result of the voltage input; a fourth switch having a first node coupled to a second plate of the fourth pre-sampling capacitor and a second node coupled to one plate of the second sampling capacitor, wherein the fourth switch is at turned off during the sampling period and selectively turned on during the conversion period in response to the quantized result of the voltage input; a fifth switch having a first node coupled to a second plate of the fifth pre-sampling capacitor and a second node coupled to the one plate of the second sampling capacitor, wherein the fifth a switch is turned off during the sampling period and selectively turned on during the conversion period in response to the quantized result of the voltage input; a sixth switch having a first node coupled to a second plate of the sixth pre-sampling capacitor and a second node coupled to the one plate of the second sampling capacitor, wherein the sixth A switch is turned off during the sampling period and selectively turned on during the conversion period in response to the quantized result of the voltage input. The MDAC of claim 1, wherein the output port of the operational amplifier includes a non-inverting output node and an inverting output node; the sampling capacitor circuit includes a first sampling capacitor and a second sampling capacitor; and the switching circuit includes : a first switch having a first node coupled to an inverting output node of the operational amplifier and a second node coupled to a plate of the first sampling capacitor, wherein the first switch is in the sampling off during the period and on during the conversion period; and a second switch having a first node coupled to a non-inverting output node of the operational amplifier and a second node coupled to a plate of the second sampling capacitor, wherein the second switch is in the sampling period off during the transition period and on during the transition period. The MDAC of claim 1, wherein the voltage input is a differential input including a positive signal and a negative signal; the sampling capacitor circuit includes a first sampling capacitor and a second sampling capacitor, and the switch circuit includes: a first switch having a first node coupled to the negative signal and a second node coupled to a first plate of the first sampling capacitor, wherein the first switch is turned on during the sampling period and is disconnected during the transition period; a second switch having a first node coupled to the positive signal and a second node coupled to a second plate of the first sampling capacitor, wherein the second switch is turned on during the sampling period and is disconnected during the transition period; a third switch having a first node coupled to the positive signal and a second node coupled to a first plate of the second sampling capacitor, wherein the third switch is turned on during the sampling period and is turned off during the transition period; and a fourth switch having a first node coupled to the negative signal and a second node coupled to a second plate of the second sampling capacitor, wherein the fourth switch is turned on during the sampling period and is turned off during the conversion period. The MDAC of claim 1, wherein the operational amplifier is a single-stage differential amplifier without a tail current source. The MDAC of claim 1, further comprising: a first correlation level shift (CLS) capacitor; and the second CLS capacitor; Wherein, the output port of the operational amplifier includes a non-inverting output node and an inverting output node; the sampling capacitor circuit includes a first sampling capacitor and a second sampling capacitor; one plate of the first sampling capacitor is coupled to the The first plate of the first CLS capacitor; one plate of the second sampling capacitor is coupled to the first plate of the second CLS capacitor; and the switch circuit includes: A first switch having a first node coupled to the one plate of the first sampling capacitor and a second node coupled to an inverting output node of the operational amplifier, wherein the first switch is at the being turned on during the first phase of the conversion cycle and turned off during the second phase of the conversion cycle; a second switch having a first node coupled to the one plate of the second sampling capacitor and a second node coupled to a non-inverting output node of the operational amplifier, wherein the second switch is at the being turned on during the first phase of the conversion cycle and turned off during the second phase of the conversion cycle; A third switch having a first node coupled to a second plate of the first CLS capacitor and a second node coupled to a second plate of the second CLS capacitor, wherein the third switch is at being on for a start period of the second phase and off for the remainder of the second phase of the conversion cycle; a fourth switch having a first node coupled to an inverting output node of the operational amplifier and a second node coupled to the first node of the third switch, wherein the fourth switch is in the transition period is turned off during the first phase of the conversion cycle and turned on during the second phase of the conversion cycle; and a fifth switch having a first node coupled to a non-inverting output node of the operational amplifier and a second node coupled to a second node of the third switch, wherein the fifth switch is at the end of the transition cycle Off during the first phase and on during the second phase of the switching cycle. The MDAC of claim 11, wherein during the second phase of the conversion cycle, the electrical connection between the one plate of the first sampling capacitor and the one plate of the second sampling capacitor is The voltage difference acts as the MDAC output. The MDAC of claim 1, wherein the predefined voltage is a bias voltage of the operational amplifier, or the predefined voltage is one of the plurality of reference voltages. A multiplying digital-to-analog converter MDAC, comprising: Operational Amplifier; a sampling capacitor circuit; and Pre-sampling capacitor circuit; wherein, during the sampling period of the MDAC, the pre-sampling capacitor circuit samples and holds a plurality of pre-sampling reference voltages, and the sampling capacitor circuit samples the voltage input of the MDAC; wherein the pre-sampling capacitor circuit is coupled to the sampling capacitor circuit during a conversion period of the MDAC, the operational amplifier sets the operational amplifier according to the voltage input and one of the plurality of pre-sampling reference voltages The voltage output of the output port of The voltage combination of one of the reference voltages is obtained. The MDAC of claim 14, wherein the operational amplifier has a feedback factor equal to one and no charge flows between the pre-sampling capacitor circuit and the sampling capacitor circuit. The MDAC of claim 14, wherein there is no voltage change at a plate of the pre-sampling capacitor circuit that receives a reference voltage from a reference buffer. The MDAC of claim 14, further comprising: a switch circuit for controlling interconnection between the operational amplifier, the sampling capacitor circuit and the pre-sampling capacitor circuit; wherein, during a sampling period of the MDAC, the switching circuit is configured to allow the pre-sampling capacitor circuit to sample and hold the plurality of pre-sampled reference voltages, and to allow the sampling capacitor circuit to sample the MDAC's voltage input; wherein, during a conversion cycle of the MDAC, the switch circuit is used to connect the pre-sampling capacitor circuit to the sampling capacitor circuit and to allow the operational amplifier to respond to the voltage input and the plurality of pre-samples One of the reference voltages sets the voltage output at the output port of the operational amplifier, and the connection configuration between the pre-sampling capacitor circuit and the sampling capacitor circuit depends on the quantization result of the voltage input. The MDAC of claim 17, wherein the pre-sampling capacitor circuit includes a first pre-sampling capacitor, a second pre-sampling capacitor, a third pre-sampling capacitor, a fourth pre-sampling capacitor, a fifth pre-sampling capacitor, and a sixth pre-sampling capacitor a pre-sampling capacitor; and the switching circuit includes: a first switch having a first node coupled to the predefined voltage, and a first switch coupled to each of the first pre-sampling capacitor, the second pre-sampling capacitor, and the third pre-sampling capacitor a second node of a plate, wherein the first switch is on during the sampling period and the first switch is off during the conversion period; and A second switch having a first node coupled to the predefined voltage and coupled to one of each of the fourth pre-sampling capacitor, the fifth pre-sampling capacitor, and the sixth pre-sampling capacitor a second node of the plate, wherein the second switch is on during the sampling period and the second switch is off during the conversion period; Alternatively, the switch circuit includes: a first switch bank having one switch, another switch, and yet another switch; the one switch having a first node coupled to the predefined voltage, and a plate coupled to the first pre-sampling capacitor a second node of , the further switch has a first node coupled to the predefined voltage and a second node coupled to one plate of the second pre-sampling capacitor, the further switch has a coupled a first node coupled to the predefined voltage and a second node coupled to one plate of the third pre-sampling capacitor; and A second switch bank having one switch, another switch, and yet another switch; the one switch having a first node coupled to the predefined voltage, and a plate coupled to the fourth pre-sampling capacitor a second node of , the further switch has a first node coupled to the predefined voltage and a second node coupled to one plate of the fifth pre-sampling capacitor, the further switch has a coupled a first node coupled to the predefined voltage and a second node coupled to one plate of the sixth pre-sampling capacitor; Wherein, all switches included in the first switch group and the second switch group are turned on during the sampling period and turned off during the conversion period. The MDAC of claim 17, wherein the input port of the operational amplifier includes a non-inverting input node and an inverting input node; the pre-sampling capacitor circuit includes a first pre-sampling capacitor, a second pre-sampling capacitor, a third pre-sampling capacitor a sampling capacitor, a fourth pre-sampling capacitor, a fifth pre-sampling capacitor, and a sixth pre-sampling capacitor; and the switching circuit includes: a first switch having a first node coupled to a non-inverting input node of the operational amplifier and coupled to each of the first pre-sampling capacitor, the second pre-sampling capacitor, and the third pre-sampling capacitor a second node of one plate; wherein the first switch is turned off during the sampling period and turned on during the conversion period; A second switch having a first node coupled to an inverting input node of the operational amplifier and coupled to one of the fourth pre-sampling capacitor, the fifth pre-sampling capacitor, and the sixth pre-sampling capacitor a second node of one plate of each, wherein the second switch is turned off during the sampling period and turned on during the conversion period; Alternatively, the switch circuit includes: a first switch bank having one switch, another switch and yet another switch; the one switch having a first node coupled to a non-inverting input node of the operational amplifier and one coupled to the first pre-sampling capacitor a second node of the plate, the other switch having a first node coupled to a non-inverting input node of the operational amplifier and a second node of one plate coupled to the second pre-sampling capacitor, the yet another switch has a first node coupled to a non-inverting input node of the operational amplifier and a second node coupled to one plate of the third pre-sampling capacitor; and A second switch bank having one switch, another switch and yet another switch; the one switch having a first node coupled to an inverting input node of the operational amplifier and a second switch coupled to the fourth pre-sampling capacitor a second node of one plate, the other switch having a first node coupled to the inverting input node of the operational amplifier and a second node of the one plate coupled to the fifth pre-sampling capacitor, and the further switch has a first node coupled to an inverting input node of the operational amplifier and a second node coupled to one plate of the sixth pre-sampling capacitor; Wherein, all switches included in the first switch group and the second switch group are turned off during the sampling period and turned on during the conversion period. The MDAC of claim 17, wherein the pre-sampling capacitor circuit includes a first pre-sampling capacitor, a second pre-sampling capacitor, a third pre-sampling capacitor, a fourth pre-sampling capacitor, a fifth pre-sampling capacitor, and a sixth pre-sampling capacitor a pre-sampling capacitor, wherein the first plate of the first pre-sampling capacitor, the first plate of the second pre-sampling capacitor, and the first plate of the third pre-sampling capacitor are coupled to each other, and the The first plate of the fourth pre-sampling capacitor, the first plate of the fifth pre-sampling capacitor, and the first plate of the sixth pre-sampling capacitor are coupled to each other; and the switch circuit includes: a first switch having a first node coupled to the first reference voltage and a second node coupled to a second plate of the first pre-sampling capacitor, wherein the first switch is in the sampling period turned on during the conversion period and turned off during the conversion cycle; a second switch having a first node coupled to the second reference voltage and a second node coupled to a second plate of the second pre-sampling capacitor, wherein the second switch is in the sampling period turned on during the conversion period and turned off during the conversion cycle; a third switch having a first node coupled to the third reference voltage and a second node coupled to a second plate of the third pre-sampling capacitor, wherein the third switch is in the sampling period turned on during the conversion period and turned off during the conversion cycle; a fourth switch having a first node coupled to the third reference voltage and a second node coupled to a second plate of the fourth pre-sampling capacitor, wherein the fourth switch is in the sampling period turned on during the conversion period and turned off during the conversion cycle; a fifth switch having a first node coupled to the second reference voltage and a second node coupled to a second plate of the fifth pre-sampling capacitor, wherein the fifth switch is in the sampling period turned on during the conversion period and turned off during the conversion period; and a sixth switch having a first node coupled to the first reference voltage and a second node coupled to a second plate of the sixth pre-sampling capacitor, wherein the sixth switch is in the sampling period on during the transition period and off during the transition period. The MDAC of claim 17, wherein the sampling capacitor circuit includes a first sampling capacitor and a second sampling capacitor; the pre-sampling capacitor circuit includes a first pre-sampling capacitor, a second pre-sampling capacitor, a third pre-sampling capacitor capacitors, a fourth pre-sampling capacitor, a fifth pre-sampling capacitor, and a sixth pre-sampling capacitor, wherein the first plates of the first pre-sampling capacitor, the second pre-sampling capacitor, and the third pre-sampling capacitor are each other coupled, and the first plates of the fourth pre-sampling capacitor, the fifth pre-sampling capacitor, and the sixth pre-sampling capacitor are coupled to each other; and the switch circuit includes: a first switch having a first node coupled to a second plate of the first pre-sampling capacitor and a second node coupled to one plate of the first sampling capacitor, wherein the first switch is at turned off during the sampling period and selectively turned on during the conversion period in response to a quantized result of the voltage input; A second switch having a first node coupled to a second plate of the second pre-sampling capacitor and a second node coupled to the one plate of the first sampling capacitor, wherein the second a switch is turned off during the sampling period and selectively turned on during the conversion period in response to the quantized result of the voltage input; A third switch having a first node coupled to a second plate of the third pre-sampling capacitor and a second node coupled to the one plate of the first sampling capacitor, wherein the third a switch is turned off during the sampling period and selectively turned on during the conversion period in response to the quantized result of the voltage input; a fourth switch having a first node coupled to a second plate of the fourth pre-sampling capacitor and a second node coupled to one plate of the second sampling capacitor, wherein the fourth switch is at turned off during the sampling period and selectively turned on during the conversion period in response to the quantized result of the voltage input; a fifth switch having a first node coupled to a second plate of the fifth pre-sampling capacitor and a second node coupled to the one plate of the second sampling capacitor, wherein the fifth a switch is turned off during the sampling period and selectively turned on during the conversion period in response to the quantized result of the voltage input; a sixth switch having a first node coupled to a second plate of the sixth pre-sampling capacitor and a second node coupled to the one plate of the second sampling capacitor, wherein the sixth A switch is turned off during the sampling period and selectively turned on during the conversion period in response to the quantized result of the voltage input. The MDAC of claim 17, wherein, The output port of the operational amplifier includes a non-inverting output node and an inverting output node; the sampling capacitor circuit includes a first sampling capacitor and a second sampling capacitor; and the switching circuit includes: a first switch having a first node coupled to an inverting output node of the operational amplifier and a second node coupled to a plate of the first sampling capacitor, wherein the first switch is in the sampling off during the period and on during the conversion period; and a second switch having a first node coupled to a non-inverting output node of the operational amplifier and a second node coupled to a plate of the second sampling capacitor, wherein the second switch is in the sampling period off during the transition period and on during the transition period. The MDAC of claim 17, wherein, The voltage input is a differential input including a positive signal and a negative signal; the sampling capacitor circuit includes a first sampling capacitor and a second sampling capacitor, and the switch circuit includes: a first switch having a first node coupled to the negative signal and a second node coupled to a first plate of the first sampling capacitor, wherein the first switch is turned on during the sampling period and is disconnected during the transition period; a second switch having a first node coupled to the positive signal and a second node coupled to a second plate of the first sampling capacitor, wherein the second switch is turned on during the sampling period and is disconnected during the transition period; a third switch having a first node coupled to the positive signal and a second node coupled to a first plate of the second sampling capacitor, wherein the third switch is turned on during the sampling period and is turned off during the transition period; and a fourth switch having a first node coupled to the negative signal and a second node coupled to a second plate of the second sampling capacitor, wherein the fourth switch is turned on during the sampling period and is turned off during the conversion period. The MDAC of claim 17, further comprising: a first associated level shift CLS capacitor; and the second CLS capacitor; Wherein, the output port of the operational amplifier includes a non-inverting output node and an inverting output node; the sampling capacitor circuit includes a first sampling capacitor and a second sampling capacitor; one plate of the first sampling capacitor is coupled to the The first plate of the first CLS capacitor; one plate of the second sampling capacitor is coupled to the first plate of the second CLS capacitor; and the switch circuit includes: A first switch having a first node coupled to the one plate of the first sampling capacitor and a second node coupled to an inverting output node of the operational amplifier, wherein the first switch is at the being turned on during the first phase of the conversion cycle and turned off during the second phase of the conversion cycle; a second switch having a first node coupled to the one plate of the second sampling capacitor and a second node coupled to a non-inverting output node of the operational amplifier, wherein the second switch is at the being turned on during the first phase of the conversion cycle and turned off during the second phase of the conversion cycle; A third switch having a first node coupled to a second plate of the first CLS capacitor and a second node coupled to a second plate of the second CLS capacitor, wherein the third switch is at being on for a start period of the second phase and off for the remainder of the second phase of the conversion cycle; a fourth switch having a first node coupled to an inverting output node of the operational amplifier and a second node coupled to the first node of the third switch, wherein the fourth switch is in the transition period is turned off during the first phase of the conversion cycle and turned on during the second phase of the conversion cycle; and a fifth switch having a first node coupled to a non-inverting output node of the operational amplifier and a second node coupled to a second node of the third switch, wherein the fifth switch is at the end of the transition cycle Off during the first phase and on during the second phase of the switching cycle. The MDAC of claim 24, wherein during the second phase of the conversion cycle, the electrical connection between the one plate of the first sampling capacitor and the one plate of the second sampling capacitor is The voltage difference acts as the MDAC output. A pipelined analog-to-digital converter ADC comprising: a plurality of stages, connected in a pipelined manner, and arranged to produce a plurality of digital outputs, respectively; and a combining circuit for combining the plurality of digital outputs; Wherein at least one of the plurality of stages includes: a quantization circuit and the multiplying digital-to-analog converter MDAC described in any one of claim items 1-13 or the MDAC described in any one of claim items 14-25; The quantization circuit is configured to generate a quantization result of the voltage input of at least one of the plurality of stages, wherein the digital output of at least one of the plurality of stages depends on the quantization result of the voltage input.

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