CN110311681B - N-bit successive approximation type ADC and signal output control method thereof - Google Patents
N-bit successive approximation type ADC and signal output control method thereof Download PDFInfo
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- CN110311681B CN110311681B CN201910603947.4A CN201910603947A CN110311681B CN 110311681 B CN110311681 B CN 110311681B CN 201910603947 A CN201910603947 A CN 201910603947A CN 110311681 B CN110311681 B CN 110311681B
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- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
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Abstract
The application discloses an N-bit successive approximation ADC and a signal output control method thereof, wherein the signal output control method is applied to a logic controller in the N-bit successive approximation ADC and comprises the following steps: controlling an N-bit comparison circuit in the N-bit successive approximation type ADC to sample a lower polar plate; controlling an N-bit comparison circuit to keep charges, and taking the output of a comparator in the N-bit comparison circuit as the highest bit of a digital signal to be output; and controlling the N-bit comparison circuit to repeatedly redistribute charges, and sequentially taking the output of the comparator as the current upper bit of the digital signal to be output. The method adopts a lower polar plate sampling control mode, so that the input signal and the comparator are respectively positioned at two sides of the polar plate of the capacitor, thereby effectively reducing the influence of parasitic capacitance, effectively weakening the non-ideal effects such as clock feed-through, charge injection and the like, and further improving the ADC conversion output precision and the product economic benefit.
Description
Technical Field
The application relates to the technical field of electronics, in particular to an N-bit successive approximation type ADC and a signal output control method thereof.
Background
Successive approximation (Successive Approximation Register, SAR) ADCs are common structures in medium and high resolution ADC applications with sample rates below 5 Msps. The resolution of the SAR ADC is typically 8-16 bits, and in each conversion process, the digital signal to be output is finally obtained by traversing all the quantized values and converting them into analog values, and comparing them one by one with the input signal. In the prior art, the N-bit successive approximation type ADC mostly adopts a capacitance upper polar plate sampling mode, and because the capacitance upper polar plate is also connected with the input end of the comparator, non-ideal effects such as clock feed-through, charge injection and the like are easier to occur, and the output precision is further influenced. In view of this, it has been a great need for a person skilled in the art to provide a solution to the above-mentioned technical problems.
Disclosure of Invention
The invention aims to provide an N-bit successive approximation type ADC and a signal output control method thereof so as to effectively improve output precision.
In order to solve the above technical problems, in a first aspect, the present application discloses a signal output control method of an N-bit successive approximation ADC, which is applied to a logic controller in the N-bit successive approximation ADC, including:
controlling an N-bit comparison circuit in the N-bit successive approximation type ADC to sample a lower polar plate;
Controlling the N-bit comparison circuit to keep charges, and taking the output of a comparator in the N-bit comparison circuit as the highest bit of a digital signal to be output;
and controlling the N-bit comparison circuit to repeatedly redistribute charges, and sequentially taking the output of the comparator as the current high bit of the digital signal to be output.
Optionally, the controlling the N-bit comparing circuit in the N-bit successive approximation ADC to perform the down-plate sampling includes:
the first input end of the comparator is controlled to be connected with a common mode reference voltage source through a first connecting switch; the second input end of the comparator is controlled to be connected with the common mode reference voltage source through a second connecting switch; the first input end of the comparator is connected with the upper polar plate of each first capacitor in the first capacitor array, and the second input end of the comparator is connected with the upper polar plate of each second capacitor in the second capacitor array;
the lower polar plate of the first capacitor of the control Nth bit is connected with a first differential input signal line through a first switch array; the lower polar plate of the second capacitor of the control Nth bit is connected with a second differential input signal line through a second switch array;
the lower polar plates of the rest first capacitors are controlled to be connected with a grounding wire through the first switch array; and controlling the lower polar plates of the rest second capacitors to be connected with the grounding wire through the second switch array.
Optionally, the controlling the N-bit comparing circuit to perform charge retention and taking the output of the comparator in the N-bit comparing circuit as the most significant bit of the digital signal to be output includes:
controlling the first connecting switch and the second connecting switch to be disconnected;
the lower polar plate of the Nth first capacitor is controlled to be connected with the common mode reference voltage source through the first switch array; the lower polar plate of the Nth second capacitor is controlled to be connected with the common mode reference voltage source through the second switch array;
and obtaining the output of the comparator and taking the output as the Nth bit of the digital signal to be output.
Optionally, the controlling the N-bit comparing circuit to repeatedly redistribute charges, and sequentially taking the output of the comparator as the current next highest bit of the digital signal to be output includes:
judging whether the output of the comparator is in a high level or not;
if yes, the lower polar plate of the Nth first capacitor is controlled to be connected to the grounding wire through the first switch array; if not, the lower polar plate of the Nth second capacitor is controlled to be connected to the grounding wire through the second switch array;
let i=1;
obtaining the output of the comparator and taking the output as the N-i bit of the digital signal to be output;
Judging whether N-i=1 is true or not;
if yes, outputting the digital signal to be output;
if not, judging whether the N-i bit of the digital signal to be output is at a high level;
if the N-i bit of the digital signal to be output is high level, the lower polar plate of the second capacitor for controlling the N-i bit is connected to the common mode reference voltage source through the second switch array; if the N-i bit of the digital signal to be output is low level, the lower polar plate of the first capacitor for controlling the N-i bit is connected to the common mode reference voltage source through the first switch array;
let i add 1; and continuing to execute the step of acquiring the output of the comparator and taking the output as the N-i bit of the digital signal to be output.
In a second aspect, the present application further provides an N-bit successive approximation ADC, comprising an N-bit comparison circuit and a logic controller;
the logic controller is used for controlling the N-bit comparison circuit to sample a lower polar plate; controlling the N-bit comparison circuit to carry out charge retention so as to take the output of a comparator in the N-bit comparison circuit as the highest bit of a digital signal to be output; and controlling the N-bit comparison circuit to repeatedly redistribute charges so as to sequentially take the output of the comparator as the current high bit of the digital signal to be output.
Optionally, the N-bit comparison circuit includes the comparator, a first capacitor array, a second capacitor array, a first switch array, and a second switch array;
the upper polar plate of each first capacitor in the first capacitor array is connected with the first input end of the comparator, and the upper polar plate of each second capacitor in the second capacitor array is connected with the second input end of the comparator; the first switch array is used for controlling the sampling of the lower polar plate of the first capacitor array; the second switch array is used for controlling the sampling of the lower polar plate of the second capacitor array;
the comparator is used for comparing the output voltage of the upper polar plate of the first capacitor array with the output voltage of the upper polar plate of the second capacitor array and outputting a comparison result.
Optionally, the N-bit comparison circuit further includes a first connection switch and a second connection switch;
the first end of the first connecting switch is connected with the upper polar plate of each first capacitor; the first end of the second connecting switch is connected with the upper polar plate of each second capacitor;
the second end of the first connecting switch and the second end of the second connecting switch are connected with the common mode reference voltage source so as to provide common mode reference voltage for the first capacitor array and the second capacitor array when the lower polar plate is sampled.
Optionally, each first capacitor corresponds to a switch in the first switch array one by one; the lower electrode plate of the Nth first capacitor is in switching connection with a common mode reference voltage source or a ground wire or a first differential input signal wire through a corresponding switch, and the lower electrode plates of the other first capacitors are in switching connection with the common mode reference voltage source or the ground wire through corresponding switches;
each second capacitor corresponds to a switch in the second switch array one by one; the lower polar plate of the Nth second capacitor is in switching connection with a common mode reference voltage source or a ground wire or a second differential input signal wire through a corresponding switch, and the lower polar plates of the other second capacitors are in switching connection with the common mode reference voltage source or the ground wire through corresponding switches.
Optionally, the first switch array comprises a first single pole three throw switch and N-1 first single pole double throw switches;
the fixed end of the first single-pole three-throw switch is connected with the lower polar plate of the Nth-bit first capacitor, the first movable end is connected with the common mode reference voltage source, the second movable end is connected with the grounding wire, and the third movable end is connected with the first differential input signal wire; the fixed end of each first single-pole double-throw switch is connected with the corresponding lower polar plate of the first capacitor, the first movable end is connected with the common mode reference voltage source, and the second movable end is connected with the grounding wire;
The second switch array comprises a second single-pole three-throw switch and N-1 second single-pole double-throw switches;
the fixed end of the second single-pole three-throw switch is connected with the lower polar plate of the Nth second capacitor, the first movable end is connected with the common mode reference voltage source, the second movable end is connected with the grounding wire, and the third movable end is connected with the second differential input signal wire; the fixed end of each second single-pole double-throw switch is connected with the corresponding lower polar plate of the second capacitor, the first movable end is connected with the common mode reference voltage source, and the second movable end is connected with the grounding wire.
Optionally, the ratio of the capacitance values of the first capacitors and the ratio of the capacitance values of the second capacitors are: 1:1:2 1 :2 2 :…:2 N-2 ；
The first capacitors and the second capacitors are arranged in ascending order according to the capacitance value, and the capacitance value of the ith first capacitor is equal to that of the ith second capacitor.
The signal output control method of the N-bit successive approximation type ADC, provided by the application, is applied to a logic controller in the N-bit successive approximation type ADC, and comprises the following steps: controlling an N-bit comparison circuit in the N-bit successive approximation type ADC to sample a lower polar plate; controlling the N-bit comparison circuit to keep charges, and taking the output of a comparator in the N-bit comparison circuit as the highest bit of a digital signal to be output; and controlling the N-bit comparison circuit to repeatedly redistribute charges, and sequentially taking the output of the comparator as the current high bit of the digital signal to be output.
Therefore, the signal output control method of the N-bit successive approximation type ADC disclosed by the application specifically adopts a lower polar plate sampling control mode, namely, an input signal to be sampled is arranged on one side of a lower polar plate of a capacitor, so that the input signal and a comparator are respectively positioned on two sides of the polar plate of the capacitor, the influence of parasitic capacitance is further effectively reduced, the undesirable effects such as clock feed-through and charge injection are effectively weakened, and the ADC conversion output precision and the product economic benefit are further improved. The N-bit successive approximation ADC provided by the application has the beneficial effects.
Drawings
In order to more clearly illustrate the prior art and the technical solutions in the embodiments of the present application, the following will briefly describe the drawings that need to be used in the description of the prior art and the embodiments of the present application. Of course, the following figures related to the embodiments of the present application are only some of the embodiments of the present application, and it is obvious to those skilled in the art that other figures can be obtained from the provided figures without any inventive effort, and the obtained other figures also belong to the protection scope of the present application.
Fig. 1 is a flowchart of a signal output control method of an N-bit successive approximation ADC according to an embodiment of the present disclosure;
FIG. 2 is a flow chart of a down plate sampling process disclosed in an embodiment of the present application;
FIG. 3 is a schematic diagram of a 3-bit comparison circuit switched from bottom plate sampling to charge retention according to an embodiment of the present disclosure;
FIG. 4 is a flow chart of a charge retention process disclosed in an embodiment of the present application;
FIG. 5 is a flow chart of a charge redistribution process disclosed in an embodiment of the present application;
FIG. 6 is a schematic diagram of a 3-bit comparison circuit for charge redistribution according to an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of a 3-bit comparison circuit for charge redistribution according to an embodiment of the present disclosure;
FIG. 8 is a schematic diagram of a comparison of the signal output control method of an N-bit successive approximation ADC provided in the present application with the power consumption of the prior art;
fig. 9 is a schematic structural diagram of an N-bit successive approximation ADC according to an embodiment of the present application.
Detailed Description
The core of the application is to provide an N-bit successive approximation type ADC and a signal output control method thereof so as to effectively improve the output precision.
In order to more clearly and completely describe the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
At present, in the prior art, in the process of converting and outputting, an upper polar plate sampling mode is mostly adopted, so that the input end of the comparator and a signal to be sampled are connected on the same polar plate side of the capacitor, namely the upper polar plate side, the influence of parasitic capacitance is increased, and the circuit is more prone to non-ideal effects such as clock feed-through, charge injection and the like. In view of the above, the present application provides an N-bit successive approximation ADC, which can effectively solve the above-mentioned problems.
Referring to fig. 1, an embodiment of the application discloses a signal output control method of an N-bit successive approximation ADC, which is applied to a logic controller in the N-bit successive approximation ADC, and mainly includes the following steps:
s101: the N-bit comparison circuit 100 in the N-bit successive approximation ADC is controlled to perform the down-plate sampling.
It should be noted that, in the N-bit successive approximation ADC provided in the embodiment of the present application, a lower plate sampling mode is specifically adopted, instead of an upper plate sampling mode.
In general, the N-bit comparison circuit 100 is constructed based on a capacitor, a comparator, and the like, and an input signal of the N-bit successive approximation ADC is typically sampled to one plate side of the capacitor based on an associated switching device. Typically, the comparator is connected to one plate of the capacitor, which may be referred to as the "top plate"; the other plate is correspondingly referred to as the "bottom plate". The lower polar plate sampling mode adopted by the application specifically samples the input signal to one side of the lower polar plate of the capacitor, namely, the side with the different connection positions with the comparator.
S102: the N-bit comparison circuit 100 is controlled to perform charge retention, and the output of the comparator in the N-bit comparison circuit 100 is used as the highest bit of the digital signal to be output.
S103: the N-bit comparison circuit 100 is controlled to repeatedly perform charge redistribution, and sequentially takes the output of the comparator as the current next highest bit of the digital signal to be output.
Specifically, the signal output control method of the N-bit successive approximation type ADC provided by the application specifically comprises three main processes of lower polar plate sampling, charge holding and charge redistribution. And the N-bit successive approximation type ADC is used for successive DA conversion by utilizing the charge redistribution process, so that the digital signal to be output corresponding to the input signal is successively approximated, and AD conversion is realized.
The signal output control method of the N-bit successive approximation ADC disclosed in the present application is applied to a logic controller 200 in the N-bit successive approximation ADC, and includes: controlling an N-bit comparison circuit 100 in the N-bit successive approximation type ADC to sample a lower polar plate; controlling the N-bit comparison circuit 100 to perform charge retention, and taking the output of a comparator in the N-bit comparison circuit 100 as the highest bit of a digital signal to be output; the N-bit comparison circuit 100 is controlled to repeatedly perform charge redistribution, and sequentially takes the output of the comparator as the current next highest bit of the digital signal to be output.
Therefore, the signal output control method of the N-bit successive approximation type ADC disclosed by the application specifically adopts a lower polar plate sampling control mode, namely, an input signal to be sampled is arranged on one side of a lower polar plate of a capacitor, so that the input signal and a comparator are respectively positioned on two sides of the polar plate of the capacitor, the influence of parasitic capacitance is further effectively reduced, the undesirable effects such as clock feed-through and charge injection are effectively weakened, and the ADC conversion output precision and the product economic benefit are further improved.
Further, the step S101 may be specifically referred to fig. 2, and fig. 2 is a flowchart of a lower plate sampling process disclosed in an embodiment of the present application, and mainly includes the following steps:
s201: the first input end of the control comparator is connected with a common mode reference voltage source through a first connecting switch S1; the second input of the control comparator is connected to the common mode reference voltage source via a second connection switch S2.
The first input end of the comparator is connected with the upper polar plate of each first capacitor in the first capacitor array, and the second input end of the comparator is connected with the upper polar plate of each second capacitor in the second capacitor array.
Specifically, the common mode reference voltage source is used for providing a common mode reference voltage in the lower polar plate sampling stage, and charges are provided for the first capacitor array and the second capacitor array so as to facilitate the subsequent charge holding process and charge redistribution process.
S202: the lower polar plate of the first capacitor C1N of the N-th bit is controlled to be connected with a first differential input signal line through a first switch array; the lower polar plate of the second capacitor C2N of the control Nth bit is connected with a second differential input signal line through a second switch array.
It should be noted that the N-bit successive approximation ADC provided in the embodiment of the present application adopts a differential input mode, and signal inputs are provided at two input ends of the comparator. The first capacitor array and the first switch array are located at a first input end side of the comparator, and the second capacitor array and the second switch array are located at a second input end side of the comparator. The first capacitor array comprises N first capacitors, the second capacitor array comprises N second capacitors, N is the number of the first capacitors and also the number of the second capacitors, and the number of bits of the digital signals to be output of the N-bit successive approximation type ADC is determined to be N.
For the first capacitor array, under the control of the logic controller 200, the lower electrode plate of the nth first capacitor may be connected to the first differential input signal line through the first switch array, so as to implement sampling of the lower electrode plate. For the second capacitor array, under the control of the logic controller 200, the lower electrode plate of the nth second capacitor may be connected to the second differential input signal line through the second switch array, so as to implement sampling of the lower electrode plate.
S203: the lower polar plates of the other first capacitors are controlled to be connected with a grounding wire through a first switch array; the lower polar plates of the other second capacitors are controlled to be connected with a grounding wire through a second switch array.
The signal output control method provided in the present application will be described below by taking a 3-bit comparison circuit, i.e., n=3 as an example. Referring to fig. 3, fig. 3 is a schematic diagram of a 3-bit comparison circuit according to an embodiment of the present application from a bottom plate sampling to a charge holding.
The sampling of the lower electrode plate is completed through the 3-bit comparison circuit after S101. Under the control of the logic controller 200, the first connection switch S1 and the second connection switch S2 are both closed, and the potentials of the non-inverting input end and the inverting input end of the comparator are both the common mode reference voltage Vcm output by the common mode reference voltage source; the lower electrode plate of the 3 rd first capacitor C13 is connected with the reverse differential input signal Vin, and the lower electrode plates of the 2 nd first capacitor C12 and the 1 st first capacitor C11 are grounded; the lower electrode plate of the 3 rd second capacitor C23 is connected with the positive phase difference input signal Vip, and the lower electrode plates of the 2 nd second capacitor C22 and the 1 st second capacitor C21 are grounded.
The relationship between the common mode reference voltage Vcm and the positive phase difference input signal Vip and the negative phase difference input signal Vin is: vcm= (vip+vin)/2.
The capacitance values of the capacitors are respectively as follows: c13 =c23=2c; c12 =c22=c; c11 =c21=c.
The charge amount of the first capacitor array is: q11=2c· (Vcm-Vin) +2c·vcm;
the charge amount of the second capacitor array is: q12=2c· (Vcm-Vip) +2c·vcm.
Further, the step S102 may be specifically referred to fig. 4, and fig. 4 is a flowchart of a charge holding process disclosed in an embodiment of the present application, and mainly includes the following steps:
s301: the first connection switch S1 and the second connection switch S2 are controlled to be both opened.
S302: the lower polar plate of the first capacitor C1N at the N-th position is controlled to be connected with a common mode reference voltage source through a first switch array; the lower polar plate of the second capacitor C2N of the N-th control bit is connected with a common mode reference voltage source through a second switch array.
S303: the output of the comparator is obtained and used as the nth bit of the digital signal to be output.
Still taking the example of the 3-bit comparison circuit shown in fig. 3, i.e., n=3, the charge retention is completed by the 3-bit comparison circuit after S102.
Under the control of the logic controller 200, the first connection switch S1 and the second connection switch S2 are both turned off; the lower polar plates of the 3 rd first capacitor C13 and the 3 rd second capacitor C23 are switched and connected to a common mode reference voltage source, and the potential is the common mode reference voltage Vcm; the lower electrode plates of the 2 nd first capacitor C12, the 1 st first capacitor C11, the 2 nd second capacitor C22 and the 1 st second capacitor C21 are not changed and still grounded. Then, the output of the comparator is taken as the most significant bit (nth bit) of the digital signal to be output, and for a 3-bit comparison circuit (n=3), the nth bit of the digital signal to be output can be denoted as B2.
Let the voltage at the non-inverting input of the comparator be Vdacp1, let the potential at the inverting input of the comparator be Vdacn1,
the charge of the first capacitor array is then: q21=2c· (Vdacp 1-Vcm) +2c·vdacp1;
the charge amount of the second capacitor array is: q22=2c· (Vdacn 1-Vcm) +2c·vdacn1.
Q11=q21 according to charge conservation; q12=q22; this can be achieved by:
further, it can be seen that:
when Vip > Vin, vdacp1> Vdacn1 exists, and the comparator outputs a high level, so that b2=1;
when Vip < Vin, vdacp1< Vdacn1, the comparator output is low, b2=0.
In the switching process from the sampling of the lower polar plate to the charge holding, the power consumption generated by the positive input end side of the comparator is specifically as follows:
Edacp1＝-2C·Vcm·[(Vdacp1-Vcm)-(Vcm-Vin)]；
the power consumption generated by the inverting input terminal side of the comparator is specifically:
Edacn1＝-2C·Vcm·[(Vdacn1-Vcm)-(Vcm-Vip)]；
the power consumption generated by the whole 3-bit comparison circuit in the process is specifically:
E1＝Edacp1+Edacn1＝-2C·Vcm·[-Vcm+(Vip+Vin)/2]＝0。
therefore, the power consumption generated in the process from the sampling of the lower polar plate to the charge holding, namely the first step of switching is zero, so that the power consumption is greatly reduced, and the economic benefit of the product is improved.
Further, the step S103 may be specifically referred to fig. 5, and fig. 5 is a flowchart of a charge redistribution process disclosed in an embodiment of the present application, and mainly includes the following steps:
S401: judging whether the output of the comparator is in a high level or not; if yes, go to S402; if not, the process advances to S403.
S402: the lower polar plate of the first capacitor C1N at the N-th position is controlled to be connected to a grounding wire through a first switch array; and proceeds to S404.
Still taking a 3-bit comparison circuit, i.e., n=3 as an example, referring to fig. 6, fig. 6 is a schematic diagram of charge redistribution performed by the 3-bit comparison circuit according to the embodiment of the present application.
If b2=1, the lower plate of the nth first capacitor C1N can be grounded from the common mode reference voltage source in the second switching process, i.e. the potential of the lower plate of the nth first capacitor C1N is changed to 0. According to conservation of charge, the potential at the non-inverting input of the comparator will become:
the potential of the inverting input end of the comparator is not changed, and the potential is as follows:
the power consumption generated by the whole 3-bit comparison circuit in the process is specifically:
E2＝Edacp2+Edacn2＝-2C·Vcm·[(Vdacp2-0)-(Vdacp1-Vcm)]-0＝0。
therefore, in the N-bit successive approximation ADC provided in the embodiment of the present application, if b2=1, in the second switching process, that is, in the process of performing the first load redistribution from the charge retention, the power consumption is zero, so that the conversion power consumption is greatly reduced, and the product economic benefit is improved.
And, from the above analysis, it can be deduced that:
when Vip-Vin > Vcm, vdacp2> Vdacn2 exists, and the comparator outputs a high level, so that b1=1;
when Vip-Vin < Vcm, vdacp2< Vdacn2, the comparator outputs low level, let b1=0;
wherein B1 represents the 2 nd bit of the digital signal to be output.
S403: the lower polar plate of the second capacitor C2N at the N-th position is controlled to be connected to a grounding wire through a second switch array; and proceeds to S404.
Still taking a 3-bit comparison circuit, i.e., n=3 as an example, referring to fig. 7, fig. 7 is a schematic diagram of charge redistribution performed by another 3-bit comparison circuit according to an embodiment of the present application.
If b2=0, the lower plate of the nth second capacitor C2N can be grounded to the ground by the common mode reference voltage source in the second switching process, i.e. the potential of the lower plate of the nth second capacitor C2N is made to be 0. According to conservation of charge, the potential at the inverting input of the comparator will become:
the potential of the non-inverting input end of the comparator is not changed, and the potential is as follows:
the power consumption generated by the whole 3-bit comparison circuit in the process is specifically:
E2＝Edacp2+Edacn2＝0-2C·Vcm·[(Vdacn2-0)-(Vdacn1-Vcm)]＝0。
therefore, in the N-bit successive approximation ADC provided in the embodiment of the present application, if b2=0, in the second switching process, that is, in the process of performing the first load redistribution from the charge retention, the power consumption is zero, so that the conversion power consumption is greatly reduced, and the product economic benefit is improved.
And after the second step of switching, it can be seen from the above analysis:
when Vip-Vin-Vcm, vdacp2> Vdacn2, the comparator outputs high level, which can make b1=1;
when Vip-Vin < -Vcm, vdacp2< Vdacn2 exists, and the comparator outputs a low level, so that B1=0;
wherein B1 represents the 2 nd bit of the digital signal to be output.
S404: let i=1; the process advances to S405.
S405: obtaining the output of the comparator and taking the output as the N-i bit of the digital signal to be output; proceed to S406.
When i=1, for the 3-bit comparison circuit, the output of the comparator after being switched by the second-step switch may be determined as the 2 nd bit, i.e., the B1 bit, of the digital signal to be output.
S406: judging whether N-i=1 is true or not; if yes, go to S407; if not, the process advances to S408.
For the N-bit comparison circuit 100, if N-i=1 is satisfied, it indicates that the 1 st bit, i.e. the B0 bit, of the digital signal to be output is already determined, so far the digital-to-analog conversion is completed, the switching process is completed, and the digital signal to be output can be output; if N-i=1 is not satisfied, it indicates that the digital-to-analog conversion is not completed, and the next switching needs to be continued.
S407: and outputting the digital signal to be output.
S408: judging whether the N-i bit of the digital signal to be output is at a high level; if yes, go to S409; if not, the process proceeds to S410.
S409: the lower polar plate of the second capacitor of the N-i bit is controlled to be connected to a common mode reference voltage source through a second switch array; the process advances to S411.
Specifically, if the N-i bit of the digital signal to be output is at a high level, the potential of the lower plate of the second capacitor of the N-i bit may be changed to the common mode reference voltage Vcm.
Taking the case of b2=1 as shown in fig. 6 as an example, if b1=1 when i=1, the lower plate of the second capacitor C22 at the 2 nd bit can be changed from ground to the common mode reference voltage source during the third switching process, so that the potential of the lower plate of the second capacitor C22 at the 2 nd bit becomes the common mode reference voltage Vcm. According to conservation of charge, the potential at the inverting input of the comparator will become:
the potential of the non-inverting input end of the comparator is not changed, and the potential is as follows:
the power consumption generated by the whole 3-bit comparison circuit in the third step of switching process is specifically as follows:
after the third switching, it can be deduced from the above analysis:
when Vip-Vin > 3.vcm/2, vdacp3> Vdacn3 exists, and the comparator outputs a high level, so that b0=1;
when Vip-Vin is less than 3.vcm/2, vdacp3 is less than Vdacn3, and the comparator outputs low level to make B0=0;
wherein B0 represents bit 1 of the digital signal to be output.
Taking the case of b2=0 as shown in fig. 7 as an example, if b1=1 when i=1, the lower plate of the second capacitor C22 at the 2 nd bit can be changed from ground to the common mode reference voltage source during the third switching process, so that the potential of the lower plate of the second capacitor C22 at the 2 nd bit becomes the common mode reference voltage Vcm. According to conservation of charge, the potential at the inverting input of the comparator will become:
the potential of the non-inverting input end of the comparator is not changed, and the potential is as follows:
the power consumption generated by the whole 3-bit comparison circuit in the third step of switching process is specifically as follows:
after the third switching, it can be deduced from the above analysis:
when Vip-Vin > -Vcm/2, vdacp3> Vdacn3, the comparator outputs high level, let b0=1;
when Vip-Vin < -Vcm/2, vdacp3< Vdacn3 exists, and the comparator outputs a low level, so that b0=0;
wherein B0 represents bit 1 of the digital signal to be output.
S410: the lower polar plate of the first capacitor of the N-i bit is controlled to be connected to a common mode reference voltage source through a first switch array; the process advances to S411.
Specifically, if the N-i bit of the digital signal to be output is at a low level, the potential of the lower plate of the first capacitor of the N-i bit may be changed to the common mode reference voltage Vcm.
Taking the case of b2=1 as shown in fig. 6 as an example, if b1=0 when i=1, the lower plate of the 2 nd first capacitor C12 can be grounded and connected to the common mode reference voltage source during the third switching step, so that the potential of the lower plate of the 2 nd second capacitor C22 becomes the common mode reference voltage Vcm. According to conservation of charge, the potential at the non-inverting input of the comparator will become:
the potential of the inverting input end of the comparator is not changed, and the potential is as follows:
the power consumption generated by the whole 3-bit comparison circuit in the third step of switching process is specifically as follows:
and, after the third step switch is switched, it can be seen from the above analysis:
when Vip-Vin > Vcm/2, vdacp3> Vdacn3, the comparator outputs high level, and b0=1;
when Vip-Vin < Vcm/2, vdacp3< Vdacn3, comparator output low level, b0=0;
wherein B0 represents bit 1 of the digital signal to be output.
Taking the case of b2=0 as shown in fig. 7 as an example, if b1=1 when i=1, the lower plate of the 2 nd first capacitor C12 can be changed from ground to the common mode reference voltage source during the third switching step, so that the potential of the lower plate of the 2 nd first capacitor C12 becomes the common mode reference voltage Vcm. According to conservation of charge, the potential at the non-inverting input of the comparator will become:
The potential of the inverting input end of the comparator is not changed, and the potential is as follows:
the power consumption generated by the whole 3-bit comparison circuit in the third step of switching process is specifically as follows:
and, after the third step switch is switched, it can be seen from the above analysis:
when Vip-Vin > -3.vcm/2, vdacp3> Vdacn3 exists, and the comparator outputs a high level, so that b0=1;
when Vip-Vin < -3.vcm/2, vdacp3< Vdacn3 exists, the comparator outputs low level, and B0=0 can be caused;
wherein B0 represents bit 1 of the digital signal to be output.
As can be seen from the above, for the N-bit successive approximation ADC with n=3 provided in the present embodiment:
if Vip-Vin >3·vcm/2, the digital signal to be output is b2b1b0=111;
if Vcm < Vip-Vin <3·vcm/2, the digital signal to be output is b2b1b0=110;
if Vcm/2< vip-Vin < Vcm, the digital signal to be output is b2b1b0=101;
if 0< vip-Vin < Vcm/2, the digital signal to be output is b2b1b0=100;
if-Vcm/2 < vip-Vin <0, the digital signal to be output is b2b1b0=011;
if-Vcm < Vip-Vin < -Vcm/2, the digital signal to be output is b2b1b0=010;
if-3.vcm/2 < vip-Vin < -Vcm, the digital signal to be output is b2b1b0=001;
If Vip-Vin < -3·vcm/2, the digital signal to be output is b2b1b0=000.
S411: let i add 1; the process advances to S405.
Since the third step of switching, the switching operations are similar to the third step of switching operations until N-i=1, and the 1 st bit or the lowest bit B0 of the digital signal to be output is determined. For the case of N >3, those skilled in the art can refer to the relevant content of n=3 in analogy, and the description thereof will be omitted.
According to the signal output control method provided by the embodiment of the application, the lower polar plate sampling mode is adopted, and the output result with higher accuracy can be obtained by sequentially switching and sequentially comparing, so that the data accuracy and the accuracy are improved. In addition, the power consumption generated in the process of switching from the sampling of the lower polar plate to the charge holding and the process of carrying out the first charge redistribution by the charge holding is 0, so the conversion power consumption can be effectively reduced, and the economic benefit is greatly improved.
Referring to fig. 8, fig. 8 is a schematic diagram comparing the signal output control method of the N-bit successive approximation ADC provided in the present application with the power consumption of the prior art. Where n=10.
It can be seen that the average power consumption of the signal output control method of the N-bit successive approximation ADC provided by the present application is significantly lower than that of the monosonic method and the vcm-based method in the prior art.
Referring to fig. 9, an embodiment of the present application discloses an N-bit successive approximation ADC, which includes an N-bit comparison circuit 100 and a logic controller 200;
the logic controller 200 is used for controlling the N-bit comparison circuit 100 to sample the lower electrode plate; controlling the N-bit comparison circuit 100 to perform charge retention so as to take the output of the comparator in the N-bit comparison circuit 100 as the highest bit of the digital signal to be output; the N-bit comparison circuit 100 is controlled to repeatedly perform charge redistribution so as to sequentially take the output of the comparator as the current next highest bit of the digital signal to be output.
Wherein, further, the N-bit comparing circuit 100 includes a comparator, a first capacitor array, a second capacitor array, a first switch array and a second switch array;
the upper polar plates of all the first capacitors in the first capacitor array are connected with the first input end of the comparator, and the upper polar plates of all the second capacitors in the second capacitor array are connected with the second input end of the comparator; the first switch array is used for controlling the sampling of the lower polar plate of the first capacitor array; the second switch array is used for controlling the sampling of the lower polar plate of the second capacitor array;
the comparator is used for comparing the output voltage of the upper electrode plate of the first capacitor array with the output voltage of the upper electrode plate of the second capacitor array and outputting a comparison result.
It should be noted that, in the N-bit successive approximation ADC provided in the embodiment of the present application, a lower plate sampling mode is specifically adopted, instead of an upper plate sampling mode.
Specifically, the N-bit successive approximation ADC provided in the embodiment of the present application adopts a differential input mode, and signal inputs are provided at two input ends of the comparator. The first capacitor array and the first switch array are located at a first input end side of the comparator, and the second capacitor array and the second switch array are located at a second input end side of the comparator. The first capacitor array comprises N first capacitors, the second capacitor array comprises N second capacitors, N is the number of the first capacitors and also the number of the second capacitors, and the number of bits of the digital signals to be output of the N-bit successive approximation type ADC is determined to be N.
For the first capacitor array, under the control of the logic controller 200, the lower electrode plate of the nth first capacitor C1N may implement lower electrode plate sampling through the first switch array. Because the input signal during sampling is specifically on one side of the lower polar plate of the first capacitor C1N at the nth position, and the first input end of the comparator is on one side of the upper polar plate of the first capacitor C1N at the nth position, it can be seen that in the N-bit successive approximation type ADC provided by the embodiment of the application, the input signal and the comparator are respectively positioned on two sides of the polar plate of the first capacitor C1N at the nth position, so that the influence of parasitic capacitance can be effectively reduced, the non-ideal effects such as clock feedthrough and charge injection are reduced, and the conversion output precision and the product economic benefit of the ADC are improved. The second capacitor array is similar to this and will not be described again here.
Based on the above, as a specific implementation manner, in the N-bit successive approximation ADC provided in the embodiment of the present application, the N-bit comparison circuit 100 further includes a first connection switch S1 and a second connection switch S2;
the first end of the first connecting switch S1 is connected with the upper polar plates of the first capacitors; the first end of the second connecting switch S2 is connected with the upper polar plates of the second capacitors;
the second end of the first connection switch S1 and the second end of the second connection switch S2 are both connected to a common mode reference voltage source so as to provide a common mode reference voltage for the first capacitor array and the second capacitor array when the lower electrode plate is sampled.
It should be noted that, the logic controller 200 may perform on-off control on each switch in the first switch array and the second switch array, and may also perform on-off control on the first connection switch S1 and the second connection switch S2, so as to further control the first capacitor array and the second capacitor array to perform three processes of down-plate sampling, charge holding and charge redistribution, thereby obtaining the digital signal to be output of the N-bit successive approximation ADC through successive control and adjustment.
In addition, the N-bit successive approximation ADC provided in the embodiment of the present application has additional beneficial effects: the N-bit successive approximation type ADC provided by the embodiment of the application only needs to use one common mode reference voltage source, and does not need to use other reference voltages, so that the cost is effectively saved, and the structure is simple and convenient to realize.
Based on the above, as a specific implementation manner, in the N-bit successive approximation ADC provided in the embodiment of the present application, each first capacitor corresponds to a switch in the first switch array one by one; the lower polar plates of the N-th first capacitor are in switching connection with a common mode reference voltage source or a ground wire or a first differential input signal wire through corresponding switches, and the lower polar plates of the other first capacitors are in switching connection with the common mode reference voltage source or the ground wire through corresponding switches;
each second capacitor corresponds to a switch in the second switch array one by one; the lower polar plates of the N-th second capacitor are in switching connection with a common mode reference voltage source or a ground wire or a second differential input signal wire through corresponding switches, and the lower polar plates of the other second capacitors are in switching connection with the common mode reference voltage source or the ground wire through corresponding switches.
Wherein, further, the first switch array includes first single pole three throw switch and N-1 first single pole double throw switch;
the fixed end of the first single-pole three-throw switch is connected with the lower polar plate of the Nth first capacitor C1N, the first movable end is connected with a common mode reference voltage source, the second movable end is connected with a grounding wire, and the third movable end is connected with a first differential input signal wire; the fixed end of each first single-pole double-throw switch is connected with the lower polar plate of the corresponding first capacitor, the first movable end is connected with a common mode reference voltage source, and the second movable end is connected with a ground wire;
The second switch array comprises a second single-pole three-throw switch and N-1 second single-pole double-throw switches;
the fixed end of the second single-pole three-throw switch is connected with the lower polar plate of the Nth second capacitor C2N, the first movable end is connected with a common mode reference voltage source, the second movable end is connected with a grounding wire, and the third movable end is connected with a second differential input signal wire; the fixed end of each second single-pole double-throw switch is connected with the lower polar plate of the corresponding second capacitor, the first movable end is connected with a common mode reference voltage source, and the second movable end is connected with a grounding wire.
Thus, in this embodiment, during the bottom plate sampling phase, the logic controller 200 may control each switch to the following states: the first connecting switch S1 and the second connecting switch S2 are closed, the fixed end and the third movable end of the first single-pole three-throw switch are closed, the fixed end and the third movable end of the second single-pole three-throw switch are closed, the fixed end and the second movable end of each first single-pole double-throw switch are closed, and the fixed end and the second movable end of each second single-pole double-throw switch are closed.
During the charge retention phase, the logic controller 200 may control the various switches to the following states: the first connecting switch S1 and the second connecting switch S2 are opened, the fixed end of the first single-pole three-throw switch is closed with the first movable end, the fixed end of the second single-pole three-throw switch is closed with the first movable end, the fixed ends of the first single-pole double-throw switches are closed with the second movable ends, and the fixed ends of the second single-pole double-throw switches are closed with the second movable ends.
In the charge redistribution stage, the logic controller 200 determines the closing state of each switch according to the output result of the comparator. For specific details, reference may be made to the signal output control method in the foregoing, and details are not repeated here.
Based on the foregoing, as a specific implementation manner, in the N-bit successive approximation ADC provided in the embodiment of the present application, the ratio of the capacitance values of each first capacitor to the capacitance value of each second capacitor is:
1:1:2 1 :2 2 :…:2 N-2 ；
the first capacitors and the second capacitors are arranged in ascending order according to the capacitance value, and the capacitance value of the first capacitor at the ith position is equal to the capacitance value of the second capacitor at the ith position.
Specifically, in the present embodiment, the capacitance value set in the power of 2 rule is matched with the binary digital signal; and the capacitance value of the ith first capacitor is equal to that of the ith second capacitor, so that differential matching can be realized. Taking the first capacitor array as an example, the N first capacitors in the first capacitor array are ranked in ascending order according to the capacitance value, that is, the first capacitor with smaller capacitance value has smaller rank and the first capacitor with larger capacitance value has larger rank. Thus, the nth first capacitor C1N is the first capacitor with the largest capacitance, and may be referred to as the highest first capacitor. The second capacitor array is similar.
Thus, if the capacitance values of the 1 st first capacitor C11 and the 1 st second capacitor C21 are both C, the capacitance values of the 2 nd first capacitor C12 and the 2 nd second capacitor C22 are both C, the capacitance values of the 3 rd first capacitor C13 and the 3 rd second capacitor C23 are both 2C, … …, and the capacitance values of the N first capacitor C1N and the N second capacitor C2N are both 2 N-2 C。
It should be noted that the 1 st first capacitor C11 is a redundant capacitor, so as to ensure that the sum of the capacitance values of the first capacitor array also meets the power law of 2, so that the capacitance values of the 1 st first capacitor C11 and the 2 nd first capacitor C12 are the same. The second capacitor C21 of the 1 st bit is similar, and will not be described here again.
In this application, each embodiment is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the apparatus disclosed in the examples, since it corresponds to the method disclosed in the examples, the description is relatively simple, and the relevant points are referred to in the description of the method section.
It should also be noted that in this document, relational terms such as "first" and "second" are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The technical scheme provided by the application is described in detail. Specific examples are set forth herein to illustrate the principles and embodiments of the present application, and the description of the examples above is only intended to assist in understanding the methods of the present application and their core ideas. It should be noted that it would be obvious to those skilled in the art that various improvements and modifications can be made to the present application without departing from the principles of the present application, and such improvements and modifications fall within the scope of the present application.
Claims (9)
1. The signal output control method of the N-bit successive approximation type ADC is characterized by being applied to a logic controller in the N-bit successive approximation type ADC and comprising the following steps of:
controlling an N-bit comparison circuit in the N-bit successive approximation type ADC to sample a lower polar plate;
controlling the N-bit comparison circuit to keep charges, and taking the output of a comparator in the N-bit comparison circuit as the highest bit of a digital signal to be output;
the N-bit comparison circuit is controlled to repeatedly redistribute charges, and the output of the comparator is sequentially used as the current high bit of the digital signal to be output;
the controlling the N-bit comparison circuit in the N-bit successive approximation ADC to perform the down-plate sampling includes:
The first input end of the comparator is controlled to be connected with a common mode reference voltage source through a first connecting switch; the second input end of the comparator is controlled to be connected with the common mode reference voltage source through a second connecting switch; the first input end of the comparator is connected with the upper polar plate of each first capacitor in the first capacitor array, and the second input end of the comparator is connected with the upper polar plate of each second capacitor in the second capacitor array;
the lower polar plate of the first capacitor of the control Nth bit is connected with a first differential input signal line through a first switch array; the lower polar plate of the second capacitor of the control Nth bit is connected with a second differential input signal line through a second switch array;
the lower polar plates of the rest first capacitors are controlled to be connected with a grounding wire through the first switch array; and controlling the lower polar plates of the rest second capacitors to be connected with the grounding wire through the second switch array.
2. The signal output control method according to claim 1, wherein the controlling the N-bit comparison circuit to perform charge holding and taking an output of a comparator in the N-bit comparison circuit as a most significant bit of a digital signal to be output includes:
Controlling the first connecting switch and the second connecting switch to be disconnected;
the lower polar plate of the Nth first capacitor is controlled to be connected with the common mode reference voltage source through the first switch array; the lower polar plate of the Nth second capacitor is controlled to be connected with the common mode reference voltage source through the second switch array;
and obtaining the output of the comparator and taking the output as the Nth bit of the digital signal to be output.
3. The signal output control method according to claim 2, wherein the controlling the N-bit comparison circuit to repeatedly perform charge redistribution and sequentially taking the output of the comparator as the current next higher order of the digital signal to be output includes:
judging whether the output of the comparator is in a high level or not;
if yes, the lower polar plate of the Nth first capacitor is controlled to be connected to the grounding wire through the first switch array; if not, the lower polar plate of the Nth second capacitor is controlled to be connected to the grounding wire through the second switch array;
let i=1;
obtaining the output of the comparator and taking the output as the N-i bit of the digital signal to be output;
judging whether N-i=1 is true or not;
if yes, outputting the digital signal to be output;
If not, judging whether the N-i bit of the digital signal to be output is at a high level;
if the N-i bit of the digital signal to be output is high level, the lower polar plate of the second capacitor for controlling the N-i bit is connected to the common mode reference voltage source through the second switch array; if the N-i bit of the digital signal to be output is low level, the lower polar plate of the first capacitor for controlling the N-i bit is connected to the common mode reference voltage source through the first switch array;
let i add 1; and continuing to execute the step of acquiring the output of the comparator and taking the output as the N-i bit of the digital signal to be output.
4. The N-bit successive approximation type ADC is characterized by comprising an N-bit comparison circuit and a logic controller;
the logic controller is used for controlling the N-bit comparison circuit to sample a lower polar plate; controlling the N-bit comparison circuit to carry out charge retention so as to take the output of a comparator in the N-bit comparison circuit as the highest bit of a digital signal to be output; the N-bit comparison circuit is controlled to repeatedly redistribute charges so as to sequentially take the output of the comparator as the current high-order bit of the digital signal to be output;
wherein, the controlling the N-bit comparison circuit to sample the lower polar plate includes:
The first input end of the comparator is controlled to be connected with a common mode reference voltage source through a first connecting switch; the second input end of the comparator is controlled to be connected with the common mode reference voltage source through a second connecting switch; the first input end of the comparator is connected with the upper polar plate of each first capacitor in the first capacitor array, and the second input end of the comparator is connected with the upper polar plate of each second capacitor in the second capacitor array;
the lower polar plate of the first capacitor of the control Nth bit is connected with a first differential input signal line through a first switch array; the lower polar plate of the second capacitor of the control Nth bit is connected with a second differential input signal line through a second switch array;
the lower polar plates of the rest first capacitors are controlled to be connected with a grounding wire through the first switch array; and controlling the lower polar plates of the rest second capacitors to be connected with the grounding wire through the second switch array.
5. The N-bit successive approximation ADC of claim 4, wherein the N-bit comparison circuit comprises the comparator, a first capacitor array, a second capacitor array, a first switch array and a second switch array;
the upper polar plate of each first capacitor in the first capacitor array is connected with the first input end of the comparator, and the upper polar plate of each second capacitor in the second capacitor array is connected with the second input end of the comparator; the first switch array is used for controlling the sampling of the lower polar plate of the first capacitor array; the second switch array is used for controlling the sampling of the lower polar plate of the second capacitor array;
The comparator is used for comparing the output voltage of the upper polar plate of the first capacitor array with the output voltage of the upper polar plate of the second capacitor array and outputting a comparison result.
6. The N-bit successive approximation ADC of claim 5, wherein the N-bit comparison circuit further comprises a first connection switch and a second connection switch;
the first end of the first connecting switch is connected with the upper polar plate of each first capacitor; the first end of the second connecting switch is connected with the upper polar plate of each second capacitor;
the second end of the first connecting switch and the second end of the second connecting switch are connected with the common mode reference voltage source so as to provide common mode reference voltage for the first capacitor array and the second capacitor array when the lower polar plate is sampled.
7. The N-bit successive approximation ADC of claim 5 wherein,
each first capacitor corresponds to a switch in the first switch array one by one; the lower electrode plate of the Nth first capacitor is in switching connection with a common mode reference voltage source or a ground wire or a first differential input signal wire through a corresponding switch, and the lower electrode plates of the other first capacitors are in switching connection with the common mode reference voltage source or the ground wire through corresponding switches;
Each second capacitor corresponds to a switch in the second switch array one by one; the lower polar plate of the Nth second capacitor is in switching connection with a common mode reference voltage source or a ground wire or a second differential input signal wire through a corresponding switch, and the lower polar plates of the other second capacitors are in switching connection with the common mode reference voltage source or the ground wire through corresponding switches.
8. The N-bit successive approximation ADC of claim 7, wherein the first switch array comprises a first single pole, three throw switch and N-1 first single pole, double throw switches;
the fixed end of the first single-pole three-throw switch is connected with the lower polar plate of the Nth-bit first capacitor, the first movable end is connected with the common mode reference voltage source, the second movable end is connected with the grounding wire, and the third movable end is connected with the first differential input signal wire; the fixed end of each first single-pole double-throw switch is connected with the corresponding lower polar plate of the first capacitor, the first movable end is connected with the common mode reference voltage source, and the second movable end is connected with the grounding wire;
the second switch array comprises a second single-pole three-throw switch and N-1 second single-pole double-throw switches;
The fixed end of the second single-pole three-throw switch is connected with the lower polar plate of the Nth second capacitor, the first movable end is connected with the common mode reference voltage source, the second movable end is connected with the grounding wire, and the third movable end is connected with the second differential input signal wire; the fixed end of each second single-pole double-throw switch is connected with the corresponding lower polar plate of the second capacitor, the first movable end is connected with the common mode reference voltage source, and the second movable end is connected with the grounding wire.
9. The N-bit successive approximation ADC according to any one of claims 5 to 8, wherein the ratio of the capacitance values of each of the first capacitors and the ratio of the capacitance values of each of the second capacitors are:
1:1:21:22:…:2N-2；
the first capacitors and the second capacitors are arranged in ascending order according to the capacitance value, and the capacitance value of the ith first capacitor is equal to that of the ith second capacitor.
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| TW201444297A (en) * | 2013-05-15 | 2014-11-16 | Realtek Semiconductor Corp | Successive-approximation-register analog-to-digital converter (SAR ADC) with programmable gain of amplitude of input signal and method therefor |
| CN106301364A (en) * | 2016-08-25 | 2017-01-04 | 东南大学 | A kind of gradual approaching A/D converter structure and low power consumption switch method thereof |
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| US8638248B2 (en) * | 2011-10-07 | 2014-01-28 | Nxp, B.V. | Input-independent self-calibration method and apparatus for successive approximation analog-to-digital converter with charge-redistribution digital to analog converter |
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| TW201444297A (en) * | 2013-05-15 | 2014-11-16 | Realtek Semiconductor Corp | Successive-approximation-register analog-to-digital converter (SAR ADC) with programmable gain of amplitude of input signal and method therefor |
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