TWI509669B - 使用多重側壁影像移轉技術於結構中圖案化特徵之方法 - Google Patents

使用多重側壁影像移轉技術於結構中圖案化特徵之方法 Download PDF

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TWI509669B
TWI509669B TW101144277A TW101144277A TWI509669B TW I509669 B TWI509669 B TW I509669B TW 101144277 A TW101144277 A TW 101144277A TW 101144277 A TW101144277 A TW 101144277A TW I509669 B TWI509669 B TW I509669B
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Nicholas V Licausi
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Description

使用多重側壁影像移轉技術於結構中圖案化特徵之方法
一般而言，本發明涉及複雜半導體裝置的製造，尤其涉及利用多側壁圖像移轉技術在例如用於形成積體電路裝置的材料層或半導體基板等結構中圖案化特徵的多種方法。
製造例如中央處理單元(CPU)、儲存裝置、專用積體電路(application specific integrated circuit；ASIC)等先進積體電路需要依據特定的電路佈局在特定的晶片面積中形成大量電路元件，其中，場效電晶體(NMOS及PMOS電晶體)是製造此類積體電路裝置中使用的一種重要類型的電路元件。場效電晶體，無論是NMOS電晶體還是PMOS電晶體，通常包括形成於半導體基板中由通道區隔離的摻雜源極汲極區。閘極絕緣層位於該通道區上方，導電閘極電極位於該閘極絕緣層上方。通過在該閘極電極施加適當的電壓，使該通道區導電，從而允許電流自源極區流向汲極區。
為形成此類積體電路裝置，需以極細緻的順序或流程執行大量處理操作，例如沈積製程、蝕刻製程、加熱製程、遮罩操作等。一般而言，積體電路裝置的形成尤其包括形成複數個材料層並圖案化或移除該些材料層的部分，從而定義理想的結構，例如閘極 電極、側間隙壁(sidewall spacer)等。裝置設計人員基本通過縮小電晶體的尺寸或按比例縮小電晶體的各元件的尺寸，例如電晶體的閘極長度，而得以成功改進電晶體裝置的電性功能。實際上，當前電晶體的裝置尺寸已縮小至難以使用基於193奈米的光微影工具及技術直接圖案化此類特徵的程度。因此，裝置設計人員採用多種技術來圖案化極小特徵。這樣的一種技術通常稱作側壁圖像移轉技術。
第1A至1E圖例示現有的側壁圖像移轉技術。如第1A圖所示，在例如半導體基板的結構10上方形成芯軸(mandrel)12。芯軸12可由多種材料製成，例如非晶矽、多晶矽等。芯軸12的尺寸可依據特定的應用而變化。可利用現有的沈積、光微影及蝕刻工具以及技術沈積並圖案化芯軸材料層，從而形成芯軸12。接著，如第1B圖所示，在芯軸12及結構10上方共形沈積間隙壁材料層14。間隙壁材料層14可由多種材料組成，例如氮化矽、二氧化矽等。如第1C圖所示，執行非等向性蝕刻製程，以定義與芯軸12相鄰的間隙壁14A。接著，如第1D圖所示，通過執行選擇性蝕刻製程移除芯軸12，保留間隙壁14A作為後續蝕刻製程的遮罩，從而在結構10中定義特徵18，如第1E圖所示。
本發明提供利用多側壁圖像移轉技術在例如用於形成積體電路裝置的材料層或半導體基板等結構中圖案化特徵的多種方法。
下面提供本發明的簡要總結，以提供本發明的一些態樣的基本理解。本發明內容並非詳盡概述本發明。其並非意圖識別本發明的關鍵或重要元件或劃定本發明的範圍。其唯一目的在於提供 一些簡化的概念，作為後面所討論的更詳細說明的前序。
一般而言，本發明提供利用多側壁圖像移轉技術在例如用於形成積體電路裝置的材料層或半導體基板等結構中圖案化特徵的多種方法。在一實施例中，該方法包括：在結構上方形成第一芯軸；形成鄰近該第一芯軸的複數個第一間隙壁；形成複數個第二芯軸，其中，各該第二芯軸形成於鄰近該第一間隙壁的其中一第一間隙壁；以及形成複數個第二間隙壁，其中，各該第二間隙壁形成於鄰近該第二芯軸的其中一第二芯軸。該方法還包括：執行至少一蝕刻製程，以相對該第一間隙壁及該第二間隙壁選擇性移除該第一芯軸及該第二芯軸，從而定義由該第一間隙壁及該第二間隙壁組成的蝕刻遮罩；以及在該結構上通過該蝕刻遮罩執行至少一蝕刻製程，以在該結構中定義複數個特徵。
在另一實施例中，該方法包括：在結構上方形成第一芯軸；形成鄰近該第一芯軸的複數個第一間隙壁，其中，各該第一間隙壁具有第一寬度；以及形成複數個第二芯軸，其中，各該第二芯軸形成於鄰近該第一間隙壁的其中一第一間隙壁。在該實施例中，該方法還包括：形成複數個第二間隙壁，其中，各該第二間隙壁形成於鄰近該第二芯軸的其中一第二芯軸，且各該第二間隙壁具有不同於該第一寬度的第二寬度；執行至少一蝕刻製程，以相對該第一間隙壁及該第二間隙壁選擇性移除該第一芯軸及該第二芯軸，從而定義由該第一間隙壁及該第二間隙壁組成的蝕刻遮罩；以及在該結構上通過該蝕刻遮罩執行至少一蝕刻製程，以在該結構中定義複數個特徵。
100‧‧‧裝置
10、110‧‧‧結構
12‧‧‧芯軸
14‧‧‧間隙壁材料層
14A‧‧‧間隙壁
18、120A、120B‧‧‧特徵
112‧‧‧第一芯軸
112W、114AW、116AW、118AW、119、120AW、120BW‧‧‧寬度
114‧‧‧第一間隙壁材料層
114A‧‧‧第一間隙壁
116A‧‧‧第二芯軸
118‧‧‧第二間隙壁材料層
118A‧‧‧第二間隙壁
130‧‧‧蝕刻遮罩
132A、132B‧‧‧溝槽
140、140A‧‧‧閘極絕緣材料層
142‧‧‧閘極電極材料層
142A‧‧‧閘極電極
150‧‧‧半導體基板
160‧‧‧閘極結構
200‧‧‧FinFET裝置
204‧‧‧閘極覆蓋層
208‧‧‧側間隙壁
209‧‧‧絕緣材料
210‧‧‧半導體材料層
結合附圖參照下面的說明可理解本發明，該等附圖中相同的元件符號代表類似的元件，其中：第1A至1E圖例示現有的側壁圖像移轉技術；第2A至2P圖顯示本發明在例如用於形成積體電路裝置的材料層中或半導體基板中圖案化特徵的多種方法；以及第3A至3C圖顯示可利用這裡所揭露的方法形成新穎的鰭式場效電晶體(FinFET)裝置的實施例。
儘管這裡揭露的發明主題容許各種修改及替代形式，但附圖中以示例形式顯示其特定的實施例，且在此進行詳細描述。不過，應當理解，這裡對特定實施例的說明並非意圖將本發明限於所揭露的特定形式，相反，意圖涵蓋落入由所附申請專利範圍定義的精神及範圍內的所有修改、等同及替代。
下面描述本發明的不同實施例。出於清楚目的，並非實際實施中的全部特徵都描述於本說明書中。當然，應當瞭解，在任意此類實際實施例的開發中，必須作大量的特定實施決定以滿足開發者的特定目標，例如符合與系統相關及與商業相關的約束條件，該等約束條件因不同實施而異。而且，應當瞭解，此類開發努力可能複雜而耗時，但其仍然是本領域技術人員借助本說明書所執行的常規程式。
下面參照附圖描述本發明主題。附圖中示意各種結構、系統及裝置是出於解釋目的以及避免模糊本發明與本領域技術人員已知的細節。但是，本發明包括該等附圖以描述並解釋實施例。這裡所用的詞語和片語的意思應當解釋為與相關領域技術人員對該 等詞語及片語的理解一致。這裡的術語或片語的連貫使用並不意圖暗含特別的定義，也就是與本領域技術人員所理解的通常慣用意思不同的定義。若術語或片語意圖具有特定意義，也就是不同於本領域技術人員所理解的意思，則此類特別定義會以直接明確地提供該術語或片語的特定定義的定義方式明確表示於說明書中。
本發明提供利用多側壁圖像移轉技術在例如用於形成積體電路裝置的材料層或半導體基板等結構中圖案化特徵的多種方法。在完整閱讀本申請後，本領域的技術人員很容易瞭解，本方法適用於多種裝置，包括但不限於，ASIC、邏輯裝置、記憶體裝置等。而且，本發明可用於形成積體電路產品的任意不同類型的特徵，例如線(line)、溝槽、閘極電極結構、FinFET裝置的鰭片(fin)等。下面參照附圖詳細描述這裡所揭露的方法及裝置的不同實施例。
第2A至2J圖顯示在用於製造積體電路裝置的結構上形成多種特徵的方法。如第2A圖所示，在結構110上方形成第一芯軸112。結構110意圖代表製造積體電路產品中可使用的任意類型的結構或材料層。例如，結構110可為半導體基板、金屬層、氮化矽層、多晶矽層、閘極電極材料層等。第一芯軸112可由多種材料製成，例如非晶矽、多晶矽等。第一芯軸112的尺寸可依據特定的應用而變化。例如，在一實施例中，第一芯軸112的高度可約為80奈米，寬度112W可約為40奈米。可利用已知的沈積、光微影及蝕刻工具及技術沈積並圖案化芯軸材料層，從而可形成第一芯軸112。
接著，如第2B圖所示，在第一芯軸112及結構110上方共形沈積第一間隙壁材料層114。第一間隙壁材料層114可由多種材料 組成，例如氮化矽、二氧化矽等。第一間隙壁材料層114的厚度可依據要形成於結構110中的特徵的尺寸而變化，後面將作詳細描述。
接著，如第2C圖所示，在第一間隙壁材料層114上執行非等向性蝕刻製程，以定義鄰近第一芯軸112的複數個第一間隙壁114A。在一實施例中，第一間隙壁114A的寬度114AW可約為10至25奈米。
接著，如第2D圖所示，在第一芯軸112及第一間隙壁114A上方共形沈積芯軸材料層116。芯軸材料層116可由多種材料組成，例如非晶矽、多晶矽等。芯軸材料層116的厚度可依據形成於結構110中的特徵的尺寸而變化，後面將作詳細描述。芯軸材料層116可由與第一芯軸112相同的材料製成，但並非必須。
接著，如第2E圖所示，在芯軸材料層116上執行非等向性蝕刻製程，以定義鄰近第一間隙壁114A的複數個第二芯軸116A。第二芯軸116A的寬度116AW可與第一芯軸112的寬度112W相同。或者，第二芯軸116A的寬度116AW可與第一芯軸112的寬度112W不同，也就是，寬度116AW可大於或小於寬度112W。在一實施例中，第二芯軸116A的寬度116AW可約為20至40奈米。
接著，如第2F圖所示，在第2E圖所示的多種結構上方共形沈積第二間隙壁材料層118。第二間隙壁材料層118可由多種材料組成，例如氮化矽、二氧化矽等。第二間隙壁材料層118的厚度可依據將在結構110中形成的特徵的尺寸而變化，後面將作詳細描述。第二間隙壁材料層118可由與第一間隙壁材料層114相同的材料製成，但並非必須。
接著，如第2G圖所示，在第二間隙壁材料層118上執行非等向性蝕刻製程，以定義鄰近各該第二間隙壁114A的複數個第二間隙壁118A。在一實施例中，第二間隙壁118A的寬度118AW可約為5至15奈米。在一實施例中，第二間隙壁118A的寬度118AW可不同於第一間隙壁114A的寬度114A，從而可在結構110中可形成不同尺寸的特徵。在這裡揭露的其他實施例中，第二間隙壁118A的寬度118AW可大體相同或大於第一間隙壁114A的寬度114A。
接著，如第2H圖所示，執行一個或複數個蝕刻製程，以相對第一間隙壁114A及第二間隙壁118A選擇性移除第一芯軸112及第二芯軸116。第一間隙壁114A及第二間隙壁118A定義蝕刻遮罩130，該蝕刻遮罩130可用於在結構110中定義多種特徵120，後面將作詳細描述。
第2I圖顯示執行蝕刻製程後的裝置，其中，通過遮罩層130在結構110上執行該蝕刻製程，濕式或乾式蝕刻製程，從而在結構110中定義複數個特徵120。如前所述，利用這裡所揭露的方法可形成多種不同類型的特徵，例如線、溝槽、閘極電極結構、FinFET裝置的鰭片等。因此，本發明不限於任意特定類型的特徵。在這裡所述的實施例中，在結構110中形成複數個特徵120A、120B。第2J圖顯示剝離遮罩層120後的裝置100。在這裡所揭露的實施例中，特徵120A(對應第一間隙壁114A)的寬度120AW大於特徵120B(對應第二間隙壁118A)的寬度120BW。
第2K至2M圖顯示可採用這裡所揭露的方法的另一實施例。如第2K圖所示，第二芯軸116A的寬度119大於第一芯軸112的 寬度112W，而第一間隙壁114A的寬度與第二間隙壁118A的寬度相同。如第2L圖所示，執行一個或複數個蝕刻製程以相對第一間隙壁114A及第二間隙壁118A選擇性移除第一芯軸112及第二芯軸116。第一間隙壁114A及第二間隙壁118A定義蝕刻遮罩130，該蝕刻遮罩130可用於在結構110中定義多種特徵120，後面將作詳細描述。第2M圖顯示執行蝕刻製程後的裝置100，其中，通過遮罩層130在結構110上執行該蝕刻製程，濕式或乾式蝕刻製程，從而在結構110中定義複數個溝槽特徵132A、132B。在該實施例中，溝槽132A的寬度112W對應第一芯軸112的寬度，而溝槽132B的寬度119對應第二芯軸116A的寬度。
第2N至2P圖顯示可採用這裡所揭露的方法的另一實施例。如第2N圖所示，結構110可為形成於閘極絕緣材料層140上方的閘極電極材料層142，該閘極絕緣材料層140形成於半導體基板150上方。在第2N至2P圖的示例中，第一芯軸112與第二芯軸116A具有相同的寬度，第一間隙壁114A與第二間隙壁118A具有相同的寬度。如第2O圖所示，執行一個或複數個蝕刻製程，以相對第一間隙壁114A及第二間隙壁118A選擇性移除第一芯軸112及第二芯軸116。第一間隙壁114A及第二間隙壁118A定義蝕刻遮罩130。蝕刻遮罩130可用於在閘極電極材料層142中定義多種特徵。第2P圖顯示執行一個或複數個蝕刻製程後的裝置100，該等蝕刻製程可為乾式或濕式蝕刻製程，其至少執行於閘極電極材料層142上，以定義複數個閘極電極142A。在該示例中，還可通過遮罩層130執行蝕刻製程以圖案化閘極絕緣材料層140，從而定義閘極絕緣材料層140A。在該實施例中，這裡所述的方法可用 於定義裝置100的複數個閘極結構160，其中，閘極結構160由閘極絕緣層140A及閘極電極142A組成。在該示例中，閘極電極142A的關鍵尺寸對應位於其上的間隙壁的寬度。
第3A至3C圖示例可利用這裡所揭露的方法形成FinFET裝置200，其中，特徵120A、120B為FinFET裝置200的鰭片。如前所述，在一些實施例中，特徵120A、120B(或鰭片)可具有不同的寬度。在該示例中，結構110可為塊體矽基板，或為絕緣體上矽(silicon on insulator；SOI)基板的主動層。鰭片120A、120B的總體尺寸、形狀及配置可依據特定的應用而變化。
第3B圖顯示執行複數個處理操作後的FinFET裝置200。例如，利用已知技術形成裝置200的閘極電極結構202。在一實施例中，閘極結構202包括閘極絕緣層202A及閘極電極202B。在閘極電極層202B上方還形成有閘極覆蓋層204。閘極絕緣層202A可由多種不同的材料組成，例如二氧化矽、高介電常數(介電常數大於10)絕緣材料等。類似地，閘極電極202B還可由例如多晶矽或非晶矽等材料組成，或由一層或多層金屬層作為閘極電極202B。在完整閱讀本申請後，本領域的技術人員將意識到，圖中所示的FinFET裝置200的閘極結構202，也就是閘極絕緣層202A及閘極電極202B，本質上為代表性質。也就是，閘極結構202可由多種不同的材料組成，可具有多種配置，並可利用所謂的"先閘極(gate-first)"或"替代金屬閘極"技術進行製造。在一實施例中，可執行氧化製程以形成由二氧化矽組成的閘極絕緣層202A，如第3B圖所示。接著，可在裝置200上方沈積閘極電極材料及閘極覆蓋層材料，並利用已知的光微影及蝕刻技術圖案化該等層。閘極覆 蓋層204可由多種材料製成，例如氮化矽。通常，由例如氮化矽組成的側間隙壁鄰近閘極電極結構202形成，以保護並電性隔離閘極電極結構202，不過，為避免模糊本發明，第3B圖未圖示此類間隙壁。
第3C圖為一透視圖，顯示處於後期製造階段的FinFET裝置200的實施例，其中，鰭片120A、120B意圖具有不同的目標寬度，而非製造容差或誤差導致的寬度差別。利用這裡所揭露的技術，FinFET裝置200的通道寬度可根據裝置設計人員的需要而變化，以獲得所設計的特定電路所需的理想的或目標驅動電流。也就是，利用這裡所揭露的技術，可設計並製造FinFET裝置，從而使其產生的驅動電流不同於具有均一厚度的鰭片的FinFET裝置。而且，該FinFET裝置中至少一定程度取決於鰭片寬度的另一個重要參數為閾值電壓(threshold voltage)。通過利用這裡所揭露的FinFET裝置200，其中，鰭片的寬度可彼此不同，可更好地控制該裝置的閾值電壓。如上所述，裝置200包括閘極結構202及閘極覆蓋層204。在第3C圖所示的剖面中，閘極絕緣層202A未顯示於閘極電極202B下方。第3C圖顯示絕緣材料209、側間隙壁208，以及將在其中形成裝置100的源極/汲極區的半導體材料層210。間隙壁208可由多種材料形成，例如氮化矽、氮氧化矽等。可通過共形沈積間隙壁材料層並隨後執行非等向性蝕刻製程製造間隙壁208。應當理解，當申請專利範圍中提到間隙壁鄰近芯軸或反之時，間隙壁與芯軸間不要求物理接觸。也就是，例如，在一內襯層上形成第一間隙壁114A前，可在第一芯軸112上形成內襯層。在此情況下，第一間隙壁114A仍應理解為鄰近第一芯軸112。若 申請專利範圍中說明間隙壁與芯軸間有物理接觸，則該物理接觸將在申請專利範圍中陳述為間隙壁形成於芯軸"上(on)"或反之。
由於本領域技術人員可借助這裡的教導很容易地以不同但等同的方式修改並實施本發明，因此上述特定的實施例僅為說明性質。例如，可以不同的順序執行上述製程步驟。而且，本發明並不限於這裡所示架構或設計的細節，而是如下面的申請專利範圍所述。因此，顯然，可對上面揭露的特定實施例進行修改或變更，所有此類變更落入本發明的範圍及精神內。因此，申請專利範圍規定本發明的保護範圍。
100‧‧‧裝置
110‧‧‧結構
120A、120B‧‧‧特徵
120AW、120BW‧‧‧寬度

Claims (18)

  1. 一種製造半導體裝置之方法，包括：在結構上方形成第一芯軸；形成鄰近該第一芯軸的複數個第一間隙壁；形成複數個第二芯軸，各該第二芯軸形成於鄰近該第一間隙壁的其中一第一間隙壁；形成複數個第二間隙壁，各該第二間隙壁形成於鄰近該第二芯軸的其中一第二芯軸；執行至少一蝕刻製程，以相對該第一間隙壁及該第二間隙壁選擇性移除該第一芯軸及該第二芯軸，從而定義由該第一間隙壁及該第二間隙壁組成的蝕刻遮罩；以及在該結構上通過該蝕刻遮罩執行至少一蝕刻製程，以在該結構中定義複數個特徵，其中，該第一間隙壁形成於該第一芯軸上，各該第二芯軸形成於該第一間隙壁的其中一第一間隙壁上，以及各該第二間隙壁形成於該第二芯軸的其中一第二芯軸上。
  2. 如申請專利範圍第1項所述之方法，其中，該第一間隙壁的寬度與各該複數個第二間隙壁的寬度相同。
  3. 如申請專利範圍第1項所述之方法，其中，該第一間隙壁的寬度與各該複數個第二間隙壁的寬度不同。
  4. 如申請專利範圍第1項所述之方法，其中，該結構為半導體基板或材料層的其中之一。
  5. 如申請專利範圍第1項所述之方法，其中，該結構為半導體基板，以及其中，該特徵為鰭式場效電晶體裝置的鰭片。
  6. 如申請專利範圍第1項所述之方法，其中，該第一芯軸的寬度與各該複數個第二芯軸的寬度相同。
  7. 如申請專利範圍第1項所述之方法，其中，該第一芯軸的寬度與各該複數個第二芯軸的寬度不同。
  8. 如申請專利範圍第1項所述之方法，其中，該結構為閘極電極材料層，以及其中，該特徵為閘極電極。
  9. 如申請專利範圍第1項所述之方法，其中，該特徵為線或溝槽。
  10. 一種製造半導體裝置之方法，包括：在結構上方形成第一芯軸；形成鄰近該第一芯軸的複數個第一間隙壁，各該第一間隙壁具有第一寬度；形成複數個第二芯軸，各該第二芯軸形成於鄰近該第一間隙壁的其中一第一間隙壁；形成複數個第二間隙壁，各該第二間隙壁形成於鄰近該第二芯軸的其中一第二芯軸，且各該第二間隙壁具有不同於該第一寬度的第二寬度；執行至少一蝕刻製程，以相對該第一間隙壁及該第二間隙壁選擇性移除該第一芯軸及該第二芯軸，從而定義由該第一間隙壁及該第二間隙壁組成的蝕刻遮罩；以及在該結構上通過該蝕刻遮罩執行至少一蝕刻製程，以在該結構中定義複數個特徵，其中，該第一間隙壁形成於該第一芯軸上，各該第二芯軸形成於該第一間隙壁的其中一第一間隙壁上，以及各該第二間隙壁形成於該第二芯軸的其中一第二芯軸上。
  11. 如申請專利範圍第10項所述之方法，其中，該第一寬度大於該第二寬度。
  12. 如申請專利範圍第10項所述之方法，其中，該第二寬度大於該第一寬度。
  13. 如申請專利範圍第10項所述之方法，其中，該結構為半導體基板或材料層的其中之一。
  14. 如申請專利範圍第10項所述之方法，其中，該結構為半導體基板，以及其中，該特徵為鰭式場效電晶體裝置的鰭片。
  15. 如申請專利範圍第10項所述之方法，其中，該第一芯軸的寬度與各該複數個第二芯軸的寬度相同。
  16. 如申請專利範圍第10項所述之方法，其中，該第一芯軸的寬度與各該複數個第二芯軸的寬度不同。
  17. 如申請專利範圍第10項所述之方法，其中，該結構為閘極電極材料層，以及其中，該特徵為閘極電極。
  18. 如申請專利範圍第10項所述之方法，其中，該特徵為線或溝槽。
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