TWI503872B - Method for manufacturing super-connected semiconductor devices - Google Patents
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- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 13
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- 229910052698 phosphorus Inorganic materials 0.000 description 12
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- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
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- 235000012431 wafers Nutrition 0.000 description 2
- 229910052691 Erbium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Description
本發明係有關於一種超接合半導體裝置之製造方法，具有作為漂移層之超接合(super junction)構造部，該超接合構造部係於垂直於半導體基板的主表面的方向上，使進行複數配置的n型管柱及p型管柱在平行主表面的方向上交替相鄰。The present invention relates to a method of manufacturing a super-junction semiconductor device, comprising: a super junction structure portion as a drift layer, the super-junction structure portion being oriented in a direction perpendicular to a main surface of the semiconductor substrate, for performing a plurality of configurations The n-type column and the p-type column are alternately adjacent in the direction parallel to the main surface.
一般，半導體裝置(以下，亦有稱為半導體元件或單獨稱為元件的情形)係大致分為，於半導體基板的單一個面上具有電極之橫向元件，以及半導體基板的兩個面上具有電極之縱向半導體裝置(縱向元件)。縱向元件，係於接通時流動漂移電流的方向和斷開時的逆向偏壓所造成的空乏層延展的方向為相同。例如，在一般的平面型n通道縱向MOSFET的情形下，高阻抗的n- 漂移層的部分係在MOSFET為接通狀態時作為於縱向上流動電流的區域而作動，而在斷開狀態時則空乏化而提高耐壓。縮短此高阻抗的n- 漂移層的電流通路的話，因為漂移阻抗變低，所以導致降低了MOSFET的實質性的接通阻抗之效果；相反的，因為窄化由p基極區域與n- 漂移區域之間的pn接合所進行的汲-基極間空乏層的擴張寬度、快速達到矽的臨界電場強度的緣故，所以耐壓降低。反之，耐壓高的元件則因為n- 漂移層變厚，理所當然地接通阻抗變大而增加損失。這樣的接通阻抗與耐壓之間的關係稱之為取捨(trade off)關係。此取捨關係已知在IGBT、雙極性電晶體、二極體等的半導體元件中也是同樣成立。還有，該關係對於接通時流動漂移電流的方向和斷開時的逆向偏壓所造成的空乏層延展的方向不同之橫向半導體元件來說也是共通的。In general, a semiconductor device (hereinafter, also referred to as a semiconductor element or a separately referred to as an element) is roughly divided into a lateral element having an electrode on a single surface of a semiconductor substrate, and an electrode having electrodes on both sides of the semiconductor substrate. Longitudinal semiconductor device (longitudinal element). The longitudinal element is in the same direction as the direction in which the drift current flows when turned on and the reverse bias when turned off. For example, in the case of a general planar n-channel vertical MOSFET, the portion of the high-impedance n - drift layer acts as a region where the current flows in the longitudinal direction when the MOSFET is in the on state, and in the off state when the MOSFET is in the on state. Depletion increases the pressure resistance. Shortening the current path of the high-impedance n - drift layer, because the drift impedance becomes lower, the effect of reducing the substantial on-resistance of the MOSFET is caused; on the contrary, since the narrowing is caused by the p-base region and the n - drift Since the expansion width of the 汲-base interstitial layer by the pn junction between the regions rapidly reaches the critical electric field strength of the erbium, the withstand voltage is lowered. On the other hand, in the element having a high withstand voltage, since the n - drift layer becomes thick, it is a matter of course that the on-resistance becomes large and the loss is increased. Such a relationship between the on-resistance and the withstand voltage is referred to as a trade off relationship. This trade-off relationship is also known to be true also in semiconductor elements such as IGBTs, bipolar transistors, and diodes. Further, this relationship is also common to the lateral semiconductor elements in which the direction of the flow drift current at the time of the turn-on and the reverse bias at the time of the turn-off are different in the direction in which the depletion layer extends.
針對該問題的解決方法，已知有如圖7、圖8所示之超接合半導體裝置(超接合MOSFET)，其使漂移層在垂直於半導體基板的主表面的方向上為層狀或管柱狀的形狀、而且作為提升比一般的漂移層還要高的雜質濃度之複數個n型的漂移區域(n型管柱)4與p型的分隔區域(p型管柱)5，並且在平行於主表面的方向上則交替重複相鄰並列配置了pn區域，並由此來組成並作為超接合構造部10。此超接合半導體裝置，係在斷開狀態的時候，空乏化前述超接合構造部10而具有負擔耐壓的漂移層之功能。A solution for solving this problem is known as a super-bonded semiconductor device (super-bonded MOSFET) as shown in FIGS. 7 and 8 in which a drift layer is layered or columnar in a direction perpendicular to a main surface of a semiconductor substrate. a shape of the n-type drift region (n-type column) 4 and a p-type separation region (p-type column) 5 which are higher in impurity concentration than the general drift layer, and are parallel to The pn region is alternately arranged adjacent to each other in the direction of the main surface, and is thereby composed and formed as the super-joining structure portion 10. When the super-bonded semiconductor device is in the off state, the super-junction structure portion 10 is depleted and has a function of a drift layer that is resistant to withstand voltage.
前述超接合MOSFET與一般的平面型的n通道縱向MOSFET之構造上最大的不同之處，係漂移層並非單一導電型且不為均勻的不純物濃度的層，是成為如上述般地由並列pn區域所組成的超接合構造部10。在此超接合構造部10中，p型分隔區域(p型管柱)5與n型漂移區域(n型管柱)4之各個不純物濃度(以下，有單獨稱為濃度的情形)即使比同耐壓等級的一般元件高，在斷開狀態下，從超接合構造部10內的並列pn接合，空乏層往兩側展開而將漂移層整體以低電場強度來進行空乏化的緣故，所以可以圖求有高耐壓化。The maximum difference between the above-described super-bonded MOSFET and the general planar n-channel vertical MOSFET is that the drift layer is not a single conductivity type and is not a uniform impurity concentration layer, and is a parallel pn region as described above. The super-joining structure portion 10 is composed. In the super-joining structure portion 10, the respective impurity concentrations (hereinafter, referred to as concentrations) of the p-type separation region (p-type column) 5 and the n-type drift region (n-type column) 4 are even The general element of the withstand voltage level is high, and in the off state, the parallel pn junction in the super junction structure portion 10, the depletion layer is spread to both sides, and the drift layer as a whole is depleted with low electric field strength, so that it can be The figure seeks to have high withstand voltage.
在圖7所示之具備由前述並列pn區域所組成的超接合構造部10之超接合MOSFET的周邊耐壓構造部200中，需要構成於周邊耐壓構造部200內的超接合構造部10的基板表面側(上層)，配置具有均勻的不純物濃度之低濃度n- 磊晶層3。更進一步，於超接合半導體裝置的周邊耐壓構造部200，在超接合構造部10的上層所設置的前述低濃度n- 層3的表層沿著基板表面，p型保護環7根據所需的設計耐壓，以所需間隔分開的方式來做複數設置。又更進一步，此周邊耐壓構造部200具備有相互電性連接於此p型保護環7表面與最外周的p型保護環7a表面之導電性板塊9。更進一步，也於p型通道截斷區域11(或者是n型通道截斷區域也是可以的)設置電性連接的導電性板塊12。In the peripheral pressure-resistant structure portion 200 of the super-junction MOSFET including the super-junction structure portion 10 including the parallel pn region shown in FIG. 7, the super-junction structure portion 10 formed in the peripheral pressure-resistant structure portion 200 is required. On the substrate surface side (upper layer), a low concentration n - plated layer 3 having a uniform impurity concentration is disposed. Further, in the peripheral withstand voltage structure portion 200 of the super-bonded semiconductor device, the surface layer of the low-concentration n - layer 3 provided on the upper layer of the super-junction structure portion 10 is along the substrate surface, and the p-type guard ring 7 is required according to the Design the withstand voltage and do the plural settings in a way that is separated by the required interval. Further, the peripheral pressure-resistant structure portion 200 includes conductive sheets 9 electrically connected to the surface of the p-type guard ring 7 and the outermost peripheral p-type guard ring 7a. Further, an electrically connected conductive plate 12 is also provided in the p-type channel cut-off region 11 (or an n-type channel cut-off region is also possible).
另一方面，在超接合半導體裝置的元件活化部100內，於並列pn區域所組成的超接合構造部100的上層，與一般的半導體裝置同樣地，具備p基極區域13以及在此p基極區域13內的表層上的n射極區域14，於n射極區域14和n漂移區域(n型管柱)4所挾持的前述p基極區域13的表面上，介隔著閘絕緣膜15而具備有閘電極16，並設置有接觸到前述n射極區域14的表面與p基極區域13的高濃度表面之射電極17。On the other hand, in the element activating portion 100 of the super-junction semiconductor device, the upper layer of the super-junction structure portion 100 composed of the parallel pn region is provided with the p-base region 13 and the p-base as in the case of a general semiconductor device. The n-emitter region 14 on the surface layer in the polar region 13 is interposed with the gate insulating film on the surface of the p-base region 13 held by the n-emitter region 14 and the n-drift region (n-type pillar) 4 15 is provided with a gate electrode 16, and is provided with an emitter electrode 17 that contacts the surface of the n-electrode region 14 and the high-concentration surface of the p-base region 13.
作為製作該等超接合構造部10的方法，藉由重複多次磊晶成長和離子植入，將每一次的磊晶成長和離子植入所形成的厚度為較薄的前述並列pn區域，依序上下層疊而在垂直方向上成為長的形狀之方法(多段磊晶法)，是廣為所知的。As a method of fabricating the super-junction structure portion 10, by repeating epitaxial growth and ion implantation a plurality of times, each of the epitaxial growth and ion implantation is formed into a thinner parallel pn region. A method (multi-stage epitaxial method) in which the order is stacked vertically and has a long shape in the vertical direction is widely known.
關於此多段磊晶法所形成的超接合構造部之製造工程的其中一例，進行說明。前述磊晶成長和離子植入，係於高濃度n+ 矽基板1上，形成厚度12μm的低濃度n- 磊晶層2，並形成遮罩對準用的對準標記物(alignment marker)(未圖式)。形成25nm厚的網板(screen)氧化膜(未圖示)後，整個面藉由100keV的加速能量將磷離子以1×1012 cm-2 ～9×1012 cm-2 的劑量來植入離子。光蝕刻步驟後，選擇性地將硼離子與磷離子一樣作為總雜質量的方式來植入離子。去除阻材和氧化膜後且進行氫退火後，形成非摻雜的磊晶層。之後，反覆進行前述之磷和硼的離子植工程之後，完成所需厚度之由並列pn區域所組成的超接合構造部10。An example of the manufacturing process of the super-joining structure portion formed by the multi-stage epitaxial method will be described. The epitaxial growth and ion implantation are performed on a high-concentration n + germanium substrate 1 to form a low-concentration n - epitaxial layer 2 having a thickness of 12 μm, and form an alignment marker for mask alignment (not figure). After forming a 25 nm thick screen oxide film (not shown), the entire surface was implanted with a dose of 1 × 10 12 cm -2 to 9 × 10 12 cm -2 by an acceleration energy of 100 keV. ion. After the photolithography step, the ions are selectively implanted in the same manner as the phosphorus ions as the total impurity amount. After the barrier material and the oxide film are removed and hydrogen annealing is performed, an undoped epitaxial layer is formed. Thereafter, after the ion implantation process of phosphorus and boron described above is repeated, the super-bonding structure portion 10 composed of the parallel pn regions of the desired thickness is completed.
例如，在具備有用前述製造工程所製作出的超接合構造部10之超接合半導體裝置方面，n型管柱4和p型管柱5的電荷平衡很重要，而以相同者為佳。又，為了形成具備前述的耐電荷性之周邊耐壓構造部200，藉由用多段磊晶法形成複數次的磊晶層和離子植入而形成由並列pn區域所組成的超接合構造後，在該超接合構造的上層製作低濃度n-磊晶層3，並藉由載置的方式來形成。換言之，該低濃度n-磊晶層3，係在元件活化部藉由植入離子的方式來構成前述超接合構造部的上層，但是在周邊耐壓構造部200則不植入離子而藉由維持低濃度n-磊晶層3來製作而成。因為前述低濃度n- 磊晶層3的厚度需要15μm左右以上，所以1次的磊晶成長的厚度為10μm以下的話，需要的段數(磊晶成長的次數)則變成2段以上。For example, in the case of the super-bonded semiconductor device having the super-junction structure portion 10 manufactured by the above-described manufacturing process, the charge balance of the n-type pillar 4 and the p-type pillar 5 is important, and the same is preferable. Further, in order to form the peripheral withstand voltage structure portion 200 having the above-described charge resistance, a super-bonding structure composed of parallel pn regions is formed by forming a plurality of epitaxial layers and ion implantation by a multi-stage epitaxial method. A low-concentration n-epitaxial layer 3 is formed on the upper layer of the super-bonding structure, and is formed by being placed. In other words, the low-concentration n-delined layer 3 constitutes the upper layer of the super-junction structure portion by implanting ions in the element activation portion, but the peripheral pressure-resistant structure portion 200 is not implanted with ions. The low concentration n-plated layer 3 is maintained to be produced. Since the thickness of the low-concentration n - epitaxial layer 3 is required to be about 15 μm or more, the number of stages (the number of epitaxial growth) required for the epitaxial growth of one time is 10 μm or more.
在以上說明之超接合構造部的製作工程中，雖根據磷和硼的離子植入來製作出由並列pn區域所組成的超接合構造部，但是對於僅藉由硼的離子植入來製作出與前述相同的超接合構造部之製造方法，是為已知的(專利文獻1)。In the fabrication process of the super-junction structure portion described above, a super-junction structure portion composed of parallel pn regions is formed by ion implantation of phosphorus and boron, but is produced by ion implantation only by boron. The manufacturing method of the super-joining structure part similar to the above is known (patent document 1).
又，有關於藉由改變離子植入射程Rp來製作出超接合構造部的方式，來減少磊晶成長和離子植入的反覆次數，進而改善製造效率的超接合半導體裝置之製造方法，也是有公開(專利文獻2)。Further, there is a method for manufacturing a super-junction semiconductor device in which the super-bonding structure portion is formed by changing the ion implantation range Rp to reduce the number of times of epitaxial growth and ion implantation, and to improve the manufacturing efficiency. Published (Patent Document 2).
再者，如前述的超接合構造部那樣，有關於用以於深度方向形成較長形狀的雜質添加區域的氣相磊晶成長方法的文獻，是已公開了。於此文獻中，如「氣相成長工程為了抑制來自硼植入層及磷植入層的橫向自動摻雜，首先使密封用的薄磊晶矽層氣相成長後進行第二磊晶層的成長之複數階段處理者為佳。」所述的記載那樣，揭示出預先處理磊晶矽層的來源氣體之方法(專利文獻3)。Further, as in the above-described super-joining structure portion, there has been disclosed a vapor phase epitaxial growth method for forming an impurity-added region having a long shape in the depth direction. In this document, for example, "in the vapor phase growth process, in order to suppress the lateral autodoping from the boron implant layer and the phosphorus implant layer, the thin epitaxial layer for sealing is first vapor grown and then the second epitaxial layer is formed. In the above-described description, a method of processing the source gas of the epitaxial layer is disclosed (Patent Document 3).
[專利文獻][Patent Literature]
[專利文獻1] 日本特開2001-119022號專利公報[Patent Document 1] Japanese Patent Laid-Open Publication No. 2001-119022
[專利文獻2] 日本特開2007-12858號專利公報[Patent Document 2] Japanese Patent Laid-Open Publication No. 2007-12858
[專利文獻3] 日本發明第4016371號專利公報(段落0096)[Patent Document 3] Japanese Patent No. 4016371 (paragraph 0096)
在超接合半導體裝置方面，構成超接合構造部的並列pn區域之各個的總雜質量中若發生不平衡的話則耐壓的變異變大，耐壓良品率會降低。然而，前述離子植入的雜質無法避免在磊晶成長時再蒸發。磊晶成長係具體由升溫過程、氫退火、磊晶成長、降溫過程所組成，但是雜質的再蒸發被認為是由於上述升溫過程及氫退火時的熱所發生者。再蒸發的雜質會引發混入半導體基板及磊晶成長中的膜的現象，被稱為自動摻雜的現象。磊晶成長製程中晶圓內及晶圓間若存在溫度變異的話，則根據如前述那樣的再蒸發及自動摻雜現象，於前述並列pn區域中，即使例如離子植入相同劑量，造成電荷不平衡而耐壓變異變大，成為耐壓良品率低的原因。When the total impurity amount of each of the parallel pn regions constituting the super junction structure portion is unbalanced in the super junction semiconductor device, the variation in withstand voltage is increased, and the withstand voltage yield is lowered. However, the aforementioned ion-implanted impurities cannot avoid re-evaporation during epitaxial growth. The epitaxial growth system is specifically composed of a temperature rising process, a hydrogen annealing, an epitaxial growth, and a cooling process, but re-evaporation of impurities is considered to occur due to the above-described heating process and heat during hydrogen annealing. The re-evaporated impurities cause a phenomenon of mixing into a semiconductor substrate and a film grown in epitaxial growth, which is called an automatic doping phenomenon. In the epitaxial growth process, if there is temperature variation in the wafer and between wafers, according to the re-evaporation and automatic doping phenomenon as described above, in the parallel pn region, even if, for example, ions are implanted with the same dose, the charge is not generated. Balance and pressure variation become large, which is the reason for the low pressure-resistant yield.
本發明是有鑑於前述要點所完成者。本發明的目的為提供一種降低n型管柱與p型管柱的電荷平衡不均、耐壓良品率高的超接合半導體裝置之製造方法。The present invention has been accomplished in view of the foregoing points. An object of the present invention is to provide a method of manufacturing a super-junction semiconductor device which reduces charge balance unevenness of an n-type column and a p-type column and has a high withstand voltage yield.
在本發明中，為了達成前述發明目的，作為一種超接合半導體裝置之製造方法，係於高濃度之第1導電型半導體基板上，藉由重複多次並堆疊磊晶成長與第1導電型雜質及第2導電型雜質的離子植入，形成超接合構造部作為漂移層，其中該超接合構造部由具有在垂直於上述半導體基板的主表面的方向上較長之形狀，且在平行於主表面的方向交替相鄰配置的第1導電型區域與第2導電型區域組成；其在於：藉由加速能量分別於上述第1導電型區域及第2導電型區域進行離子植入，使得各區域所植入之總雜質量相等，並且使得離子植入剛結束時之深度方向之雜質濃度峰值位置於上述第1導電型區域與第2導電型區域幾乎一致。又，前述剛植入離子後的雜質濃度峰值位置比0.2μm深者亦為佳。In the present invention, in order to achieve the above object, a method of manufacturing a super-junction semiconductor device is performed by repeatedly epitaxially growing epitaxial growth and first conductivity type impurities by repeating a plurality of times on a high-concentration first conductivity type semiconductor substrate. And ion implantation of the second conductivity type impurity, forming a super junction structure portion having a shape elongated in a direction perpendicular to a main surface of the semiconductor substrate, and being parallel to the main The first conductive type region and the second conductive type region which are alternately arranged in the direction of the surface are formed by ion implantation by the acceleration energy in the first conductive type region and the second conductive type region, respectively. The total impurity amount implanted is equal, and the impurity concentration peak position in the depth direction immediately after the ion implantation is almost coincident with the first conductivity type region and the second conductivity type region. Further, it is also preferable that the peak position of the impurity concentration immediately after the implantation of ions is deeper than 0.2 μm.
又，在本發明中，為了達成前述發明的目的，作為一種超接合半導體裝置之製造方法，係於高濃度之第1導電型半導體基板上，藉由重複多次並堆疊磊晶成長與第1導電型雜質以及第2導電型雜質之離子植入，形成超接合構造部作為漂移層，其中該超接合構造部由具有在垂直於上述半導體基板的主表面的方向上較長之形狀，且在平行於主表面的方向交替相鄰配置的第1導電型區域與第2導電型區域組成；其在於：藉由磊晶成長形成上述第1導電型區域時，將上述磊晶成長前的氫退火溫度與磊晶成長的開始溫度設為低於1100℃。Further, in the present invention, in order to achieve the object of the above invention, a method of manufacturing a super-bonded semiconductor device is performed on a first-conductivity-type semiconductor substrate having a high concentration by repeating a plurality of epitaxial growths and a first The ion implantation of the conductive type impurity and the second conductivity type impurity forms a super junction structure portion as a drift layer, wherein the super junction structure portion has a shape that is long in a direction perpendicular to a main surface of the semiconductor substrate, and The first conductive type region and the second conductive type region which are alternately arranged adjacent to each other in a direction parallel to the main surface; wherein when the first conductive type region is formed by epitaxial growth, the hydrogen annealing before the epitaxial growth is performed The temperature and the starting temperature of the epitaxial growth were set to be lower than 1100 °C.
又更進一步地，在本發明中，為了達成前述發明的目的，作為一種超接合半導體裝置之製造方法，係於高濃度之第1導電型半導體基板上，藉由重複多次並堆疊磊晶成長與第1導電型雜質以及第2導電型雜質的離子植入，形成超接合構造部作為漂移層，其中該超接合構造部由具有在垂直於上述半導體基板的主表面的方向上較長之形狀，且在平行於主表面的方向為交替相鄰配置的第1導電型區域與第2導電型區域組成；其在於：藉由磊晶成長形成上述第1導電型區域時，作為上述磊晶成長前之前處理，於進行使用過氧化氫水與氨水之基板清洗處理以及稀釋氟酸處理之後，將磊晶成長的開始溫度設為950℃以下Further, in the present invention, in order to achieve the object of the invention, a method for manufacturing a super-junction semiconductor device is performed by repeating epitaxial growth by repeating a plurality of times on a first-conductivity-type semiconductor substrate having a high concentration. The ion implantation of the first conductivity type impurity and the second conductivity type impurity forms a super junction structure portion having a shape elongated in a direction perpendicular to a main surface of the semiconductor substrate as a drift layer And the first conductive type region and the second conductive type region which are alternately arranged adjacent to each other in a direction parallel to the main surface; wherein when the first conductive type region is formed by epitaxial growth, the epitaxial growth is performed Before the previous treatment, after the substrate cleaning treatment using hydrogen peroxide water and ammonia water and the diluted hydrofluoric acid treatment, the starting temperature of the epitaxial growth is set to 950 ° C or less.
根據本發明，可以降低構成超接合構造部之n型管柱與p型管柱的電荷平衡不均、可以作為耐壓良品率高的超接合半導體裝置之製造方法。According to the present invention, it is possible to reduce the charge balance unevenness of the n-type column and the p-type column constituting the super-junction structure portion, and to manufacture a super-bonding semiconductor device having a high withstand voltage yield.
以下，有關於本發明之超接合半導體裝置之製造方法的實施例，參閱圖面詳細說明之。本發明只要不超過其主旨，就不受限於以下所說明的實施例中之記載。以下所說明的實施例中，將第1導電型作為n型、第2導電型作為p型來進行說明。Hereinafter, an embodiment of a method of manufacturing a super-bonded semiconductor device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the embodiments described below as long as it does not exceed the gist of the invention. In the examples described below, the first conductivity type will be described as an n-type and a second conductivity type as a p-type.
其次，有關於本發明之超接合半導體裝置之製造方法，尤其是超接合構造部之製作方法，參閱圖面說明之。圖1為以跟本發明有關的實施例1、2、3來進行說明之超接合半導體裝置之製造方法之超接合構造部的剖面模式圖。圖7為跟本發明的實施例1、2、3有關的超接合MOSFET之要部剖面模式圖。圖8為跟本發明的實施例1、2、3有關的超接合MOSFET的元件活化部之模式剖面立體圖。Next, a method of manufacturing the super-bonded semiconductor device of the present invention, in particular, a method of fabricating the super-bonded structure portion will be described with reference to the drawings. Fig. 1 is a cross-sectional schematic view showing a super-junction structure portion of a method of manufacturing a super-junction semiconductor device according to the first, second, and third embodiments of the present invention. Fig. 7 is a schematic cross-sectional view showing the principal part of the super-junction MOSFET according to the first, second, and third embodiments of the present invention. Fig. 8 is a schematic cross-sectional perspective view showing the element activating portion of the super junction MOSFET according to the first, second, and third embodiments of the present invention.
有關本發明的超接合半導體裝置係作成具備有如圖7所示之在n+ 矽基板1以及n- 層2上交替配置有n型管柱4以及p型管柱5之超接合構造部10之構成。更進一步，與通常的MOSFET同樣地，於元件活化部100內，具有p基極區域13、n射極區域14、閘極絕緣膜15、閘極電極16、射極電極17；於周邊耐壓構造部200內，具有保護環7、場絕緣膜8、通道截斷區域11、通道截斷電極12。又更進一步，於超接合半導體裝置之周邊耐壓構造部200內的超接合構造部10的上層，設置有低濃度n- 磊晶層3。The super junction semiconductor device according to the present invention is provided with a super junction structure portion 10 in which an n-type pillar 4 and a p-type pillar 5 are alternately arranged on the n + tantalum substrate 1 and the n - layer 2 as shown in FIG. Composition. Further, similarly to the normal MOSFET, the element active portion 100 includes the p base region 13, the n emitter region 14, the gate insulating film 15, the gate electrode 16, and the emitter electrode 17; The structure portion 200 has a guard ring 7, a field insulating film 8, a channel cut-off region 11, and a channel shutoff electrode 12. Further, a low-concentration n - epitaxial layer 3 is provided on the upper layer of the super-junction structure portion 10 in the peripheral pressure-resistant structure portion 200 of the super-bonded semiconductor device.
圖2至圖4為表示有於圖1所示之超接合半導體裝置之超接合構造部之製造工程在各階段中的半導體基板之主要部位剖面模式圖。如圖2所示，在n+ 矽基板1上藉由摻雜磊晶生長以例如12μm左右的厚度來形成n- 層2，於其上藉由磊晶生長以例如3μm的厚度形成非摻雜層3a後，以光蝕刻工程，形成每段的疊合時所需要的對準標記物(alignment marker)(未圖式)。2 to 4 are schematic cross-sectional views showing main parts of a semiconductor substrate in each stage of the manufacturing process of the super junction structure portion of the super junction semiconductor device shown in Fig. 1. As shown in FIG. 2, an n - layer 2 is formed on the n + germanium substrate 1 by doping epitaxial growth with a thickness of, for example, about 12 μm, on which an undoped layer is formed by epitaxial growth to a thickness of, for example, 3 μm. After layer 3a, an alignment marker (not shown) required for the superposition of each segment is formed by photolithography.
如圖3所示，對於n型雜質4a，例如將磷予以離子植入到整個面，對於p型雜質5a，則例如將硼予以離子植入到用光阻遮罩6做選擇性遮罩的開口部。此時，考慮到後面的熱擴散工程，光阻遮罩6之開口寬設為殘留寬之1/4左右，與其相對應地，硼離子之植入量(劑量)設為磷的4倍左右。之後，如圖4所示，藉由磊晶生長，而以例如7μm的厚度形成非摻雜層3b。再次與上述同樣地進行n型雜質4a以及p型雜質5a的離子植入。之後，直到形成與設計耐壓所期望之厚度為止，重複進行如此這些磊晶成長和離子植入。最後，例如以5μm左右之厚度之非摻雜層進行披覆後，利用熱處理進行雜質的熱擴散，形成如圖1所示之超接合構造部10。在此，形成n型管柱4以及p型管柱5之際的離子植入時，控制離子植入之硼及磷的再蒸發量，而保持n型管柱4以及p型管柱5間之電荷平衡，乃是在確保由超接合構造部10所引起的變異較小之耐壓特性上，是為重要的。悉知的是，n型管柱4及p型管柱5間的離子植入之雜質量，即使設定成與離子植入時相同劑量，結果亦會經常產生變異。As shown in FIG. 3, for the n-type impurity 4a, for example, phosphorus is ion-implanted to the entire surface, and for the p-type impurity 5a, for example, boron is ion-implanted into the selective mask with the photoresist mask 6. Opening. At this time, in consideration of the subsequent thermal diffusion process, the opening width of the photoresist mask 6 is set to about 1/4 of the residual width, and correspondingly, the implantation amount (dose) of boron ions is set to about 4 times that of phosphorus. . Thereafter, as shown in FIG. 4, the undoped layer 3b is formed with a thickness of, for example, 7 μm by epitaxial growth. The ion implantation of the n-type impurity 4a and the p-type impurity 5a is performed again in the same manner as described above. Thereafter, such epitaxial growth and ion implantation are repeated until the desired thickness is formed and designed. Finally, for example, after coating with an undoped layer having a thickness of about 5 μm, heat diffusion of impurities is performed by heat treatment to form a super-bonding structure portion 10 as shown in FIG. 1 . Here, when ion implantation is performed on the n-type column 4 and the p-type column 5, the amount of re-evaporation of boron and phosphorus in the ion implantation is controlled, and the n-type column 4 and the p-type column 5 are maintained. The charge balance is important in ensuring the withstand voltage characteristics in which the variation caused by the super-joining structure portion 10 is small. It is known that the impurity quality of ion implantation between the n-type column 4 and the p-type column 5 is often mutated even if it is set to the same dose as that during ion implantation.
在此，考慮到前述變異的原因之一係存在離子植入的雜質之蒸發的話，使硼與磷的離子植入時的加速能量變化並且改變離子植入的射程Rp，亦即，測定改變離子植入的植入深度時的再蒸發量。其結果如圖5所示。由圖5可知，射程Rp若相同，亦即，若深度方向的雜質濃度峰值位置相同的話，就硼和磷而言相對於劑量的再蒸發量相同。若p型雜質5a與n型雜質4a的蒸發量相同的話，則即使有蒸發，亦可保持電荷平衡。此外，在圖6，進一步表示雜質濃度峰值位置位於比自基板表面更深0.2μm之情形時，可抑制上述蒸發之變異。因此，深度方向之雜質濃度峰值位置，比自基板表面更深0.2μm者為佳。Here, considering one of the reasons for the aforementioned variation is the evaporation of impurities implanted by ions, the acceleration energy of the implantation of boron and phosphorus ions changes and the range of ion implantation Rp is changed, that is, the change ion is determined. The amount of re-evaporation at the implant depth of implantation. The result is shown in Fig. 5. As can be seen from Fig. 5, if the range Rp is the same, that is, if the peak position of the impurity concentration in the depth direction is the same, the amount of re-evaporation with respect to the dose is the same for boron and phosphorus. When the evaporation amount of the p-type impurity 5a and the n-type impurity 4a is the same, the charge balance can be maintained even if there is evaporation. Further, in Fig. 6, it is further shown that when the peak position of the impurity concentration is located 0.2 μm deeper than the surface of the substrate, the above-described variation in evaporation can be suppressed. Therefore, the peak position of the impurity concentration in the depth direction is preferably 0.2 μm deeper than the surface of the substrate.
作為有關於本發明的超接合半導體裝置之製造方法之實施的型態之一，作為用於形成超接合構造部之製程條件，乃是將磷以200keV、將硼以80keV的加速能量的離子植入條件來進行，此時的離子植入後的射程Rp(峰值深)為約0.25μm。此結果可知的是，可以抑制前述超接合構造部之並列pn區域的再蒸發量，更進一步可以使硼與磷的再蒸發量相同，可以降低並列pn區域間的電荷不平衡引起之耐壓變異。As one of the types of implementations of the method for fabricating the super-junction semiconductor device of the present invention, as a process condition for forming the super-junction structure portion, ion implantation of phosphorus at a rate of 80 keV with an acceleration energy of 80 keV is used. The conditions were carried out, and the range Rp (peak depth) after ion implantation at this time was about 0.25 μm. As a result, it is understood that the amount of re-evaporation of the parallel pn region of the super-junction structure portion can be suppressed, and the re-evaporation amount of boron and phosphorus can be made the same, and the withstand voltage variation caused by the charge imbalance between the parallel pn regions can be reduced. .
說明有關於實施例2之超接合半導體裝置的超接合構造部之製造方法。在實施例2，其特徵在於，針對如前述圖1～圖4中所示之對n+ Si基板上的磊晶層的形成，將作為前處理之氫退火溫度(1000℃下2分鐘的氫退火)與磊晶成長溫度，以低於1100℃的溫度來進行。但是，在此製作方法的情況下，僅使溫度降低時，擔心有由於前處理溫度較低，不能對矽表面進行充分的淨化，因為成長溫度也比較低，故結晶性下降。其結果，由於結晶性下降引起之對準標記物的形狀崩壞，導致圖案對準不正確，產生難以將形成超接合構造部之磊晶層進行正確重疊之問題。為此，在實施例2中，在增加不發生前述問題之製造條件的基礎上製作超接合構造部。以下，說明有關於這樣的超接合構造部之製造條件。A method of manufacturing the super junction structure portion of the super junction semiconductor device of the second embodiment will be described. In the second embodiment, for the formation of the epitaxial layer on the n + Si substrate as shown in the foregoing FIGS. 1 to 4, the hydrogen annealing temperature (the hydrogen at 1000 ° C for 2 minutes) is used as the pretreatment. Annealing) and epitaxial growth temperature are carried out at temperatures below 1100 °C. However, in the case of this production method, when the temperature is lowered only, there is a fear that the surface of the crucible cannot be sufficiently purified because the pretreatment temperature is low, and the growth temperature is also low, so that the crystallinity is lowered. As a result, the shape of the alignment mark collapses due to a decrease in crystallinity, resulting in an incorrect alignment of the pattern, which causes a problem that it is difficult to accurately overlap the epitaxial layers forming the super-junction structure portion. For this reason, in the second embodiment, the super-joining structure portion was produced in addition to the manufacturing conditions in which the above problems were not caused. Hereinafter, the manufacturing conditions of such a super-joining structure portion will be described.
作為在前述n+ Si基板上使磊晶層成長之前處理，係進行氫退火處理，但在其稍早之前，使用在過氧化氫液中添加氨水之混合液，即RCA清洗。其理由為，藉由剛在n+ Si基板的表面上形成了化學氧化之後，立即進行氫退火處理，即使溫度較低，亦容易獲得矽清洗表面。根據該表面清洗化方法，可形成結晶性良好之磊晶成長。又更進一步，磊晶成長亦藉由低於1100℃之低溫下進行，而易於抑制自Si基板向外面擴散並且抑制自動摻雜。但是，若全面進行於所謂低於前述1100℃之低溫下的磊晶成長，則存在對準標記物的形狀崩壞增大之問題，所以在前述低溫下的磊晶成長停留於可抑制自動摻雜所必要之最低厚度的磊晶成長。之後，實行升溫到可抑制對準標記物的形狀崩壞之1100℃以上，而進行磊晶成長至所需厚度為止之方法。利用這樣的超接合構造部之製作方法，因為可以於超接合構造部的磊晶成長時抑制自動摻雜，所以即使為低於1100℃之低溫，亦可以製作出由結晶性較好的並列pn區域所組成的超接合構造部，而可以以較高的耐壓良品率來製造超接合半導體裝置。The hydrogen annealing treatment was performed before the epitaxial layer was grown on the n + Si substrate. However, a mixture of ammonia water added to the hydrogen peroxide solution, that is, RCA cleaning, was used a little earlier. The reason for this is that immediately after the chemical oxidation is formed on the surface of the n + Si substrate, the hydrogen annealing treatment is performed, and even if the temperature is low, the ruthenium cleaning surface is easily obtained. According to this surface cleaning method, epitaxial growth with good crystallinity can be formed. Further, epitaxial growth is also performed at a low temperature of less than 1,100 ° C, and it is easy to suppress diffusion from the Si substrate to the outside and suppress automatic doping. However, if the epitaxial growth at a low temperature lower than the above-described 1100 ° C is carried out in an all-round manner, there is a problem that the shape of the alignment mark collapses, so that the epitaxial growth at the low temperature is stopped to suppress the automatic doping. The minimum thickness of epitaxial growth necessary for miscellaneous materials. Thereafter, the temperature is raised to 1100 ° C or more which can suppress the collapse of the shape of the alignment mark, and the method of epitaxial growth to the desired thickness is performed. According to the method for producing the super-junction structure portion, since the auto-doping can be suppressed during the epitaxial growth of the super-junction structure portion, even if the temperature is lower than 1,100 ° C, a parallel pn having better crystallinity can be produced. The super junction structure portion composed of the regions can be used to manufacture the super junction semiconductor device at a high withstand voltage yield.
說明有關於實施例3之超接合半導體裝置的超接合構造部之製造方法。在實施例3方面，是為一種製造方法，其特徵在於，針對如前述圖1～圖4中所示之對n+ Si基板上的磊晶層的形成，將作為前處理之氫退火溫度與磊晶成長溫度，以低於1000℃的溫度來進行。A method of manufacturing the super junction structure portion of the super junction semiconductor device of the third embodiment will be described. In the third embodiment, it is a manufacturing method characterized in that, for the formation of the epitaxial layer on the n + Si substrate as shown in the foregoing FIGS. 1 to 4, the hydrogen annealing temperature as the pretreatment is The epitaxial growth temperature is carried out at a temperature lower than 1000 °C.
於無氫退火處理之情形下，亦可以以低於1000℃以下的溫度來進行磊晶成長。此情況為，用以磊晶成長的950℃為止之升溫過程中將矽表面的淨化功能利用作為磊晶成長的前處理之方法。但是，無法充分淨化矽表面，與前述實施例2同樣地，擔心有結晶性下降之情事。其結果，由於結晶性下降引起之對準標記物的形狀崩壞，導致圖案對準不正確，產生難以將形成超接合構造部之磊晶層進行正確重疊的問題。為此，在實施例3中，在更增加不發生前述問題之製造條件的基礎上製作超接合構造部。以下，說明有關於這樣的超接合構造部之製造條件。In the case of no hydrogen annealing treatment, epitaxial growth can also be performed at a temperature lower than 1000 ° C. In this case, the purification function of the surface of the crucible is used as a pretreatment method for epitaxial growth during the temperature rise process at 950 ° C for epitaxial growth. However, the surface of the crucible cannot be sufficiently purified, and similarly to the above-described second embodiment, there is a concern that crystallinity is lowered. As a result, the shape of the alignment mark collapses due to a decrease in crystallinity, resulting in an incorrect pattern alignment, which causes a problem that it is difficult to accurately overlap the epitaxial layers forming the super-junction structure portion. For this reason, in the third embodiment, the super-joining structure portion is produced in addition to the manufacturing conditions in which the above-described problem does not occur. Hereinafter, the manufacturing conditions of such a super-joining structure portion will be described.
作為在前述n+ 矽基板1上使磊晶層成長之前處理，係不進行氫退火處理，而在前述的RCA清洗中進一步加上稀釋氟酸處理。藉由該稀釋氟酸處理，而於將Si基板表面進行氫端鍵結的狀態下進行磊晶成長。磊晶成長係於950℃以下的溫度來進行。n+ 矽基板1表面，係於升溫至950℃以下之特定溫度為止之際，氫脫離而可獲得清潔的矽表面。由此，即使於950℃以下的低溫，亦可成為結晶性良好的磊晶成長。磊晶成長亦藉由在前述那樣的低溫下來進行，而易於抑制自Si基板向外面擴散並且抑制自動摻雜。但是，也與實施例2同樣地在實施例3中，因為對準標記物的形狀崩壞變大，所以首先以950℃進行前述低溫下可抑制自動摻雜所必要的最低厚度之磊晶成長。之後，實行升溫到可抑制對準標記物的形狀崩壞之1100℃以上，而進行磊晶成長至所需厚度為止之方法。As the treatment before the epitaxial layer is grown on the n + germanium substrate 1, the hydrogen annealing treatment is not performed, and the diluted hydrofluoric acid treatment is further added to the above RCA cleaning. Epitaxial growth is carried out in a state in which the surface of the Si substrate is hydrogen-bonded by the diluted hydrofluoric acid treatment. The epitaxial growth is carried out at a temperature of 950 ° C or lower. On the surface of the n +矽 substrate 1, when the temperature is raised to a specific temperature of 950 ° C or lower, hydrogen is removed to obtain a clean tantalum surface. Therefore, even at a low temperature of 950 ° C or lower, epitaxial growth with good crystallinity can be obtained. The epitaxial growth is also carried out at a low temperature as described above, and it is easy to suppress diffusion from the Si substrate to the outside and suppress automatic doping. However, in the same manner as in the second embodiment, since the shape of the alignment mark is broken, the epitaxial growth of the minimum thickness necessary for suppressing the automatic doping at the low temperature is first performed at 950 ° C. . Thereafter, the temperature is raised to 1100 ° C or more which can suppress the collapse of the shape of the alignment mark, and the method of epitaxial growth to the desired thickness is performed.
根據實施例3，可以藉由在低溫下對磊晶成長的表面進行清洗，來改善低溫磊晶成長之結晶性。為了抑制自動摻雜而在低溫下進行磊晶成長。但是，膜厚係防止自動摻雜之最低限的厚度(例如，1μm左右)。藉此，可抑制標記物的形狀崩壞。之後進行升溫，以1100℃且以結晶性良好的條件進行磊晶成長至目的之特定厚度為止。藉此，可以一邊抑制自動摻雜，一邊於不使結晶性惡化之情況下抑制對準標記物之形狀崩壞。以抑制自動摻雜的方式，而可以控制由高精度的並列pn區域所組成的超接合構造部之雜質濃度，並且可以保持並列pn區域之電荷平衡，所以可以實現因提高超接合半導體裝置之耐壓良品率等所致的低成本化。According to the third embodiment, the crystallinity of the low-temperature epitaxial growth can be improved by washing the epitaxially grown surface at a low temperature. Epitaxial growth is performed at a low temperature in order to suppress autodoping. However, the film thickness prevents the minimum thickness of the automatic doping (for example, about 1 μm). Thereby, the shape collapse of the marker can be suppressed. Thereafter, the temperature was raised, and epitaxial growth was carried out at a temperature of 1100 ° C under conditions of good crystallinity to a specific thickness for the purpose. Thereby, it is possible to suppress the collapse of the shape of the alignment mark without deteriorating the crystallinity while suppressing the automatic doping. By suppressing the automatic doping, the impurity concentration of the super junction structure portion composed of the high-precision parallel pn region can be controlled, and the charge balance of the parallel pn region can be maintained, so that the resistance of the super junction semiconductor device can be improved. Reduce the cost of good products and other factors.
1‧‧‧n+ 矽基板1‧‧‧n +矽 substrate
2‧‧‧n- 層2‧‧‧n - layer
3‧‧‧低濃度n- 磊晶層3‧‧‧Low concentration n - plated layer
4‧‧‧n型管柱4‧‧‧n type tubular string
4a‧‧‧n型雜質4a‧‧‧n type impurity
5‧‧‧p型管柱5‧‧‧p-type column
5a‧‧‧p型雜質5a‧‧‧p type impurity
6‧‧‧光阻遮罩6‧‧‧Light-shielding mask
10‧‧‧超接合構造部10‧‧‧Super Joint Construction Department
100‧‧‧元件活化部100‧‧‧Component Activation Department
200‧‧‧周邊耐壓構造部200‧‧‧Peripheral pressure structure
[圖1]有關於本發明的超接合半導體裝置之製造方法之超接合構造部的剖面模式圖。Fig. 1 is a cross-sectional schematic view showing a super junction structure portion of a method of manufacturing a super junction semiconductor device according to the present invention.
[圖2]表示有關本發明的超接合半導體裝置之製造方法之製造工程之半導體基板的要部剖面圖(其1)。FIG. 2 is a cross-sectional view (1) of a principal part of a semiconductor substrate showing a manufacturing process of a method of manufacturing a super-bonded semiconductor device according to the present invention.
[圖3]表示有關本發明的超接合半導體裝置之製造方法之製造工程之半導體基板的要部剖面圖(其2)。3 is a cross-sectional view (2) of a principal part of a semiconductor substrate showing a manufacturing process of a method of manufacturing a super-bonded semiconductor device according to the present invention.
[圖4]表示有關本發明的超接合半導體裝置之製造方法之製造工程之半導體基板的要部剖面圖(其3)。4 is a cross-sectional view (3) of a principal part of a semiconductor substrate showing a manufacturing process of a method of manufacturing a super-bonded semiconductor device according to the present invention.
[圖5]表示硼和磷的再蒸發量的雜質濃度峰值深度依賴性之關係圖。Fig. 5 is a graph showing the relationship between the peak depth dependence of the impurity concentration of the re-evaporation amount of boron and phosphorus.
[圖6]相對於雜質濃度峰值深度之再蒸發比例與變異間之關係圖。[Fig. 6] A graph showing the relationship between the re-evaporation ratio and the variation with respect to the peak depth of the impurity concentration.
[圖7]有關本發明之超接合MOSFET之要部剖面圖。Fig. 7 is a cross-sectional view of an essential part of a super junction MOSFET according to the present invention.
[圖8]有關本發明之超接合MOSFET的元件活化部之模式剖面立體圖。Fig. 8 is a schematic cross-sectional perspective view showing an element activating portion of the super junction MOSFET of the present invention.
1．．．n+ 矽基板1. . . n + germanium substrate
2．．．n- 層2. . . n - layer
4．．．n型管柱4. . . N-type column
5．．．p型管柱5. . . P-type column
10．．．超接合構造部10. . . Super joint structure
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| US9842911B2 (en) | 2012-05-30 | 2017-12-12 | Vishay-Siliconix | Adaptive charge balanced edge termination |
| US9105717B2 (en) * | 2013-12-04 | 2015-08-11 | Infineon Technologies Austria Ag | Manufacturing a semiconductor device using electrochemical etching, semiconductor device and super junction semiconductor device |
| US9887259B2 (en) | 2014-06-23 | 2018-02-06 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
| CN105900245B (en) * | 2014-07-04 | 2019-08-06 | 富士电机株式会社 | Semiconductor device |
| JP6375743B2 (en) | 2014-07-15 | 2018-08-22 | 富士電機株式会社 | Manufacturing method of semiconductor device |
| EP3183754A4 (en) | 2014-08-19 | 2018-05-02 | Vishay-Siliconix | Super-junction metal oxide semiconductor field effect transistor |
| JP6477174B2 (en) | 2015-04-02 | 2019-03-06 | 富士電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| US9881997B2 (en) | 2015-04-02 | 2018-01-30 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method of semiconductor device |
| JP6824115B2 (en) | 2017-06-19 | 2021-02-03 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor devices |
| US10636660B2 (en) | 2018-09-28 | 2020-04-28 | General Electric Company | Super-junction semiconductor device fabrication |
| TWI787819B (en) * | 2021-05-14 | 2022-12-21 | 國立臺灣大學 | Three-dimensional superjunction power semiconductor with concentration variation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20010032998A1 (en) * | 2000-03-17 | 2001-10-25 | Susumu Iwamoto | Super-junction semiconductor device and method of manufacturing the same |
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| JP3714509B2 (en) * | 1997-09-29 | 2005-11-09 | 株式会社Ｓｕｍｃｏ | Method for manufacturing thin film epitaxial wafer |
| JP4927401B2 (en) * | 1998-11-12 | 2012-05-09 | 富士電機株式会社 | Super junction semiconductor device |
| JP2001119022A (en) * | 1999-10-20 | 2001-04-27 | Fuji Electric Co Ltd | Semiconductor device and manufacturing method therefor |
| JP4016371B2 (en) * | 1999-11-10 | 2007-12-05 | 信越半導体株式会社 | Manufacturing method of silicon epitaxial wafer |
| JP2002008994A (en) * | 2000-06-22 | 2002-01-11 | Ulvac Japan Ltd | Manufacturing method for thin film |
| EP1267415A3 (en) * | 2001-06-11 | 2009-04-15 | Kabushiki Kaisha Toshiba | Power semiconductor device having resurf layer |
| WO2005001916A1 (en) * | 2003-06-26 | 2005-01-06 | Shin-Etsu Handotai Co., Ltd. | Method for producing silicon epitaxial wafer and silicon epitaxial wafer |
| JP2007012858A (en) * | 2005-06-30 | 2007-01-18 | Toshiba Corp | Semiconductor element and its manufacturing method |
| JP4564510B2 (en) * | 2007-04-05 | 2010-10-20 | 株式会社東芝 | Power semiconductor device |
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| US20010032998A1 (en) * | 2000-03-17 | 2001-10-25 | Susumu Iwamoto | Super-junction semiconductor device and method of manufacturing the same |
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| TW201145361A (en) | 2011-12-16 |
| JP2011192824A (en) | 2011-09-29 |
| CN102194701A (en) | 2011-09-21 |
| CN102194701B (en) | 2014-03-26 |
| JP5985789B2 (en) | 2016-09-06 |
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