JP5757355B2 - Manufacturing method of super junction semiconductor device - Google Patents

Description

  The present invention provides a super junction structure portion in which a plurality of n-type columns and p-type columns arranged alternately in the direction perpendicular to the main surface of the semiconductor substrate as the drift layer are alternately adjacent to each other in the parallel direction to the main surface. The present invention relates to a method for manufacturing a junction semiconductor device.

  Generally, a semiconductor device (hereinafter also referred to as a semiconductor element or simply an element) is divided into a horizontal element having an electrode on one side of a semiconductor substrate and a vertical semiconductor device (vertical element) having electrodes on both sides of the semiconductor substrate. Broadly divided. In the vertical element, the direction in which the drift current flows when turned on is the same as the direction in which the depletion layer extends due to the reverse bias voltage when turned off. For example, in the case of a normal planar type n-channel vertical MOSFET, the portion of the high resistance n-drift layer functions as a region for flowing a drift current in the vertical direction when the MOSFET is in the on state, and is depleted in the off state. To increase pressure resistance. Shortening the current path of the high-resistance n-drift layer lowers the drift resistance, leading to an effect of lowering the substantial on-resistance of the MOSFET, but conversely, between the p base region and the n-drift region. The width of the depletion layer between the drain and base proceeding from the pn junction is narrow and the critical electric field strength of silicon is reached quickly, so that the breakdown voltage is lowered. On the other hand, in an element with a high breakdown voltage, the n- drift layer is thick, so the on-resistance is inevitably increased and the loss is increased. Such a relationship between on-resistance and breakdown voltage is called a trade-off relationship. It is known that this trade-off relationship is similarly established in semiconductor elements such as IGBTs, bipolar transistors, and diodes. This relationship is also common to lateral semiconductor elements in which the direction in which the drift current flows when on and the direction in which the depletion layer extends due to the reverse bias when off is different.

  As a solution to this problem, as shown in FIGS. 7 and 8, the drift layer has a layered or columnar shape in a direction perpendicular to the main surface of the semiconductor substrate, and has an impurity concentration higher than that of a normal drift layer. A plurality of elevated n-type drift regions (n-type columns) 4 and p-type partition regions (p-type columns) 5 are used, and the superstructures are formed of parallel pn regions that are alternately and repeatedly adjacent to each other in the parallel direction to the main surface. A superjunction semiconductor device (superjunction MOSFET) having a junction structure 10 is known. This superjunction semiconductor device has the function of a drift layer in which the superjunction structure 10 is depleted and bears a withstand voltage when in an off state.

  The major difference in structure between the superjunction MOSFET and the normal planar type n-channel vertical MOSFET is that the drift layer is not a single conductivity type layer having a uniform impurity concentration, but a parallel pn as described above. That is, the superjunction structure portion 10 is made of a region. In this superjunction structure portion 10, the impurity concentrations (hereinafter sometimes simply referred to as concentrations) of the p-type partition region (p-type column) 5 and the n-type drift region (n-type column) 4 are the same. Even if it is higher than the normal element of the breakdown voltage class, in the off state, the depletion layer spreads on both sides from the parallel pn junction in the superjunction structure 10, and the entire drift layer is depleted with low electric field strength. Can be planned.

In the peripheral withstand voltage structure portion 200 of the superjunction MOSFET including the super junction structure portion 10 composed of the parallel pn regions shown in FIG. 7, the substrate surface side (upper layer) of the super junction structure portion 10 in the peripheral withstand voltage structure portion 200 is one. A configuration is required in which the low-concentration n-epitaxial layer 3 having such an impurity concentration is disposed. Further, the peripheral breakdown voltage structure 200 of the superjunction semiconductor device has a p-type guard ring 7 along the substrate surface on the surface of the low-concentration n-epitaxial layer 3 provided on the superjunction structure 10. A plurality are provided so as to be separated at a required interval according to the design withstand voltage. Furthermore, the peripheral pressure-resistant structure portion 200 includes the surface of the p-type guard ring 7 and the outermost peripheral p.
A conductive plate 9 electrically connected to the surface of the mold guard ring 7a is provided. Further, a conductive plate 12 that is electrically connected to the p-type channel stopper region 11 (or may be an n-type channel stopper region) is also provided.

  On the other hand, in the element active part 100 of the superjunction semiconductor device, n is formed on the upper layer of the superjunction structure part 10 composed of parallel pn regions and on the p base region 13 and the surface layer in the p base region 13 in the same manner as in a normal semiconductor device. An emitter region 14 is provided, and a gate electrode 16 is provided on the surface of the p base region 13 sandwiched between the n emitter region 14 and the n drift region (n-type column) 4 via a gate insulating film 15. An emitter electrode 17 is provided in contact with the high concentration surface of the p base region 13.

  As a method for manufacturing such a superjunction structure 10, the thin parallel pn regions formed one by one by epitaxial growth and ion implantation are stacked one after another by repeating epitaxial growth and ion implantation many times. A method of making the shape long in the vertical direction (multi-stage epitaxial method) is well known.

  An example of the manufacturing process of the superjunction structure by the multistage epitaxial method will be described. In the epitaxial growth and ion implantation, a low concentration n− epitaxial layer 2 having a thickness of 12 μm is formed on a high concentration n + Si substrate 1, and an alignment marker (not shown) for mask alignment is formed. After forming a screen oxide film (not shown) having a thickness of 25 nm, phosphorus ions are implanted into the entire surface with an acceleration energy of 100 keV at a dose of 1 × 10 12 cm −2 to 9 × 10 12 cm −2. After the photolithography process, boron ions are selectively implanted so as to have the same total impurity amount as phosphorus ions. After removing the resist and the oxide film, after hydrogen annealing, a non-doped epitaxial layer is formed. After that, the above-described phosphorus and boron ion implantation steps are repeated to obtain a superjunction structure portion 10 composed of a parallel pn region having a required thickness.

  For example, in a superjunction semiconductor device including the superjunction structure unit 10 manufactured in the above-described manufacturing process, the charge balance between the n-type column 4 and the p-type column 5 is important and is preferably the same. In addition, in order to form the peripheral withstand voltage structure 200 having the above-mentioned charge resistance, after forming a superjunction structure composed of parallel pn regions by multiple times of epitaxial layer formation and ion implantation by a multistage epitaxial method, The low-concentration n-epitaxial layer 3 is formed on the upper layer of the junction structure and formed. In other words, the low-concentration n-epitaxial layer 3 forms an upper layer of the superjunction structure portion by ion implantation in the element active portion, but the peripheral breakdown voltage structure portion 200 is low without ion implantation. It is fabricated by leaving the concentration n − epitaxial layer 3 as it is. Since the thickness of the low-concentration n− epitaxial layer 3 is required to be about 15 μm or more, if the thickness of one epitaxial growth is set to 10 μm or less, the required number of steps (number of epitaxial growths) is two or more.

  In the manufacturing process of the superjunction structure described above, a superjunction structure composed of parallel pn regions is fabricated by ion implantation of phosphorus and boron, but a superjunction structure similar to that described above is fabricated only by ion implantation of boron. The manufacturing method is already known (Patent Document 1).

  Also disclosed is a method of manufacturing a superjunction semiconductor device that improves the manufacturing efficiency by reducing the number of repetitions of epitaxial growth and ion implantation by changing the ion implantation range Rp to produce a superjunction structure portion ( Patent Document 2).

Further, literature on a vapor phase epitaxial growth method for forming an impurity-added region having a shape that is long in the depth direction as in the above-described superjunction structure is disclosed. In this document, “a vapor phase growth process is performed by first vapor-depositing a thin epitaxial silicon layer for sealing in order to suppress lateral autodoping from a boron implantation layer and a phosphorus implantation layer, and then a second epitaxial layer. As described above, it is desirable to use a multi-stage process in which the main growth is performed. ”A method of processing the source gas of the epitaxial silicon layer first is disclosed (Patent Document 3).

JP 2001-1119022 A JP 2007-12858 A Japanese Patent No. 4016371 (paragraph 0096)

  In a superjunction semiconductor device, when the total impurity amount of each parallel pn region constituting the superjunction structure portion is unbalanced, the variation in breakdown voltage increases and the breakdown voltage non-defective rate decreases. However, it is inevitable that the ion-implanted impurities are reevaporated during epitaxial growth. Epitaxial growth specifically includes a temperature raising process, hydrogen annealing, epitaxial growth, and a temperature lowering process, and it is considered that the re-evaporation of impurities is generated by heat during the temperature raising process or hydrogen annealing. The re-evaporated impurities cause a phenomenon called auto-doping that is taken into the semiconductor substrate or the film being epitaxially grown. If there is temperature variation within and between wafers in the epitaxial growth process, even if the same dose is ion-implanted into the parallel pn regions due to the re-evaporation or auto-doping phenomenon as described above, charge imbalance is caused. The variation in withstand voltage becomes large, which causes a decrease in the yield rate of non-defective products.

  The present invention has been made in view of the above points. An object of the present invention is to provide a method of manufacturing a superjunction semiconductor device that reduces charge balance variation between an n-type column and a p-type column and has a high breakdown voltage non-defective product rate.

In the present invention, a first conductive type region and a second conductive type region which are long in the direction perpendicular to the main surface of the high-concentration first conductivity type semiconductor substrate and are alternately arranged adjacent to each other in the direction parallel to the main surface. In the method of manufacturing a superjunction semiconductor device in which a superjunction structure is formed as a drift layer, the method includes a layer formation step of epitaxially growing a first conductivity type semiconductor layer on the high concentration first conductivity type semiconductor substrate, Thereafter, an epitaxial layer is grown on the upper surface of the first conductive type semiconductor layer, and an entire surface ion implantation step for implanting ions of the first conductive type impurity on the entire surface of the epitaxial layer, and the epitaxial layer after the entire surface ion implantation step. A resist mask is formed on the upper surface, and a selective ion implantation step of selectively implanting ions of impurities of the second conductivity type, and the resist after the selective ion implantation step And a removing step for removing the plurality of discs, and a step of repeating the plurality of times. After the step of repeating the plurality of times, the first conductivity type impurity and the second conductivity type impurity are thermally diffused by heat treatment to cause the first conductivity. It includes a thermal diffusion step of forming a mold region and the second conductivity type region, a substrate cleaning treatment by the entire ion implantation respectively previous step is hydrogen peroxide and ammonia water in the layer forming step and the repeated several times laminating process and has a cleaning step of performing hydrogen annealing below 1100 ° C. after the said entire ion implantation the epitaxial layer of the lamination step of repeating the plurality of times and the first semiconductor layer of the layer forming step, the starting temperature of each of the epitaxial growth Is a method of manufacturing a superjunction semiconductor device at a temperature lower than 1100 ° C.

  In the present invention, the first conductivity type region and the second conductivity type region which are long in the direction perpendicular to the main surface of the high-concentration first conductivity type semiconductor substrate and are alternately adjacent to each other in the direction parallel to the main surface. A superjunction semiconductor device manufacturing method for forming a superjunction structure as a drift layer includes a layer formation step of epitaxially growing a first conductivity type semiconductor layer on the high-concentration first conductivity type semiconductor substrate. After the step, an epitaxial layer is grown on the upper surface of the first conductivity type semiconductor layer, and an entire surface ion implantation step for implanting ions of the first conductivity type impurity on the entire surface of the epitaxial layer, and after the entire surface ion implantation step, A resist mask is formed on the upper surface of the epitaxial layer, and a selective ion implantation process for selectively implanting ions of impurities of the second conductivity type, and the resist after the selective ion implantation process. And a removal step of removing the stock mask, and a first step of conducting the first conductivity by thermally diffusing the first conductivity type impurity and the second conductivity type impurity by heat treatment after the plurality of times of the lamination step. A thermal diffusion step of forming a mold region and a second conductivity type region, and before the entire surface ion implantation step of the layer formation step and the lamination step repeated a plurality of times, respectively, a substrate cleaning process with hydrogen peroxide water and ammonia water, respectively The first semiconductor layer in the layer forming step and the epitaxial layer in the flush ion implantation in the laminating step that has been repeated a plurality of times have an epitaxial growth start temperature of 950 respectively. A method for manufacturing a superjunction semiconductor device, characterized in that the temperature is not higher than ° C.

  According to the present invention, variation in charge balance between the n-type column and the p-type column constituting the superjunction structure can be reduced, and a method of manufacturing a superjunction semiconductor device with a high breakdown voltage yield can be obtained.

It is a cross-sectional schematic diagram of the super junction structure part concerning the manufacturing method of the super junction semiconductor device of this invention. It is principal part sectional drawing (the 1) of the semiconductor substrate which shows the manufacturing process concerning the manufacturing method of the super junction semiconductor device of this invention. It is principal part sectional drawing (the 2) of the semiconductor substrate which shows the manufacturing process concerning the manufacturing method of the super junction semiconductor device of this invention. It is principal part sectional drawing (the 3) of the semiconductor substrate which shows the manufacturing process concerning the manufacturing method of the super junction semiconductor device of this invention. It is a relationship figure which shows the impurity concentration peak depth dependence of the amount of reevaporation of boron and phosphorus. It is a relationship figure between the re-evaporation ratio with respect to impurity concentration peak depth, and dispersion | variation. It is principal part sectional drawing of the super junction MOSFET concerning this invention. It is a typical section perspective view of the element active part of the super junction MOSFET concerning the present invention.

  Embodiments of the method for manufacturing a superjunction semiconductor device according to the present invention will be described below in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist. In the embodiments described below, the first conductivity type will be described as n-type and the second conductivity type will be described as p-type.

  Next, a method for manufacturing a superjunction semiconductor device according to the present invention, in particular, a method for manufacturing a superjunction structure will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view of a superjunction structure portion of a superjunction semiconductor device described in Examples 1, 2, and 3 according to the present invention. FIG. 7 is a schematic cross-sectional view of an essential part of a superjunction MOSFET according to Examples 1, 2, and 3 of the present invention. FIG. 8 is a schematic cross-sectional perspective view of the element active portion of the superjunction MOSFET according to Examples 1, 2, and 3 of the present invention.

The superjunction semiconductor device according to the present invention includes a superjunction structure 10 in which n-type columns 4 and p-type columns 5 are alternately arranged on an n + Si substrate 1 and an n− layer 2 as shown in FIG. ing. Further, like the normal MOSFET, in the element active part 100, the p base region 13, the n emitter region 14, the gate insulating film 15, the gate electrode 16, the emitter electrode 17, and the peripheral breakdown voltage structure part 200 are provided. 7, a field insulating film 8, a channel stopper region 11, and a channel stopper electrode 12 are provided. Furthermore, a low-concentration n− epitaxial layer 3 is provided on the superjunction structure portion 10 in the peripheral breakdown voltage structure portion 200 of the superjunction semiconductor device.

  2 to 4 are schematic cross-sectional views of the main part of the semiconductor substrate showing the manufacturing process of the superjunction structure of the superjunction semiconductor device shown in FIG. As shown in FIG. 2, after an n− layer 2 is formed on the n + Si substrate 1 by doped epitaxial growth, for example, with a thickness of about 12 μm, and a non-doped layer 3a is formed thereon by epitaxial growth, for example, with a thickness of 3 μm. In the photolithography process, alignment markers (not shown) necessary for superimposing each stage are formed.

  As shown in FIG. 3, n-type impurity 4 a, for example, phosphorus is ion-implanted over the entire surface, and p-type impurity 5 a, for example, boron is ion-implanted into the opening selectively masked with resist mask 6. At this time, considering the subsequent thermal diffusion process, the opening width of the resist mask 6 is set to about 1/4 of the remaining width, and the boron ion implantation amount (dose amount) is set to about four times that of phosphorus. Thereafter, as shown in FIG. 4, a non-doped layer 3b is formed by epitaxial growth to a thickness of, for example, 7 μm. Again, ion implantation of n-type impurity 4a and p-type impurity 5a is performed in the same manner as described above. Thereafter, the epitaxial growth and the ion implantation are repeated until a desired thickness related to the design withstand voltage is obtained. Finally, after capping with a non-doped layer having a thickness of about 5 μm, for example, the impurity is thermally diffused by heat treatment to form the superjunction structure 10 shown in FIG.

  Here, in the ion implantation for forming the n-type column 4 and the p-type column 5, the amount of re-evaporation of the implanted boron and phosphorus is controlled, and the charge balance between the n-type column 4 and the p-type column 5 is maintained. It is important to secure a withstand voltage characteristic with small variations due to the super junction structure 10. It has been found that even if the amount of impurities by ion implantation between the n-type column 4 and the p-type column 5 is set to the same dose amount during ion implantation, the result often varies.

  Therefore, it is considered that one of the causes of the variation is evaporation of the implanted impurity, and the acceleration energy at the time of boron and phosphorus ion implantation is changed to change the ion implantation range Rp, that is, by ion implantation. The amount of reevaporation when the implantation depth was changed was measured. The result is shown in FIG. As can be seen from FIG. 5, if the range Rp is the same, that is, if the impurity concentration peak position in the depth direction is the same, the amount of reevaporation with respect to the dose is the same for boron and phosphorus. If the evaporation amounts of the p-type impurity 5a and the n-type impurity 4a are the same, the charge balance can be maintained even if evaporation occurs. FIG. 6 shows that the variation in evaporation can be suppressed when the impurity concentration peak position is deeper than 0.2 μm from the substrate surface. Accordingly, the impurity concentration peak position in the depth direction is preferably deeper than 0.2 μm from the substrate surface.

  As one embodiment of the method for manufacturing a superjunction semiconductor device of the present invention, the process conditions for forming the superjunction structure were performed under the conditions of ion implantation of phosphorus at an acceleration energy of 200 keV and boron of 80 keV. The range Rp (peak depth) after ion implantation at this time was about 0.25 μm. As a result, the re-evaporation amount of the parallel pn region in the super junction structure can be suppressed, and the re-evaporation amount of boron and phosphorus can be made the same, and the withstand voltage variation due to the charge imbalance between the parallel pn regions. It was found that can be reduced.

A method for manufacturing the superjunction structure portion of the superjunction semiconductor device according to Example 2 will be described. In Example 2, the formation of the epitaxial layer on the n + Si substrate as shown in FIGS. 1 to 4 is performed by setting the hydrogen annealing temperature (hydrogen annealing at 1000 ° C. for 2 minutes) and the epitaxial growth temperature as 1100 ° C. as pretreatment. It is characterized by being carried out at a temperature below. However, in the case of this manufacturing method, there is a concern that the crystallinity may be lowered because the pretreatment temperature is low and the silicon surface cannot be sufficiently cleaned and the growth temperature is low simply by lowering the temperature. As a result, there is a problem that pattern alignment becomes inaccurate due to the collapse of the shape of the alignment marker due to the decrease in crystallinity, and it is difficult to accurately stack the epitaxial layers in the formation of the superjunction structure portion. Therefore, in Example 2, the super junction structure is manufactured after adding manufacturing conditions that do not cause the above-described problems. Hereinafter, manufacturing conditions for such a super-junction structure will be described.

  As a pretreatment for growing an epitaxial layer on the n + Si substrate, a hydrogen annealing treatment is performed. Immediately before that, so-called RCA cleaning using a mixed solution of ammonia water is added to a hydrogen peroxide solution. The reason is that a silicon clean surface can be easily obtained even at a low temperature by performing a hydrogen annealing treatment immediately after chemical oxide is formed on the surface of the n + Si substrate. According to this surface cleaning method, epitaxial growth with good crystallinity becomes possible. Furthermore, by performing epitaxial growth at a low temperature of less than 1100 ° C., it becomes easy to suppress autodoping by suppressing outward diffusion from the Si substrate. However, if all epitaxial growth is performed at a low temperature of less than 1100 ° C., there is a problem that the shape of the alignment marker is greatly deformed. Therefore, the epitaxial growth at the low temperature is limited to the epitaxial growth with the minimum thickness necessary for suppressing auto-doping. . Thereafter, the epitaxial growth is performed by raising the temperature to 1100 ° C. or higher, which can suppress the deformation of the alignment marker to a required thickness. By adopting such a method for manufacturing a superjunction structure portion, autodoping can be suppressed during epitaxial growth in the superjunction structure portion. Therefore, even if the temperature is lower than 1100 ° C., the super pn region having good crystallinity is formed. A junction structure portion can be manufactured, and a super junction semiconductor device can be manufactured with a high yield rate.

  A method for manufacturing a superjunction structure portion of a superjunction semiconductor device according to Example 3 will be described. Example 3 is a manufacturing method characterized in that the formation of the epitaxial layer on the n + Si substrate as shown in FIGS. 1 to 4 is performed by performing a hydrogen annealing temperature and an epitaxial growth temperature as pre-treatment at a temperature of 1000 ° C. or less. is there.

  Epitaxial growth can also be performed at a temperature of 1000 ° C. or less without hydrogen annealing treatment. In this case, the silicon surface cleaning function is used as a pretreatment for epitaxial growth in the temperature rising process up to 950 ° C. for epitaxial growth. However, the silicon surface cannot be sufficiently cleaned, and there is a concern that the crystallinity is lowered as in Example 2. As a result, there arises a problem that pattern alignment becomes inaccurate due to the collapse of the shape of the alignment marker due to the decrease in crystallinity, making it difficult to accurately stack the epitaxial layers in the formation of the superjunction structure. Therefore, in Example 3, the super junction structure part is manufactured after further adding manufacturing conditions that do not cause the above-described problem. Hereinafter, manufacturing conditions for such a super-junction structure will be described.

  As a pretreatment for growing an epitaxial layer on the n + Si substrate 1, a diluted hydrofluoric acid treatment is further added to the RCA cleaning described above without performing a hydrogen annealing treatment. Epitaxial growth is performed with the Si substrate surface terminated with hydrogen by this diluted hydrofluoric acid treatment. Epitaxial growth is performed at a temperature of 950 ° C. or lower. When the temperature of the n + Si substrate 1 is raised to a predetermined temperature of 950 ° C. or less, hydrogen is desorbed and a clean silicon surface is obtained. This enables epitaxial growth with good crystallinity even at a low temperature of 950 ° C. or lower. Epitaxial growth is also performed at a low temperature as described above, so that outdiffusion from the Si substrate can be suppressed and autodoping can be easily suppressed. However, in Example 3 as in Example 2, the shape of the alignment marker is greatly deformed. Therefore, at the low temperature, epitaxial growth with a minimum thickness necessary to suppress autodoping is first performed at 950 ° C. Thereafter, the epitaxial growth is performed by raising the temperature to 1100 ° C. or higher, which can suppress the deformation of the alignment marker to a required thickness.

  According to Example 3, the crystallinity of the epitaxial growth at a low temperature can be improved by cleaning the surface on which the epitaxial growth is performed at a low temperature. In order to suppress auto-doping, epitaxial growth is performed at a low temperature. However, the film thickness is set to a minimum thickness (for example, about 1 μm) to prevent auto-doping. As a result, the mark shape collapse can be suppressed. Thereafter, the temperature is raised, and epitaxial growth is performed at 1100 ° C. to a desired predetermined thickness under good crystallinity conditions. As a result, it is possible to suppress the shape collapse of the alignment marker without deteriorating crystallinity while suppressing autodoping. By suppressing auto-doping, it becomes possible to control the impurity concentration of the superjunction structure part consisting of a high-precision parallel pn region and to maintain the charge balance of the parallel pn region, thus improving the breakdown voltage non-defective rate of the superjunction semiconductor device. The cost can be reduced by such as.

1 n + Si substrate 2 n-layer 3 low-concentration n-epitaxial layer 4 n-type column 4a n-type impurity 5 p-type column 5a p-type impurity 6 resist mask 10 superjunction structure part 100 element active part 200 peripheral breakdown voltage structure part

Claims (3)

A superjunction structure having a shape that is long in the direction perpendicular to the main surface of the high-concentration first conductivity type semiconductor substrate and that is alternately arranged adjacent to each other in the direction parallel to the main surface. In a method for manufacturing a superjunction semiconductor device that forms a drift layer,
A layer forming step of epitaxially growing a first conductivity type semiconductor layer on the high concentration first conductivity type semiconductor substrate;
After the layer forming step,
An entire surface ion implantation step of growing an epitaxial layer on the upper surface of the first conductivity type semiconductor layer and implanting an ion of a first conductivity type impurity on the entire surface of the epitaxial layer;
A selective ion implantation step of forming a resist mask on the upper surface of the epitaxial layer after the entire surface ion implantation step and selectively implanting ions of a second conductivity type impurity;
A removal step of removing the resist mask after the selective ion implantation step, and a lamination step that repeats a plurality of times,
A thermal diffusion step of thermally diffusing the first conductivity type impurity and the second conductivity type impurity by heat treatment after the plurality of lamination steps to form the first conductivity type region and the second conductivity type region; Prepared,
Having the entire ion implantation process before cleaning step of performing hydrogen annealing below 1100 ° C. After the substrate cleaning process with hydrogen peroxide solution and aqueous ammonia each laminating step of repeating the layer formation step and the plurality of times,
The first semiconductor layer in the layer forming step and the epitaxial layer in the whole surface ion implantation in the stacking step that is repeated a plurality of times each have an epitaxial growth start temperature of less than 1100 ° C. Method. A superjunction structure having a shape that is long in the direction perpendicular to the main surface of the high-concentration first conductivity type semiconductor substrate and that is alternately arranged adjacent to each other in the direction parallel to the main surface. In a method for manufacturing a superjunction semiconductor device that forms a drift layer,
A layer forming step of epitaxially growing a first conductivity type semiconductor layer on the high concentration first conductivity type semiconductor substrate;
After the layer forming step,
An entire surface ion implantation step of growing an epitaxial layer on the upper surface of the first conductivity type semiconductor layer and implanting an ion of a first conductivity type impurity on the entire surface of the epitaxial layer;
A selective ion implantation step of forming a resist mask on the upper surface of the epitaxial layer after the entire surface ion implantation step and selectively implanting ions of a second conductivity type impurity;
A removal step of removing the resist mask after the selective ion implantation step, and a lamination step that repeats a plurality of times,
A thermal diffusion step of thermally diffusing the first conductivity type impurity and the second conductivity type impurity by heat treatment after the plurality of lamination steps to form the first conductivity type region and the second conductivity type region; Prepared,
Before the entire surface ion implantation step of the layer forming step and the laminating step repeated a plurality of times, a cleaning step of performing a diluted hydrofluoric acid treatment after a substrate cleaning treatment with hydrogen peroxide solution and ammonia water, respectively,
The first semiconductor layer in the layer forming step and the epitaxial layer in the flush ion implantation in the laminating step that is repeated a plurality of times each have an epitaxial growth start temperature of 950 ° C. or less. Method. 3. The method of manufacturing a superjunction semiconductor device according to claim 1, wherein each epitaxial growth is performed to a predetermined thickness, and then the temperature is raised to 1100 ° C. or more to further epitaxially grow.