JP5985789B2 - Manufacturing method of super junction semiconductor device - Google Patents
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Description
本発明は、ドリフト層として半導体基板の主面に垂直方向に、複数配置されるｎ型カラムおよびｐ型カラムを主面に平行方向に交互に隣接させる超接合（スーパージャンクション）構造部を有する超接合半導体装置の製造方法に関する。 The present invention provides a super junction structure portion in which a plurality of n-type columns and p-type columns arranged alternately in the direction perpendicular to the main surface of the semiconductor substrate as the drift layer are alternately adjacent to each other in the parallel direction to the main surface. The present invention relates to a method for manufacturing a junction semiconductor device.
一般に半導体装置（以降、半導体素子または単に素子と言うこともある）は、半導体基板の片面に電極をもつ横型素子と、半導体基板の両面に電極をもつ縦型半導体装置（縦型素子）とに大別される。縦型素子は、オン時にドリフト電流が流れる方向と、オフ時の逆バイアス電圧による空乏層が延びる方向とが同じである。たとえば、通常のプレーナ型のｎチャネル縦型ＭＯＳＦＥＴの場合、高抵抗のｎ−ドリフト層の部分は、ＭＯＳＦＥＴがオン状態の時は縦方向にドリフト電流を流す領域として働き、オフ状態の時は空乏化して耐圧を高める。この高抵抗のｎ−ドリフト層の電流経路を短くすることは、ドリフト抵抗が低くなるのでＭＯＳＦＥＴの実質的なオン抵抗を下げる効果に繋がるものの、逆にｐベース領域とｎ−ドリフト領域との間のｐｎ接合から進行するドレイン−ベース間空乏層の広がる幅が狭く、シリコンの臨界電界強度に速く達するため、耐圧が低下する。逆に耐圧の高い素子では、ｎ−ドリフト層が厚くなるため必然的にオン抵抗が大きくなり、損失が増すことになる。このようなオン抵抗と耐圧との間の関係をトレードオフ関係と言う。このトレードオフ関係は、ＩＧＢＴ、バイポーラトランジスタ、ダイオード等の半導体素子においても同様に成立することが知られている。また、この関係は、オン時にドリフト電流が流れる方向と、オフ時の逆バイアスによる空乏層の延びる方向が異なる横型半導体素子についても共通である。 Generally, a semiconductor device (hereinafter also referred to as a semiconductor element or simply an element) is divided into a horizontal element having an electrode on one side of a semiconductor substrate and a vertical semiconductor device (vertical element) having electrodes on both sides of the semiconductor substrate. Broadly divided. In the vertical element, the direction in which the drift current flows when turned on is the same as the direction in which the depletion layer extends due to the reverse bias voltage when turned off. For example, in the case of a normal planar type n-channel vertical MOSFET, the portion of the high resistance n − drift layer functions as a region for flowing a drift current in the vertical direction when the MOSFET is in the on state, and is depleted when in the off state. To increase pressure resistance. Shortening the current path of the high-resistance n − drift layer lowers the drift resistance, leading to an effect of lowering the substantial on-resistance of the MOSFET, but conversely between the p base region and the n − drift region. The width of the depletion layer between the drain and base proceeding from the pn junction is narrow and the critical electric field strength of silicon is reached quickly, so that the breakdown voltage is lowered. On the other hand, in an element with a high breakdown voltage, the n − drift layer is thick, so the on-resistance is inevitably increased and the loss is increased. Such a relationship between on-resistance and breakdown voltage is called a trade-off relationship. It is known that this trade-off relationship is similarly established in semiconductor elements such as IGBTs, bipolar transistors, and diodes. This relationship is also common to lateral semiconductor elements in which the direction in which the drift current flows when on and the direction in which the depletion layer extends due to the reverse bias when off is different.
この問題に対する解決法として、図７、図８に示すように、ドリフト層を、半導体基板の主面に垂直方向では、層状またはカラム状の形状であって、通常のドリフト層よりも不純物濃度を高めた複数のｎ型のドリフト領域（ｎ型カラム）４とｐ型の仕切領域（ｐ型カラム）５とし、主面に平行方向では交互に繰り返し隣接するように配置した並列ｐｎ領域からなる超接合構造部１０とした超接合半導体装置（超接合ＭＯＳＦＥＴ）が知られている。この超接合半導体装置は、オフ状態の時は前記超接合構造部１０が空乏化して耐圧を負担するドリフト層の機能を有する。
As a solution to this problem, as shown in FIGS. 7 and 8, the drift layer has a layered or columnar shape in a direction perpendicular to the main surface of the semiconductor substrate, and has an impurity concentration higher than that of a normal drift layer. A plurality of elevated n-type drift regions (n-type columns) 4 and p-type partition regions (p-type columns) 5 are used, and the superstructures are formed of parallel pn regions that are alternately and repeatedly adjacent to each other in the parallel direction to the main surface. A superjunction semiconductor device (superjunction MOSFET) having a
前記超接合ＭＯＳＦＥＴと通常のプレーナ型のｎチャネル縦型ＭＯＳＦＥＴとの構造上の大きな違いは、ドリフト層が、単一の導電型で一様の不純物濃度の層ではなく、前述のような並列ｐｎ領域からなる超接合構造部１０にされていることである。この超接合構造部１０では、それぞれのｐ型の仕切り領域（ｐ型カラム）５とｎ型のドリフト領域（ｎ型カラム）４の不純物濃度（以降、単に濃度と表記することがある）が同耐圧クラスの通常の素子よりも高くても、オフ状態では超接合構造部１０内の並列ｐｎ接合から空乏層が両側に広がってドリフト層全体を低い電界強度で空乏化するため、高耐圧化を図ることができる。
The major difference in structure between the superjunction MOSFET and the normal planar type n-channel vertical MOSFET is that the drift layer is not a single conductivity type layer having a uniform impurity concentration, but a parallel pn as described above. That is, the
図７に示す、前記並列ｐｎ領域からなる超接合構造部１０を備える超接合ＭＯＳＦＥＴの周縁耐圧構造部２００では、周縁耐圧構造部２００内の超接合構造部１０の基板表面側（上層）に一様な不純物濃度を有する低濃度ｎ−エピタキシャル層３を配置する構成を必要とする。さらに、超接合半導体装置の周縁耐圧構造部２００には、超接合構造部１０の上層に設けられる前記低濃度ｎ−エピタキシャル層３の表層に基板表面に沿ってｐ型ガードリング７が、所要の設計耐圧に応じて、所要の間隔で離間するように複数設けられる。またさらに、この周縁耐圧構造部２００は、このｐ型ガードリング７表面と、最外周のｐ型ガードリング７ａ表面とに相互に電気的に接続される導電性プレート９を備える。さらに、ｐ型チャネルストッパー領域１１（もしくはｎ型チャネルストッパー領域でもよい）にも電気的に接続される導電性プレート１２が設けられる。
In the peripheral withstand
一方、超接合半導体装置の素子活性部１００内では並列ｐｎ領域からなる超接合構造部１０の上層に、通常の半導体装置と同様に、ｐベース領域１３とこのｐベース領域１３内の表層にｎエミッタ領域１４を備え、ｎエミッタ領域１４とｎドリフト領域（ｎ型カラム）４に挟まれる前記ｐベース領域１３表面にゲート絶縁膜１５を介してゲート電極１６を備え、前記ｎエミッタ領域１４表面とｐベース領域１３の高濃度表面とに接触するエミッタ電極１７が設けられる。
On the other hand, in the element
そのような超接合構造部１０を作製する方法として、エピタキシャル成長とイオン注入を多数回繰り返すことにより、一回のエピタキシャル成長とイオン注入毎に形成される厚さの薄い前記並列ｐｎ領域を順次上下に積み重ねて垂直方向に長い形状にする方法（多段エピタキシャル法）はよく知られている。
As a method for manufacturing such a
この多段エピタキシャル法による超接合構造部の製造工程の一例について説明する。前記エピタキシャル成長とイオン注入は、高濃度ｎ＋Ｓｉ基板１上に、厚さ１２μｍの低濃度ｎ−エピタキシャル層２を形成し、マスク合わせ用のアライメントマーカー（図示せず）を形成する。２５ｎｍ厚さのスクリーン酸化膜（図示せず）形成後、全面にリンイオンを１００ｋｅＶの加速エネルギーによりドーズ量１×１０１２ｃｍ−２〜９×１０１２ｃｍ−２で、イオン注入する。フォトリソグラフィ工程後ボロンイオンを選択的にリンイオンと同じ総不純物量となるようにイオン注入する。レジストと酸化膜除去後、水素アニールした後、ノンドープのエピタキシャル層を形成する。その後、前述のリンとボロンのイオン注入工程以降を繰り返して所要の厚さの並列ｐｎ領域からなる超接合構造部１０とする。
An example of the manufacturing process of the superjunction structure by the multistage epitaxial method will be described. In the epitaxial growth and ion implantation, a low concentration n −
たとえば、前述の製造工程で作製された超接合構造部１０を備える超接合半導体装置では、ｎ型カラム４とｐ型カラム５とのチャージバランスが重要であり、同じであることが望ましい。また、前述の耐電荷性を備える周縁耐圧構造部２００を形成するためには、多段エピタキシャル法で複数回のエピタキシャル層形成とイオン注入により並列ｐｎ領域からなる超接合構造を形成した後、該超接合構造の上層に低濃度ｎ−エピタキシャル層３を作製し、載置することにより形成される。別の言い方をすると、この低濃度ｎ−エピタキシャル層３は、素子活性部ではイオン注入することにより前記超接合構造部の上層を構成するが、周縁耐圧構造部２００ではイオン注入をせずに低濃度ｎ−エピタキシャル層３のままとすることにより作製される。前記低濃度ｎ−エピタキシャル層３の厚さは１５μｍ前後以上必要であるので、１回のエピタキシャル成長の厚さを１０μｍ以下とすると、必要な段数（エピタキシャル成長の回数）は２段以上となる。
For example, in a superjunction semiconductor device including the
以上説明した超接合構造部の製造工程では、リンとボロンのイオン注入によって並列ｐｎ領域からなる超接合構造部を作製したが、ボロンのイオン注入のみにより前述と同様の超接合構造部を作製する製造方法については既に知られている（特許文献１）。 In the manufacturing process of the superjunction structure described above, a superjunction structure composed of parallel pn regions is fabricated by ion implantation of phosphorus and boron, but a superjunction structure similar to that described above is fabricated only by ion implantation of boron. The manufacturing method is already known (Patent Document 1).
また、イオン注入飛程Ｒｐを変えて超接合構造部を作製することにより、エピタキシャル成長とイオン注入の繰り返し回数を減らして、製造効率を改善する超接合半導体装置の製造方法についても公開されている（特許文献２）。 Also disclosed is a method of manufacturing a superjunction semiconductor device that improves the manufacturing efficiency by reducing the number of repetitions of epitaxial growth and ion implantation by changing the ion implantation range Rp to produce a superjunction structure portion ( Patent Document 2).
また、前述の超接合構造部のように、深さ方向に長い形状の不純物添加領域を形成するための気相エピタキシャル成長方法に関する文献が公開されている。この文献には「気相成長工程は、硼素注入層及び燐注入層からの横方向オートドープを抑制するために、まず封止用の薄いエピタキシャルシリコン層を気相成長してから第二エピタキシャル層の本成長を行う複数段階処理とすることが望ましい。」という記載のように、エピタキシャルシリコン層のソースガスを先に処理する方法が示されている（特許文献３）。 Further, literature on a vapor phase epitaxial growth method for forming an impurity-added region having a shape that is long in the depth direction as in the above-described superjunction structure is disclosed. In this document, “a vapor phase growth process is performed by first vapor-depositing a thin epitaxial silicon layer for sealing in order to suppress lateral autodoping from a boron implantation layer and a phosphorus implantation layer, and then a second epitaxial layer. As described above, it is desirable to use a multi-stage process in which the main growth is performed. ”A method of processing the source gas of the epitaxial silicon layer first is disclosed (Patent Document 3).
超接合半導体装置では、超接合構造部を構成する並列ｐｎ領域のそれぞれの総不純物量にアンバランスが生じると耐圧のばらつきが大きくなり、耐圧良品率が低下する。しかしながら、前記イオン注入した不純物は、エピタキシャル成長時に再蒸発することは避けられない。エピタキシャル成長は具体的に、昇温過程、水素アニール、エピタキシャル成長、降温過程からなるが、不純物の再蒸発は前記昇温過程や水素アニール時の熱により発生するものと考えられている。再蒸発した不純物は半導体基板やエピタキシャル成長中の膜に取り込まれるオートドーピングと呼ばれる現象を引き起こす。エピタキシャル成長プロセスにおけるウエハ内およびウエハ間に温度ばらつきが存在すると、前述のような再蒸発やオートドープ現象によって、前記並列ｐｎ領域に、たとえ同ドーズ量をイオン注入したとしても、チャージアンバランスをもたらして耐圧ばらつきが大きくなり、耐圧良品率低下の原因となる。 In a superjunction semiconductor device, when the total impurity amount of each parallel pn region constituting the superjunction structure portion is unbalanced, the variation in breakdown voltage increases and the breakdown voltage non-defective rate decreases. However, it is inevitable that the ion-implanted impurities are reevaporated during epitaxial growth. Epitaxial growth specifically includes a temperature raising process, hydrogen annealing, epitaxial growth, and a temperature lowering process, and it is considered that the re-evaporation of impurities is generated by heat during the temperature raising process or hydrogen annealing. The re-evaporated impurities cause a phenomenon called auto-doping that is taken into the semiconductor substrate or the film being epitaxially grown. If there is temperature variation within and between wafers in the epitaxial growth process, even if the same dose is ion-implanted into the parallel pn regions due to the re-evaporation or auto-doping phenomenon as described above, charge imbalance is caused. The variation in withstand voltage becomes large, which causes a decrease in the yield rate of non-defective products.
本発明は前述した点に鑑みてなされたものである。本発明の目的は、ｎ型カラムとｐ型カラムのチャージバランスばらつきを低減し、耐圧良品率の高い超接合半導体装置の製造方法を提供することである。 The present invention has been made in view of the above points. An object of the present invention is to provide a method of manufacturing a superjunction semiconductor device that reduces charge balance variation between an n-type column and a p-type column and has a high breakdown voltage non-defective product rate.
本発明では、前記発明の目的を達成するため、高濃度第１導電型半導体基板高濃度第１導電型半導体基板の主面に垂直方向に長い形状であって、主面に平行方向では交互に隣接配置される第１導電型領域と第２導電型領域からなる超接合構造部をドリフト層として形成する超接合半導体装置の製造方法において、前記高濃度第１導電型半導体基板上に第１導電型半導体層をエピタキシャル成長する層形成工程を備え、前記層形成工程の後に、前記第１導電型半導体層の上面にエピタキシャル層を成長させ、該エピタキシャル層の全面に第１導電型の不純物のイオン注入を行う全面イオン注入工程と、前記全面イオン注入工程後に前記エピタキシャル層上面にレジストマスクを形成し、第２導電型の不純物のイオン注入を選択的に行う選択的イオン注入工程と、前記選択的イオン注入工程後に前記レジストマスクを除去する除去工程と、を複数回繰り返す積層工程を備え、前記複数回繰り返す積層工程後に熱処理により前記第１導電型の不純物と前記第２導電型の不純物を熱拡散して前記第１導電型領域および第２導電型領域を形成する熱拡散工程と、を備え、前記第１導電型領域および第２導電型領域にそれぞれイオン注入する総不純物量が等しく、前記複数回繰り返す前記全面イオン注入工程および前記選択的イオン注入工程では、イオン注入された前記第１導電型の不純物と前記第２導電型の不純物のそれぞれの不純物濃度ピーク位置が前記エピタキシャル層の表面から一致する深さになるような加速エネルギーでイオン注入を行い、前記それぞれの不純物濃度ピーク位置が、前記エピタキシャル層の表面から０．２μｍの深さより深くすることを特徴とする。
In the present invention, in order to achieve the object of the present invention, the high-concentration first conductive semiconductor substrate has a shape that is long in the direction perpendicular to the main surface of the high-concentration first conductive semiconductor substrate, and alternately in a direction parallel to the main surface. In a method of manufacturing a superjunction semiconductor device, in which a superjunction structure portion composed of a first conductivity type region and a second conductivity type region arranged adjacent to each other is formed as a drift layer, a first conductivity is formed on the high concentration first conductivity type semiconductor substrate. A layer forming step of epitaxially growing the type semiconductor layer, and after the layer forming step, an epitaxial layer is grown on the upper surface of the first conductive type semiconductor layer, and ion implantation of the first conductive type impurity is performed on the entire surface of the epitaxial layer. A selective ion implantation process for selectively performing ion implantation of impurities of the second conductivity type by forming a resist mask on the upper surface of the epitaxial layer after the entire surface ion implantation process. And a removal step of removing the resist mask after the selective ion implantation step, and a step of repeating the plurality of times, and the first conductivity type impurities and the first by heat treatment after the plurality of repetitions of the lamination step. A thermal diffusion step of thermally diffusing impurities of two conductivity types to form the first conductivity type region and the second conductivity type region, and ion-implanting into the first conductivity type region and the second conductivity type region, respectively. In the entire surface ion implantation step and the selective ion implantation step, which have the same total impurity amount and are repeated a plurality of times, the respective impurity concentration peak positions of the first conductivity type impurity and the second conductivity type impurity implanted by ion implantation There performing ion implantation at an acceleration energy such that the depth to match the surface of the epitaxial layer, wherein each of the impurity concentration peak position, Serial characterized by deeper than the depth of 0.2μm from the surface of the epitaxial layer.
本発明によれば、超接合構造部を構成するｎ型カラムとｐ型カラムのチャージバランスばらつきを低減することができ、耐圧良品率の高い超接合半導体装置の製造方法とすることができる。 According to the present invention, variation in charge balance between the n-type column and the p-type column constituting the superjunction structure can be reduced, and a method of manufacturing a superjunction semiconductor device with a high breakdown voltage yield can be obtained.
以下、本発明の超接合半導体装置の製造方法にかかる実施例について、図面を参照して詳細に説明する。本発明はその要旨を超えない限り、以下に説明する実施例の記載に限定されるものではない。以下に説明する実施例では、第１導電型をｎ型、第２導電型をｐ型として説明する。 Embodiments of the method for manufacturing a superjunction semiconductor device according to the present invention will be described below in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist. In the embodiments described below, the first conductivity type will be described as n-type and the second conductivity type will be described as p-type.
次に、本発明の超接合半導体装置の製造方法について、特には超接合構造部の作製方法について、図面を参照して説明する。図１は本発明にかかる実施例１、２、３で説明する超接合半導体装置の超接合構造部の断面模式図である。図７は本発明の実施例１、２、３にかかる超接合ＭＯＳＦＥＴの要部断面模式図である。図８は本発明の実施例１、２、３にかかる超接合ＭＯＳＦＥＴの素子活性部の模式的断面斜視図である。 Next, a method for manufacturing a superjunction semiconductor device according to the present invention, in particular, a method for manufacturing a superjunction structure will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view of a superjunction structure portion of a superjunction semiconductor device described in Examples 1, 2, and 3 according to the present invention. FIG. 7 is a schematic cross-sectional view of an essential part of a superjunction MOSFET according to Examples 1, 2, and 3 of the present invention. FIG. 8 is a schematic cross-sectional perspective view of the element active portion of the superjunction MOSFET according to Examples 1, 2, and 3 of the present invention.
本発明にかかる超接合半導体装置は図７に示すようなｎ＋Ｓｉ基板１およびｎ−層２上にｎ型カラム４およびｐ型カラム５が交互に配置された超接合構造部１０を備える構成となっている。さらに、通常のＭＯＳＦＥＴと同様に、素子活性部１００内には、ｐベース領域１３、ｎエミッタ領域１４、ゲート絶縁膜１５、ゲート電極１６、エミッタ電極１７、周縁耐圧構造部２００内に、ガードリング７、フィールド絶縁膜８、チャネルストッパー領域１１、チャネルストッパー電極１２を備えている。またさらに、超接合半導体装置の周縁耐圧構造部２００内の超接合構造部１０の上層には、低濃度ｎ−エピタキシャル層３が設けられている。
A superjunction semiconductor device according to the present invention includes a
図２から図４は、図１に示す超接合半導体装置の超接合構造部の製造工程を段階ごとに示す半導体基板の要部断面模式図である。図２に示すように、ｎ＋Ｓｉ基板１上にｎ−層２をドープドエピタキシャル成長により、たとえば１２μｍ程度の厚みで形成し、その上にノンドープ層３ａをエピタキシャル成長により、たとえば３μｍの厚みで形成した後、フォトリソグラフィ工程で、各段ごとの重ね合わせの際に必要となるアライメントマーカー（図示しない）を形成する。
2 to 4 are schematic cross-sectional views of the main part of the semiconductor substrate showing the manufacturing process of the superjunction structure of the superjunction semiconductor device shown in FIG. As shown in FIG. 2, an n − layer 2 is formed on the n + Si substrate 1 by doped epitaxial growth to a thickness of, for example, about 12 μm, and a
図３に示すように、ｎ型不純物４ａ、たとえばリンを全面にイオン注入し、ｐ型不純物５ａ、たとえばボロンを、レジストマスク６で選択的にマスクした開口部にイオン注入する。この時、後の熱拡散工程を考慮してレジストマスク６の開口幅は残し幅の１／４程度とし、それに応じてボロンイオンの注入量（ドーズ量）はリンの４倍程度とする。その後、図４に示すように、ノンドープ層３ｂをエピタキシャル成長により、たとえば７μｍの厚みで形成する。再度前述と同様にｎ型不純物４ａおよびｐ型不純物５ａのイオン注入を行う。その後、設計耐圧に関係する所望の厚さになるまでこれらエピタキシャル成長とイオン注入を繰り返し行う。最後に、たとえば５μｍ程度の厚さのノンドープ層でキャップした後、熱処理により不純物の熱拡散を行って図１に示す超接合構造部１０を形成する。
As shown in FIG. 3, n-type impurity 4 a, for example, phosphorus is ion-implanted over the entire surface, and p-type impurity 5 a, for example, boron is ion-implanted into the opening selectively masked with resist mask 6. At this time, considering the subsequent thermal diffusion process, the opening width of the resist mask 6 is set to about 1/4 of the remaining width, and the boron ion implantation amount (dose amount) is set to about four times that of phosphorus. Thereafter, as shown in FIG. 4, a non-doped layer 3b is formed by epitaxial growth to a thickness of, for example, 7 μm. Again, ion implantation of n-type impurity 4a and p-type impurity 5a is performed in the same manner as described above. Thereafter, the epitaxial growth and the ion implantation are repeated until a desired thickness related to the design withstand voltage is obtained. Finally, after capping with a non-doped layer having a thickness of about 5 μm, for example, the impurity is thermally diffused by heat treatment to form the
ここで、ｎ型カラム４およびｐ型カラム５を形成する際のイオン注入において、イオン注入したボロンおよびリンの再蒸発量を制御し、ｎ型カラム４およびｐ型カラム５間のチャージバランスを保持することが超接合構造部１０によるばらつきの小さい耐圧特性を確保する上で重要である。ｎ型カラム４およびｐ型カラム５間のイオン注入による不純物量はイオン注入時に同ドーズ量に設定しても、結果的にはばらつきを生じることが多いことが分かっている。
Here, in the ion implantation for forming the n-
そこで、前記ばらつきの原因の一つにイオン注入した不純物の蒸発があると考え、ボロンとリンのイオン注入の際の加速エネルギーを変化させてイオン注入の飛程Ｒｐを変え、すなわち、イオン注入による注入深さを変えたときの再蒸発量を測定した。その結果を図５に示す。図５より、飛程Ｒｐが同じであれば、すなわち、深さ方向の不純物濃度ピーク位置が同じであれば、ボロンとリンとでドーズ量に対する再蒸発する量が同じであることがわかる。ｐ型不純物５ａとｎ型不純物４ａの蒸発量が同じであれば、蒸発があったとしてもチャージバランスは保持できる。また、図６では、さらに不純物濃度ピーク位置が基板表面から０．２μｍより深い場合に前記蒸発のばらつきが抑制できることを示している。従って、深さ方向の不純物濃度ピーク位置は基板表面から０．２μｍより深いことが好ましい。 Therefore, it is considered that one of the causes of the variation is evaporation of the implanted impurity, and the acceleration energy at the time of boron and phosphorus ion implantation is changed to change the ion implantation range Rp, that is, by ion implantation. The amount of reevaporation when the implantation depth was changed was measured. The result is shown in FIG. As can be seen from FIG. 5, if the range Rp is the same, that is, if the impurity concentration peak position in the depth direction is the same, the amount of reevaporation with respect to the dose is the same for boron and phosphorus. If the evaporation amounts of the p-type impurity 5a and the n-type impurity 4a are the same, the charge balance can be maintained even if evaporation occurs. FIG. 6 shows that the variation in evaporation can be suppressed when the impurity concentration peak position is deeper than 0.2 μm from the substrate surface. Accordingly, the impurity concentration peak position in the depth direction is preferably deeper than 0.2 μm from the substrate surface.
本発明の超接合半導体装置の製造方法にかかる実施の一形態として、超接合構造部を形成するためのプロセス条件として、リンを２００ｋｅＶで、ボロンを８０ｋｅＶの加速エネルギーのイオン注入条件で行った、このときのイオン注入後の飛程Ｒｐ（ピーク深さ）は約０．２５μｍであった。この結果、前記超接合構造部における並列ｐｎ領域の再蒸発量を抑制することができ、さらにボロンとリンの再蒸発量を同じにすることができ、並列ｐｎ領域間のチャージアンバランスによる耐圧ばらつきは低減できることが分かった。 As one embodiment of the method for manufacturing a superjunction semiconductor device of the present invention, the process conditions for forming the superjunction structure were performed under the conditions of ion implantation of phosphorus at an acceleration energy of 200 keV and boron of 80 keV. The range Rp (peak depth) after ion implantation at this time was about 0.25 μm. As a result, the re-evaporation amount of the parallel pn region in the super junction structure can be suppressed, and the re-evaporation amount of boron and phosphorus can be made the same, and the withstand voltage variation due to the charge imbalance between the parallel pn regions. It was found that can be reduced.
実施例２にかかる超接合半導体装置の超接合構造部の作製方法について説明する。実施例２では、前記図１〜図４に示すようなｎ＋Ｓｉ基板上へのエピタキシャル層の形成を、前処理としての水素アニール温度（１０００℃で２分間の水素アニール）とエピタキシャル成長温度とを１１００℃未満の温度で行うことを特徴とする。しかし、この作製方法の場合、単に温度を下げただけでは、前処理温度が低く十分なシリコン表面の清浄化ができず、成長温度も低いので結晶性が低下することが懸念される。その結果、結晶性の低下によるアライメントマーカーの形状崩れによりパターン合わせが不正確になり、超接合構造部の形成におけるエピタキシャル層の正確な積み重ねが困難になるという問題が発生する。そのため、実施例２では、前述の問題が起きないような製造条件を加えた上で超接合構造部を作製する。以下、そのような超接合構造部の製造条件について説明する。 A method for manufacturing the superjunction structure portion of the superjunction semiconductor device according to Example 2 will be described. In Example 2, the formation of the epitaxial layer on the n + Si substrate as shown in FIGS. 1 to 4 is carried out by using a hydrogen annealing temperature as a pretreatment (hydrogen annealing at 1000 ° C. for 2 minutes) and an epitaxial growth temperature. It is characterized by being performed at a temperature below 1100 ° C. However, in the case of this manufacturing method, there is a concern that the crystallinity may be lowered because the pretreatment temperature is low and the silicon surface cannot be sufficiently cleaned and the growth temperature is low simply by lowering the temperature. As a result, there is a problem that pattern alignment becomes inaccurate due to the collapse of the shape of the alignment marker due to the decrease in crystallinity, and it is difficult to accurately stack the epitaxial layers in the formation of the superjunction structure portion. Therefore, in Example 2, the super junction structure is manufactured after adding manufacturing conditions that do not cause the above-described problems. Hereinafter, manufacturing conditions for such a super-junction structure will be described.
前記ｎ＋Ｓｉ基板上にエピタキシャル層を成長させる前処理として、水素アニール処理を行うが、その直前にさらに、過酸化水素液にアンモニア水との混合液を用いるいわゆるＲＣＡ洗浄を加える。その理由は、ｎ＋Ｓｉ基板の表面にケミカルオキサイドを形成した直後に水素アニール処理を行うことでシリコン清浄表面が低温でも得られ易くなるからである。この表面清浄化方法によれば、結晶性の良いエピタキシャル成長が可能になる。またさらに、エピタキシャル成長も１１００℃未満の低温で行うことにより、Ｓｉ基板からの外方拡散を抑えオートドープを抑えやすくなる。ただし、前記１１００℃未満という低い温度でのエピタキシャル成長を全部行うと、アライメントマーカーの形状崩れが大きくなる問題があるので、前記低温でのエピタキシャル成長はオートドープを抑えるのに必要な最低厚みのエピタキシャル成長にとどめる。その後、所要の厚みまで、アライメントマーカーの形状崩れを抑えることのできる１１００℃以上に昇温してエピタキシャル成長を行う方法とする。このような超接合構造部の作製方法とすることにより、超接合構造部におけるエピタキシャル成長の際にオートドープを抑えることができるので、１１００℃未満の低温でも、結晶性のよい並列ｐｎ領域からなる超接合構造部を作製することができ、超接合半導体装置を高い耐圧良品率で製造することができる。 As a pretreatment for growing an epitaxial layer on the n + Si substrate, a hydrogen annealing treatment is performed. Immediately before that, so-called RCA cleaning using a mixed solution of ammonia water and hydrogen peroxide solution is added. The reason is that a silicon clean surface can be easily obtained even at a low temperature by performing a hydrogen annealing treatment immediately after chemical oxide is formed on the surface of the n + Si substrate. According to this surface cleaning method, epitaxial growth with good crystallinity becomes possible. Furthermore, by performing epitaxial growth at a low temperature of less than 1100 ° C., it becomes easy to suppress autodoping by suppressing outward diffusion from the Si substrate. However, if all epitaxial growth is performed at a temperature as low as less than 1100 ° C., there is a problem that the shape of the alignment marker is greatly deformed. . Thereafter, the epitaxial growth is performed by raising the temperature to 1100 ° C. or higher, which can suppress the deformation of the alignment marker to a required thickness. By adopting such a method for manufacturing a superjunction structure part, autodoping can be suppressed during epitaxial growth in the superjunction structure part. A junction structure portion can be manufactured, and a super junction semiconductor device can be manufactured with a high yield rate.
実施例３にかかる超接合半導体装置の超接合構造部の作製方法について説明する。実施例３では、前記図１〜図４に示すようなｎ＋Ｓｉ基板上のエピタキシャル層の形成を前処理としての水素アニール温度とエピタキシャル成長温度を１０００℃以下の温度で行うことを特徴とする製造方法である。 A method for manufacturing a superjunction structure portion of a superjunction semiconductor device according to Example 3 will be described. In Example 3, the formation of the epitaxial layer on the n + Si substrate as shown in FIGS. 1 to 4 is performed at a hydrogen annealing temperature and an epitaxial growth temperature as pre-treatment at a temperature of 1000 ° C. or less. Is the method.
水素アニール処理無しで、エピタキシャル成長を１０００℃以下の温度で行うこともできる。この場合は、エピタキシャル成長のための９５０℃までの昇温過程でシリコン表面の清浄化機能をエピタキシャル成長の前処理として利用する方法である。しかし、シリコン表面の清浄化が充分にはできなくて前記実施例２と同様に、結晶性が低下することが懸念される。その結果、結晶性の低下によるアライメントマーカーの形状崩れによりパターン合わせが不正確になり、超接合構造部の形成におけるエピタキシャル層の正確な積み重ねが困難になる問題が発生する。そのため、実施例３では、前述の問題が起きないような製造条件をさらに加えた上で超接合構造部を作製する。以下、そのような超接合構造部の製造条件について説明する。 Epitaxial growth can also be performed at a temperature of 1000 ° C. or less without hydrogen annealing treatment. In this case, the silicon surface cleaning function is used as a pretreatment for epitaxial growth in the temperature rising process up to 950 ° C. for epitaxial growth. However, the silicon surface cannot be sufficiently cleaned, and there is a concern that the crystallinity is lowered as in Example 2. As a result, there arises a problem that pattern alignment becomes inaccurate due to the collapse of the shape of the alignment marker due to the decrease in crystallinity, making it difficult to accurately stack the epitaxial layers in the formation of the superjunction structure. Therefore, in Example 3, the super junction structure part is manufactured after further adding manufacturing conditions that do not cause the above-described problem. Hereinafter, manufacturing conditions for such a super-junction structure will be described.
前記ｎ＋Ｓｉ基板１上にエピタキシャル層を成長させる前処理として、水素アニール処理をせずに、前述のＲＣＡ洗浄にさらに希釈フッ酸処理を加える。この希釈フッ酸処理によりＳｉ基板表面を水素終端した状態でエピタキシャル成長を行う。エピタキシャル成長は９５０℃以下の温度で行う。ｎ＋Ｓｉ基板１表面は、９５０℃以下の所定温度まで昇温する際に水素が脱離して清浄なシリコン表面が得られる。このことにより９５０℃以下の低温でも結晶性の良いエピタキシャル成長が可能になる。エピタキシャル成長も前述のような低温で行うことによりＳｉ基板からの外方拡散を抑えオートドープを抑えやすくなる。ただし、実施例２と同様に実施例３でも、アライメントマーカーの形状崩れが大きくなってしまうので、前記低温ではオートドープを抑えるのに必要な最低限の厚みのエピタキシャル成長を９５０℃でまず行う。その後、所要の厚みまで、アライメントマーカーの形状崩れを抑えることのできる１１００℃以上に昇温してエピタキシャル成長を行う方法とする。 As a pretreatment for growing an epitaxial layer on the n + Si substrate 1, a dilute hydrofluoric acid treatment is further added to the RCA cleaning described above without performing a hydrogen annealing treatment. Epitaxial growth is performed with the Si substrate surface terminated with hydrogen by this diluted hydrofluoric acid treatment. Epitaxial growth is performed at a temperature of 950 ° C. or lower. When the temperature of the n + Si substrate 1 is raised to a predetermined temperature of 950 ° C. or lower, hydrogen is desorbed and a clean silicon surface is obtained. This enables epitaxial growth with good crystallinity even at a low temperature of 950 ° C. or lower. Epitaxial growth is also performed at a low temperature as described above, so that outdiffusion from the Si substrate can be suppressed and autodoping can be easily suppressed. However, in Example 3 as in Example 2, the shape of the alignment marker is greatly deformed. Therefore, at the low temperature, epitaxial growth with a minimum thickness necessary to suppress autodoping is first performed at 950 ° C. Thereafter, the epitaxial growth is performed by raising the temperature to 1100 ° C. or higher, which can suppress the deformation of the alignment marker to a required thickness.
実施例３によれば、エピタキシャル成長する表面を低温で清浄化することで、低温のエピタキシャル成長の結晶性を改善することができる。オートドープを抑えるために低温でエピタキシャル成長する。しかし膜厚はオートドープを防ぐ最小限の厚み（たとえば、１μｍ程度）とする。このことで、マーク形状崩れを抑えることができる。その後昇温して１１００℃で目的の所定の厚みまで結晶性のよい条件でエピタキシャル成長を行う。このことで、オートドープを抑えつつ、結晶性を悪化させずにアライメントマーカーの形状崩れを抑えることが可能になる。オートドープを抑えることで、高精度の並列ｐｎ領域からなる超接合構造部の不純物濃度のコントロールが可能になり、並列ｐｎ領域のチャージバランスを保持できるので、超接合半導体装置の耐圧良品率の向上等による低コスト化が可能になる。 According to Example 3, the crystallinity of the epitaxial growth at a low temperature can be improved by cleaning the surface on which the epitaxial growth is performed at a low temperature. In order to suppress auto-doping, epitaxial growth is performed at a low temperature. However, the film thickness is set to a minimum thickness (for example, about 1 μm) to prevent auto-doping. As a result, the mark shape collapse can be suppressed. Thereafter, the temperature is raised, and epitaxial growth is performed at 1100 ° C. to a desired predetermined thickness under good crystallinity conditions. As a result, it is possible to suppress the shape collapse of the alignment marker without deteriorating crystallinity while suppressing autodoping. By suppressing auto-doping, it becomes possible to control the impurity concentration of the superjunction structure part consisting of a high-precision parallel pn region and to maintain the charge balance of the parallel pn region, thus improving the breakdown voltage non-defective rate of the superjunction semiconductor device. The cost can be reduced by such as.
１ ｎ＋Ｓｉ基板
２ ｎ−層
３ 低濃度ｎ−エピタキシャル層
４ ｎ型カラム
４ａ ｎ型不純物
５ ｐ型カラム
５ａ ｐ型不純物
６ レジストマスク
１０ 超接合構造部
１００ 素子活性部
２００ 周縁耐圧構造部
DESCRIPTION OF SYMBOLS 1 n + Si substrate 2 n - layer 3 Low concentration n-epitaxial layer 4 n-type column 4a n-type impurity 5 p-type column 5a p-type impurity 6 Resist
Claims (1)
前記高濃度第１導電型半導体基板上に第１導電型半導体層をエピタキシャル成長する層形成工程を備え、
前記層形成工程の後に、
前記第１導電型半導体層の上面にエピタキシャル層を成長させ、該エピタキシャル層の全面に第１導電型の不純物のイオン注入を行う全面イオン注入工程と、
前記全面イオン注入工程後に前記エピタキシャル層上面にレジストマスクを形成し、第２導電型の不純物のイオン注入を選択的に行う選択的イオン注入工程と、
前記選択的イオン注入工程後に前記レジストマスクを除去する除去工程と、を複数回繰り返す積層工程を備え、
前記複数回繰り返す積層工程後に熱処理により前記第１導電型の不純物と前記第２導電型の不純物を熱拡散して前記第１導電型領域および第２導電型領域を形成する熱拡散工程と、を備え、
前記第１導電型領域および第２導電型領域にそれぞれイオン注入する総不純物量が等しく、
前記複数回繰り返す前記全面イオン注入工程および前記選択的イオン注入工程では、イオン注入された前記第１導電型の不純物と前記第２導電型の不純物のそれぞれの不純物濃度ピーク位置が前記エピタキシャル層の表面から一致する深さになるような加速エネルギーでイオン注入を行い、
前記それぞれの不純物濃度ピーク位置は前記エピタキシャル層の表面から０．２μｍの深さより深いことを特徴とする超接合半導体装置の製造方法。 A superjunction structure having a shape that is long in the direction perpendicular to the main surface of the high-concentration first conductivity type semiconductor substrate and that is alternately arranged adjacent to each other in the direction parallel to the main surface. In a method for manufacturing a superjunction semiconductor device that forms a drift layer,
A layer forming step of epitaxially growing a first conductivity type semiconductor layer on the high concentration first conductivity type semiconductor substrate;
After the layer forming step,
An entire surface ion implantation step of growing an epitaxial layer on the upper surface of the first conductivity type semiconductor layer and implanting an ion of a first conductivity type impurity on the entire surface of the epitaxial layer;
A selective ion implantation step of forming a resist mask on the upper surface of the epitaxial layer after the entire surface ion implantation step and selectively implanting ions of a second conductivity type impurity;
A removal step of removing the resist mask after the selective ion implantation step, and a lamination step that repeats a plurality of times,
A thermal diffusion step of thermally diffusing the first conductivity type impurity and the second conductivity type impurity by heat treatment after the plurality of lamination steps to form the first conductivity type region and the second conductivity type region; Prepared,
The total amount of impurities implanted into the first conductivity type region and the second conductivity type region is equal,
In the entire surface ion implantation step and the selective ion implantation step that are repeated a plurality of times, the respective impurity concentration peak positions of the first conductivity type impurity and the second conductivity type impurity that are ion implanted are the surface of the epitaxial layer. Ion implantation is performed with acceleration energy that matches the depth from
Each of the impurity concentration peak positions is deeper than the depth of 0.2 μm from the surface of the epitaxial layer .
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| US9431249B2 (en) | 2011-12-01 | 2016-08-30 | Vishay-Siliconix | Edge termination for super junction MOSFET devices |
| US9614043B2 (en) | 2012-02-09 | 2017-04-04 | Vishay-Siliconix | MOSFET termination trench |
| US9842911B2 (en) | 2012-05-30 | 2017-12-12 | Vishay-Siliconix | Adaptive charge balanced edge termination |
| US9105717B2 (en) * | 2013-12-04 | 2015-08-11 | Infineon Technologies Austria Ag | Manufacturing a semiconductor device using electrochemical etching, semiconductor device and super junction semiconductor device |
| US9887259B2 (en) | 2014-06-23 | 2018-02-06 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
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| JP6375743B2 (en) | 2014-07-15 | 2018-08-22 | 富士電機株式会社 | Manufacturing method of semiconductor device |
| US9882044B2 (en) | 2014-08-19 | 2018-01-30 | Vishay-Siliconix | Edge termination for super-junction MOSFETs |
| US9881997B2 (en) | 2015-04-02 | 2018-01-30 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method of semiconductor device |
| JP6477174B2 (en) | 2015-04-02 | 2019-03-06 | 富士電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| JP6824115B2 (en) | 2017-06-19 | 2021-02-03 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor devices |
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