TWI500122B - Semiconductor package substrate and manufacturing method of the same - Google Patents
Semiconductor package substrate and manufacturing method of the same Download PDFInfo
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- TWI500122B TWI500122B TW100107258A TW100107258A TWI500122B TW I500122 B TWI500122 B TW I500122B TW 100107258 A TW100107258 A TW 100107258A TW 100107258 A TW100107258 A TW 100107258A TW I500122 B TWI500122 B TW I500122B
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
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- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Description
本發明係關於一種半導體元件搭載用基板及其製造方法，尤其係關於一種使用金屬板之半導體元件搭載用基板及其製造方法。The present invention relates to a substrate for mounting a semiconductor element and a method of manufacturing the same, and more particularly to a substrate for mounting a semiconductor element using a metal plate and a method of manufacturing the same.
習知以來，已知有如下半導體裝置之製造方法：於由金屬板所構成之引線框架材料的兩面形成電鍍層，於背面側形成抗蝕刻光阻膜後，於表面側以電鍍層作為遮罩而進行半蝕刻，且搭載半導體元件而進行打線及樹脂密封(例如，參照專利文獻1)。於該半導體裝置之製造方法中，進行樹脂密封後，去除引線框架材料之背面側的抗蝕刻光阻膜且進行蝕刻加工，而使外部連接端子部突出並獨立，來製造半導體裝置。Conventionally, there has been known a method of manufacturing a semiconductor device in which a plating layer is formed on both surfaces of a lead frame material made of a metal plate, an etching resist film is formed on the back side, and a plating layer is used as a mask on the surface side. On the other hand, a semiconductor device is mounted and a wire is bonded and a resin is sealed (for example, see Patent Document 1). In the method of manufacturing a semiconductor device, after the resin sealing is performed, the etching resist film on the back side of the lead frame material is removed and etched, and the external connection terminal portion is protruded and independent, thereby manufacturing a semiconductor device.
又，作為類似之半導體裝置，於外部連接端子部成為樹脂突起之構造的半導體裝置中，首先，使用在形成於金屬板之既定位置的凹部以電鍍形成有金屬膜之引線框架材料，且於形成有金屬膜之側搭載半導體元件後，將該半導體元件之電極與形成於引線框架材料之凹部中的金屬膜(鍍膜)進行打線，且以樹脂密封半導體元件及導線。接著，於最後蝕刻並完全去除引線框架材料之金屬板，藉此形成由金屬膜包覆之樹脂突起成為外部連接端子部的半導體裝置(參照專利文獻2)。用於該半導體裝置之引線框架材料，金屬板未殘留於外部連接端子部，形成於引線框架材料之金屬膜(鍍膜)殘留於外部連接端子部。Further, in a similar semiconductor device, in a semiconductor device having a structure in which an external connection terminal portion is a resin bump, first, a lead frame material in which a metal film is formed by plating in a concave portion formed at a predetermined position of a metal plate is used and formed. After the semiconductor element is mounted on the side of the metal film, the electrode of the semiconductor element and the metal film (plating film) formed in the concave portion of the lead frame material are wired, and the semiconductor element and the lead are sealed with a resin. Then, the metal plate of the lead frame material is finally etched and completely removed, thereby forming a semiconductor device in which the resin protrusion covered with the metal film serves as an external connection terminal portion (see Patent Document 2). In the lead frame material used in the semiconductor device, the metal plate does not remain in the external connection terminal portion, and the metal film (plating film) formed on the lead frame material remains in the external connection terminal portion.
[習知技術文獻][Practical Technical Literature]
[專利文獻][Patent Literature]
[專利文獻1]日本特開2001-24135號公報[Patent Document 1] Japanese Patent Laid-Open Publication No. 2001-24135
[專利文獻2]日本特開平10-247715號公報[Patent Document 2] Japanese Patent Laid-Open No. Hei 10-247715
然而，專利文獻1之圖1所揭示之構成中，於引線框架材料之背面側形成有抗蝕刻光阻膜且以光阻膜覆蓋背面側之狀態下，進行自引線框架材料之表面側的加工(既定深度之蝕刻加工)，至半導體裝置之樹脂密封為止。However, in the configuration disclosed in FIG. 1 of Patent Document 1, the surface of the lead frame material is processed in a state in which an etching resist film is formed on the back side of the lead frame material and the back side is covered with a photoresist film. (etching processing at a predetermined depth) until the resin of the semiconductor device is sealed.
於該方法中，於由一個業者總括地進行自引線框架材料之加工至半導體裝置之製造為止之情形時雖然無問題，然而於僅將已加工之引線框架材料作為半導體元件搭載用基板出貨，而由另一業者製造半導體裝置之情形時，必須於已去除抗蝕刻光阻膜之狀態下出貨，因此存在無法應對該種企業形態之問題。即，由於附加去除形成於半導體元件搭載用基板之背面之抗蝕刻光阻膜的步驟，而造成製造成本之增加，因此對半導體裝置之製造業者方而言，通常要求於已去除多餘的抗蝕刻光阻膜之狀態下交貨。In this method, there is no problem in the case where the processing of the lead frame material is performed in a semiconductor device, and only the processed lead frame material is shipped as a substrate for mounting the semiconductor element. On the other hand, when a semiconductor device is manufactured by another manufacturer, it is necessary to ship the state in which the etching resist film has been removed. Therefore, there is a problem that the form of the enterprise cannot be handled. In other words, since the step of removing the etching resist film formed on the back surface of the semiconductor element mounting substrate is added, the manufacturing cost is increased, and therefore, it is generally required for the manufacturer of the semiconductor device to remove excess etching resistance. Delivery under the condition of the photoresist film.
另一方面，於專利文獻1所揭示之構成中，若於已去除背面側之抗蝕刻劑之狀態下交納半導體元件搭載用基板，則由於形成於背面側之電鍍層係自金屬板之平面凸起形成，故於其後之半導體裝置之製造步驟中，存在依次搬送至多個步驟而進行加工時，容易對背面側之電鍍層造成損傷之問題。尤其，存在如下問題：於進行蝕刻加工時，蝕刻液自所產生之損傷部分滲透，而蝕刻加工由金屬板所構成之引線框架材料。On the other hand, in the configuration disclosed in Patent Document 1, when the semiconductor element mounting substrate is removed in a state where the etching resist on the back side is removed, the plating layer formed on the back side is convex from the plane of the metal plate. Since it is formed, in the subsequent manufacturing steps of the semiconductor device, there is a problem that the plating layer on the back side is easily damaged when it is sequentially transferred to a plurality of steps for processing. In particular, there is a problem that the etching liquid penetrates from the damaged portion generated during the etching process, and the lead frame material composed of the metal plate is etched.
因此，本發明之目的在於，提供一種半導體元件搭載用基板及其製造方法，其即使於作為半導體元件搭載用基板進行出貨之情形時，亦可於其後之半導體裝置之組裝步驟，防止因搬送等引起之電鍍層的損傷。In view of the above, it is an object of the present invention to provide a semiconductor element mounting substrate and a method of manufacturing the same, which can prevent the cause of the semiconductor device assembly step after the semiconductor device mounting substrate is shipped. Damage to the plating layer caused by transportation, etc.
為達成上述目的，第1發明之半導體元件搭載用基板係於金屬板之兩面形成有既定形狀之電鍍層，其特徵在於：該電鍍層包含保護電鍍層，該保護電鍍層係在形成於該金屬基板之表面的凹部內，以比該凹部之深度更薄的厚度形成。In order to achieve the above object, a semiconductor element mounting substrate according to a first aspect of the invention is characterized in that a plating layer having a predetermined shape is formed on both surfaces of a metal plate, wherein the plating layer includes a protective plating layer formed on the metal. The recess in the surface of the substrate is formed to have a thickness thinner than the depth of the recess.
藉此，即使於搬送時，由於金屬板之平坦部與搬送構件接觸，而可防止電鍍層與搬送構件之接觸，故可保護電鍍層，防止損傷。Thereby, even when the flat portion of the metal plate is in contact with the conveying member at the time of conveyance, contact between the plating layer and the conveying member can be prevented, so that the plating layer can be protected from damage.
第2發明係如第1發明之半導體元件搭載用基板，其中，該保護電鍍層形成於該金屬板一面；另一面，係於該金屬板之未實施加工之部分形成有該電鍍層。According to a second aspect of the invention, in the semiconductor element mounting substrate of the first aspect of the invention, the protective plating layer is formed on one surface of the metal plate, and the other surface is formed on a portion of the metal plate that is not processed.
藉此，可僅於必須保護電鍍層之面形成凹部及凹部內之電鍍層，而以最低限度之加工進行電鍍層之保護。Thereby, the plating layer in the concave portion and the concave portion can be formed only on the surface where the plating layer must be protected, and the plating layer can be protected with a minimum of processing.
第3發明係如第2發明之半導體元件用基板，其中，該另一面係搭載有半導體元件之面；該一面係背面。According to a third aspect of the invention, in the substrate for a semiconductor device of the second aspect of the invention, the surface of the semiconductor element is mounted on the other surface;
藉此，可於搬送及處理中，保護與軌道及平台等支承構件之接觸較多的半導體元件搭載用基板背面之電鍍層，從而可使半導體元件搭載用基板符合半導體裝置製造製程之實際情況。By this, it is possible to protect the plating layer on the back surface of the semiconductor element mounting substrate which is in contact with the supporting member such as the rail and the platform during the transportation and the processing, and the semiconductor element mounting substrate can conform to the actual manufacturing process of the semiconductor device.
第4發明之半導體元件搭載用基板之製造方法係於金屬板之兩面形成既定形狀之電鍍層，其特徵在於包含：光阻遮罩形成步驟，其於該金屬板之兩面形成用以形成既定形狀之電鍍層的光阻遮罩；蝕刻步驟，其於該金屬板之一面，藉由蝕刻加工而於該金屬板之自該光阻遮罩露出之部分形成凹部；第1電鍍步驟，其於該凹部內以比該凹部之深度更薄的厚度形成電鍍層；及第2電鍍步驟，其於該金屬板之另一面形成電鍍層。A method of manufacturing a substrate for mounting a semiconductor element according to a fourth aspect of the invention is to form a plating layer having a predetermined shape on both surfaces of a metal plate, comprising: a photoresist mask forming step of forming a predetermined shape on both surfaces of the metal plate a photoresist mask of the electroplated layer; an etching step of forming a recess on a portion of the metal plate exposed from the photoresist mask on one side of the metal plate; a first electroplating step A plating layer is formed in the recess by a thickness thinner than a depth of the recess; and a second plating step of forming a plating layer on the other surface of the metal plate.
藉此，凹部內之電鍍層形成為低於金屬板之表面，故可製造能夠保護凹部內之電鍍層之構成的半導體元件用基板。Thereby, since the plating layer in the concave portion is formed to be lower than the surface of the metal plate, a substrate for a semiconductor element capable of protecting the plating layer in the concave portion can be manufactured.
第5發明係如第4發明之半導體元件搭載用基板之製造方法，其中，該光阻遮罩用於該蝕刻步驟及該電鍍步驟之兩者。According to a fourth aspect of the invention, in the method of manufacturing a substrate for mounting a semiconductor element according to the fourth aspect of the invention, the photoresist mask is used for both the etching step and the plating step.
藉此，可於1次之光阻遮罩之形成中進行蝕刻步驟及電鍍步驟之兩者之加工，而可幾乎不增加實質性之步驟數量地製造具有電鍍層保護之效果的半導體元件搭載用基板。By this, it is possible to perform both the etching step and the plating step in the formation of the primary photoresist mask, and it is possible to manufacture the semiconductor element having the effect of protecting the plating layer without substantially increasing the number of steps. Substrate.
第6發明係如第5發明之半導體元件搭載用基板之製造方法，其中，該蝕刻步驟係對未搭載有半導體元件之背面進行。According to a sixth aspect of the invention, in the method of manufacturing a substrate for mounting a semiconductor element according to the fifth aspect of the invention, the etching step is performed on a back surface on which the semiconductor element is not mounted.
藉此，可保護搬送及處理時與支承構件接觸機會較多之背面之電鍍層，而可配合製造製程有效地防止電鍍層之損傷。Thereby, it is possible to protect the plating layer on the back side which has a large chance of contact with the supporting member during transportation and processing, and it is possible to effectively prevent the damage of the plating layer in accordance with the manufacturing process.
第7發明係如第6發明之半導體元件搭載用基板之製造方法，其中，該第1電鍍步驟及該第2電鍍步驟同時進行。According to a seventh aspect of the invention, in the method of manufacturing a substrate for mounting a semiconductor element according to the sixth aspect of the invention, the first plating step and the second plating step are simultaneously performed.
藉此，可同時加工兩面，從而可不於表面側及背面側進行差別較大之步驟，且低成本並短時間地進行半導體元件搭載用基板之製造。By this, it is possible to process both surfaces at the same time, and it is possible to carry out the manufacture of the semiconductor element mounting substrate at a low cost and in a short time without performing a step which is largely different on the front side and the back side.
第8發明係如第7發明之半導體元件搭載用基板之製造方法，其進一步包含：光阻遮罩去除步驟，其於該第1電鍍步驟及該第2電鍍步驟之後，去除該光阻遮罩；第2光阻遮罩形成步驟，其形成覆蓋搭載有半導體元件之表面側之電鍍層的光阻遮罩、及覆蓋該背面整體之光阻遮罩；及半蝕刻步驟，其對該表面側進行半蝕刻加工。According to a seventh aspect of the invention, there is provided a method of manufacturing a substrate for mounting a semiconductor element according to the seventh aspect of the invention, further comprising: a photoresist mask removing step of removing the photoresist mask after the first plating step and the second plating step a second photoresist mask forming step of forming a photoresist mask covering the plating layer on the surface side on which the semiconductor element is mounted, and a photoresist mask covering the entire back surface; and a half etching step on the surface side Perform a half etching process.
藉此，可於表面側形成容易搭載半導體元件、且容易進行打線之段差，從而半導體元件搭載功能可維持如習知般之水準。Thereby, the semiconductor element can be easily mounted on the surface side, and the step of wire bonding can be easily performed, and the semiconductor element mounting function can be maintained at a level as is conventional.
第9發明係如第8發明之半導體裝置搭載用基板之製造方法，其中，覆蓋該表面側之電鍍層的該光阻遮罩，係形成為覆蓋大於該電鍍層之區域。According to a ninth aspect of the invention, in the method of manufacturing a substrate for mounting a semiconductor device according to the eighth aspect of the invention, the photoresist mask covering the plating layer on the front side is formed to cover a region larger than the plating layer.
藉此，即使於進行半蝕刻時，亦因電鍍層成為遮蔽之狀態而可防止毛邊及脫落等造成不良之原因。Thereby, even when the half etching is performed, the plating layer is shielded, and it is possible to prevent defects such as burrs and falling off.
根據本發明，可於半導體裝置之組裝步驟中，防止電鍍層之損傷。According to the present invention, damage of the plating layer can be prevented in the assembly step of the semiconductor device.
以下，參照圖式，對用以實施本發明之形態進行說明。Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
圖1係表示使用本發明之實施形態之半導體元件搭載用基板30製造的半導體裝置之構成之一例之剖面圖。於圖1中，本實施形態之半導體元件搭載用基板30具有金屬板10及電鍍層20、21。又，使用本實施形態之半導體元件搭載用基板30製造之半導體裝置，除具備半導體元件搭載用基板30以外，還具備半導體元件50、導線60及密封樹脂70。FIG. 1 is a cross-sectional view showing an example of a configuration of a semiconductor device manufactured by using the semiconductor element mounting substrate 30 of the embodiment of the present invention. In the semiconductor element mounting substrate 30 of the present embodiment, the metal plate 10 and the plating layers 20 and 21 are provided. In addition, the semiconductor device manufactured by the semiconductor element mounting substrate 30 of the present embodiment includes the semiconductor element 50, the lead 60, and the sealing resin 70 in addition to the semiconductor element mounting substrate 30.
於本實施形態之半導體元件用搭載基板30中，金屬板10係由含有銅、鐵等之金屬材料所構成之基板。只要由具有導電性及適當之機械強度的金屬材料構成金屬板10，則可使用各種金屬基板。In the semiconductor device mounting substrate 30 of the present embodiment, the metal plate 10 is a substrate made of a metal material such as copper or iron. As long as the metal plate 10 is made of a metal material having electrical conductivity and appropriate mechanical strength, various metal substrates can be used.
金屬板10係於背面側具有平坦部11a及凹部12。又，於表面側具有端子區域13a及半導體元件搭載區域14。再者，金屬板10之厚度亦可為例如100 μm～數百μm左右之厚度。又，半導體元件搭載區域14之厚度亦可為例如金屬板10整體厚度(自最下部起至最上部為止之厚度)之1/3左右的厚度。The metal plate 10 has a flat portion 11a and a recess 12 on the back side. Moreover, the terminal region 13a and the semiconductor element mounting region 14 are provided on the surface side. Further, the thickness of the metal plate 10 may be, for example, a thickness of about 100 μm to several hundreds μm. Moreover, the thickness of the semiconductor element mounting region 14 may be, for example, about 1/3 of the thickness of the entire metal plate 10 (thickness from the lowermost portion to the uppermost portion).
此處，所謂表面側係指於半導體裝置製造製程之後續步驟中搭載有半導體元件50之側，其相反側未搭載半導體元件50，且將用作外部連接端子之側稱作背面側。Here, the front side refers to the side on which the semiconductor element 50 is mounted in the subsequent step of the semiconductor device manufacturing process, and the semiconductor element 50 is not mounted on the opposite side, and the side serving as the external connection terminal is referred to as the back side.
背面側之平坦部11a係直接利用金屬板10之面的面。即，其係未實施任何蝕刻等加工之平坦面。另一方面，凹部12係藉由蝕刻腐蝕並去除平坦部11a形成之凹陷部分。於凹部12之內部，即凹部12之底面部，形成有電鍍層20。電鍍層20係以比凹部12之深度更薄之厚度，且覆蓋凹部12之底面整體之方式形成。因此，於將半導體元件搭載用基板30載置於搬送機構或處理裝置之支承構件，例如軌道或平台上之情形時，則成為平坦部11a與支承構件之面接觸，而電鍍層20不與支承構件之面接觸之狀態。由此，可防止電鍍層20由於與支承構件之摩擦而被削除並損傷。如此，電鍍層20具有藉由凹部12而被保護之形狀，故亦可稱為保護電鍍層20。The flat portion 11a on the back side directly uses the surface of the surface of the metal plate 10. That is, it is a flat surface which is not subjected to any processing such as etching. On the other hand, the concave portion 12 is etched by etching and removes the depressed portion formed by the flat portion 11a. A plating layer 20 is formed inside the recess 12, that is, on the bottom surface of the recess 12. The plating layer 20 is formed to have a thickness thinner than the depth of the concave portion 12 and to cover the entire bottom surface of the concave portion 12. Therefore, when the semiconductor element mounting substrate 30 is placed on a support member of a transport mechanism or a processing device, for example, on a rail or a land, the flat portion 11a is brought into surface contact with the support member, and the plating layer 20 is not supported. The state of the surface contact of the component. Thereby, the plating layer 20 can be prevented from being removed and damaged by friction with the supporting member. Thus, since the plating layer 20 has a shape protected by the concave portion 12, it can also be referred to as a protective plating layer 20.
再者，電鍍層20可由各種金屬材料而構成，亦可由適合於鎳、鈀、金等之構裝之材料而構成。此等材料既可單獨使用，亦可使用複數種。於使用複數種金屬材料之情形時，亦可積層各種金屬層而構成電鍍層20。Further, the plating layer 20 may be composed of various metal materials, or may be composed of a material suitable for the structure of nickel, palladium, gold, or the like. These materials can be used alone or in multiples. When a plurality of metal materials are used, various metal layers may be laminated to form the plating layer 20.
另一方面，關於表面側，端子區域13a成為直接利用金屬板10之面的面，且半導體元件搭載區域14成為藉由蝕刻而去除金屬板10之區域。其中，亦存在對端子區域13a施加少量蝕刻加工作為電鍍預處理之情形。On the other hand, on the surface side, the terminal region 13a is a surface on which the surface of the metal plate 10 is directly used, and the semiconductor element mounting region 14 is a region where the metal plate 10 is removed by etching. Among them, there is also a case where a small amount of etching processing is applied to the terminal region 13a as a plating pretreatment.
半導體元件50係形成有既定之電子電路之IC(Integrated Circuit，積體電路)。於半導體元件50，形成有用以對電子電路進行電氣訊號及電力之輸入輸出的電極51。半導體元件50通常以未形成有電極51之下表面52作為下側，且以形成有電極51之電極形成面53為上側，經由晶片接合材料而搭載於半導體元件搭載用基板30上。又，藉由使用導線60進行打線，而將半導體元件50之電極51連接至形成於半導體元件搭載用基板30之端子區域13a中之電鍍層21，藉此進行半導體元件50之電子電路與端子區域13a的電氣連接。由此，將電極51及電鍍層21連接之導線60較佳為較短而非較長，故應使電極51與電鍍層21之高度接近，且半導體元件搭載區域14構成為蝕刻金屬板10之表面側的凹陷面。The semiconductor element 50 is an IC (Integrated Circuit) in which a predetermined electronic circuit is formed. An electrode 51 for inputting and outputting electrical signals and electric power to an electronic circuit is formed in the semiconductor element 50. The semiconductor element 50 is generally mounted on the semiconductor element mounting substrate 30 via the die bonding material, with the lower surface 52 of the electrode 51 not being formed as the lower side and the electrode forming surface 53 on which the electrode 51 is formed. Further, by wire bonding using the wire 60, the electrode 51 of the semiconductor element 50 is connected to the plating layer 21 formed in the terminal region 13a of the semiconductor element mounting substrate 30, whereby the electronic circuit and the terminal region of the semiconductor device 50 are performed. 13a electrical connection. Therefore, the wire 60 connecting the electrode 51 and the plating layer 21 is preferably shorter rather than longer, so that the height of the electrode 51 and the plating layer 21 should be close, and the semiconductor element mounting region 14 is configured to etch the metal plate 10. The concave surface on the surface side.
又，端子區域13a係連接有導線60之面，故為了可靠地進行連接，較佳為儘可能平坦之面。因此，以金屬板10之表面之未實施加工的平坦面之部分作為端子區域13a。其中，亦存在為了去除氧化膜，而對端子區域13a施加有極少量之蝕刻處理作為電鍍預處理之情形。Further, since the terminal region 13a is connected to the surface of the wire 60, it is preferable to be as flat as possible in order to reliably connect. Therefore, a portion of the flat surface of the surface of the metal plate 10 that has not been processed is used as the terminal region 13a. Among them, in order to remove the oxide film, a very small amount of etching treatment is applied to the terminal region 13a as a plating pretreatment.
為使打線容易，而於該端子區域13a之表面上形成有電鍍層21。電鍍層21與電鍍層20同樣地，可使用各種金屬材料。例如，亦可根據用途而使用適合於鎳、鈀、金等之構裝之金屬材料。In order to facilitate wire bonding, a plating layer 21 is formed on the surface of the terminal region 13a. As the plating layer 21, similarly to the plating layer 20, various metal materials can be used. For example, a metal material suitable for a nickel, palladium, gold or the like may be used depending on the application.
如此，本實施形態之半導體元件搭載用基板30構成為，可於構裝半導體元件50而製造半導體裝置之步驟中，防止半導體元件搭載用基板30之背面側的電鍍層20之損傷，且可於表面側可靠地打線於電鍍層21上。In the semiconductor device mounting substrate 30 of the present embodiment, the semiconductor device 50 can be prevented from being damaged by the plating layer 20 on the back side of the semiconductor device mounting substrate 30 in the step of manufacturing the semiconductor device. The surface side is reliably wired on the plating layer 21.
其次，使用圖2，對本實施形態之半導體元件搭載用基板30之製造方法進行說明。圖2係表示本實施形態之半導體元件搭載用基板30之製造方法的一系列步驟之例之圖。再者，對與已使用圖1說明之構成要素相同的構成要素，附上與圖1相同之參考符號，並省略其說明。Next, a method of manufacturing the semiconductor element mounting substrate 30 of the present embodiment will be described with reference to FIG. FIG. 2 is a view showing an example of a series of steps in the method of manufacturing the semiconductor element mounting substrate 30 of the present embodiment. It is to be noted that the same reference numerals are attached to the same components as those in FIG. 1 and the description thereof will be omitted.
圖2(A)係表示光阻遮罩形成步驟之一例之圖。於光阻遮罩形成步驟中，藉由光阻而於金屬板10之兩面形成遮罩40、41。只要可發揮作為遮罩40、41之功能，光阻即可使用包含塗布型之各種光阻，例如，亦可使用乾膜光阻。將乾膜光阻黏貼(積層)於金屬板10之表面11、13上，且使用玻璃遮罩進行曝光，並於曝光後進行顯影形成既定之圖案，藉此可形成光阻遮罩40、41。光阻圖案係以如下方式形成：對金屬板10之背面側的表面11而言，使形成凹部12之部分露出，且對金屬板10之表面側的表面13而言，使形成電鍍層之部分露出。Fig. 2(A) is a view showing an example of a step of forming a photoresist mask. In the photoresist mask forming step, masks 40, 41 are formed on both sides of the metal plate 10 by photoresist. As long as the functions as the masks 40 and 41 can be exerted, various photoresists including a coating type can be used as the photoresist, and for example, dry film photoresist can also be used. The dry film resist is adhered (laminated) on the surfaces 11 and 13 of the metal plate 10, and exposed using a glass mask, and developed after exposure to form a predetermined pattern, whereby the photoresist masks 40, 41 can be formed. . The photoresist pattern is formed in such a manner that the surface 11 on the back side of the metal plate 10 is exposed, and the surface 13 on the surface side of the metal plate 10 is formed into a portion on which the plating layer is formed. Exposed.
此處，如圖1中所說明般，表面側係於半導體裝置製造製程之步驟中搭載有半導體元件50之面，而背面側係未搭載半導體元件50之面。Here, as described in FIG. 1, the surface side is mounted on the surface of the semiconductor device 50 in the step of manufacturing the semiconductor device, and the surface on the back side is not mounted on the semiconductor element 50.
再者，光阻亦可使用可用於蝕刻加工及電鍍加工之兩者中之光阻。本實施形態之半導體元件搭載用基板之製造方法中，於背面側進行蝕刻加工後，緊接著於已進行蝕刻加工之部位上進行電鍍加工，此時，可使用相同之光阻。Further, the photoresist can also use a photoresist which can be used in both etching processing and electroplating processing. In the method of manufacturing a semiconductor element mounting substrate of the present embodiment, after the etching process is performed on the back surface side, the plating process is performed next to the portion where the etching process has been performed. In this case, the same photoresist can be used.
又，於表面側，亦可使用與背面側相同之光阻，因此可以完全相同之步驟進行表面側與背面側之光阻遮罩形成步驟，故可簡化光阻遮罩形成步驟之整體。Further, since the same photoresist as the back surface side can be used on the surface side, the step of forming the photoresist mask on the front side and the back side can be performed in the same step, so that the entire step of forming the photoresist mask can be simplified.
再者，只要為可用於蝕刻加工及電鍍加工之兩者之光阻，則光阻即可使用乾膜光阻、塗布型光阻等各種光阻。Further, as long as it is used for both the etching process and the plating process, various photoresists such as a dry film photoresist and a coating photoresist can be used as the photoresist.
圖2(B)係表示蝕刻步驟之一例之圖。於蝕刻步驟中，對金屬板10之背面側進行蝕刻加工，而於未被光阻遮罩40覆蓋之金屬板10之露出面形成凹部12。再者，凹部12以深度大於後續電鍍步驟中形成之電鍍層20的厚度之方式形成。藉此，即使於凹部12之底部表面形成有電鍍層20，在搬送時電鍍層20亦不接觸於軌道或裝置，而是與金屬板10之表面11接觸，從而可保護電鍍層20。Fig. 2(B) is a view showing an example of an etching step. In the etching step, the back side of the metal plate 10 is etched, and the concave portion 12 is formed on the exposed surface of the metal plate 10 not covered by the photoresist mask 40. Further, the recess 12 is formed to a depth greater than the thickness of the plating layer 20 formed in the subsequent plating step. Thereby, even if the plating layer 20 is formed on the bottom surface of the concave portion 12, the plating layer 20 does not contact the rail or the device at the time of conveyance, but is in contact with the surface 11 of the metal plate 10, so that the plating layer 20 can be protected.
凹部12之深度可藉由與電鍍層20之厚度的關係而相對地確定。通常，於電鍍步驟中，預先確定使電鍍層20之厚度為多少μm。然後，使用電流密度、時間、電鍍液濃度等參數進行控制，以使電鍍層20成為既定之厚度。由此，藉由預先步驟而確定使電鍍層20之厚度為多少μm，故以比電鍍層20之既定厚度更深的方式而確定凹部12之深度。再者，電鍍層20之厚度亦可根據用途及目的而適當地確定，例如，亦可形成為厚度2～5 μm左右之電鍍層20。The depth of the recess 12 can be relatively determined by the relationship with the thickness of the plating layer 20. Usually, in the plating step, it is predetermined how many μm the thickness of the plating layer 20 is made. Then, control is performed using parameters such as current density, time, and plating solution concentration so that the plating layer 20 has a predetermined thickness. Thus, by determining the thickness of the plating layer 20 by a predetermined number of steps in advance, the depth of the concave portion 12 is determined to be deeper than the predetermined thickness of the plating layer 20. Further, the thickness of the plating layer 20 can be appropriately determined depending on the use and purpose, and for example, the plating layer 20 having a thickness of about 2 to 5 μm can also be formed.
又，針對使凹部12比電鍍層20之厚度深何種程度，亦可根據各種用途及目的而確定。然而，若大幅度深於電鍍層20之厚度，則所需之蝕刻加工時間將長至必要以上，因此亦可以稍微深於電鍍層20之厚度的方式形成凹部12。例如，亦可形成較電鍍層20之厚度深2 μm左右之凹部12。Further, how much the recessed portion 12 is deeper than the thickness of the plating layer 20 can be determined according to various uses and purposes. However, if the thickness of the plating layer 20 is substantially deeper, the etching processing time required will be longer than necessary, so that the recess 12 can be formed slightly deeper than the thickness of the plating layer 20. For example, a recess 12 having a thickness of about 2 μm deeper than the plating layer 20 may be formed.
蝕刻加工可藉由各種蝕刻方法而進行，例如，亦可進行濕式之噴淋式蝕刻加工。此外，雖然費用上變高，然而亦能以乾式蝕刻來進行蝕刻加工。The etching process can be performed by various etching methods, for example, wet-type shower etching. Further, although the cost is high, the etching process can also be performed by dry etching.
圖2(C)係表示電鍍步驟之一例之圖。於電鍍步驟中，藉由電鍍而於光阻遮罩40、41之露出部分形成有電鍍層20、21。於金屬板10之表面側，於未實施任何加工之平坦面13上形成有電鍍層21，於背面側，於凹部12之底面的表面上形成有電鍍層20。Fig. 2(C) is a view showing an example of a plating step. In the electroplating step, the plating layers 20, 21 are formed on the exposed portions of the photoresist masks 40, 41 by electroplating. On the surface side of the metal plate 10, a plating layer 21 is formed on the flat surface 13 where no processing is performed, and a plating layer 20 is formed on the surface of the bottom surface of the concave portion 12 on the back side.
於所形成之電鍍層20、21在表面側與背面側為相同之電鍍層20、21之情形時，可同時對表面背面進行電鍍處理。電鍍處理亦可藉由例如濕式之電性電鍍而進行。於採用電性電鍍之情形時，如上所述，可藉由電流密度、電鍍時間、電鍍液之濃度等而控制所形成之電鍍層20、21的厚度。In the case where the plating layers 20, 21 are formed in the same plating layer 20, 21 on the front side and the back side, the surface back surface can be simultaneously plated. The plating treatment can also be carried out by, for example, wet electrical plating. In the case of electroplating, as described above, the thickness of the formed plating layers 20, 21 can be controlled by current density, plating time, concentration of the plating solution, and the like.
又，於背面側與表面側，亦可使電鍍層20、21為不同構成。例如，可掩蓋背面側，而於表面側形成適合於導線接合之電鍍層21。或者相反地，亦可掩蓋表面側，而於背面側形成適合於焊錫連接之電鍍層20。如此，即使於顧客對表面側或背面側有特殊要求之情形時，亦可藉由對有要求之面個別進行電鍍處理而細緻地應對。Further, the plating layers 20 and 21 may have different configurations on the back side and the front side. For example, the back side can be masked, and a plating layer 21 suitable for wire bonding can be formed on the surface side. Or conversely, the surface side may be masked, and a plating layer 20 suitable for solder bonding may be formed on the back side. In this way, even when the customer has special requirements on the front side or the back side, it is possible to deal with it in detail by performing plating treatment on the required surface.
圖2(D)係表示光阻遮罩去除步驟之一例之圖。於光阻遮罩去除步驟中，對背面側、表面側之兩者均去除光阻遮罩40、41。再者，對於光阻遮罩40、41之去除，例如，若光阻為乾膜光阻，則可剝離光阻而進行；若光阻為塗布型光阻，則可藉由溶解去除而進行。Fig. 2(D) is a view showing an example of the step of removing the photoresist mask. In the photoresist mask removing step, the photoresist masks 40, 41 are removed for both the back side and the surface side. Furthermore, for the removal of the photoresist masks 40 and 41, for example, if the photoresist is a dry film photoresist, the photoresist can be stripped; if the photoresist is a coating photoresist, it can be removed by dissolution. .
圖2(E)係表示第2光阻遮罩形成步驟之一例之圖。於第2光阻遮罩形成步驟中，以覆蓋整個金屬板10之背面側與表面側之電鍍層21的方式形成光阻遮罩42、43。於背面側，包含形成有電鍍層20之凹部12以及金屬板10之表面本身即端子區域11a在內，全部由光阻遮罩42覆蓋。Fig. 2(E) is a view showing an example of the step of forming the second photoresist mask. In the second photoresist mask forming step, the photoresist masks 42, 43 are formed so as to cover the plating layer 21 on the back side and the front side of the entire metal plate 10. On the back side, the recess 12 including the plating layer 20 and the surface of the metal plate 10 itself, that is, the terminal region 11a, are all covered by the photoresist mask 42.
另一方面，於表面側，以覆蓋形成有電鍍層21之區域的方式形成光阻遮罩43。此時，光阻遮罩43亦可以覆蓋大於電鍍層21之區域的方式形成。於表面側形成覆蓋較電鍍層21之區域更大之區域的光阻遮罩43之目的是為了使電鍍層21下方之金屬板10不由之後的蝕刻加工而被蝕刻加工。於電鍍層21下方之金屬板10被蝕刻之情形時，電鍍層21成為「遮蔽」之狀態，且該部分成為毛邊及脫落等不良之原因，因此為防止該問題，亦可使金屬板10殘留於較電鍍層21之區域更大(廣)的區域中。又，亦考慮使金屬板10殘留於與電鍍層21之區域相同之區域中，然而加工較為困難，而使金屬板10殘留於略大於電鍍層21之區域中較為容易。On the other hand, on the surface side, the photoresist mask 43 is formed so as to cover the region where the plating layer 21 is formed. At this time, the photoresist mask 43 may be formed to cover a region larger than the plating layer 21. The purpose of forming the photoresist mask 43 on the surface side to cover a region larger than the region of the plating layer 21 is to cause the metal plate 10 under the plating layer 21 to be etched without being subjected to subsequent etching. When the metal plate 10 under the plating layer 21 is etched, the plating layer 21 is "shielded", and this portion is a cause of defects such as burrs and detachment. Therefore, in order to prevent this problem, the metal plate 10 may remain. In a larger (wide) area than the area of the plating layer 21. Further, it is also considered that the metal plate 10 remains in the same region as the region of the plating layer 21, but processing is difficult, and it is easy to leave the metal plate 10 slightly larger than the region of the plating layer 21.
再者，於第2光阻遮罩形成步驟中，可積層乾膜光阻作為光阻，亦可使用其他光阻。Further, in the second photoresist mask forming step, a dry film photoresist may be laminated as a photoresist, and other photoresist may be used.
藉由該步驟，對於半導體元件搭載面而言，可針對端子區域11a可靠地殘留金屬板10中未實施加工之部分，而利用適合於打線之平坦面。By this step, the semiconductor element mounting surface can reliably retain the portion of the metal plate 10 that is not processed in the terminal region 11a, and a flat surface suitable for wire bonding can be used.
圖2(F)係表示半蝕刻步驟之一例之圖。於半蝕刻步驟中，自金屬板10之表面側起進行半蝕刻加工。針對未形成有電鍍層21之表面13，藉由半蝕刻步驟自金屬板10之表面側起蝕刻必要之深度。於半蝕刻步驟中，蝕刻加工於中途停止，故半導體元件搭載用基板30成為端子部不個別地分離獨立，而全部連結之狀態。藉由半蝕刻步驟，而經半蝕刻加工之部分成為半導體元件搭載區域14，未經半蝕刻加工而殘留之部分成為端子區域13a。Fig. 2(F) is a view showing an example of a half etching step. In the half etching step, a half etching process is performed from the surface side of the metal plate 10. For the surface 13 on which the plating layer 21 is not formed, the necessary depth is etched from the surface side of the metal plate 10 by a half etching step. In the half etching step, the etching process is stopped in the middle, and the semiconductor element mounting substrate 30 is in a state in which the terminal portions are not individually separated and are all connected. By the half etching step, the half-etched portion becomes the semiconductor element mounting region 14, and the portion remaining without the half etching process becomes the terminal region 13a.
半蝕刻加工之深度亦可為例如金屬板10之深度的2/3左右。例如，於金屬板10為100～200 μm之情形時，亦可蝕刻至60～140 μm左右之深度。The depth of the half etching process may be, for example, about 2/3 of the depth of the metal plate 10. For example, when the metal plate 10 is 100 to 200 μm, it may be etched to a depth of about 60 to 140 μm.
再者，半蝕刻步驟中，由第2光阻遮罩42完全覆蓋背面側，故除噴淋式之濕式蝕刻以外，亦可採用浸漬式之濕式蝕刻。又，根據需要亦可使用乾式蝕刻，與圖2(B)中所說明之蝕刻步驟相同。Further, in the half etching step, since the second photoresist mask 42 completely covers the back surface side, in addition to the shower type wet etching, immersion type wet etching may be employed. Further, dry etching may be used as needed, which is the same as the etching step described in FIG. 2(B).
圖2(G)係表示第2光阻遮罩去除步驟之一例之圖。於第2光阻遮罩去除步驟中，完全去除金屬板10之背面側及表面側的第2光阻遮罩42、43。然後，完成於金屬板10之表面11、12、13、14上一概未形成光阻遮罩42、43之可直接出貨之形態的半導體元件搭載用基板30。Fig. 2(G) is a view showing an example of the second photoresist mask removing step. In the second photoresist mask removing step, the second photoresist masks 42, 43 on the back side and the front side of the metal plate 10 are completely removed. Then, the semiconductor element mounting substrate 30 in which the photoresist masks 42 and 43 are directly formed on the surfaces 11 , 12 , 13 , and 14 of the metal plate 10 is not formed.
藉由該製造方法而製造之半導體元件搭載用基板30係如圖2(G)所示，背面側之電鍍層20形成於金屬板10之凹部12之中，故於後續步驟中，可防止於搬送時金屬板10之平坦部接觸於軌道等，且可防止與電鍍層20接觸。As shown in FIG. 2(G), the semiconductor element mounting substrate 30 manufactured by the manufacturing method is formed in the concave portion 12 of the metal plate 10 in the back surface side, so that it can be prevented in the subsequent step. The flat portion of the metal plate 10 is in contact with the rail or the like at the time of conveyance, and can be prevented from coming into contact with the plating layer 20.
再者，圖2(G)所示之半導體元件搭載用基板30於出貨後，為半導體裝置製造業者所使用，且如圖1中所示，將半導體元件50搭載於半導體元件搭載區域14上，使用導線60進行打線，並以密封樹脂70進行樹脂密封。In addition, the semiconductor device mounting substrate 30 shown in FIG. 2(G) is used by a semiconductor device manufacturer after shipment, and the semiconductor device 50 is mounted on the semiconductor device mounting region 14 as shown in FIG. The wire 60 is used for wire bonding, and the sealing resin 70 is used for resin sealing.
圖3係表示使用本實施形態之半導體元件搭載用基板30，而於半導體製造製程之後續步驟中完成的半導體裝置之一例之圖。FIG. 3 is a view showing an example of a semiconductor device completed in a subsequent step of the semiconductor manufacturing process using the semiconductor element mounting substrate 30 of the present embodiment.
使用本實施形態之半導體元件搭載用基板30的半導體裝置與圖1所示之半導體裝置的不同之處在於，半導體元件搭載部16與端子部15分離。圖3可認為是後續步驟中圖1之下一步驟。成為圖1所示之狀態後，以背面側之電鍍層20作為遮罩，而進行金屬板10之背面之蝕刻加工。藉此，端子部15與半導體元件部16分離，而完成半導體裝置作為半導體組件之集合體。此後，藉由切斷並分割各個半導體組件，而完成各個半導體裝置。The semiconductor device using the semiconductor element mounting substrate 30 of the present embodiment is different from the semiconductor device shown in FIG. 1 in that the semiconductor element mounting portion 16 is separated from the terminal portion 15. Figure 3 can be considered as a step in Figure 1 in the subsequent steps. After the state shown in FIG. 1 is obtained, the back surface side plating layer 20 is used as a mask, and the back surface of the metal plate 10 is etched. Thereby, the terminal portion 15 is separated from the semiconductor element portion 16, and the semiconductor device is completed as an assembly of semiconductor components. Thereafter, each semiconductor device is completed by cutting and dividing the respective semiconductor components.
[實施例][Examples]
對實施圖2所示之半導體裝置之製造方法，而製造本實施形態之半導體裝置的實施例進行說明。再者，對於至此為止之說明所對應的構成要素，附上相同之參考符號，且省略其說明。An embodiment in which the semiconductor device of the present embodiment is manufactured by the method of manufacturing the semiconductor device shown in Fig. 2 will be described. The constituent elements corresponding to the description so far are denoted by the same reference numerals, and the description thereof will be omitted.
準備板厚為0.125 mm之銅材料作為金屬板10。首先，於光阻遮罩形成步驟中，於金屬板10之兩面，積層厚度20 μm之乾膜光阻。乾膜光阻採用可用於電鍍加工及蝕刻加工之兩者之通常市售之商品。A copper material having a thickness of 0.125 mm was prepared as the metal plate 10. First, in the photoresist mask forming step, a dry film photoresist having a thickness of 20 μm is laminated on both sides of the metal plate 10. Dry film photoresists are commonly used commercially available products for both electroplating and etching processes.
此後，使用為表面側用及背面側用而準備且形成有既定圖案之玻璃遮罩進行曝光、顯影，而如圖2(A)所示，於金屬板10之兩面形成光阻遮罩40、41。Thereafter, exposure and development are performed using a glass mask prepared for the front side and the back side and formed with a predetermined pattern, and as shown in FIG. 2(A), a photoresist mask 40 is formed on both surfaces of the metal plate 10, 41.
於蝕刻步驟中，如圖2(B)所示，僅於背面側進行蝕刻加工，藉此於金屬板10上形成凹部12。蝕刻加工係將溶解銅材料之蝕刻液噴射至背面側而進行處理。又，凹部12之深度設定為大於其次形成之電鍍層20的厚度約2 μm左右之值。In the etching step, as shown in FIG. 2(B), the etching process is performed only on the back side, whereby the concave portion 12 is formed on the metal plate 10. In the etching process, the etching liquid in which the copper material is dissolved is sprayed onto the back side and processed. Further, the depth of the concave portion 12 is set to be larger than the thickness of the plating layer 20 formed second, which is about 2 μm.
於電鍍步驟中，如圖2(C)所示，於金屬板10之背面側及表面側依次實施鍍鎳、鍍鈀及鍍金，而使成為積層金屬層之電鍍層20、21以2.15 μm之總厚度形成。於該階段中，背面側之電鍍層20以於金屬板10之凹部12的內部覆蓋凹部12之底面的方式形成。In the electroplating step, as shown in FIG. 2(C), nickel plating, palladium plating, and gold plating are sequentially performed on the back surface side and the surface side of the metal plate 10, and the plating layers 20 and 21 which become the laminated metal layers are 2.15 μm. The total thickness is formed. At this stage, the plating layer 20 on the back side is formed so that the inside of the concave portion 12 of the metal plate 10 covers the bottom surface of the concave portion 12.
於光阻遮罩去除步驟中，如圖2(D)所示，剝離去除乾膜光阻之光阻遮罩40、41。In the photoresist mask removing step, as shown in FIG. 2(D), the dry film photoresist photoresist masks 40, 41 are peeled off.
於第2光阻遮罩形成步驟中，首先，於金屬板10之兩面再次積層乾膜光阻。然後，對表面側，使用玻璃遮罩進行曝光，並經過顯影，而如圖2(E)所示，形成略大於電鍍層21之區域且包含電鍍層21的光阻遮罩43。對背面側，則形成覆蓋整個表面之光阻遮罩42。In the second photoresist mask forming step, first, a dry film photoresist is laminated on both sides of the metal plate 10. Then, on the surface side, exposure is performed using a glass mask, and development is performed, and as shown in FIG. 2(E), a photoresist mask 43 including a plating layer 21 which is slightly larger than the region of the plating layer 21 is formed. On the back side, a photoresist mask 42 covering the entire surface is formed.
於半蝕刻步驟中，如圖2(F)所示，進行半蝕刻加工，而自金屬板10之表面側的表面13形成深度約85 μm之深掘凹陷。經半蝕刻之部分成為半導體元件搭載區域14。In the half etching step, as shown in Fig. 2(F), a half etching process is performed, and a deep sag having a depth of about 85 μm is formed from the surface 13 on the surface side of the metal plate 10. The half-etched portion becomes the semiconductor element mounting region 14.
於第2光阻遮罩去除步驟中，如圖2(G)所示，剝離去除背面側及表面側之光阻42、43。於該步驟中，完成本實施例之半導體元件搭載用基板10。In the second photoresist mask removing step, as shown in FIG. 2(G), the photoresists 42, 43 on the back side and the front side are removed. In this step, the semiconductor element mounting substrate 10 of the present embodiment is completed.
於如此所得之半導體元件搭載用基板30上，以與習知相同之步驟搭載半導體元件50，並使用導線60進行接合，而將半導體元件50之電極51與形成於端子區域13a上之電鍍層21連接。其後，藉由使用密封樹脂70進行樹脂密封而結束製造步驟，成為圖1所示之狀態。又，若觀察金屬板10之背面側的電鍍層20上是否有瑕疵產生，發現完全未產生瑕疵。On the semiconductor element mounting substrate 30 thus obtained, the semiconductor element 50 is mounted in the same manner as in the prior art, and the bonding is performed using the wires 60, and the electrode 51 of the semiconductor element 50 and the plating layer 21 formed on the terminal region 13a are formed. connection. Thereafter, the resin sealing is performed by using the sealing resin 70, and the manufacturing process is completed, and the state shown in FIG. 1 is obtained. Further, when the occurrence of flaws on the plating layer 20 on the back side of the metal plate 10 was observed, it was found that no flaw was generated at all.
如此，根據本實施例之半導體元件搭載用基板30及其製造方法，可確認為即使於後續步驟中形成半導體裝置之情形時，形成於金屬板10之背面側的電鍍層20亦不會產生損傷，而可保護電鍍層20之構成。As described above, according to the semiconductor element mounting substrate 30 of the present embodiment and the method of manufacturing the same, it can be confirmed that the plating layer 20 formed on the back side of the metal plate 10 does not cause damage even when the semiconductor device is formed in the subsequent step. The composition of the plating layer 20 can be protected.
以上，對本發明之較佳實施例詳細地進行了說明，然而本發明不限定於上述之實施例，可不脫離本發明之範圍，對上述之實施例施加各種變形及置換。The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the embodiments described above, and various modifications and substitutions may be made to the above-described embodiments without departing from the scope of the invention.
[產業上之可利用性][Industrial availability]
本發明可用於半導體組件等半導體裝置中所使用之引線框架等半導體元件搭載用基板。The present invention can be applied to a semiconductor element mounting substrate such as a lead frame used in a semiconductor device such as a semiconductor device.
10．．．金屬板10. . . Metal plate
11、13．．．表面11,13. . . surface
11a．．．平坦部11a. . . Flat part
12．．．凹部12. . . Concave
13a．．．端子區域13a. . . Terminal area
14．．．半導體元件搭載區域14. . . Semiconductor component mounting area
15．．．端子部15. . . Terminal part
16．．．半導體元件搭載部16. . . Semiconductor component mounting unit
20．．．電鍍層(保護電鍍層)20. . . Plating layer (protective plating)
21．．．電鍍層twenty one. . . Plating
30．．．半導體元件搭載用基板30. . . Semiconductor component mounting substrate
40、41、42、43．．．光阻遮罩40, 41, 42, 43. . . Photoresist mask
5．．．半導體元件5. . . Semiconductor component
51．．．半導體元件之電極51. . . Electrode of semiconductor component
52．．．半導體元件之下表面52. . . Surface under the semiconductor component
53．．．半導體元件之電極形成面53. . . Electrode forming surface of semiconductor element
60．．．導線60. . . wire
70．．．密封樹脂70. . . Sealing resin
圖1係表示使用本實施形態之半導體元件搭載用基板30的半導體裝置之構成之一例之剖面圖。FIG. 1 is a cross-sectional view showing an example of a configuration of a semiconductor device using the semiconductor element mounting substrate 30 of the present embodiment.
圖2係表示本實施形態之半導體元件搭載用基板30之製造方法的一系列步驟例之圖。圖2(A)係表示光阻遮罩形成步驟之一例之圖。圖2(B)係表示蝕刻步驟之一例之圖。圖2(C)係表示電鍍步驟之一例之圖。圖2(D)係表示光阻遮罩去除步驟之一例之圖。圖2(E)係表示第2光阻遮罩形成步驟之一例之圖。圖2(F)係表示半蝕刻步驟之一例之圖。圖2(G)係表示第2光阻遮罩去除步驟之一例之圖。FIG. 2 is a view showing a series of steps of a method of manufacturing the semiconductor element mounting substrate 30 of the present embodiment. Fig. 2(A) is a view showing an example of a step of forming a photoresist mask. Fig. 2(B) is a view showing an example of an etching step. Fig. 2(C) is a view showing an example of a plating step. Fig. 2(D) is a view showing an example of the step of removing the photoresist mask. Fig. 2(E) is a view showing an example of the step of forming the second photoresist mask. Fig. 2(F) is a view showing an example of a half etching step. Fig. 2(G) is a view showing an example of the second photoresist mask removing step.
圖3係表示使用本實施形態之半導體元件搭載用基板30而完成之半導體裝置的一例之圖。FIG. 3 is a view showing an example of a semiconductor device completed by using the semiconductor element mounting substrate 30 of the present embodiment.
10．．．金屬板10. . . Metal plate
11a．．．平坦部11a. . . Flat part
12．．．凹部12. . . Concave
13a．．．端子區域13a. . . Terminal area
14．．．半導體元件搭載區域14. . . Semiconductor component mounting area
20．．．電鍍層(保護電鍍層)20. . . Plating layer (protective plating)
21．．．電鍍層twenty one. . . Plating
30．．．半導體元件搭載用基板30. . . Semiconductor component mounting substrate
50．．．半導體元件50. . . Semiconductor component
51．．．半導體元件之電極51. . . Electrode of semiconductor component
52．．．半導體元件之下表面52. . . Surface under the semiconductor component
53．．．半導體元件之電極形成面53. . . Electrode forming surface of semiconductor element
60．．．導線60. . . wire
70．．．密封樹脂70. . . Sealing resin
Claims (8)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010052273A JP5578704B2 (en) | 2010-03-09 | 2010-03-09 | Semiconductor device mounting substrate and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201145476A TW201145476A (en) | 2011-12-16 |
| TWI500122B true TWI500122B (en) | 2015-09-11 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100107258A TWI500122B (en) | 2010-03-09 | 2011-03-04 | Semiconductor package substrate and manufacturing method of the same |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP5578704B2 (en) |
| KR (1) | KR101307030B1 (en) |
| CN (1) | CN102194763B (en) |
| TW (1) | TWI500122B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI765068B (en) * | 2017-07-19 | 2022-05-21 | 日商大口電材股份有限公司 | Semiconductor element mounting substrate and method for manufacturing the same |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI427839B (en) * | 2010-12-03 | 2014-02-21 | Ind Tech Res Inst | Apparatuses and methods of depositing film patterns |
| WO2013114985A1 (en) * | 2012-02-01 | 2013-08-08 | 株式会社パイオラックスメディカルデバイス | Guide wire |
| JP5878054B2 (en) * | 2012-03-27 | 2016-03-08 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method and semiconductor device |
| JP2014027266A (en) * | 2012-06-20 | 2014-02-06 | Asahi Kasei Electronics Co Ltd | Semiconductor package and manufacturing method of the same |
| JP6044936B2 (en) * | 2013-04-24 | 2016-12-14 | Ｓｈマテリアル株式会社 | Manufacturing method of semiconductor device mounting substrate |
| JP6539928B2 (en) * | 2015-12-14 | 2019-07-10 | 大口マテリアル株式会社 | Lead frame for mounting a semiconductor device and method of manufacturing the same |
| JP6792106B2 (en) * | 2017-03-30 | 2020-11-25 | スピードファム株式会社 | Work carrier and manufacturing method of work carrier |
| JP7408886B2 (en) | 2020-03-31 | 2024-01-09 | 長華科技股▲ふん▼有限公司 | Substrate for mounting semiconductor elements |
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| JPS62286260A (en) * | 1986-06-04 | 1987-12-12 | Oki Electric Ind Co Ltd | Substrate connection structure of semiconductor |
| JPH10242367A (en) * | 1997-02-25 | 1998-09-11 | Fujitsu Ltd | Semiconductor device and its manufacture |
| JP2000100843A (en) * | 1998-09-17 | 2000-04-07 | Mitsubishi Electric Corp | Semiconductor package and manufacture thereof |
| JP2000260897A (en) * | 1999-03-10 | 2000-09-22 | Shinko Electric Ind Co Ltd | Carrier for semiconductor device and manufacture of the carrier, and manufacture of the semiconductor device |
| JP2001358254A (en) * | 2000-06-15 | 2001-12-26 | Shinko Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101095527B1 (en) * | 2009-11-04 | 2011-12-19 | 엘지이노텍 주식회사 | Leadframe and method of manufacturig same |
-
2010
- 2010-03-09 JP JP2010052273A patent/JP5578704B2/en active Active
-
2011
- 2011-03-03 KR KR1020110019018A patent/KR101307030B1/en not_active IP Right Cessation
- 2011-03-04 CN CN201110054138.6A patent/CN102194763B/en not_active Expired - Fee Related
- 2011-03-04 TW TW100107258A patent/TWI500122B/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62286260A (en) * | 1986-06-04 | 1987-12-12 | Oki Electric Ind Co Ltd | Substrate connection structure of semiconductor |
| JPH10242367A (en) * | 1997-02-25 | 1998-09-11 | Fujitsu Ltd | Semiconductor device and its manufacture |
| JP2000100843A (en) * | 1998-09-17 | 2000-04-07 | Mitsubishi Electric Corp | Semiconductor package and manufacture thereof |
| JP2000260897A (en) * | 1999-03-10 | 2000-09-22 | Shinko Electric Ind Co Ltd | Carrier for semiconductor device and manufacture of the carrier, and manufacture of the semiconductor device |
| JP2001358254A (en) * | 2000-06-15 | 2001-12-26 | Shinko Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI765068B (en) * | 2017-07-19 | 2022-05-21 | 日商大口電材股份有限公司 | Semiconductor element mounting substrate and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101307030B1 (en) | 2013-09-11 |
| CN102194763A (en) | 2011-09-21 |
| JP5578704B2 (en) | 2014-08-27 |
| TW201145476A (en) | 2011-12-16 |
| JP2011187742A (en) | 2011-09-22 |
| CN102194763B (en) | 2015-09-23 |
| KR20110102181A (en) | 2011-09-16 |
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