TWI495105B - 金屬閘極奈米線薄膜電晶體元件及其製造方法 - Google Patents
金屬閘極奈米線薄膜電晶體元件及其製造方法 Download PDFInfo
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- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical group [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 6
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- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Description
本發明係關於一種金屬閘極奈米線薄膜電晶體元件，特別是一種利用後段金屬堆疊技術達成三維堆疊結構之金屬閘極奈米線薄膜電晶體元件。
近幾年來，利用互補式金屬氧化物半導體(CMOS,Complementary Metal-Oxide-Semiconductor)製程所開發的矽上單晶片技術已成為目前系統整合的主流，而為了達成超高元件陣列密度，平面電晶體元件的單元尺寸微縮已經達到製程的極限，傳統用矽晶圓作為基礎之半導體元件製程慢慢地遇到了技術瓶頸與投資成本不斷增加的問題，因此，相關研發人員試著用奈米級分子來製造「奈米級電晶體」，藉由在相同晶片面積下放進比傳統多出數百倍之電晶體數量的技術，以達到半導體製程微縮化的目標。然而複雜的三維堆疊製程步驟，使得元件單元製造方法和連接間的寄生電阻效應成為最大的問題。
美國專利公開第US 2005/0176226 A1號，係揭露一多層堆疊的底部閘極薄膜電晶體結構，實現高影像點的陣列排列，雖然其製程容易，但是元件尺寸很難繼續微縮。
美國專利公開第US 2008/0293246 A1號，係揭露一具有奈米線通道以及一矽化物底層接觸之垂直場效應電晶體，其藉由垂直閘極結構來控制電晶體通道電位，能有較好的閘極控制能力，但卻需要六道光罩來實現元件陣列結構。
美國專利公開第US 2010/0330759 A1號，係揭露一具有圍繞式閘極
(surrounding gate)之奈米線電晶體，雖然圍繞式閘極的結構，只需要四道光罩就能實現元件陣列結構，但是元件特性將受到複雜的閘極結構製程的影響。
美國專利公開第US 2009/0065852 A1中，係揭露一種具有奈米線通道之非揮發性記憶體裝置及其製造方法，雖然其利用隔離裝置(spacer)的殘留得到微小尺寸的奈米線，但同時需要額外的硬遮蔽層製程，來形成隔離裝置奈米線。同時在硬遮蔽層底部過度蝕刻的側邊，閘極介電層很難均勻覆蓋在閘極表面。
因此，如何設計出一可繼續微縮元件尺寸、減少實現元件陣列結構之光罩數、元件特性不容易受到閘極結構製程影響以及閘極介電層可均勻覆蓋在閘極表面之金屬閘極奈米線薄膜電晶體元件及其製造方法，便成為相關廠商以及相關研發人員所共同努力的目標。
本發明人有鑑於習知之金屬閘極奈米線薄膜電晶體元件無法繼續微縮元件尺寸、實現元件陣列結構之光罩數過多、元件特性容易受到閘極結構製程影響以及閘極介電層無法均勻覆蓋在閘極表面之缺失，乃積極著手進行開發，以期可以改進上述既有之缺點，經過不斷地試驗及努力，終於開發出本發明。
本發明之目的，係為提供一可繼續微縮元件尺寸、減少實現元件陣列結構之光罩數、元件特性不容易受到閘極結構製程影響以及閘極介電層可均勻覆蓋在閘極表面之金屬閘極奈米線薄膜電晶體元件及其製造方法。
為了達成上述之目的，本發明之金屬閘極奈米線薄膜電晶體元件，係
包括：一半導體基板包括：一基底層；一內層介電層，係堆疊於該基底層之上；至少一金屬線層係各自包括至少一互相被該內層介電層隔開之金屬線，該至少一金屬線之其中一金屬線係為金屬線閘極；以及至少一中介窗(via)層係堆疊於該金屬線層之上，該等中介窗層其中之一中介窗層係具有一凹槽，且該等中介窗層係各自包括至少一互相被該內層介電層隔開之中介窗，且該中介窗係各自堆疊於該等金屬線之其中之一，該至少一中介窗中堆疊於該金屬線閘極之上之中介窗係為閘極中介窗，該閘極中介窗內包括二奈米線通道；一介電層係堆疊於該半導體基板之上；一半導體薄膜(semiconductor film)層係堆疊於該介電層上；一導電層係形成於該半導體薄膜層上；一源極係形成於相鄰該閘極中介窗之其中一中介窗位置處，並與該閘極中介窗之一端連結；以及一汲極係形成於相鄰該閘極中介窗之另一中介窗位置處，並與該閘極中介窗之另一端連結。
為了達成上述之目的，本發明之金屬閘極奈米線薄膜電晶體元件之製造方法，係應用於一半導體基板，該半導體基板係包括一基底層、一內層介電層、至少一層金屬線層以及至少一層中介窗(via)層，該內層介電層係堆疊於該基底層之上，該等金屬線層係與該等中介窗層交錯堆疊，該等金屬
線層係各自包括至少一互相被該內層介電層隔開之金屬線，該至少一金屬線之其中一金屬線係為金屬線閘極，該中介窗層係堆疊於該金屬線層之上，且該等中介窗層係各自包括至少一互相被該內層介電層隔開之中介窗，且該中介窗係各自堆疊於該等金屬線之其中之一，該至少一中介窗中堆疊於該金屬線閘極之上之中介窗係為閘極中介窗，該金屬閘極奈米線薄膜電晶體元件之製造方法係包括步驟：對該半導體基板表面進行研磨；對該等中介窗層之其中之一中介窗層進行蝕刻；於該半導體基板上堆疊一介電層；於該介電層上堆疊一半導體薄膜(semiconductor film)層；於該半導體薄膜層上形成一導電層；於相鄰該閘極中介窗之二中介窗位置處分別定義出一源極區域以及一汲極區域，其中該源極區域以及該汲極區域係分別與該閘極中介窗之兩端連結；形成一源極、一汲極，並形成二奈米線通道於該閘極中介窗內；以及活化該源極以及該汲極內之導電層。
透過上述之裝置及方法，本發明相較於先前技術具有下列優點：1.不需用高解析的圖樣光罩，就可以製造出低於50奈米線寬的奈米線薄膜電晶體陣列；2.本發明利用現有的頂層金屬層(top metal)和頂層中介窗(top via)再加上額外一道源/汲極區定義，共只要三道光罩就能實現元件陣列結構；
3.本發明先利用金屬線層來定義底部閘極，然後再作奈米線通道，這種後奈米線的製作方法，降低奈米線受後續製程的影響，使得奈米線更單純而穩定；以及4.本發明先將金屬線層的過度蝕刻，利用原本金屬導線間的絕綠層的側邊當作硬遮蔽層，而之後閘極介電層可以均勻的覆蓋在底部閘極金屬線層上，大幅降低隔離裝置(spacer)奈米線的製程困難度。
為使熟悉該項技藝人士瞭解本發明之目的，兹配合圖式將本發明之較佳實施例詳細說明如下。
請參考第一以及第六A至六H圖所示，本發明之金屬閘極奈米線薄膜電晶體元件(1)係包括：一半導體基板(10)包括：一基底層(100)；一內層介電層(101)，係堆疊於該基底層(100)之上；至少一金屬線層(102)係各自包括至少一互相被該內層介電層(101)隔開之金屬線(1020)，該至少一金屬線(1020)之其中一金屬線(1020)係為金屬線閘極(1020a)；以及至少一中介窗層(103)係堆疊於該金屬線層(102)之上，該等中介窗層(103)其中之一中介窗層(103)係具有一凹槽，且該等中介窗層(103)係各自包括至少一互相被該內層介電層(101)隔開之中介窗(1030)，且該中介窗(1030)係各自堆疊於該等金屬線(1020)之其中之一，該至少一中介窗(1030)中堆疊於該金屬線閘極(1020a)之上之中介窗(1030)係為閘極中介窗
(1030a)，該閘極中介窗(1030a)內包括二奈米線通道(1030a0)；一介電層(11)係堆疊於該半導體基板(10)之上；一半導體薄膜(semiconductor film)層(12)係堆疊於該介電層(11)上；一導電層(13)係形成於該半導體薄膜層(12)上；一源極(14)係形成於相鄰該閘極中介窗(1030a)之其中一中介窗(1030)位置處，並與該閘極中介窗(1030a)之一端連結；以及一汲極(15)係形成於相鄰該閘極中介窗(1030a)之另一中介窗(1030)位置處，並與該閘極中介窗(1030a)之另一端連結。
請參考第二以及第六A至六H圖所示，在本發明之一實施例中，該基底層(100)更包括：至少一互補式金屬氧化物半導體井(1000,CMOS Well,Complementary Metal-Oxide-Semiconductor Well)；至少一多晶矽薄膜電晶體(1001)，係堆疊於該互補式金屬氧化物半導體井(1000)之上；至少一淺溝渠隔離(STI,Shallow Trench Isolation)單元(1002)，係用以隔開該等互補式金屬氧化物半導體井(1000)，以及隔開該等多晶矽薄膜電晶體(1001)；以及至少一接觸通道(1003)，係用以連接該等多晶矽薄膜電晶體(1001)其中之一以及該等金屬線層(102)中最底層之金屬線層(102)。
其中該等中介窗層(103)係由鎢、銅或鋁所組成，但本發明並不以此為限，該等中介窗層(103)亦可以由其它高導電性之金屬組成。該等奈米線通道(1030a0)係為邊襯奈米線(spacer nanowire)。
該介電層(11)係為一氧化物-氮化物-氧化物層(ONO layer)、氧化物層、氧化物-氮化物層、氮化物層或高介電層(high K layer)。
該半導體薄膜層(12)係為矽薄膜層、鍺薄膜層或矽鍺薄膜層。
該導電層(13)係利用離子摻雜、沈積一矽化物層或臨場摻雜(in-situ doped)方式形成。
請參考第一、三以及四圖所示，其中第四圖係為本發明之金屬閘極奈米線薄膜電晶體元件(1)閘極偏壓大於臨界電壓1伏特、2伏特、3伏特、4伏特以及5伏特之汲極電流與汲極偏壓之關係圖，本發明之金屬閘極奈米線薄膜電晶體元件(1)與先前技術之相比，雖然需要較大的閘極偏壓才能工作，但先前技術之金屬閘極奈米線薄膜電晶體元件(1)並不能如同本發明之金屬閘極奈米線薄膜電晶體元件(1)利用低溫製程製作。
請參考第一、五以及第六A至六H圖所示，本發明之金屬閘極奈米線薄膜電晶體元件之製造方法(2)，係應用於一半導體基板(10)，該半導體基板(10)係包括一基底層(100)、一內層介電層(101)、至少一金屬線層(102)以及至少一中介窗(via)層(103)，該內層介電層(101)係堆疊於該基底層(100)之上，該等金屬線層(102)係各自包括至少一互相被該內層介電層(101)隔開之金屬線(1020)，該至少一金屬線(1020)之其中一金屬線(1020)係為金屬線閘極(1020a)，該中介窗層(103)係堆疊於該金屬線層(102)之上，且該等中介窗層(103)係各自包括至少一互相被該內層介電層(101)隔開之中介窗(1030)，且該中介窗(1030)係各自堆疊於該等金屬線(1020)之其中之一，該至少一中介窗(1030)中堆疊於該金屬線閘極(1020a)之上之中介窗(1030)係為閘極中介窗(1030a)，該金屬閘極奈米線薄膜電晶體元件之製造方法(2)係包括步驟：
步驟200：對該半導體基板(10)表面進行研磨；步驟201：對該等中介窗層(103)之其中之一中介窗層(103)進行蝕刻；步驟202：於該半導體基板(10)上堆疊一介電層(11)；步驟203：於該介電層(11)上堆疊一半導體薄膜(semiconductor film)層(12)；步驟204：於該半導體薄膜層(12)上形成一導電層(13)；步驟205：於相鄰該閘極中介窗(1030a)之二中介窗(1030)位置處分別定義出一源極區域(14a)以及一汲極區域(15a)，其中該源極區域(14a)以及該汲極區域(15a)係分別與該閘極中介窗(1030a)之兩端連結；步驟206：形成一源極(14)、一汲極(15)，並形成二奈米線通道(1030a0)於該閘極中介窗(1030a)內；以及步驟207：活化該源極(14)以及該汲極(15)內之導電層(13)。
在本發明之一實施例中，該基底層(100)更包括：至少一互補式金屬氧化物半導體井(1000,CMOS Well,Complementary Metal-Oxide-Semiconductor Well)；至少一多晶矽薄膜電晶體(1001)，係堆疊於該互補式金屬氧化物半導體井(1000)之上；至少一淺溝渠隔離(STI,Shallow Trench Isolation)單元(1002)，係用以隔開該等互補式金屬氧化物半導體井(1000)，以及隔開該等多晶矽薄膜電晶體(1001)；以及至少一接觸通道(1003)，係用以連接該等多晶矽薄膜電晶體(1001)
其中之一以及該等金屬線層(102)中最底層之金屬線層(102)。
其中該等中介窗層(1030)係由鎢、銅或鋁所組成，但本發明並不以此為限，該等中介窗層(103)亦可以由其它高導電性之金屬組成。其中該介電層(11)係為一氧化物-氮化物-氧化物層(ONO layer)。該半導體薄膜層(12)係為矽薄膜層、鍺薄膜層或矽鍺薄膜層。
其中該步驟200係利用化學機械研磨(CMP,chemical mechanical polishing)對該半導體基板(10)表面進行研磨。
該步驟201係對該等中介窗層(103)之其中之一中介窗層(103)進行過蝕刻(over etch)。
該步驟203係利用低溫化學氣相沈積(low temperature chemical vapor deposition)、超高頻等離子增強化學氣相沈積(VHFPECVD,very high frequency plasma enhanced chemical vapor deposition)形成該半導體薄膜層(12)。
該步驟204係利用離子摻雜、沈積一矽化物層或臨場摻雜(in-situ doped)方式完成。
該步驟206係利用乾式蝕刻形成邊襯奈米線(spacer nanowire)於該閘極中介窗(1030a)內而完成。
該步驟207係利用低於攝氏500度之低溫退火方式完成，在本發明之一較佳實施例中，該低溫退火方式係為微波退火方式，但本發明並不以此為限，在本發明之另一實施例中，該低溫退火方式係為雷射退火方式。
請參考第七圖所示，本發明之金屬閘極奈米線薄膜電晶體元件(1)以及金屬閘極奈米線薄膜電晶體元件之製造方法(2)可以應用於一元件陣列結
構，將該源極(14)當作一接地線，該汲極(15)當作一位元線，該金屬線閘極(1020a)當作一字元線，適當地設定該汲極(15)以及該金屬線閘極(1020a)之訊號，即可以控制所要工作之電晶體元件。在本發明之另一實施例中，係將該源極(14)當作一位元線，該汲極(15)當作一接地線。
由於本發明，先利用金屬線層來定義底部閘極，然後再作奈米線通道，因此可降低奈米線受後續製程的影響，使得奈米線更單純而穩定；再者本發明先將金屬線層過度蝕刻，利用原本金屬導線間的絕綠層的側邊當作硬遮敝層，使得閘極介電層可以均勻的覆蓋在底部閘極金屬線層上，大幅降低隔離裝置奈米線的製程困難度；此外，本發明不但可不需用高解析的圖樣光罩就可以製造出低於50奈米線寬的奈米線薄膜電晶體陣列，且利用低阻質的金屬線層作為底部閘極電極可進一步降低各元件單元間的寄生電阻問題；再者，其結構型態並非所屬技術領域中之人士所能輕易思及而達成者，實具有新穎性以及進步性無疑。
透過上述之詳細說明，即可充分顯示本發明之目的及功效上均具有實施之進步性，極具產業之利用性價值，且為目前市面上前所未見之新發明，完全符合發明專利要件，爰依法提出申請。唯以上所述著僅為本發明之較佳實施例而已，當不能用以限定本發明所實施之範圍。即凡依本發明專利範圍所作之均等變化與修飾，皆應屬於本發明專利涵蓋之範圍內，謹請 貴審查委員明鑑，並祈惠准，是所至禱。
(1)‧‧‧金屬閘極奈米線薄膜電晶體元件
(10)‧‧‧半導體基板
(100)‧‧‧基底層
(101)‧‧‧內層介電層
(102)‧‧‧金屬線層
(1020)‧‧‧金屬線
(1020a)‧‧‧金屬線閘極
(103)‧‧‧中介窗層
(1030)‧‧‧中介窗
(1030a)‧‧‧閘極中介窗
(1030a0)‧‧‧奈米線通道
(11)‧‧‧介電層
(12)‧‧‧半導體薄膜層
(13)‧‧‧導電層
(14)‧‧‧源極
(15)‧‧‧汲極
(2)‧‧‧金屬閘極奈米線薄膜電晶體元件之製造方法
200‧‧‧步驟
201‧‧‧步驟
202‧‧‧步驟
203‧‧‧步驟
204‧‧‧步驟
205‧‧‧步驟
206‧‧‧步驟
207‧‧‧步驟
第一圖係為本發明之金屬閘極奈米線薄膜電晶體元件之示意
圖；第二圖係為本發明之金屬閘極奈米線薄膜電晶體元件之一實施例；第三圖係為本發明之金屬閘極奈米線薄膜電晶體元件之汲極電流與閘極偏壓之關係圖；第四圖係為本發明之金屬閘極奈米線薄膜電晶體元件之汲極電流與汲極偏壓之關係圖；第五圖係為本發明之金屬閘極奈米線薄膜電晶體元件之製造方法之步驟流程圖；第六a圖係為本發明之金屬閘極奈米線薄膜電晶體元件之製造方法之步驟200之示意圖；第六b圖係為本發明之金屬閘極奈米線薄膜電晶體元件之製造方法之步驟201之示意圖；第六c圖係為本發明之金屬閘極奈米線薄膜電晶體元件之製造方法之步驟202之示意圖；第六d圖係為本發明之金屬閘極奈米線薄膜電晶體元件之製造方法之步驟203之示意圖；第六e圖係為本發明之金屬閘極奈米線薄膜電晶體元件之製造方法之步驟204之示意圖；第六f圖係為本發明之金屬閘極奈米線薄膜電晶體元件之製造方法之步驟205之示意圖；第六g圖係為本發明之金屬閘極奈米線薄膜電晶體元件之製造方法
之步驟206之示意圖；第六h圖係為本發明之金屬閘極奈米線薄膜電晶體元件之製造方法之步驟207之示意圖；以及第七圖係為本發明應用於元件陣列結構之示意圖。
(1)‧‧‧金屬閘極奈米線薄膜電晶體元件
(10)‧‧‧半導體基板
(100)‧‧‧基底層
(101)‧‧‧內層介電層
(102)‧‧‧金屬線層
(1020)‧‧‧金屬線
(1020a)‧‧‧金屬線閘極
(103)‧‧‧中介窗層
(1030)‧‧‧中介窗
(1030a)‧‧‧閘極中介窗
(1030a0)‧‧‧奈米線通道
(11)‧‧‧介電層
(12)‧‧‧半導體薄膜層
(13)‧‧‧導電層
(14)‧‧‧源極
(15)‧‧‧汲極
Claims (14)
- 一種金屬閘極奈米線薄膜電晶體元件，係包括：一半導體基板包括：一基底層；一內層介電層，係堆疊於該基底層之上；至少一金屬線層係各自包括至少一互相被該內層介電層隔開之金屬線，該至少一金屬線之其中一金屬線係為金屬線閘極；以及至少一中介窗(via)層係堆疊於該金屬線層之上，該等中介窗層其中之一中介窗層係具有一凹槽，且該等中介窗層係各自包括至少一互相被該內層介電層隔開之中介窗，且該中介窗係各自堆疊於該等金屬線之其中之一，該至少一中介窗中堆疊於該金屬線閘極之上之中介窗係為閘極中介窗，該閘極中介窗內包括二奈米線通道；一介電層係堆疊於該半導體基板之上；一半導體薄膜(semiconductor film)層係堆疊於該介電層上；一導電層係形成於該半導體薄膜層上；一源極係形成於相鄰該閘極中介窗之其中一中介窗位置處，並與該閘極中介窗之一端連結；以及一汲極係形成於相鄰該閘極中介窗之另一中介窗位置處，並與該閘極中介窗之另一端連結。
- 如申請專利範圍第1項所述之金屬閘極奈米線薄膜電晶體元件，其中該基底層更包括：至少一互補式金屬氧化物半導體井(CMOS Well,Complementary Metal-Oxide-Semiconductor Well)；至少一多晶矽薄膜電晶體，係堆疊於該互補式金屬氧化物半導體井之上；至少一淺溝渠隔離(STI,Shallow Trench Isolation)單元，係用以隔開該等互補式金屬氧化物半導體井，以及隔開該等多晶矽薄膜電晶體；以及至少一接觸通道，係用以連接該等多晶矽薄膜電晶體其中之一以及該等金屬線層中最底層之金屬線層。
- 如申請專利範圍第1或2項所述之金屬閘極奈米線薄膜電晶體元件，其中該介電層係為氧化物-氮化物-氧化物層(ONO layer)、氧化物層、氧化物-氮化物層、氮化物層或高介電層(high K layer)。
- 如申請專利範圍第1或2項所述之金屬閘極奈米線薄膜電晶體元件，其中該等奈米線通道係為邊襯奈米線(spacer nanowire)。
- 如申請專利範圍第1或2項所述之金屬閘極奈米線薄膜電晶體元件，其中該半導體薄膜層係為矽薄膜層、鍺薄膜層或矽鍺薄膜層。
- 一種金屬閘極奈米線薄膜電晶體元件之製造方法，係應用於一半導體基板，該半導體基板係包括一基底層、一內層介電層、至少一金屬線層以及至少一中介窗(via)層，該內層介電層係堆疊於該基底層之上，該等金屬線層係各自包括至少一互相被該內層介電層隔開之金屬線，該至少一金屬線之其中一金屬線係為金屬線閘極，該中介窗層係堆疊於該金屬線層之上，且該等中介窗層係各自包括至少一互相被該內層介電層隔開之中介窗，且該中介窗係各自堆疊於該等金屬線之其中之一，該至少一中介窗中堆疊於該金屬線閘極之上之中介窗係為閘極中介窗，該金屬閘極奈米線薄 膜電晶體元件之製造方法係包括步驟：對該半導體基板表面進行研磨；對該等中介窗層之之其中之一中介窗層進行蝕刻；於該半導體基板上堆疊一介電層；於該介電層上堆疊一半導體薄膜(semiconductor film)層；於該半導體薄膜層上形成一導電層；於相鄰該閘極中介窗之二中介窗位置處分別定義出一源極區域以及一汲極區域，其中該源極區域以及該汲極區域係分別與該閘極中介窗之兩端連結；形成一源極、一汲極，並形成二奈米線通道於該閘極中介窗內；以及活化該源極以及該汲極內之導電層。
- 如申請專利範圍第6項所述之金屬閘極奈米線薄膜電晶體元件之製造方法，其中該基底層更包括：至少一互補式金屬氧化物半導體井(CMOS Well,Complementary Metal-Oxide-Semiconductor Well)；至少一多晶矽薄膜電晶體，係堆疊於該互補式金屬氧化物半導體井之上；至少一淺溝渠隔離(STI,Shallow Trench Isolation)單元，係用以隔開該等互補式金屬氧化物半導體井，以及隔開該等多晶矽薄膜電晶體；以及至少一接觸通道，係用以連接該等多晶矽薄膜電晶體其中之一以及該等金屬線層中最底層之金屬線層。
- 如申請專利範圍第6或7項所述之金屬閘極奈米線薄膜電晶體元件之製造方法，其中該介電層係為一氧化物-氮化物-氧化物層(ONO layer)。
- 如申請專利範圍第6或7項所述之金屬閘極奈米線薄膜電晶體元件之製造方法，其中該對該半導體基板表面進行研磨步驟係利用化學機械研磨(CMP,chemical mechanical polishing)對該半導體基板表面進行研磨；該於該介電層上堆疊一半導體薄膜層步驟係利用低溫化學氣相沈積(low temperature chemical vapor deposition)、超高頻等離子增強化學氣相沈積(VHFPECVD,very high frequency plasma enhanced chemical vapor deposition)形成該半導體薄膜層。
- 如申請專利範圍第6或7項所述之金屬閘極奈米線薄膜電晶體元件之製造方法，其中該對該等中介窗層之其中之一中介窗層進行蝕刻步驟係對該等中介窗層之其中之一中介窗層進行過蝕刻(over etch)。
- 如申請專利範圍第6或7項所述之金屬閘極奈米線薄膜電晶體元件之製造方法，其中該於該半導體薄膜層堆疊一導電層步驟係利用離子摻雜、沈積一矽化物層或臨場摻雜(in-situ doped)方式完成。
- 如申請專利範圍第6或7項所述之金屬閘極奈米線薄膜電晶體元件之製造方法，其中該形成一源極、一汲極，並形成二奈米線通道於該閘極中介窗內步驟係利用乾式蝕刻形成邊襯奈米線(spacer nanowire)於該閘極中介窗內而完成。
- 如申請專利範圍第6或7項所述之金屬閘極奈米線薄膜電晶體元件之製造方法，其中該活化該源極以及該汲極內之導電層步驟係利用低於攝氏500度之低溫微波退火方式或低溫雷射退火方式完成。
- 如申請專利範圍第6或7項所述之金屬閘極奈米線薄膜電晶體元件之製造方法，其中該半導體薄膜層係為矽薄膜層、鍺薄膜層或矽鍺薄膜層。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100147632A TWI495105B (zh) | 2011-12-21 | 2011-12-21 | 金屬閘極奈米線薄膜電晶體元件及其製造方法 |
| US13/451,390 US20130161755A1 (en) | 2011-12-21 | 2012-04-19 | Thin film transistor and fabricating method |
| US14/107,742 US8987071B2 (en) | 2011-12-21 | 2013-12-16 | Thin film transistor and fabricating method |
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| TW100147632A TWI495105B (zh) | 2011-12-21 | 2011-12-21 | 金屬閘極奈米線薄膜電晶體元件及其製造方法 |
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| TWI495105B true TWI495105B (zh) | 2015-08-01 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5627103A (en) * | 1995-03-02 | 1997-05-06 | Sony Corporation | Method of thin film transistor formation with split polysilicon deposition |
| US20050179964A1 (en) * | 2002-07-11 | 2005-08-18 | Yoshihiro Izumi | Thin film phototransistor, active matrix substrate using the phototransistor, and image scanning device using the substrate |
| US20070037411A1 (en) * | 2001-09-17 | 2007-02-15 | Koninklijke Philips Electronics, N.V. | Method of manufacturing an electronic device |
| US20080293246A1 (en) * | 2005-05-23 | 2008-11-27 | International Business Machines Corporation | Vertical fet with nanowire channels and a silicided bottom contact |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7279385B2 (en) * | 2004-12-20 | 2007-10-09 | Macronix International Co., Ltd. | Flash memory device and manufacturing method thereof |
| EP1859481A1 (en) * | 2005-02-28 | 2007-11-28 | STMicroelectronics S.r.l. | Method for realising a nanometric circuit architecture between standard electronic components and semiconductor device obtained with said method |
| US7910467B2 (en) * | 2009-01-16 | 2011-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for treating layers of a gate stack |
| WO2011077946A1 (en) * | 2009-12-25 | 2011-06-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
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- 2011-12-21 TW TW100147632A patent/TWI495105B/zh not_active IP Right Cessation
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5627103A (en) * | 1995-03-02 | 1997-05-06 | Sony Corporation | Method of thin film transistor formation with split polysilicon deposition |
| US20070037411A1 (en) * | 2001-09-17 | 2007-02-15 | Koninklijke Philips Electronics, N.V. | Method of manufacturing an electronic device |
| US20050179964A1 (en) * | 2002-07-11 | 2005-08-18 | Yoshihiro Izumi | Thin film phototransistor, active matrix substrate using the phototransistor, and image scanning device using the substrate |
| US20080293246A1 (en) * | 2005-05-23 | 2008-11-27 | International Business Machines Corporation | Vertical fet with nanowire channels and a silicided bottom contact |
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| US20130161755A1 (en) | 2013-06-27 |
| TW201327818A (zh) | 2013-07-01 |
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