TWI489752B - Charge pump for controllable turn on time of sharing transistor - Google Patents

Description

A charge pump capable of controlling the on-time of a common transistor

The present invention relates to a charge pump (CP: Charge Pump), and more particularly to a charge pump capable of controlling a common transistor on-time, which is adjusted so that a control signal for controlling a source switching action and a control signal for controlling a common transistor action have A certain time difference, first turn on the common transistor to reach a certain voltage level, prevent the reverse current generated after the source switch is turned off, and maintain the dynamic current stability (Dynamic Current) loaded in the loop filter, which can be widely used. Most electronic/semiconductor components that require electronic circuitry.

Generally, the charge pump is an electronic circuit that adjusts a voltage in a loop filter according to a pulse signal to increase or decrease a specific amount of charge, and the pulse signal is in a phase locked loop (PLL: Phase Locked Loop). The main divider output frequency obtained by feedback and dividing the standard frequency of the standard frequency divider and the output signal of the voltage controlled oscillator is outputted after comparison in a phase detector (PFD: Phase Frequency Detector).

Therefore, if the phase detector (PFD) outputs a positive pulse, the charge pump supplies a current corresponding to the pulse amount of the capacitor to the capacitor provided in the loop filter, and accumulates the charge to increase the voltage; if the phase detector (PFD) outputs a negative pulse from which the charge pump reversely absorbs a current corresponding to the amount of charge of its pulse width, reducing the charge reduction voltage.

The prior charge pump, as shown in FIG. 1, includes: a current source portion that supplies current to the loop filter; a current sinking portion that sinks current from the loop filter; and a standard current supply portion that supplies a bias current And a sharing portion, each of which is connected to a source switch and an absorption switch provided in the current source portion and the current absorbing portion.

At this time, the current source portion is a current mirror structure composed of a PMOS transistor, and the current sink portion is a current mirror structure composed of an NMOS transistor.

The current source portion is connected between the voltage source (Vdd) and the output terminal (Vout), and includes: a source switch (P3) for loading a source control signal (UP_b) generated by the phase detector (PFD) a first control switch (P1, P2) in which a constant current (I _{UP, REF} ) is loaded as a control signal to the gate. At this time, the source switch (P3) turns on when the source control signal (UP_b) is 0, and causes the source current to flow from the voltage source (Vdd) to the loop filter through the output terminal (Vout), thereby Accumulate charge.

In addition, the current absorbing portion is connected between the output terminal (Vout) and a ground voltage (GND), and includes: an absorption switch (N3), and an absorption control signal (DN) generated by the phase detector (PFD) The second control switch (N1, N2) loads a constant current (I _{DN, REF} ) as a control signal in the standard current supply unit. At this time, the absorption switch (N3) turns on when the absorption control signal (DN) is 1, and causes the absorption current to flow from the output terminal (Vout) to the ground voltage (GND), thereby extruding the electric charge.

In addition, the sharing portion includes: a first common transistor (N5) having one terminal connected to one terminal of the source switch and the other terminal connected to a ground power source, and the gate is loaded by the gate An NMOS transistor of a source control signal (UP_b); a second common transistor (P5) having one terminal connected to one of the terminals of the absorbing switch and the other terminal connected to a voltage source loaded by the gate It is composed of a PMOS transistor that absorbs a control signal (DN).

In the previous source switch type charge pump, the gates of the source switch (P3) and the first common transistor (N5) form a common node with each other and load the same source control signal (UP_b); The gates of the absorption switch (N3) and the second common transistor (P5) form a common node with each other and load the same absorption control signal (DN).

Thus, since the same source control signal (UP_b) is simultaneously loaded to the source switch (P3) and the first common transistor (N5), the first share is shared when the source control signal (UP_b) transitions from 1 to 0. transistor (N5) remain open (Turn off) state, but the source switch (P3) will turn on (Turn on), a current source (I ₁₎ from the voltage source (Vdd) through the output terminal (Vout) Flow, accumulate charge in the loop filter. However, after accumulating the charge corresponding to the output pulse width of the phase detector, the source control signal (UP_b) is switched from 0 to 1, and the source switch (P3) is turned off, and the voltage source (Vdd) is turned off. supply, and the first common electrode crystals (N5) is turned on, the power supply connected to the ground, thereby cutting off the current source (I ₁₎ supplied.

At this time, since the source control signal (UP_b) is simultaneously loaded to the source switch (P3) and the first common transistor (N5), within the cutoff time of the source switch (P3), the first The common transistor (N5) is turned on, and the voltage source flows to the ground power source through the source switch (P3) and the first common transistor (N5) to lower the voltage of the node a.

Therefore, the output terminal (Vout) voltage is higher than the a node voltage, and the reverse current flows from the output terminal (Vout) through the first control switch (P2), the a node, and the first common transistor (N5), as shown in FIG. As shown, the value of the dynamic current (I ₃ ) supplied to the loop filter will be lowered, and the output voltage of the output terminal will gradually decrease, so that the voltage cannot be adjusted to the value required by the loop filter.

In addition, since the same absorption control signal (DN) is simultaneously loaded to the absorption switch (N3) and the second common transistor (P5), the second sharing is performed when the absorption control signal (DN) is switched from 0 to 1. The transistor (P5) remains in the Turn off state, but the absorption switch (N3) will turn "Turn on" and the absorption current (I ₂ ) flows from the loop filter through the output terminal (Vout) Ground the power supply (GND) to squeeze the charge.

However, after the radiation corresponding to the output of the phase detector output pulse width, the absorption control signal (DN) is switched from 1 to 0, the absorption switch (N3) is turned off, and the output terminal (Vout) is cut off. Supply, while the second common transistor (P5) is turned on, connected to a voltage source (Vdd), thereby cutting off the absorption current (I ₂ ) supply.

At this time, since the absorption control signal (DN) is simultaneously loaded to the absorption switch (N3) and the second common transistor (P5), within the cut-off time of the absorption switch (N3), the second The common transistor (P5) is turned on, and the voltage source (Vdd) flows to the ground power source through the absorption switch (N3) and the second common transistor (P5) to increase the voltage of the b node.

Therefore, the output terminal (Vout) voltage is lower than the b-node voltage, and the reverse current flows from the b-node through the second control switch (N2) to the output terminal (Vout), which changes the dynamic current supplied to the loop filter. (Dynamic current, I ₃ ) value, so that the voltage cannot be adjusted to the value required by the loop filter.

Thus, the reverse current caused by the unstable voltage of the source switch (P3) and the absorption switch (N3) at the terminal of the first and second common transistors will change the dynamics supplied to the loop filter. The current, abnormal operation occurs, and the voltage of the phase difference is correctly calibrated according to the phase comparison result of the phase detector to the voltage controlled oscillator, so that spurious phenomenon often occurs in the phase locked loop (PLL).

It is an object of the present invention to provide a power that can control the turn-on time of a shared transistor. The charge pump is adjusted so that the control signals of the cut-off source switch and the absorption switch and the control signal for turning on the common transistor have different conversion times, and the first common power is turned on before the source switch and the absorption switch are turned on. The crystal and the second common transistor cause a terminal of the common transistor to reach a certain voltage level, thereby preventing the abnormal current caused by the reverse current caused by the switching of the source switch and the absorption switch.

The object of the present invention is achieved by providing a charge pump capable of controlling a common transistor turn-on time by increasing or decreasing a charge adjustment loop filter based on a pulse signal of a standard frequency and an output frequency compared by a phase detector. The voltage charge pump includes: a current source unit having a source control signal generated by the phase detector and adjusted by a timing controller, and a source switch loaded in the gate; and a current sinking unit having a phase detection The device generates an absorption control signal adjusted by the timing controller and is loaded in the absorption switch of the gate; the sharing portion is composed of a common transistor connected to the source switch and the absorption switch; and a timing controller generates and supplies control The signal is adjusted to adjust the operating time of the common transistor and the operating time of the source switch and the absorption switch. In addition, the common portion of the present invention is characterized in that it comprises: a first common transistor having one terminal connected to a source switch composed of a PMOS transistor and the other terminal connected to a ground power source, and the timing control is loaded by the gate thereof The first shared control signal generated by the device is composed of an NMOS transistor; the second common transistor has one terminal connected to the absorption switch formed by the NMOS transistor and the other terminal connected to the electricity The voltage source is composed of a PMOS transistor whose gate is loaded with a second common control signal generated by the timing controller.

In addition, the shared controller of the present invention is characterized in that a first common control signal is generated to turn on the first common transistor before the source switch is turned off; and to generate a second common control signal to The second common transistor is turned on before the absorption switch is turned off.

In addition, the timing controller of the present invention is characterized in that: a first delay unit delays a signal generated by the phase detector; and a flip-flop that outputs an output signal of the first delay unit as an input One and second common control signals.

In addition, the first delay unit of the present invention is characterized in that an output terminal is connected to the source switch and the absorption switch, and the delayed source control signal is loaded to the gate of the source switch, and the delayed absorption control signal is carried. The gate of the absorption switch is input, the conversion time of the source control signal and the absorption control signal is recognized, and the on-times of the first and second common transistors are determined.

In addition, the present invention is characterized in that the trigger output terminal (Q) loads the first common control signal converted before the cut-off time of the source switch, and the gate to the first common transistor is turned on; The gate loaded to the second common transistor is turned on before the second common control signal of the cutoff time of the absorption switch.

In addition, the present invention is characterized in further comprising a second delay unit connected between the trigger output terminal (Qb) and the reset terminal (Rn) to load the output signal as a trigger. Resetting the signal, converting the first and second common control signals again, determining a time during which the first and second common transistors remain in an on state.

The invention turns on the common control signal of the common transistor, before the source control signal and the absorption control signal, so that the common transistor is turned on first, then the source switch and the absorption switch are cut off, and the source switch and the absorption switch are pre-set. The voltage level of the terminal is kept at a certain value, and the voltage difference between the output terminal and the output terminal is reduced, thereby preventing the reverse current from the output terminal when the source switch and the absorption switch are cut off, and supplementing the dynamic current above and below the current mismatch ( Mismatch) makes it stable, significantly reducing the spurious phenomenon of the phase-locked loop (PLL).

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

According to an embodiment of the present invention, a charge pump capable of controlling a common transistor on-time, as shown in FIG. 3, includes: a current source portion 100 for supplying a current accumulation charge to a loop filter; and a current sinking portion 200 from the ring The circuit filter obtains a current supply and absorbs the charge; the standard current supply unit 300 supplies a certain bias current; a sharing portion 400 is connected to the source switch and the absorption switch provided in the current source portion and the current sink portion; timing The controller 500 generates and supplies a control signal for adjusting the turn-on time of the transistor.

The current source portion 100 is a current mirror structure composed of a PMOS transistor, connected between a voltage source (Vdd) and an output terminal (Vout), including: a source switch (MP3), which is to be phase detector ( PFD) generation (UP_b), the source control signal (UP_bbb) adjusted by the timing controller 500 is loaded to its gate; the first control switch (MP1, MP2), in the standard current supply unit 300, the standard current (I _ref ) Loaded as a control signal to its gate. At this time, the source switch (MP3) turns on when the source control signal (UP_bbb) is 0, and causes the source current to flow from the voltage source (Vdd) to the loop filter through the output terminal (Vout), thereby Accumulate charge. In the source control signal, the English letter "b" indicates "bar".

One terminal of the source switch (MP3) is connected to the voltage source (Vdd), the other terminal is connected to one terminal of the first control switch (MP2), and the source switch (MP3) and the first control The common connection terminal of the switch (MP2) is connected to one of the terminals of the first common transistor (MN5) which will be described later. In addition, the other terminal of the first control switch (MP2) is connected to the output terminal (Vout).

The current absorbing portion 200 is a current mirror structure composed of an NMOS transistor, and is connected between the output terminal (Vout) and a ground voltage (GND), and includes: an absorption switch (MN3), which is to be phase-detected. (PFD) generation (DN), the absorption control signal (DN_bb) adjusted by the timing controller 500 is loaded to its gate; the second control switch (MN1, MN2), in the standard current supply unit 300, the standard current (I) _Ref ) is loaded as a control signal to its gate.

At this time, the absorption switch (MN3) is turned on when the absorption control signal (DN_bb) is 1, and causes an absorption current to flow from the output terminal (Vout) to the output terminal (Vout), thereby discharging the electric charge.

One terminal of the absorption switch (MN3) is connected to the ground voltage (GND), the other terminal is connected to one terminal of the second control switch (MN2), and the absorption switch (MN3) and the second control The common connection terminal of the switch (MN2) is connected to one terminal of a second common transistor (MP5) which will be described later. In addition, the other terminal of the second control switch (MN2) is connected to the output terminal (Vout).

In addition, the sharing 400 includes a first common transistor (MN5), one terminal of which is connected to a common terminal of the source switch (MP3) and the first control switch (MP2), and the other terminal is connected. The grounding power source is composed of an NMOS transistor with a first common control signal (SHP) mounted on its gate; a second common transistor (MP5) having a terminal connected to the absorption switch (MN3) and a second control switch The common terminal of (MN2) is connected to a voltage source and is composed of a PMOS transistor having a second common control signal (SHN) applied to its gate.

As shown in FIG. 4, the timing controller 500 is configured to adjust the turn-off time of the source switch (MP3) and the turn-on time of the first common transistor (MN5). Different, and the absorption switch (MN3) cut-off time and the second common transistor (MP5) turn-on time are different, including: a first delay unit (Delay Cell A) 510, delaying the phase a source control signal (DU_b) generated by a detector (PFD) and an absorption control signal (DN); a flip-flop 520 that receives the signal delayed by the first delay unit as an input, and outputs the first and second shared control Signal (SHP, SHN); and second delay unit (Delay Cell B) 530. Delay the signal delayed by the first delay unit and load the reset signal as a trigger.

At this time, the output end of the first delay unit 510 is connected to the source switch (MP3) and the absorption switch (MN3), and the source control signal (UP_bbb) delayed for a certain time is loaded to the gate of the source switch (MP3). And load the absorption control signal (DN_bb) to the gate of the absorption switch (MN5).

In addition, the output terminal (Q) of the flip-flop 520 is connected to the first common transistor (MN5), loads a first common control signal (SHP), and is connected to the second common transistor (MP5). , loading the second common control signal (SHN).

At this time, the first shared control signal (SHP) is converted before the source control signal (UP_bbb), and the second shared control signal (SHN) is adjusted by the timing controller 500. Conversion is performed prior to the absorption control signal (DN_bb). Therefore, the first common transistor (MN5) is turned on before the source switch (MP3) is turned off, and the second common transistor (MP5) is pre-arranged before the absorption switch (MN3) is turned off. Turn on.

In addition, the second delay unit 530 determines a time when the first and second common transistors (MN5, MP5) remain in an ON state, and is connected to an output terminal (Qb) and a reset terminal (Rn) of the flip-flop 520. Between the delay signal is loaded into the touch The reset signal of the transmitter converts the first and second common control signals (SHP, SHN) to turn on the first and second common transistors.

Next, the action of the charge pump of the present invention which can control the on-time of the common transistor will be explained.

Figure 5 is a timing diagram of control signals for controlling the on-time of the transistor at the timing controller in accordance with the present invention.

As shown in FIG. 5, first, in the phase detector (PFD), if the source control signal (UP_b) of the positive pulse is loaded to the first delay unit (Delay Cell A) of the timing controller, the output delay is fixed. The source of time control signal (UP_bbb) is loaded to the source switch (MP3).

At this time, the source switch (MP3) and the first common transistor (MN5) are both in the off state while the source control signal (UP_bbb) is held for 1, and if the source control signal (UP_bbb) Switching from 1 to 0, the first common transistor (MN5) remains off, but the source switch (MP3) will be turned on, causing the source current (I ₁ ) to pass from the voltage source (Vdd) through the source. The switch (MP3) and the first control switch (MP2) flow to the output terminal (Vout). The source current (I ₁ ) of the flow is a dynamic current (I ₃ ) that is passed to a loop filter to accumulate charge and adjust the voltage in the capacitor.

Thereafter, after accumulating the charge corresponding to the output pulse of the phase detector (PFD), the first common control signal (SHP) is adjusted by the timing controller before the source switch (MP3) is turned off, first Convert from 0 to 1. Therefore, the first common transistor (MN5) will be turned on, and a portion (I ₄ ) of the current originally flowing through the source switch (MP3) flows in, raising the voltage level of the node A (node A).

In addition, after the first common transistor (MN5) is turned on and the voltage level of the node A is raised, the source control signal (UP_bbb) that is switched from 0 to 1 is loaded, thereby cutting off the source switch ( MP3). At this time, after the source switch is turned off, since the node A has been raised to a certain voltage level, a voltage difference is not generated with the output terminal (Vout), so that no reverse current is generated or its value is small.

In addition, in the phase detector (PFD), if the absorption control signal (DN) of the negative pulse is loaded to the first delay unit (Delay Cell A) of the timing controller, the absorption control signal delayed by a certain time is outputted. (DN_bb) and loaded into the absorption switch (MN3).

At this time, the absorption switch (MN3) and the second common transistor (MP5) are both in the off state while the absorption control signal (DN_bb) remains 0, and if the absorption control signal (DN_bb) Switching from 0 to 1, the second common transistor (MP5) remains in the off state, but the absorption switch (MN3) will be turned on and the charge accumulated in the loop filter is extruded. The absorption current (I ₂ ) flows from the output terminal (Vout) to the ground power source (GND) through the second control switch (MN2) and the absorption switch (MN3). The absorption current (I ₂ ) of the flow is a dynamic current (I ₃ ), which accumulates the charge of the capacitor and adjusts the voltage.

Thereafter, after emitting the charge corresponding to the output pulse of the phase detector (PFD), the second common control signal (SHN) is adjusted by the timing controller before the absorption switch (MN3) is turned off, first Convert from 1 to 0. Therefore, the second common transistor (MP5) will be turned on, and the current (I ₅ ) flows from the voltage source (Vdd) through the second common transistor (MP5) and the absorption switch (MN3), thereby improving the node B (node). B) The voltage level.

In addition, after the second common transistor (MP5) is turned on and raises the voltage level of the node B, the absorption control signal (DN_bb) that is switched from 1 to 0 is loaded, thereby cutting off the absorption switch ( MN3). At this time, after the absorption switch is turned off, since the node B has been raised to a certain voltage level, a voltage difference is not generated with the output terminal (Vout), so that no reverse current is generated or its value is small.

As described above, the timing controller recognizes in advance the transition state of the source control signal (UP_b) and the absorption control signal (DN) from the phase detector, before cutting off the source switch (MP3) or the absorption switch (MN3), first Turn on the first common transistor (MN5) or the second common transistor (MP5) to keep the node A or the node B at a certain voltage level, and prevent the source switch (MP3) or the absorption switch (MN3) from being turned off. The change in dynamic current caused by current.

Further, by using the output of the second delay unit (Delay Cell B) 530 of the timing controller as an input flip-flop 520, after a certain period of time, the first common control signal (SHP) is reconverted to 0, and the second share The control signal (SHN) will be reconverted to 1, thereby cutting off the first and second common transistors (MN5, MP5).

Therefore, as described above, the common control signal for turning on the first and second transistors (MN5, MP5) is loaded before the control signal of the source switch (MP3) and the absorption switch (MN3) is turned off, so that One of the terminals of the first and second control switches maintains a certain voltage level to prevent the reverse current generated when the source control signal and the absorption control signal are switched, so that the voltage of the output terminal (Vout) is high as shown in the graph of FIG. Or low, can also maintain a stable dynamic current, can more accurately simulate the quantitative information of the output terminal (Vout), get close to the theoretical results.

That is, in the prior art, after the source switch and the sink switch are turned off, until the node A (node A) and the node B (node B) reach a certain voltage level, at the output terminal (Vout) and the node A and the node B Voltage distribution occurs to generate a reverse current, and a waveform shown by a broken line in the source current (I ₁ ), the absorption current (I ₂ ), and the dynamic current (I ₃ ) as shown in FIG. 6 appears, but according to the present invention The first and second common transistors (MN5, MP5) are turned on in advance, so that the node A and the node B first reach a certain voltage level, and after the source switch (MP3) and the absorption switch (MN3) are turned off, A reverse current is generated such that the source current (I ₁ ), the sink current (I ₂ ), and the dynamic current (I ₃ ) exhibit only waveforms shown by straight lines.

The present invention has been described by the related embodiments, but the embodiments are merely examples for implementing the invention. It must be pointed out that the disclosed embodiments do not limit the present invention. The scope of the Ming. On the contrary, modifications and equivalents of the spirit and scope of the invention are included in the scope of the invention.

100‧‧‧ Current Source Division

200‧‧‧ Current Absorption Department

300‧‧‧Standard Current Supply Department

400‧‧ ‧Shared Department

500‧‧‧Time Controller

510‧‧‧First delay unit

520‧‧‧ Trigger

530‧‧‧second delay unit

1 is a previous charge pump circuit diagram; FIG. 2 is a diagram of an output voltage and current using a previous charge pump; FIG. 3 is a circuit diagram of a charge pump capable of controlling a common transistor turn-on time according to the present invention; FIG. 5 is a timing diagram of a control signal for controlling the on-time of the transistor in the timing controller according to the present invention; FIG. 6 is a graph showing the output voltage and current of the charge pump capable of controlling the on-time of the common transistor according to the present invention.

100. . . Current source

200. . . Current absorbing part

300. . . Standard current supply

400. . . Sharing department

500. . . Timing controller

Claims (5)

A charge pump capable of controlling a common transistor on-time, in a charge pump that adjusts a loop filter voltage by increasing or decreasing a charge according to a pulse signal of a standard frequency and an output frequency compared by a phase detector, including: a current source a current switch having a source control signal loaded in the gate thereof; a current sinking portion having an absorption switch for loading an absorption control signal into the gate; and a first common transistor having a terminal connected to the source switch, and One terminal is connected to the grounding power source, and the first common control signal is loaded on the door; the second common transistor has one terminal connected to the absorption switch, the other terminal is connected to the voltage source, and the second common control signal is loaded on the gate; And the timing controller generates the control signal, the absorption control signal, the first control signal and the second common control signal are supplied to the source switch, the absorption switch, the first common transistor and the second common transistor pass the The operation of the timing controller, when the state of the source control signal changes the source switch from off to on, the state of the first common control signal is cut off a source switch, and when the state of the source control signal changes the source switch from on to off, the state of the first common control signal turns on the first common switch before the source switch is turned off to prevent a change in dynamic current caused by a reverse current after the source switch is turned off; By the action of the timing controller, when the state of the absorption control signal changes the absorption switch from off to on, the state of the second common control signal cuts off the absorption switch, and when the state of the absorption control signal is When the source switch changes from on to off, the state of the second common control signal turns on the second common switch before the absorption switch is turned off to prevent the dynamics caused by the reverse current after the absorption switch is turned off. Current changes. A charge pump capable of controlling a common transistor on-time as described in claim 1, wherein the source switch is composed of a PMOS transistor; the absorption switch is composed of an NMOS transistor; the first common transistor is The NMOS transistor is configured; the second common transistor is composed of a PMOS transistor. A charge pump capable of controlling a common transistor on-time as described in claim 1, wherein the timing controller comprises: a first delay unit that delays a signal generated by the phase detector; and a trigger And outputting the first and second common control signals by using the output signal of the first delay unit as an input. A charge pump capable of controlling a common transistor on-time as described in claim 4, wherein the first delay unit has an output connected to the source switch and the absorption switch, and the delayed source control signal is carried. Entering the gate of the source switch, and loading the delayed absorption control signal into the gate of the absorption switch, identifying the conversion time of the source control signal and the absorption control signal, and determining the connection of the first and second common transistors Pass time. A charge pump capable of controlling a common transistor on-time as described in claim 4, further comprising a second delay unit connected between the trigger output terminal (Qb) and the reset terminal (Rn) The output signal is loaded into a reset signal of the flip-flop, and the first and second common control signals are converted again to determine the time during which the first and second common transistors remain in an on state.