TWI488266B - 內連線結構與其形成方法 - Google Patents

內連線結構與其形成方法 Download PDF

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TWI488266B
TWI488266B TW102138018A TW102138018A TWI488266B TW I488266 B TWI488266 B TW I488266B TW 102138018 A TW102138018 A TW 102138018A TW 102138018 A TW102138018 A TW 102138018A TW I488266 B TWI488266 B TW I488266B
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layer
forming
oxide
copper
manganese
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TW201419445A (zh
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Yu Hung Lin
Chi Yu Chou
Kuei Pin Lee
Chen Kuang Lien
Yu Chang Hsiao
Yao Hsiang Liang
Yu Min Chang
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Taiwan Semiconductor Mfg Co Ltd
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Description

內連線結構與其形成方法
本發明係關於半導體元件，更特別關於銅內連線與其形成方法。
半導體元件具有多種電子應用，比如個人電腦、手機、數位相機、及其他電子設備。隨著技術進步，對尺寸更小且功能更強的半導體元件需求也隨之增加。當元件密度增加時，亦需縮小後段製程(BEOL)內連線結構的導線與其間距寬度。
為了達成上述需求，需改變過去用於半導體元件設計的習知材料。為了減少RC延遲，需採用低介電常數(low-k)材料作為絕緣材料，並將內連線材料由鋁轉為銅。與鋁相較，銅具有較低電阻率與較高電遷移電阻。以銅作為半導體元件內連線的好處，包括更快的操作速度與更小的線寬。舉例來說，銅內連線與低介電常數之介電材料的結合可降低RC延遲，進而增加內連線速度。
銅內連線之形成方法通常為鑲嵌製程而非直接蝕刻。鑲嵌製程一般為單鑲嵌或雙鑲嵌，包括圖案化與蝕刻金屬間介電層(IMD)以形成開口，再將銅填入開口中。由於銅易於擴散至某些介電材料中，特別是某些低介電常數之介電材料， 一般在形成銅前會先沉積擴散阻障層於鑲嵌開口之內壁上。耐火金屬(如鉭或鈦)或其氮化物可作為擴散阻障層。然而位於銅鑲嵌結構中的耐火金屬膜具有高電阻，這會增加銅線路電阻與RC延遲，特別是在小尺寸的結構中。
近年來銅線路持續縮小，因此擴散阻障層的厚度亦隨之變薄。在形成較小尺寸的內連線時，物理氣相沉積(PVD)製程難以沉積較薄的TaN/Ta阻障層。原子層沉積(ALD)製程可用以沉積非常薄且厚度一致的擴散阻障層，但ALD製程的沉積速率極慢且產量不佳。此外，TaN/Ta的擴散阻障膜無法與金屬間介電層具有良好的黏著力。舉例來說，銅線路將由界面剝落，進而劣化半導體元件的良率。
如此一來，目前亟需改良銅內連線中的擴散阻障層，以及其形成方法。
本發明一實施例提供元件的形成方法，包括：形成介電層於基板上；形成開口於介電層中；形成含金屬層於開口上；形成阻障層於含金屬層上；將導電層填入開口中；以及進行熱製程以形成金屬氧化物阻障層於導電層下。
本發明另一實施例提供一種元件的形成方法，包括：形成介電層於基板上；形成開口於介電層中；形成銅錳層於介電層中的開口上；形成α相鉭層於銅錳層上；將導電層填入開口中；進行化學機械研磨製程，以移除開口之外的部份導電層；以及進行熱製程，以形成氧化錳阻障層於導電層下。
本發明又一實施例提供一種元件，包括：介電層， 位於基板上；導電襯墊物，襯墊介電層中的側壁；鉭層，鄰接導電襯墊物的側壁；以及金屬氧化物，形成於鉭層與介電層之間。
100‧‧‧方法
102、104、106、108、110、112‧‧‧步驟
200‧‧‧半導體元件
202‧‧‧半導體基板
204‧‧‧第一蝕刻停止層
206‧‧‧介電層
208‧‧‧凹陷孔洞
208L‧‧‧較低的接觸孔部份
208U‧‧‧較高的溝槽部份
210‧‧‧含銅層
212‧‧‧阻障層
214‧‧‧導電物
216‧‧‧第二蝕刻停止層
218‧‧‧熱處理
220‧‧‧擴散阻障層
第1圖為本發明某些實施例中，製作半導體元件之方法的流程圖；以及第2至8圖係本發明某些實施例中，半導體元件之內連線結構的製程剖視圖。
本發明之實施例提供形成於半導體元件中的銅內連線結構內之阻障層，以及其形成方法。這些方法可應用於多種製造商、工廠、與產業，比如積體電路產業、微電子產業、及光電產業。圖式標號將用以搭配說明實施例與實例，並儘可能以相同標號標示圖式中的相同部份。在圖式中，一實施例的形狀與厚度可能稍微誇大以利清楚說明。說明書將說明本發明中裝置的組成單元。可以理解的是，當這些單元屬本技術領域之通常知識時，將不會特別描述這些單元。此外，形成某層於另一層或基板上的敘述包含兩者直接接觸，或兩者之間隔有其他額外層而非直接接觸。
第1圖為本發明某些實施例中，製作半導體元件200之方法100的流程圖。第2至8圖係本發明一實施例中，以第1圖之方法100製作半導體元件200的製程剖視圖。半導體元件200可為微處理器、記憶單元、及/或其他積體電路(IC)。必需 注意的是，第1圖並未形成完整的半導體元件200，其形成方法可為互補式金氧半(CMOS)製程技術。綜上所述，可以理解的是在第1圖之方法100之前、之中、或之後可進行其他額外步驟，而某些其他步驟將簡述於下。此外，第1至8圖已簡化以利了解本發明。舉例來說，雖然圖式中只有半導體元件200，但應理解IC可包含多種其他元件，比如電晶體、電阻、電容、電感、熔絲、或類似物。
如第1及2圖所示，方法100之步驟102形成凹陷孔洞208於介電層206中。在某些實施例中，介電層206指的是金屬間介電(IMD)層。在某些實施例中，第一蝕刻停止層204係形成於半導體基板202上及介電層206下。在某些實施例中，凹陷孔洞208係形成於介電層206與第一蝕刻停止層204中。半導體基板202為應用於半導體積體電路製程的基板，而積體電路可形成其中及/或其上。「半導體基板」的定義包含任何半導體材料組成，比如含有或不含磊晶層之矽基板、包含埋置絕緣層的絕緣層上矽基板、或具有矽鍺層的基板。「積體電路」指的是具有多重個別電路單元的電子電路，比如電晶體、二極體、電阻、電容、電感、及其他主動或被動半導體元件。形成於半導體基板202之上及/或之中的導電區，係部份的導電線路且具有經平坦化製程(比如化學機械研磨)處理的露出表面。導電區的適用材料可包含但不限於銅、鋁、銅合金、或其他導電材料。銅內連線層可為半導體元件的第一層或其他層。
在某些實施例中，第一蝕刻停止層204可在後續蝕刻製程中控制蝕刻終點。在某些實施例中，第一蝕刻停止層204 之組成可為氧化矽、氮化矽、碳化矽、氮氧化矽、或上述之組合。在某些實施例中，第一蝕刻停止層204之厚度介於約10Å至約1000Å之間。第一蝕刻停止層204可由任何沉積技術形成，比如低壓化學氣相沉積(LPCVD)、常壓化學氣相沉積(APCVD)、電漿增強化學氣相沉積(PECVD)、物理氣相沉積(PVD)、濺鍍、或未來發展的沉積技術。
介電層206可為單層或多層結構。在某些實施例中，介電層206之厚度取決於形成方法，可介於約1000Å至30000Å之間。在某些實施例中，介電層206為氧化矽、掺雜碳之氧化矽、相對低介電常數之介電材料(介電常數低於4.0)、或上述之組合。在某些實施例中，介電層206之組成包含低介電常數之介電材料、超低介電常數之介電材料、孔洞狀低介電常數之介電材料、或上述之組合。「低介電常數」的定義為介電常數小於或等於3.0。「超低介電常數(ELK)」指的是介電常數小於或等於2.5，較佳介於1.9至2.5之間。「孔洞狀低介電常數」指的是介電常數小於或等於2.0，較佳小於或等於1.5。在實施例中，低介電常數之材料的種類廣泛，比如旋轉塗佈的無機介電物、旋轉塗佈的有機介電物、孔洞狀介電材料、有機高分子、有機氧化矽玻璃、FSG(SiOF系列材料)、HSQ(氫倍半矽氧烷)系列材料、MSQ(甲基倍半矽氧烷)系列材料、或孔洞狀有機系列材料。在某些實施例中，介電層206可由任何沉積技術形成，比如化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、遠端電漿增強式化學氣相沉積(RPECVD)、液態源霧化化學沉積(LSMCD)、塗佈、旋轉塗佈、或用以形成薄膜層於基 板上的任何製程。
在實施例中，介電層206為含氮層、含碳層、或含氮與含碳層，以提高對後續之化學機械研磨(CMP)製程的抗腐蝕性，及/或增加其抗電移能力。在一實施例中，介電層206為含矽與含氮的介電層。在另一實施例中，介電層206為含矽與含碳的介電層。在其他實施例中，介電層206為含矽、含氮、與含碳的介電層。在一實施例中，介電層206中碳與矽的重量比大於或等於0.5。在另一實施例中，介電層206中氮與矽之重量比大於或等於0.3。在其他實施例中，介電層206中碳與矽之重量比大於或等於0.5，且氮與矽之重量比大於或等於0.3。
凹陷孔洞208可為雙鑲嵌開口(包含較高的溝槽部份208U與較低的接觸孔部份208L)，藉由圖案化形成於介電層206與第一蝕刻停止層204中，以定義半導體基板202上的接觸區。雖然實施例的圖式為IMD層中的雙鑲嵌開口，但亦可應用於IMD層中的單鑲嵌開口。雙鑲嵌技術包含「接觸孔優先」的圖案化方法或「溝槽優先」的圖案化方法，均以一般的微影技術、遮罩技術、與非等向蝕刻技術(如電漿蝕刻或反應性離子蝕刻)形成較高的溝槽部份208U與較低的接觸孔部份208L。在另一實施例中，底部蝕刻停止層(未圖示)、中間蝕刻停止層(未圖示)、研磨停止層(未圖示)、或抗反射塗層(ARC，未圖示)係沉積於介電層206之中或之上，以決定何時停止特定的蝕刻製程。
如第1及3圖所示，方法100之步驟104形成含銅層210於上述結構上。含銅層210襯墊凹陷孔洞208之側壁與底 部，並形成於介電層206上。在一實施例中，含銅層210為包含主要金屬元素(如銅元素)與其他額外金屬元素的金屬合金層。在某些實施例中，額外金屬元素包含錳(Mn)、鋁(Al)、鈦(Ti)、鈮(Nb)、鉻(Cr)、釩(V)、釔(Y)、鎝(Tc)、錸(Re)、鈷(Co)、或上述之組合。
在某些實施例中，含銅層210為面心立方(FCC)結晶結構的銅錳(CuMn)層。在某些實施例中，銅錳層中錳與銅的比例介於約0.05%至約10.00%之間。在某些實施例中，含銅層210之厚度介於約1Å至約150Å之間。在某些實施例中，含銅層之厚度介於約5Å至約50Å之間。在某些實施例中，含銅層210之沉積方法為物理氣相沉積(PVD)、化學氣相沉積(CVD)、電漿增強式化學氣相沉積(PECVD)、低壓CVD(LPCVD)、或其他常見的沉積技術。
如第1及4圖所示，方法100之步驟106形成阻障層212於含銅層210上。阻障層212可避免之後形成的導電物擴散至較下方的介電層206中。在某些實施例中，阻障層212包含鉭、鈦、或類似物。在某些實施例中，阻障層212之厚度介於約10Å至約250Å之間。在某些實施例中，含銅層210與阻障層212的總厚度小於約120Å，以避免在後續開口填充製程中造成間隙填充問題。鉭層具有兩種不同相，比如具有體心立方(BCC)相之α相鉭層，或具有四方相的β相鉭層。α相鉭層之電阻率低於β相鉭層。當下方的層狀物具有結晶結構時，較佳採用α相鉭層。
在某些實施例中，阻障層212為α相鉭層。在某些 實施例中，阻障層212之電阻率小於約60μΩ/cm。如此一來，阻障層212之低電阻率有助於減少RC延遲問題。在另一實施例中，阻障層212為α相及/或β相的鉭層。在某些實施例中，阻障層212之沉積方法可為PVD、CVD、PECVD、LPCVD、或其他常見之沉積技術。
如第1及5圖所示，方法100之步驟108形成導電物214於阻障層212上，以填滿凹陷孔洞208。在某些實施例中，導電物214作為介電層206中的內連線結構。在某些實施例中，導電物214之沉積方法為電化學電鍍(ECP)製程。在某些實施例中，導電物214至少包括主要的金屬元素如銅。在某些實施例中，導電物214更包含額外金屬元素。在某些實施例中，導電物214包含的額外金屬元素不同於含銅層210包含的額外金屬元素。在某些實施例中，導電物214中的額外金屬元素可為鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁、或鋯。
在某些實施例中，在形成導電物214前先形成導電晶種層(未圖示)。在某些實施例中，導電晶種層至少包含主要金屬元素如銅，即導電物214所含的主要金屬元素。在某些實施例中，導電晶種層為含銅層如銅鋁合金(CuAl)、銅錳合金(CuMn)、或類似物。
如第1及6圖所示，方法100之步驟110移除介電層206上的部份導電物214。在某些實施例中，此移除製程為化學機械研磨(CMP)製程，可移除凹陷孔洞208之外的多餘導電物214、導電晶種層、阻障層212、與含銅層210。上述製程除了露出介電層206的上表面，並使結構整體具有平坦化的表面。
如第1及7圖所示，方法100之步驟112形成第二蝕刻停止層216於前述平坦化的表面上。第二蝕刻停止層216可在後續蝕刻製程中控制蝕刻終點。在某些實施例中，第二蝕刻停止層216可為氧化矽、氮化矽、碳化矽、氮氧化矽、或上述之組合。在某些實施例中，第二蝕刻停止層216之厚度介於約10Å至約1000Å之間。在某些實施例中，第二蝕刻停止層216之形成方法可為任何沉積製程，比如LPCVD、APCVD、PECVD、PVD、或濺鍍。
如第1及8圖所示，方法100之步驟114在半導體基板202上進行熱處理218。在某些實施例中，熱處理218包含回火製程。在一實施例中，熱處理218之操作溫度介於約137℃至約600℃之間。在另一實施例中，熱處理218之操作溫勿介於約280℃至約400℃之間。在一實施例中，熱處理218之操作時間介於約10分鐘至約600分鐘之間。在某些實施例中，熱處理218之操作方法包括高溫爐、快速熱製程(RTP)、或加熱板。
某些實施例中，在回火製程之中及/或之後的含銅層210中的額外金屬元素，將部份或完全擴散至介電層206的表面。在某些實施例中，擴散的額外金屬元素將與介電層206反應，以形成擴散阻障層220。擴散阻障層220自對準介電層206及含銅層210之邊界。在一實施例中，擴散阻障層220之厚度介於約1Å至約30Å之間。在另一實施例中，擴散阻障層220之厚度介於約1Å至約15Å之間。在某些實施例中，形成擴散阻障層220會消耗部份介電層206與含銅層210。在一實施例中，擴散阻障層220為金屬氧化物層，因為回火製程使介電層206中的氧 與含銅層210中的額外金屬元素反應。在某些實施例中，金屬氧化物層為氧化錳(MnOx )及/或矽氧化錳(MnSiy Oz )。在另一實施例中，金屬氧化物層為氧化鈦(TiOx )、氧化鋁(AlOx )、氧化鈷(CoOx )、氧化釩(VOx )、氧化釔(YOx )、氧化鎝(TcOx )、氧化錸(ReOx )、或上述之組合。在某些實施例中，擴散阻障層220中錳與氧之重量比介於約0.1至約10之間。擴散阻障層220可作為保護層，以避免導電物214擴散至介電層206中。
在回火製程後，含銅層210轉變為後期含銅層。在一實施例中，後期含銅層包含主要金屬元素與保留的額外金屬元素於其中，其中後期含銅層之額外金屬元素含量小於含銅層210之額外金屬元素含量。在另一實施例中，後期含銅層包含主要金屬元素但不含額外金屬元素，因為回火製程已完全消耗額外金屬元素。
熱處理的步驟可為含銅層210之形成步驟後的任何熱製程。在另一實施例中，熱處理的步驟可在形成含銅層210後立刻進行、在移除凹陷孔洞208之外的多餘部份導電物之CMP步驟後立刻進行、在形成第二蝕刻停止層216後立刻進行、或在形成鈍化層於頂金屬層上後立刻進行。
本發明實施例之半導體元件與內連線結構的優點在於自對準形成擴散阻障層，可解決接觸問題並改善封裝能力。此外，位於擴散阻障層上的阻障層可進一步避免內連線導電物擴散至IMD層，以確保封裝效果。另一方面，阻障層包含低電阻率的α相鉭層，可降低接觸電阻。上述種種均可改善元件效能。
在一實施例中，製作半導體元件的方法包括形成介電層於基板上；形成開口於介電層中；形成含金屬層於開口上；形成阻障層於含金屬層上；將導電層填入開口中；以及進行熱製程以形成金屬氧化物阻障層於導電層下。
在另一實施例中，製作半導體元件的方法包括形成介電層於基板上；形成開口於介電層中；形成銅錳層於介電層中的開口上；形成α相鉭層於銅錳層上；將導電層填入開口中；進行化學機械研磨製程，以移除開口之外的部份導電層；以及進行熱製程，以形成氧化錳阻障層於導電層下。
又一實施例中，半導體元件包括介電層，位於基板上；導電襯墊物，襯墊介電層中的側壁；鉭層，鄰接導電襯墊物的側壁；以及金屬氧化物，形成於鉭層與介電層之間。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
200‧‧‧半導體元件
202‧‧‧半導體基板
204‧‧‧第一蝕刻停止層
206‧‧‧介電層
210‧‧‧含銅層
212‧‧‧阻障層
214‧‧‧導電物
216‧‧‧第二蝕刻停止層
218‧‧‧熱處理
220‧‧‧擴散阻障層

Claims (10)

  1. 一種內連線結構的形成方法，包括：形成一介電層於一基板上；形成一開口於該介電層中；形成一含金屬層於該開口上；形成一阻障層於該含金屬層上；將一導電層填入該開口中；以及進行一熱製程以形成一金屬氧化物阻障層於該導電層下。
  2. 如申請專利範圍第1項所述之內連線結構的形成方法，其中該含金屬層之結晶結構為面心立方(FCC)結構，且其中該阻障層之結晶結構為體心立方(BCC)結構。
  3. 如申請專利範圍第1項所述之內連線結構的形成方法，其中該含金屬層係一含銅層，且其中該含銅層包括一額外金屬元素，且該額外金屬元素包括錳、鋁、鈦、鈮、鉻、釩、釔、鎝、錸、鈷、或上述之組合。
  4. 如申請專利範圍第1項所述之內連線結構的形成方法，其中該阻障層係α相鉭層，且其中該金屬氧化物阻障層係氧化錳及/或矽氧化錳。
  5. 一種內連線結構的形成方法，包括：形成一介電層於一基板上；形成一開口於該介電層中；形成一銅錳層於該介電層中的該開口上；形成一α相鉭層於該銅錳層上；將一導電層填入該開口中； 進行一化學機械研磨製程，以移除該開口之外的部份該導電層；以及進行一熱製程，以形成一氧化錳阻障層於該導電層下。
  6. 如申請專利範圍第5項所述之內連線結構的形成方法，其中該氧化錳阻障層係由該銅錳層中的錳與該介電層中的氧反應而成。
  7. 一種內連線結構，包括：一介電層，位於一基板上；一導電襯墊物，襯墊該介電層中的一側壁；一鉭層，鄰接該導電襯墊物的側壁；以及一金屬氧化物，形成於該鉭層與該介電層之間。
  8. 如申請專利範圍第7項所述之內連線結構，其中該鉭層具有體心立方結構的α相。
  9. 如申請專利範圍第7項所述之內連線結構，其中該金屬氧化物包括氧化錳、氧化鈦、氧化鋁、氧化鈷、氧化釩、氧化釔、氧化鎝、氧化錸、或上述之組合。
  10. 如申請專利範圍第7項所述之內連線結構，更包括：一銅錳層形成於該金屬氧化物與該鉭層之間。
TW102138018A 2012-11-01 2013-10-22 內連線結構與其形成方法 TWI488266B (zh)

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