TWI482428B - amplifying circuit - Google Patents

Description

amplifying circuit

The present invention relates to an amplifying circuit, and more particularly to an amplifying circuit preferably adapted for capacitive load driving.

In a driving circuit for driving a display such as a liquid crystal display (LCD) or an organic EL display, a plurality of wafers having a plurality of amplifying circuits are provided, and the plurality of amplifying circuits are used for each of the displays The unit supplies a voltage for image writing, but with the increase in size of the display or the increase in demand performance, it is required for the above-mentioned amplifier circuit to be able to drive a display having a large capacitive load with a high slew rate and low power consumption. And the size is small. Further, since the number of cells (the number of pixels) in the display to be driven causes a part of the amplifier circuits in the wafer to be connected to the display and is in a no-load state, the amplifier circuit is required to be in a no-load state. Nor does it oscillate. Further, since the wafer is inspected and the load connected to each of the amplifier circuits is smaller than the display connection, it is required to check the wafer for the above-mentioned amplifier circuit, and do not oscillate under light load conditions during evaluation. Further, by increasing the phase compensation capacitor provided in the amplifier circuit, the oscillation can be suppressed, but there is a problem that the conversion rate is deteriorated or the size is increased.

Patent Document 1 related to the above discloses a phase compensating circuit having a buffer amplifier having an input section and an output section and receiving an output section signal of an operational amplifier, and connecting one end of a phase compensating capacitor. The output of the buffer amplifier is connected to the input of the output section.

Further, Patent Document 2 discloses a configuration in which a first phase compensation section including a capacitor CC and transistors M7 and M8 and a second phase compensation including a capacitor CC' and transistors M10 to M13 are provided. The segment acts as a phase compensation segment connected to the differential input segment and the output amplification segment.

Further, Patent Document 3 discloses a drive circuit including an operational amplifier that amplifies an input signal and inputs it to a capacitive load, an operation state detection circuit that detects an operational state of the operational amplifier to a capacitive load, and A variable resistor that changes the resistance value in an operation state detected by the operation state detecting circuit connected to the output of the operational amplifier.

[Patent Document 1] Japanese Patent Laid-Open No. Hei 10-270956

[Patent Document 2] Japanese Patent Laid-Open No. 02-303204

[Patent Document 3] Japanese Patent Laid-Open Publication No. 2005-341018

However, the technique disclosed in Patent Document 1 has an advantage of improving the stability of the oscillation of the operational amplifier by providing a phase compensation capacitor and a buffer amplifier, but since the output section is configured to perform A-stage amplification by a single transistor, The voltage range (effective operating range) for amplifying the input signal is narrow, and thus it is not suitable for driving the display or the like.

Further, in the technique disclosed in Patent Document 2, it is possible to expand the voltage range in which the phase compensation section functions by providing a plurality of phase compensation sections composed of a capacitor and a transistor, but the same as the technique disclosed in Patent Document 1, since the output is The segment is configured to perform A-stage amplification by a single transistor, so that the effective operation range is narrow, and thus it is not suitable for the purpose of driving the display or the like.

Further, in the techniques disclosed in Patent Documents 1 and 2, it is possible to increase the stability of the phase compensation capacitor (it becomes difficult to oscillate), but in general, the conversion ratio of the amplifier circuit and the input amplification section of the amplifier circuit The current (the differential phase) is proportional to the current consumption of the amplifier circuit, and is inversely proportional to the phase compensation capacitor. Therefore, if the phase compensation capacitor is increased, other problems such as a decrease in the conversion ratio occur.

Further, in the technique disclosed in Patent Document 3, since it is necessary to provide an operation state detecting circuit and a variable resistor, there is a problem that not only the configuration of the amplifying circuit is complicated but also the power consumption increases. Further, the technique disclosed in Patent Document 3 has a drawback in that a through current flows in the amplifying circuit, and thus a problem such as heat generation due to the through current is caused. Hereinafter, the through current will be described.

4 is a view showing a relevant portion in which a through current is generated in a drive circuit disclosed in Patent Document 3. The drive circuit disclosed in Patent Document 3 is provided with a P-type transistor MPO and an N-type that operate as push-pull circuits in the output section. The transistor MNO, the output terminal OUT of the output section is connected to the capacitive load CL, the gate pgate of the P-type transistor MPO and the gate ngate of the N-type transistor MNO are respectively connected to the output terminal OUT of the output section via the phase compensation capacitor Cc. connection. The driving circuit disclosed in Patent Document 3 is also shown in FIG. 4, and is generally phase-compensated by the mirror effect.

In this configuration, if the input signal voltage input to the input amplification section rises from the low level to the high level with a large amplitude, the voltage output from the input amplification section to the gate pgate drops, and the P-type transistor MPO is turned on. The current that charges the capacitive load CL will flow out of the power supply WD. At this time, the voltage at the output terminal OUT rises sharply. However, since the output terminal OUT is also connected to the gate ngate via the phase compensation capacitor Cc, the phase compensation capacitor Cc is coupled (the capacitance causes the potential difference between the two ends to be small). The voltage of the gate ngate is raised, so that the N-type transistor MNO is turned on. Thereby, the through current flows from the power source through the P-type transistor MPO and the N-type transistor MNO. The time during which the through current flows is extremely short. However, since hundreds of amplifier circuits are provided in the drive circuit of the display, heat that cannot be ignored due to the through current flowing through each of the amplifier circuits is caused.

The present invention has been made in view of the above circumstances, and an object thereof is to obtain an amplifying circuit having a large effective operation range and capable of reducing capacitance of a phase compensation capacitor and suppressing a through current.

In order to achieve the above object, an amplifier circuit according to the first aspect of the invention includes an amplifier unit having an input amplification section and an output section, and the first amplification element and the second amplification element provided in the output section operate as a push-pull circuit. a first buffer having an input terminal connected to an output end of the amplifying portion, an output terminal connected to a signal input end of the first amplifying device via a first capacitor, and a second capacitor and a second amplifying device via a second capacitor The signal input end is connected to the second buffer, wherein the input end is connected to the output end of the amplifying part or the output end of the first buffer, and the output end is connected to at least the signal input end of the first amplifying element via the third capacitor. .

In the first aspect of the invention, the first amplifying element and the second amplifying element are provided in the output section including the amplifying unit that inputs the amplifying section and the output section, and the first amplifying element and the second amplifying element of the output section are used as the push-pull circuit. Since the operation is performed (the operating voltage ranges of the first amplifying element and the second amplifying element are different), a large effective operating range can be obtained. Furthermore, it is preferable that the output section of the amplifying section is configured to be capable of performing an AB-stage operation in which the operating voltage ranges of the first amplifying element and the second amplifying element partially overlap. Further, as shown in the second aspect of the invention, the output portion of the amplifying portion may be configured such that the first amplifying element is connected to the output terminals of the power supply terminal and the amplifying portion, and operates when the output voltage of the amplifying portion is increased. The amplifying elements are respectively connected to the ground terminal and the output end of the amplifying portion, and operate when the output voltage of the amplifying portion is lowered. Further, it is preferable that the input amplification section of the amplifying section is configured to be capable of performing a so-called rail-to-rail operation.

Further, according to the first aspect of the invention, the first buffer and the second buffer are provided, and the input end of the first buffer is connected to the output end of the amplifying unit, and the output end is connected to the signal input end of the first amplifying element via the first capacitor. And connected to the signal input end of the second amplifying element via the second capacitor, wherein the input end is connected to the output end of the amplifying part or the output end of the first buffer, and the output end is at least connected to the output terminal via the third capacitor. The signal input terminal of the first amplifying element is connected. In the first aspect of the invention, the first to third capacitors function as a phase compensating capacitor, and as described above, a buffer is provided between the phase compensating capacitor and the output end of the amplifying portion, and thus, for example, the patent document According to the technique disclosed in FIG. 3, the phase compensation capacitor can be reduced as compared with the case where the phase compensation is performed by the mirror effect (the configuration of FIG. 4).

That is to say, by using the phase compensation of the mirror effect, if the high frequency region is reached, not only the phase compensation capacitor Cc can function as a feedback path, but also functions as a pre-request path, resulting in zeros from the relatively low frequency region. Therefore, it is easy to generate an oscillation that detracts from the stable operation of the circuit. On the other hand, when a buffer is provided between the phase compensation capacitor and the output terminal of the amplifying portion, zero can be moved to the high frequency side, and the phase margin can be easily secured. As an example, in the configuration in which the zero (ωzm) in the configuration of FIG. 4 and the buffer of the amplification factor Ab and the phase compensation capacitor are connected to the input end of the output section of the amplifying section, Zero (ωzb), then become ωzm≒-Ao/Cc‧Ro

Ωzb≒-Ao‧Ab/Cc‧Ro

(where Ao is the amplification factor of the output section, Ab is the amplification factor of the buffer, Cc is the capacitance of the phase compensation capacitor, and Ro is the output resistance of the output section). As is clear from the above equation, the zero (ωzb) in the configuration in which the output terminal of the amplifying portion is connected to the input terminal of the output portion of the amplifying portion via the buffer of the amplification factor Ab and the phase compensation capacitor becomes a mirror effect. Since the phase compensation is zero times (ωzm), it is easier to ensure the phase margin and the phase compensation capacitor can be made smaller than the phase compensation by the mirror effect.

Therefore, in the first aspect of the invention, the phase compensation capacitor (the total value of the first to third capacitors) can be made small. Further, in the first aspect of the invention, the output end of the first buffer is connected to the signal input ends of the first amplifying element and the second amplifying element via the first capacitor and the second capacitor, and the output end of the second buffer passes through the third Since the capacitance is connected to at least the signal input end of the first amplifying element, as shown in the fourth invention described below, the operating range of the first buffer and the second buffer can be made larger, and the larger portion of the amplifying portion can be made larger. At least one of the first buffer and the second buffer is operated in the entire range of the effective operation range, so that the output voltage dependency of the phase margin can be improved.

Further, in the first aspect of the invention, the first amplifying element and the second element caused by the coupling of the phase compensating capacitor during the large amplitude operation can be reduced by reducing the phase compensating capacitor (the total value of the first to third capacitors) The voltage fluctuation at the signal input end of the amplifying element is reduced, and the voltage applied to the phase compensating capacitor via the buffer to the amplifying portion can be output by providing a buffer between the output terminal of the amplifying portion and the phase compensating capacitor. Since the voltage change changes slowly, the first amplifying element and the second amplifying element operate during the period in which the first amplifying element and the second amplifying element do not operate, and the through current can be prevented from flowing. Therefore, according to the first aspect of the invention, it is possible to obtain an amplifier circuit having a wide effective operation range and capable of reducing the capacitance of the phase compensation capacitor and suppressing the through current.

Further, in the first aspect of the invention, since the phase compensation capacitor can be reduced, the load input to the amplification section can be reduced, and the current of the input amplification section can be increased, so that the power consumption can be increased without increasing the power consumption. Conversion rate. Further, since the phase compensation capacitor can be made small, the operation state detecting circuit, the variable resistor, or the circuit belonging to the technique disclosed in Patent Document 3 can be eliminated, and thus the synergistic effect can be achieved. The circuit is small in size and consumes less power.

Further, in the first invention, for example, as disclosed in the third invention, the amplifying unit operates as a voltage follower. Further, by operating the amplifying portion as a voltage follower, the output end of the amplifying portion can be connected to the input end (specifically, the inverting input terminal) of the input amplifying portion of the amplifying portion.

Further, in the first aspect of the invention, the first buffer and the second buffer are, for example, the fourth aspect of the invention, wherein the first buffer is applied with a voltage buffer, and the output voltage of the amplifier is equal to or less than the power supply voltage. When the ground voltage is higher than the value of the first predetermined voltage, the output voltage is lower than the output voltage of the amplifying unit, and the second buffer is applied to the voltage buffer as follows. When the output voltage of the amplifier is lower than the value of the second predetermined voltage and is within a range of the ground voltage or more, the output voltage is higher than the output voltage of the amplifier by the second predetermined voltage. .

Further, in the first to fourth inventions, for example, as disclosed in the fifth aspect of the invention, it is preferable that the first capacitance is smaller than the second capacitance and the third capacitance. In the configuration in which the first to third capacitors are provided, the first capacitor is a capacitor for performing auxiliary phase compensation. In the fifth invention, since the capacitances are reduced, the first to third capacitors are used. When the total of the first to third capacitances is reduced, the same phase margin improvement effect can be obtained. Further, by reducing the total value of the first to third capacitors, the through current can be more reliably suppressed, and the conversion ratio can be further increased to make the size smaller.

Further, in the first to fourth inventions, for example, it is preferable that the output end of the second snubber is connected to the signal input end of the second amplifying element via the fourth capacitor. As described above, according to the present invention, since the first buffer and the second buffer are provided, the second buffer operates when the voltage input to the first buffer is outside the operating voltage range of the first buffer. However, when the output end of the second buffer is connected to only the signal input end of the first amplifying element via the third capacitor (when the fourth capacitor disclosed in the sixth invention is not provided), only the second buffer is used. While the device is operating, feedback is applied to the second amplifying element, so the phase margin is lowered.

On the other hand, in the sixth aspect of the invention, since the output end of the second snubber is connected to the signal input ends of the first amplifying element and the second amplifying element via the third capacitor and the fourth capacitor, During the period in which the buffer is operated, the first amplification element and the second amplification element are respectively fed back to increase the phase margin during the period in which only the second buffer operates. Therefore, according to the sixth invention, the output voltage dependency of the phase margin can be further improved.

In addition, by providing the fourth capacitor, the second capacitor connected to the signal input end of the second amplifying element can be made smaller as in the fourth capacitor, and the phase compensating capacitor (first to fourth) can be further provided. Since the total value of the capacitance is reduced, the load of the input amplification section of the amplifying section can be further reduced, and the followability of the buffer (the first buffer and the second buffer) to the output voltage change can be further improved. Therefore, the conversion rate of the amplifying circuit is further improved.

Furthermore, the configuration in which the output end of the second buffer is connected to the signal input end of the first amplifying element via the third capacitor (the configuration in which the fourth capacitor of the sixth invention is not provided) is compared with the sixth invention configuration. As described above, even if the phase margin in the voltage range in which the first buffer does not operate is lowered, it is not necessary to increase the phase margin in the voltage range (for example, due to other factors, even if the phase margin is When the degree is too low and it is difficult to oscillate, it is also possible to adopt a configuration in which the fourth capacitor is not provided as described above, and even if the configuration of the fourth capacitor is not provided, it is possible to obtain a phase compensation without increasing the phase compensation as compared with the prior art. The capacitor ensures a high phase margin over a wide voltage range.

Further, in the sixth aspect of the invention, it is preferable that the first capacitor is smaller than the third capacitor and the second capacitor is larger than the fourth capacitor, as disclosed in the seventh invention. In the configuration in which the first to fourth capacitors are provided, the first capacitor and the fourth capacitor are auxiliary phase compensation capacitors. In the seventh invention, since the capacitors are made smaller, the first to fourth capacitors are used. When the total of the first to fourth capacitors is made smaller, the same phase margin improvement effect can be obtained. In addition, by reducing the total value of the first to fourth capacitors, the through current can be reliably suppressed, and the conversion ratio can be further increased to make the size smaller.

[Effect of the invention]

As described above, in the present invention, the first buffer and the second buffer are added to the amplifying unit that operates as the push-pull circuit including the first amplifying element and the second amplifying element provided in the output stage. a buffer, wherein the input end is connected to the output end of the amplifying unit, and the output end is connected to the signal input end of the first amplifying element via the first capacitor, and the second amplifying element via the second capacitor The signal input terminal is connected to the second buffer, wherein the input end is connected to the output end of the amplifying portion or the output end of the first buffer, and the output end is connected to at least the signal input end of the first amplifying element via the third capacitor. Therefore, it has an excellent effect that the effective operation range is large and the through current can be suppressed.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[First Embodiment]

Fig. 1 shows a display device 10 of this embodiment. The display device 10 is configured such that a peripheral circuit is connected to the display 12 composed of a TFT-LCD (Thin-Film Transistor Liquid-Crystal Display). When the display 12 is a TFT-LCD, the illustration is omitted, but the display 12 is configured such that liquid crystal is sealed between a pair of transparent substrates that are disposed to face each other with a predetermined interval therebetween, and the entire surface of one of the transparent substrates is opposed to each other. Electrodes are formed on the surface, and a plurality of data lines are respectively disposed on opposite faces of the other transparent substrate, are arranged at a fixed interval along the X direction of FIG. 1 and respectively extend in the Y direction of FIG. 1; and a plurality of gate lines, Arranged at a fixed interval along the Y direction of FIG. 1 and extending in the X direction of FIG. 1 respectively; a thin film transistor (TFT) and electrodes are respectively disposed at intersections (pixel positions) of the respective data lines and the respective gate lines; Moreover, each TFT is connected to the source electrode, the gate is connected to the gate line, and the drain is connected to the data line. Furthermore, the display 12 is not limited to a TFT-LCD, and may be other well-known displays such as a plasma display or an organic EL display.

In the display 12, a plurality of source drivers 14 are attached, and each of the data lines of the display 12 is connected to any one of the plurality of source drivers 14. A plurality of gate drivers 16 are respectively connected to the timing controller 18, and the timing controller 18 is connected to the image processor 20. The image processor 20 holds the image data representing the image to be displayed on the display 12 in the video memory or the like, and outputs the synchronization signal (horizontal synchronization signal and vertical synchronization signal) to the timing controller 18 at a fixed period. And in each period of the horizontal synchronization signal, the image data on one line of the display 12 along the X direction of FIG. 1 in the held image data (presenting the data voltage supplied to each data line of the display 12) The level RGB data) is sequentially output to the timing controller 18.

The timing controller 18 reads and writes the RGB data from the memory to the respective source drivers 14 after the RGB data input from the image processor 20 is temporarily written to the memory. Further, each of the source drivers 14 inputs the RGB data of the data line connected to the own driver from the timing controller 18, and then sets the bit in a fixed period corresponding to the source driver control signal input from the timing controller 18. The data voltage presented by the input RGB data is supplied to the corresponding data line.

Further, a plurality of gate drivers 16 are added to the display 12, and the respective gate lines of the display 12 are respectively connected to any one of the plurality of gate drivers 16. The plurality of gate drivers 16 are respectively connected to the timing controller 18, and sequentially switch the gate lines for supplying the gate signals according to the gate driver control signals input from the timing controller 18, and repeat the display for a predetermined time. The gate line of any of the plurality of gate lines of 12 supplies a gate signal. When a gate signal is supplied to a certain gate line, all the TFTs on one line connected to the gate line are turned on, and the data voltage supplied via the data line connected to each of the turned-on TFTs is connected. The electrodes connected to the respective TFTs are applied to the liquid crystal so that the light transmittance of the liquid crystal in each pixel position corresponding to each of the TFTs after the switching is changed. Thereby, it is convenient to display an image on a line in the display 12. Next, the image is displayed on the display 12 by repeating the above processing.

On the other hand, each of the source drivers 14 is configured such that the drive circuits 24 shown in FIG. 2 are provided corresponding to the respective data lines of the display 12. The drive circuit 24 is configured to be connected in series with the data buffer 26 to hold the RGB data transmitted from the timing controller 18; the D/A (digital/analog) converter 28 to output the RGB data from the data buffer 26, Converting to an analog signal of a voltage level corresponding to the value of the RGB data, and outputting the analog signal; the output terminal is connected to any one of the data lines in the display 12, and the signal input from the D/A converter 28 is amplified. Supply to the data line. Furthermore, in FIG. 2, the pixel (cell) in which the amplification circuit 30 applies the material voltage (the output voltage Vout of the amplification circuit 30) via the data line is represented as the capacitive load 62.

The amplifier circuit 30 corresponds to the amplifier circuit of the present invention (more specifically, the amplifier circuits disclosed in the first to fourth and sixth inventions), and includes an input amplifier section 32 composed of a differential amplifier circuit and a P-type MOS battery. Crystal 36 and output section 34 of N-type MOS transistor 38. The differential amplifying circuit of the input amplifying section 32 uses an amplifying circuit capable of performing a so-called rail to rail operation. The non-inverting input of the input amplifying section 32 is connected to the output of the D/A converter 28, and the inverting input is connected to the output of the amplifying circuit 30. Therefore, the input amplification section 32 is combined with the output section 34 as a voltage follower, and is input to the amplification section 32 so that the output voltage outputted through the output terminal of the amplification circuit 30 follows the output from the D/A converter 28. The manner in which the voltage change of the input signal changes causes the voltage level of the signal output via the output to change. The output terminals of the input amplification section 32 are respectively connected to the gate electrode pgate of the P-type MOS transistor 36 of the output section 34 and the gate electrode ngate of the N-type MOS transistor 38.

Further, in the P-type MOS transistor 36 of the output section 34, the source electrode is connected to the power supply terminal, and the source electrode is supplied with the power supply voltage VDD, and the drain electrode is connected to the output terminal of the amplifying circuit 30, and the N-type MOS is electrically connected. In the crystal 38, the source electrode is connected to the output terminal of the amplifier circuit 30, and the drain electrode is connected to the ground terminal. The P-type MOS transistor 36 and the N-type MOS transistor 38 of the output stage 34 operate as push-pull circuits (specifically, push-pull circuits that perform AB-stage operation due to overlapping of respective operating voltage ranges), and the push-pull In the circuit, the operating voltage range is different from the voltage level of the signals input to the respective gate electrodes pgate and ngate, so that the P-type MOS transistor 36 operates under the condition that the output voltage is increased, N-type. The MOS transistor 38 operates with the output voltage lowered.

Further, the P-type MOS transistor 36 corresponds to the first amplifying element of the present invention (specifically, the first amplifying element disclosed in the second invention), and the N-type MOS transistor 38 corresponds to the second amplifying element of the present invention ( Specifically, in the second amplifying element disclosed in the second aspect of the invention, the gate electrode of the P-type MOS transistor 36 corresponds to the signal input end of the first amplifying element, and the gate electrode of the N-type MOS transistor 38 corresponds to the second electrode. Amplifying the signal input of the component.

Further, the first voltage buffer 40 and the second voltage buffer 46 are connected to the output terminal of the amplifier circuit 30, respectively. The first voltage buffer 40 includes an N-type MOS transistor 42, and a gate electrode of the N-type MOS transistor 42 as an input terminal of the first voltage buffer 40 is connected to an output terminal of the amplifier circuit 30. The drain electrode of the N-type MOS transistor 42 is connected to the power supply terminal, the supply voltage VDD is supplied to the drain electrode, and the source electrode of the N-type MOS transistor 42 is grounded via the current source 44. Further, the source electrode of the N-type MOS transistor 42 as the output end of the first voltage buffer 40 is connected to the gate electrode pgate of the P-type MOS transistor 36 of the output stage 34 via the first phase compensation capacitor 52. Further, the second phase compensation capacitor 54 is also connected to the gate electrode ngate of the N-type MOS transistor 38 of the output section 34.

Further, the second voltage buffer 46 includes a P-type MOS transistor 48, and a gate electrode of the P-type MOS transistor 48 as an input terminal of the second voltage buffer 46 is connected to an output terminal of the amplifier circuit 30. The source electrode of the P-type MOS transistor 48 is connected to the power supply terminal via the current source 50, and supplies the power supply voltage VDD to the source electrode via the current source 50, and the drain electrode of the P-type MOS transistor 48 is grounded. Further, the source electrode of the P-type MOS transistor 48, which is the output end of the second voltage buffer 46, is connected to the gate electrode pgate of the P-type MOS transistor 36 of the output section 34 via the third phase compensation capacitor 56. Further, the fourth phase compensation capacitor 58 is also connected to the gate electrode ngate of the N-type MOS transistor 38 of the output section 34.

Furthermore, the first phase compensation capacitor 52 corresponds to the first capacitor of the present invention, the second phase compensation capacitor 54 corresponds to the second capacitor of the present invention, and the third phase compensation capacitor 56 corresponds to the third capacitor of the present invention, and the fourth capacitor The phase compensation capacitor 58 corresponds to the fourth capacitor disclosed in the sixth aspect of the invention. In the first embodiment, the four phase compensation capacitors 52 to the fourth phase compensation capacitor 58 have the same capacitance. . Moreover, the source driver 14 is commonly used for driving of a display of an arbitrary number of pixels (the number of data lines). Therefore, when the number of data lines in the display of the drive target does not coincide with an integral multiple of the number of drive circuits 24 provided in the source driver 14, a part of the drive circuits 24 provided in the source driver 14 (constituting the same) The amplifying circuit 30) is maintained in an unloaded state that is not connected to the data line.

Next, the operation of the amplifier circuit 30 will be described as an operation of the first embodiment. In the output section 34 of the amplifier circuit 30, since the P-type MOS transistor 36 and the N-type MOS transistor 38 operate as a push-pull circuit (specifically, a push-pull circuit that performs AB-stage operation) as described above, it is possible to A wider effective range of operation suitable for display 12 drive (application of a data voltage to a capacitive load 62 corresponding to each pixel (cell) of display 12) is obtained.

Further, the first voltage buffer 40 of the amplifying circuit 30 is a level shifting circuit of the source follower structure of the N-type MOS transistor 42, and the output voltage Vout of the amplifying circuit 30 is opposite to the power supply voltage VDD to the ground voltage. The operation is performed within a range higher than the value of the threshold voltage Vtn of the N-type MOS transistor 42. Further, the output voltage BUFN of the first voltage buffer 40 is a voltage lower than the output voltage Vout of the amplifier circuit 30 by the threshold voltage Vtn, and the output voltage BUFN that changes according to the output voltage Vout is passed through the first phase compensation capacitor 52. It is fed back into the gate electrode pgate of the P-type MOS transistor 36, and is fed back to the gate electrode ngate of the N-type MOS transistor 38 via the second phase compensation capacitor 54.

Further, the second voltage buffer 46 is a level shifting circuit of the source follower structure of the P-type MOS transistor 48, and the output voltage Vout of the amplifying circuit 30 is lower than the power supply voltage VDD, and the P-type Mos transistor is low. The operation is performed within a range of the value of the threshold voltage Vtp of 48 to the ground voltage. Further, the output voltage BUFP of the second voltage buffer 46 becomes a voltage higher than the output voltage Vout of the amplifier circuit 30 by the threshold voltage Vtp, and the output voltage BUFP that changes according to the output voltage vout is compensated via the third phase. The capacitor 56 is fed back into the gate electrode pgate of the P-type MOS transistor 36, and is fed back to the gate electrode ngate of the N-type MOS transistor 38 via the fourth phase compensation capacitor 58.

In the amplifier circuit 30 of the first embodiment, the output voltage Vout of the amplifier circuit 30 is fed back to the output section 34 via the first voltage buffer 40, the first phase compensation capacitor 52, and the second phase compensation capacitor 54. The P-type MOS transistor 36 and the N-type MOS transistor 38 are fed back to the P-type MOS transistor of the output section 34 via the second voltage buffer 46, the third phase compensation capacitor 56, and the fourth phase compensation capacitor 58. 36 and the N-type MOS transistor 38, therefore, compared with the case where the phase compensation is performed by the mirror effect (the configuration of FIG. 4), since zero (ωzb) is Ab times (Ab is the amplification factor of the voltage buffer), Further, the phase compensation capacitor (the total capacitance of the first phase compensation capacitor 52 to the fourth phase compensation capacitor 58) for ensuring the phase margin can be reduced.

In addition, the phase compensation capacitor (the total capacitance of the first phase compensation capacitor 52 to the fourth phase compensation capacitor 58) can be made small, and the first phase compensation capacitor 52 to the fourth phase compensation capacitor can be operated during the large amplitude operation. The voltage fluctuation of the gate electrodes of the P-type MOS transistor 36 and the N-type MOS transistor 38 caused by the coupling of 58 becomes small, and therefore, the P-type MOS transistor 36 and the N-type MOS transistor 38 will not be originally performed. The operation is performed during the operation, so that the through current can be prevented from flowing. Further, by reducing the phase compensation capacitor, the load of the input amplification section 32 is reduced, and the followability of the change of the output voltage Vout by the first voltage buffer 40 and the second voltage buffer 46 is improved. Thereby, the conversion rate of the amplifying circuit 30 is increased. Further, the size of the wafer on which the amplifier circuit 30 is mounted can be reduced.

Further, in the first embodiment, the first voltage buffer 40 and the second voltage buffer 46 have different operating voltage ranges, and the maximum operating voltage in the first voltage buffer 40 matches the power supply voltage VDD, and the second voltage Since the minimum operating voltage of the buffer 46 matches the ground voltage, the first voltage buffer 40 and the second voltage buffer 46 are within the entire range of the output voltage Vout of the amplifier circuit 30 (the power supply voltage VDD to the ground voltage). At least one of them can operate, and therefore, the output voltage dependency of the phase margin can be improved as compared with the case where only one voltage buffer is provided.

[Second Embodiment]

Next, a second embodiment of the present invention will be described. The same components as those in the first embodiment are denoted by the same reference numerals and will not be described. Fig. 3 shows an amplifier circuit 60 according to the second embodiment. The configuration of the amplifier circuit 60 of the second embodiment is substantially the same as that of the amplifier circuit 30 described in the first embodiment, and differs only in that the electrostatic capacitance Cn1 of the first phase compensation capacitor 52 and the second phase compensation capacitor 54 are electrostatically charged. In the capacitor Cn1, the capacitance Cp2 of the third phase compensation capacitor 56, and the capacitance Cn2 of the fourth phase compensation capacitor 58, Cn1 and Cp2 have capacitance values: Cn and Cp1 have capacitance values: small, and the capacitance relationship is small. Cp2>Cp1 and Cn1>Cn2. As described above, the amplifier circuit 60 of the second embodiment corresponds to the amplifier circuits disclosed in the first to fourth, sixth, and seventh inventions.

Since the operation of the amplifier circuit 60 of the second embodiment is the same as that of the amplifier circuit 30 described in the first embodiment, a wide effective operation range similar to that of the amplifier circuit 30 can be obtained, and the through current can be suppressed. Further, as described above, in the first voltage buffer 40 and the second voltage buffer 46 of the amplifier circuit 60 (30), the operating voltage range of the output voltage Vout of the amplifier circuit 60 (30) is different, and the output voltage is Vout. When the power supply voltage VDD or the power supply voltage VDD is an approximate value, only the first voltage buffer 40 operates, and when the output voltage Vout is the ground voltage or an approximate value of the ground voltage, only the second voltage buffer 46 operates. Accordingly, in the second embodiment, Cn1 and Cp2 have large capacitance values, and Cn2 and Cp1 have small capacitance values.

As a result, even if the capacitance value of Cp1+Cp2 in the second embodiment is smaller than the capacitance value of Cp1+Cp2 in the first embodiment, the same phase margin improvement effect can be obtained. Further, the load of the input amplification section 32 can be made smaller by making the Cp1+Cp2 or Cn1+Cn2 capacitance value smaller, thereby further increasing the conversion ratio of the amplification circuit 30. Moreover, it is also possible to further reduce the size of the wafer.

In addition, although the configuration in which all of the first phase compensation capacitor 52 to the fourth phase compensation capacitor 58 are provided has been described above, the present invention is not limited thereto, and the fourth phase compensation capacitor (or the first phase compensation capacitor 52) may be omitted. The number of phase compensation capacitors is three. When the fourth phase compensation capacitor 58 (or the first phase compensation capacitor 52) is omitted, when the output voltage Vout of the amplifier circuit is outside the operating voltage range of the first voltage buffer 40 (or the second voltage buffer 46) The phase margin will decrease, and when the phase margin when the output voltage Vout of the amplifier circuit is not required to be outside the above-described operating voltage range is increased, a high phase margin can be obtained in the expected voltage range to make the phase The number of compensation capacitors is three.

In addition, when the fourth phase compensation capacitor 58 is omitted as described above, the magnitude relationship of the capacitances of the first phase compensation capacitor 52 to the third phase compensation capacitor 56 is Cp1<Cn1 and Cp2. When the first phase compensation capacitor 52 is omitted, the magnitude relationship of the capacitances of the second phase compensation capacitor 54 to the third phase compensation capacitor 58 is Cn2<Cn1 and Cp2. The case where the electrostatic capacitances of the three phase compensation capacitors are different as described above corresponds to the fifth invention, and the total capacitance of the three phase compensation capacitors is compared with the case where the capacitances of the three phase compensation capacitors are all equal. When the value becomes small, the same phase margin improvement effect can be obtained by making the electrostatic capacitances of the three phase compensation capacitors different as described above, and the total capacitance of the three phase compensation capacitors can be made smaller. In order to suppress the through current, increase the conversion rate, and achieve small size.

Further, in the above description, the configuration in which the input end of the second voltage buffer 46 is connected to the output terminal of the amplifier circuit 30 (60) has been described. However, the present invention is not limited thereto, and the input terminal of the second voltage buffer 46 may be connected. At the output of the first voltage buffer.

Further, in the above description, the present invention has been described with respect to an aspect of an amplifying circuit for driving a display device (supply data voltage) such as an LCD. However, in the present invention, if an amplifying circuit (calculus amplifier) is an output segment, When the push-pull circuit operates, there is no doubt that it can be applied without being used for its purpose.

10. . . Display device

12. . . monitor

14. . . Source driver

16. . . Gate driver

18. . . Timing controller

20. . . Image processor

twenty four. . . Drive circuit

26. . . Data buffer

28. . . D/A converter

30. . . amplifying circuit

32. . . Input zoom section

34. . . Output segment

36. . . P-type MOS transistor

38. . . N-type MOS transistor

40. . . 1st voltage buffer

42. . . N-type MOS transistor

44. . . Battery

46. . . Second voltage buffer

48. . . P-type MOS transistor

50. . . Battery

52. . . First phase compensation capacitor

54. . . Second phase compensation capacitor

56. . . Third phase compensation capacitor

58. . . 4th phase compensation capacitor

60. . . amplifying circuit

62. . . Capacitive load

VDD. . . voltage

MPO. . . P-type transistor

BUFP. . . The output voltage

MNO. . . N type transistor

Pgate. . . Gate of P-type transistor MPO

Ngate. . . Gate of N-type transistor MNO

FIG. 1 is a block diagram showing a schematic configuration of a display device.

Fig. 2 is a circuit diagram showing an amplifier circuit of the first embodiment.

Fig. 3 is a circuit diagram showing an amplifier circuit of the second embodiment.

4 is an explanatory view for explaining generation of a through current.

twenty four. . . Drive circuit

26. . . Data buffer

28. . . D/A converter

30. . . amplifying circuit

32. . . Input zoom section

34. . . Output segment

36. . . P-type MOS transistor

38. . . N-type MOS transistor

40. . . 1st voltage buffer

42. . . N-type MOS transistor

44. . . Battery

46. . . Second voltage buffer

48. . . P-type MOS transistor

50. . . Battery

52. . . First phase compensation capacitor

54. . . Second phase compensation capacitor

56. . . Third phase compensation capacitor

58. . . 4th phase compensation capacitor

62. . . Capacitive load

VDD. . . voltage

MPO. . . P-type transistor

BUFP. . . The output voltage

MNO. . . N type transistor

Pgate. . . Gate of P-type transistor MPO

Ngate. . . Gate of N-type transistor MNO

Claims (7)

An amplifying circuit comprising: an amplifying unit having an input amplifying section and an output section; wherein the first amplifying element and the second amplifying element provided in the output section operate as a push-pull circuit; and the first buffer is connected to the input end An output end of the amplifying unit is connected to a signal input end of the first amplifying element via a first capacitor, and is connected to a signal input end of the second amplifying element via a second capacitor; and a second buffer, an input end An output end connected to the amplifying unit or an output end of the first buffer, and an output end connected to at least a signal input end of the first amplifying element via a third capacitor. The amplifying circuit according to claim 1, wherein the first amplifying element is connected to an output end of the power supply terminal and the amplifying unit, and operates to increase an output voltage of the amplifying unit. The second amplifying elements are respectively connected to the ground terminal and the output end of the amplifying unit, and operate when the output voltage of the amplifying unit is lowered. The amplifying circuit according to claim 1, wherein the amplifying portion is configured to be operable as a voltage follower. The amplifying circuit according to claim 1, wherein the first buffer is a voltage buffer, and an output voltage of the amplifying unit is equal to or lower than a power supply voltage and higher than a ground voltage by a first predetermined voltage value or higher. The operation is performed while the voltage of the first predetermined voltage is lower than the output voltage of the amplifying unit, and the second buffer is a voltage buffer, and the output voltage of the amplifying unit is compared with the power supply voltage. When the value of the second predetermined voltage is lower than the value of the ground voltage or more, the operation is performed, and a voltage higher than the output voltage of the amplifying unit is outputted by the second predetermined voltage. The amplifier circuit according to any one of claims 1 to 4, wherein the first capacitor is smaller than the second capacitor and the third capacitor. The amplifier circuit according to any one of claims 1 to 4, wherein an output end of the second buffer is connected to a signal input end of the second amplifying element via a fourth capacitor. The amplifier circuit according to claim 6, wherein the first capacitor is smaller than the third capacitor, and the second capacitor is larger than the fourth capacitor.