KR101047109B1 - Analog buffer and its driving method, liquid crystal display device using the same and its driving method - Google Patents

Abstract

The present invention relates to an analog buffer, a driving method thereof, a liquid crystal display using the same, and a driving method thereof.

An analog buffer according to an embodiment of the present invention includes an input unit for supplying a differential signal; An amplifier for amplifying the differential signal using a current mirror; And an output unit configured to receive and output the amplified signal from the amplifier.

Description

ANALOG BUFFER, DRIVING METHOD THEREOF, LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME AND DRIVING METHOD OF LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME}             

1 is a view showing a conventional liquid crystal display device.

2 is a block diagram schematically illustrating an analog buffer according to an exemplary embodiment of the present invention.

FIG. 3 is a diagram illustrating the analog buffer of FIG. 2 in detail.

4 is a diagram illustrating an example of an output unit of FIG. 3.

5 is a diagram illustrating a conventional analog buffer.

6 is a diagram illustrating a rising interval signal flow of an analog buffer according to an exemplary embodiment of the present invention.

7 is a view illustrating a signal flow of polling interval of an analog buffer according to an embodiment of the present invention.

8 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

9A through 9D are diagrams illustrating an inversion method of the data driver of FIG. 8.                 

FIG. 10 is a diagram illustrating a signal generated from the data driver of FIGS. 9A to 9B.

11 is a diagram illustrating a notebook computer using a liquid crystal display according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

2, 222 liquid crystal panel 4, 224 gate driver

6, 226: data driver 8, 228: timing controller

12, 212: thin film transistor 100: analog buffer

110: differential input unit 120: first amplifier unit

140: second amplifier 150: output unit

160: floating source unit 170: level shifter

230: common voltage generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog buffer, and more particularly, to an analog buffer having a fast response speed while minimizing power consumption, a driving method thereof, and a liquid crystal display using the same, and a driving method thereof.                         

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal panel having a pixel matrix and a driving circuit for driving the liquid crystal panel.

Specifically, the liquid crystal display includes a liquid crystal panel 2 having a pixel matrix, a gate driver 4 for driving gate lines GL1 to GLn of the liquid crystal panel 2, as shown in FIG. A data driver 6 for driving the data lines DL1 to DLm of the liquid crystal panel 2, and a timing controller 8 for controlling the driving timing of the gate driver 4 and the data driver 6. do.

The liquid crystal panel 2 includes a pixel matrix composed of pixels 12 formed at regions defined by intersections of the gate lines GL and the data lines DL. Each of the pixels 12 includes a liquid crystal cell Clc for adjusting light transmittance according to a pixel signal, and thin film transistors TFT for driving the liquid crystal cell Clc.

The thin film transistor TFT is turned on when the gate driving signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the video signal from the data line DL to the liquid crystal cell Clc. . The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the video signal charged in the liquid crystal cell Clc.

The liquid crystal cell Clc is equivalently represented by a capacitor and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT. In addition, the liquid crystal cell Clc further includes a storage capacitor (not shown) so that the charged video signal is stably maintained until the next video signal is charged. The liquid crystal cell Clc realizes gradation by adjusting light transmittance by changing an arrangement state of liquid crystals having dielectric anisotropy according to a video signal charged through the thin film transistor TFT.

The gate driver 4 shifts the gate start pulse GSP from the timing controller 8 according to the gate shift clock GSC to sequentially gate the gate lines GL1 to GLm. Supply a scan pulse of high voltage (VGH). The gate driver 4 supplies the gate low voltage VGL to the gate lines GL in the remaining periods during which the scan pulse of the gate high voltage VGH is not supplied.

The data driver 6 generates a sampling signal by shifting the source start pulse SSP from the timing controller 8 in accordance with the source shift clock SSC. In addition, the data driver 6 latches the video data RGB input according to the source shift clock SSC according to the sampling signal and then line-by-line in response to a source output enable signal. To supply. The data driver 6 converts the digital video data RGB, which is supplied in units of lines, into analog video signals using different gamma voltages supplied from the gamma voltage generator, and supplies the analog video signal to the data lines DL1 through DLm. Here, the data driver 6 determines the polarity of the video signal in response to the polarity control signal POL from the timing controller 8 when converting the video data into a video signal.

The timing controller 8 generates a gate start pulse GSP and a gate shift clock GSC for controlling the gate driver 4, and a source start pulse SSP and a source shift clock for controlling the data driver 6. (SSC), source output enable signal SOE, polarity control signal POL, and the like. In this case, the timing controller 8 transmits a data enable (DE) signal, a horizontal sync signal (Hsync), a vertical sync signal (Vsync), and pixel data (RGB) indicating a valid data section input from the outside. Control signals such as the GSP, GSC, GOE, SSP, SSC, SOE, and POL are generated by using a dot clock (DCLK) that determines timing.

In such a liquid crystal display, the data driver 6 has an analog buffer for preventing the video signal supplied to the data line from being distorted in accordance with the RC load amount of the data line. The gate driver 4 also includes an analog buffer for preventing the gate driving signal supplied to the gate line from being distorted according to the RC load amount of the gate line.

Analog buffers typically use one stage and two stages. The one stage configuration is usually composed of an input stage consisting of a differential input unit. Since the load connected to the first stage is charged and discharged by the current of the input stage, when the load is large, the current of the input stage needs to be increased. There is a problem that increases. In addition, the one-stage configuration has a problem in that the output range for the input is limited because the input stage is configured to drive current. As a result, the one-stage configuration has a voltage gain of 30dB to 60dB, which is very low, resulting in an input / output deviation caused by an offset, resulting in a gain error.

The two-stage configuration for solving the problem of the one-stage configuration reduces power consumption by allowing a large amount of current to flow in the driving circuit by using an output stage having excellent current driving capability. In addition, the voltage gain of the input terminal and the voltage gain of the output terminal are added to increase the voltage gain, thereby reducing the input / output deviation caused by the offset. In the two stage configuration, since the output stage is separated from the input stage, the output range is not limited.

However, the analog buffer of the conventional two stage configuration having such a structure is not limited to the range of the input voltage of the input terminal, but there is a problem that the range of the output voltage is limited. Accordingly, when the load of the input terminal is increased, the current of the input terminal is increased to increase the power consumption. In addition, while there is a high gain compared to the structure of the input stage, there is a structural problem to be used in the liquid crystal display device. Accordingly, there is an urgent need for an analog buffer having low power consumption and fast response speed capable of rapidly charging and discharging the liquid crystal panel 2 while maintaining a constant current at the input terminal.

Accordingly, an object of the present invention is to provide an analog buffer, a driving method thereof, a liquid crystal display using the same, and a driving method thereof, which satisfy low power consumption and fast response speed.

In order to achieve the above object, the analog buffer according to an embodiment of the present invention and the input unit for supplying a differential signal; An amplifier for amplifying the differential signal using a current mirror; And an output unit configured to receive and output the amplified signal from the amplifier.

The input unit includes at least two current mirrors for differentially supplying an input signal.

It is further provided with a holding unit connected between the amplifying unit and the output unit to maintain a constant current flowing therein.

The amplifying unit includes a first amplifying unit configured to receive and amplify a first signal among the differential signals; And a second amplifier connected to the first amplifier through the holding unit and receiving a second signal among the differential signals to ground a signal flowing through the holding unit.

A first current mirror connected to the input unit to generate the first signal; And a second current mirror connected to the first current mirror to amplify a current flowing through the first current mirror and to be supplied to the output unit.

The transistor of the second current mirror is formed to have a size 1 to 6 times larger than that of the transistor constituting the first current mirror.                     

The second amplifier comprises: a first current mirror connected to the input unit generating the second signal; And a second current mirror connected to the first current mirror and connected to the holding unit.

At least one first current mirror connected to an output terminal of the amplifying unit to allow a constant current to flow; A second current mirror is connected to the first current mirrors and maintains a constant current in response to a signal of an input terminal.

The constant current flowing in the holding portion flows corresponding to the size of a transistor constituting the amplifier.

The output unit includes at least one compensation capacitor connected between the amplifier and the holding unit; A level shifter connected to the amplifier to shift the signal level from the amplifier; First and second transistors having a gate connected to both ends of the level shifter and a source connected to each other are provided.

An analog buffer driving method according to an embodiment of the present invention includes the steps of generating a differential signal; Amplifying the differential signal using a current mirror; Supplying the amplified differential signal through an output unit.

Amplifying the differential signal using a current mirror; Supplying the differential signal to a first current mirror included in an amplifier; And amplifying a signal flowing in the first current mirror by using a second current mirror connected to the first current mirror and included in the amplifier.

Amplifying a signal flowing through the first current mirror by using a second current mirror connected to the first current mirror may include the second current having a size of 1 to 6 times the size of a transistor constituting the first current mirror. Amplifying the signal using a mirror.

The method of driving an analog buffer according to an embodiment of the present invention further includes a holding step of maintaining a constant signal flowing through the amplification unit connected to the amplification unit.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes: a liquid crystal panel having a pixel matrix; A data driver for driving data lines of the pixel matrix; A gate driver for driving gate lines of the pixel matrix; A common voltage generator supplying a common voltage as a reference voltage to the common electrode of the pixel matrix; An analog buffer included in at least one of the data driver, the gate driver, and the common voltage generator; The analog buffer includes an input unit for supplying a differential signal; An amplifier for amplifying the differential signal using a current mirror; And an output unit configured to receive and output the amplified signal from the amplifier.

The data driver supplies a data signal, which is inverted in polarity, to the data line in response to an input polarity control signal, and the common voltage generator supplies a common voltage driven by an AC to the common electrode.

A method of driving a liquid crystal display according to an exemplary embodiment of the present invention includes generating a data signal; Generating a gate signal; Generating a common voltage signal; Amplifying any one of the data signal, the gate signal, and the common voltage signal using a current mirror; Supplying the amplified signal to a liquid crystal panel.

Other objects and advantages of the present invention in addition to the above objects will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 to 11.

2 and 3 illustrate an analog buffer, that is, an analog buffer of a data driver, according to an embodiment of the present invention.

2 and 3, the analog buffer 100 according to an embodiment of the present invention includes a high potential voltage (VDD) supply line, an input unit 110 formed of a differential input pair, and an input from the input unit 110. First and second amplifiers 120 and 140 for amplifying the current, an output unit 150 for outputting currents from the first and second amplifiers 120 and 140 to the data line, and first and second A floating source current 160 is disposed between the two amplification units 120 and 140 and connected to the output unit 150 to maintain a constant internal signal.

The input unit 110 is formed in the form of current mirrors of the N-type transistors NM1 and NM2, and transmits a signal to the first amplifier 120. The first current mirrors NM1 and NM2 and the P-type transistors PM3 and PM4. A second current mirror (PM3, PM4) is formed in the form of a current mirror to transfer a signal to the second amplifier 140. The Vin + input is supplied to the gate of NM2 and the gate of PM4, and the Vin− input is supplied to the gate of NM1 and the gate of PM3. The Vin + input and Vin- input are in the form of alternating current waves and have an input form that is out of phase with each other.

The first amplifier 120 includes third current mirrors PM7 and PM8 connected to the first current mirrors NM1 and NM2, and a fourth current mirror that amplifies the current flowing through the third current mirrors PM7 and PM8. (PM11, PM12) are provided. In detail, first, the drains of PM7 and PM8 are respectively connected to the drains of NM1 and NM2, and the sources of PM7 and PM8 are commonly connected to the high potential voltage VDD. In addition, the gate and the drain of PM7 are connected, and the gate and the drain of PM8 are also connected. These third current mirrors PM7 and PM8 are connected to each PM7 and PM11 and PM12 each having the performance of K (herein, a constant of 0 <K <6, preferably 3) times PM8. Specifically, the gate of PM7 is connected to the gate of PM11, and the gate of PM8 is connected to the gate of PM12. Here, the sources of PM11 and PM12 are commonly connected to the high potential voltage VDD. As a result, the current flowing through PM11 and PM12 is amplified by K times in preparation for the signals flowing through PM7 and PM8. Here, K times may correspond to the size ratio of the transistor.

The second amplifier 140 may include the fifth current mirrors NM9 and NM10 connected to the second current mirrors PM3 and PM4 and the sixth current mirrors for amplifying the currents of the fifth current mirrors NM9 and NM10. NM17, NM18). In detail, each drain of NM9 and NM10 is connected to drains of PM3 and PM4, respectively, and gates of NM9 and NM10 are connected to gates of NM17 and NM18, respectively. In addition, the drains and gates of NM9 and NM10 are connected, and the source is grounded. Here, NM17 and NM18 have the performance of K (wherein constants of 0 <K <6, preferably 3) times NM9 and NM10. As a result, the signal flowing through NM17 and NM18 is amplified by K times as compared with the signal flowing through NM9 and NM10. Here, K times may correspond to the size ratio of the transistor.

The floating source unit 160 may include the seventh current mirrors PM13 and PM14 and the eighth current mirrors PM15 and PM16 that control the current flowing through the fourth current mirrors PM11 and PM12, and the seventh current mirrors PM13 and PM13. 9th current mirrors NM23 and NM24 connected to PM14 to induce a constant current to flow through the analog buffer, and drains of the 6th current mirrors NM17 and NM18 to the 6th current mirrors NM17 and NM18. The tenth current mirrors NM19 and NM20 and the eleventh current mirrors NM21 and NM22 for controlling the flowing current are connected to the tenth current mirrors NM19 and NM20 and the ninth current mirrors NM23 and NM24. And the twelfth current mirrors PM25 and PM26 for directing a constant current to flow through the analog buffer.

Specifically, first, the sources of PM13 and PM14 are commonly connected to the high potential voltage VDD, and the gates of PM13 and PM14 are connected to each other. These drains of PM13 and PM14 are connected to the drains of PM11 and PM12 respectively. Each drain of PM13 and PM14 is connected to each drain of NM23 and NM24. The sources of NM23 and NM24 are connected in common and are connected to the sources of PM25 and PM26 through current sources. Here, the input of Vin- is supplied to the gates of NM23 and PM25, and the input of Vin + is supplied to the gates of NM24 and PM26.

Next, the sources of PM15 and PM16 are connected to the drains of PM11 and PM12, and the gates of PM15 and PM16 are connected to each other and biased (Vb2). The drain of PM15 is connected to the gates of PM13 and PM14 as well as to the drain of NM21 through a current source. The source of PM15 is also connected to the drain of PM13. The drain of the PM16 is connected to the drain of the NM22 via the level shifter 170 and to the PM27 formed in the output unit 150. Here, the source of PM16 is directly connected to the output unit 150 via the compensation capacitor Cc. Here, a signal generated in the drain of the PM16 is connected to one end of the level shifter 170, and the signal is shifted in level and supplied to the drain of the NM22.

In addition, each source of NM19 and NM20 is grounded in common, and each gate is connected to each other. Each drain of these NM19 and NM20 is connected to each drain of NM17 and NM18. Each drain of NM19 and NM20 is connected to each drain of PM25 and PM26.

Finally, the sources of NM21 and NM22 are connected to the drains of NM17 and NM18, and the gates are commonly biased (Vb2). The drain of NM21 is connected to the gates of NM19 and NM20. The source of NM22 connected to the drain of NM18 is directly connected to the output unit 150 via the compensation capacitor Cc, and the drain of NM22 is connected to the level shifter 170.

The output unit 150 includes a level shifter 170 to stabilize the output signal and increase efficiency. The bases of PM27 and PM28 are connected to both ends of the level shifter 170. As one form of such an output unit 150, an AC signal is applied between the first and second DC power supplies and the first and second DC power supplies connected between the gates of PM27 and PM28, as shown in FIG. This type of feature has low power consumption and low output signal voltage distortion. However, the shape of the output unit 150 used in the analog buffer according to an embodiment of the present invention is not limited to FIG. 4.                     

Meanwhile, the size of the compensation capacitor Cc connected between the first and second amplifiers 120 and 140 and the floating source unit 160 and connected to the output terminal is phase margin, which is a characteristic of the analog buffer 100. Its size is constant because it is determined by For example, an analog buffer according to an embodiment of the present invention requires a phase margin of about 60 ° or more. Here, the analog buffer according to the embodiment of the present invention is not limited to a specific phase margin.

The driving of the analog buffer according to the embodiment of the present invention having such a structure will be described with reference to a conventional structure without an amplifier.

First, Figure 5 is a view showing a conventional analog buffer.

Referring to FIG. 5, when the current of the input unit 110r is referred to as Ib, and the current flowing through the faulted cascode connected to the input terminal is Ib / 2, the current at the node P is changed from Ib / 2 to Ib or 0. Will change. Accordingly, the conventional structure is charged and discharged through the compensation capacitor Cc by this amount of change. Here, the current flowing through the compensation capacitor Cc becomes Ib / 2.

FIG. 6 illustrates the flow of current when an analog buffer according to an embodiment of the present invention has voltages at the input terminals Vin + and Vin− in a rising period.

Referring to FIG. 6, NM2 of the input unit 110 is turned on because the voltage of the input terminal Vin + is in the rising period, and accordingly, PM11 of the second current mirrors PM11 and PM12 of the first amplifier 120 is turned on. Among the first current mirrors PM7 and PM8 of the first amplifier 120, the current of the high potential voltage VDD flowing in the PM8 is amplified by K times and transmitted. Meanwhile, NM1 of the input unit 110 is turned off because the input terminal Vin- is in the rising period. Accordingly, the current I flows in the PM7 of the first current mirrors PM7 and PM8 of the first amplifier 120. The current I flowing through the PM7 is supplied to the gate of the PM12 of the first amplifier 120, and as a result, a current of "0" is transmitted to the PM12 of the first amplifier 120. At this time, a current having a constant magnitude flows through the current source flowing through the floating source unit 160. Therefore, since the current flowing through the PM11 of the first amplifier 120 is greater than the current flowing through the floating source unit 160, the current flowing through the PM12 of the first amplifier 120 becomes "0". On the other hand, at the Vin- input terminal, a current flows to PM3 of the input unit 110, and the current is supplied to each gate of NM9 of the fifth current mirror of the second amplifier 140 and NM18 of the sixth current mirror. From the node B, it can be seen that the current I flowing from the level shifter 170 flows through the NM18 of the second amplifier 140. In addition, when a rising signal is applied to each of the input terminals Vin + and Vin− included in the floating source unit 160, NM24 of the ninth current mirror of the floating source unit 160 is turned on and NM23 is turned off. Here, in the node A connected to the auxiliary capacitor Cc and the output unit 150, the PM12 of the fourth current mirror of the first amplifier 120 and the seventh current mirror of the floating source unit 160 are included. Since no current flows in the PM14, the current flowing through the NM24 and the level shifter 170 should flow through the auxiliary capacitor Cc. Therefore, the current flowing in the level shifter 170 is kept constant at I, so that the current flowing in the output unit 150 flows by 1.5 KI.

5 and 6, an analog buffer according to an exemplary embodiment of the present invention and a conventional structure will be compared.                     

First, in FIG. 6, let the current of the input unit 110 be 2I, and define each of the current sources flowing through the floating source unit 160 and the level shifter 170 as KI / 2, KI, and I. Accordingly, according to the current I associated with the first amplifier 120 among the currents of the differential input terminal 110, KI, which is the current amplified by K times the current flowing in the NM2, flows. Accordingly, 2KI + 2I flows in the current flowing through the output unit 160. Here, in the conventional structure shown in FIG. 5, if the current of the input unit 110r is Ib, if the size of the transistor is applied, the current flowing through the circuit becomes 3Ib. Accordingly, the current flowing through the analog buffer according to the embodiment of the present invention and the current in the conventional structure satisfy the following Equation 1.

3Ib = 2I (K + 1)

In addition, the current flowing through the auxiliary capacitor Cc of the analog buffer 100 is 1.5 KI. Substituting this in Equation 1 above,

Becomes

Equation 2 above shows that the analog buffer of the structure without the amplification unit can obtain a response time improvement of up to 4.5 times when compared with the magnitude of the current charged and discharged in the rising and falling intervals of Ib / 2. . Specifically, the response speed is expressed as in Equation 3 below.                     

Here, since the response speed is a slope divided by time, the ratio of the current flowing through the compensation capacitor Cc may be calculated as a ratio of the response speed. Accordingly, the current 4.5Ib / 2 flowing through the compensation capacitor Cc according to the embodiment of the present invention shows a 4.5 times improvement in performance compared to the current Ib / 2 flowing through the compensation capacitor Cc in the structure without the amplifier. Can be.

FIG. 7 illustrates a flow of current when an analog buffer according to an embodiment of the present invention passes a voltage of an input terminal through a polling period.

Referring to FIG. 7, when the voltages of the input terminals Vin + and Vin− pass through the polling period, the current flowing into the input unit 110 flows by 1.5 KI. In detail, when the voltages of the input terminals Vin + and Vin− pass through the polling period, NM2 of the input unit 110 is turned off and NM1 of the input unit 110 is turned on. Since the NM2 of the input unit 110 is turned off, the current flowing through the PM11 of the first amplifier 120 becomes "0". This current flow is the same as the principle that the current flow of the first amplifier 120 PM12 becomes "0" during the rising period. As a result, the current of the output unit 150 flows as much as 1.5 KI to the input unit 110 through the node A point. Therefore, when the characteristics of the analog buffer according to the embodiment of the present invention are compared with the conventional structure in both the rising section and the polling section, the response speed of the analog buffer 100 according to the embodiment of the present invention is not only very fast but also in the current. It can be seen that the power consumption is also low.

Here, the transistor types used in the analog buffer 100 according to the embodiment of the present invention may be switched in association with each other. That is, when the P type transistor is replaced with the N type transistor, the N type transistor may be replaced with the P type transistor in consideration of the signal flow.

8 is a diagram illustrating a liquid crystal display including an analog buffer according to an exemplary embodiment of the present invention.

Referring to FIG. 8, a liquid crystal display including an analog buffer according to an embodiment of the present invention drives the liquid crystal panel 222 having a pixel matrix and the gate lines GL1 to GLn of the liquid crystal panel 222. Generating a common voltage supplying a common voltage, which is a reference voltage, to the gate driver 224, the data driver 226 for driving the data lines DL1 to DLm of the liquid crystal panel 222, and the common electrode of the pixel matrix. The unit 230 includes a timing controller 228 for controlling driving timings of the gate driver 224 and the data driver 226.

The liquid crystal panel 222 includes a pixel matrix composed of pixels 212 formed at respective regions defined by intersections of the gate lines GL and the data lines DL. Each of the pixels 212 includes a liquid crystal cell Clc for adjusting light transmittance according to a pixel signal, and thin film transistors TFT for driving the liquid crystal cell Clc.

The thin film transistor TFT is turned on when the gate driving signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the video signal from the data line DL to the liquid crystal cell Clc. . The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the video signal charged in the liquid crystal cell Clc.

The liquid crystal cell Clc is equivalently represented by a capacitor and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell Clc further includes a storage capacitor (not shown) so that the charged video signal is stably maintained until the next video signal is charged. The liquid crystal cell Clc realizes gradation by adjusting light transmittance by changing an arrangement state of liquid crystals having dielectric anisotropy according to a video signal charged through the thin film transistor TFT.

The gate driver 224 shifts the gate start pulse GSP from the timing controller 228 according to the gate shift clock GSC to sequentially gate the gate lines GL1 to GLm. Supply a scan pulse of high voltage (VGH). The gate driver 224 supplies the gate low voltage VGL to the gate lines GL in the remaining periods during which the scan pulse of the gate high voltage VGH is not supplied.

The data driver 226 generates a sampling signal by shifting a source start pulse SSP from the timing controller 228 according to a source shift clock SSC. In addition, the data driver 226 latches the video data RGB input according to the source shift clock SSC according to the sampling signal, and then relies on a line unit in response to a source output enable (SOE) signal. To supply. The data driver 226 converts digital video data RGB, which is supplied in units of lines, into analog video signals using different gamma voltages supplied from the gamma voltage generator, and supplies the analog video signal to the data lines DL1 through DLm. Here, the data driver 226 determines the polarity of the video signal in response to the polarity control signal POL from the timing controller 228 when converting the video data into the video signal.

The common voltage generator 230 is a common voltage that is a reference voltage of a signal generated from the data driver 226 by being located on a printed circuit board (not shown) connected to a tape carrier package (TCP) on which the data driver 226 is mounted. The voltage is generated and supplied to the liquid crystal panel 222. This common voltage may be driven by alternating current and direct current.

The timing controller 228 generates a gate start pulse GSP and a gate shift clock GSC for controlling the gate driver 224, and a source start pulse SSP and a source shift clock for controlling the data driver 226. (SSC), source output enable signal SOE, polarity control signal POL, and the like. In this case, the timing controller 228 transmits a data enable (DE) signal, a horizontal sync signal (Hsync), a vertical sync signal (Vsync), and pixel data (RGB) indicating a valid data section input from the outside. Control signals such as the GSP, GSC, GOE, SSP, SSC, SOE, and POL are generated by using a dot clock (DCLK) that determines timing.

The data driver 226 and the gate driver 224 of the liquid crystal display having the above structure are analog according to an embodiment of the present invention to prevent the video signal supplied to the data line from being distorted according to the RC load amount of the line. A buffer is provided. In addition, the AC-driven common voltage generator may also include an analog buffer 100 according to an embodiment of the present invention.

Here, the driving of the analog buffer 100 will be described using the data driver 226 as an example. The data driver 226 and the data line use an inversion scheme to reduce power consumption and improve driving. This inversion method is a 1-dot inversion method in which the positive and negative polarities intersect in a horizontal line as shown in FIGS. 9A to 9D, a 2-dot inversion method that intersects by two dots, and an area unit is intersected. Square inversion method and line inversion method. The waveform applied to this inversion method is changed while crossing the positive and negative polarities as shown in FIG. 10. This waveform has a delay 210 under the influence of the resistance and the capacitor of the line. Here, the response speed can be improved by using the analog buffer according to the embodiment of the present invention. Specifically, the analog buffer according to the embodiment of the present invention amplifies the output signal and increases the response speed of the signal by increasing the amount of the supplied signal. Accordingly, in driving the liquid crystal panel 222, the delay formed due to the resistance of the line is reduced (200) and dot defects do not occur even in the inversion driving.

Such an analog buffer 100 may be used in a portable information device, a general information device, an office information device, or the like, as shown in FIG. 11.

As described above, the analog buffer according to the embodiment of the present invention amplifies the current of the input terminal and improves the response speed of the output unit by using the floating source unit. Accordingly, since the power supply having a high response speed can be supplied to the output unit without changing the current of the input terminal, power consumption can be reduced and signal distortion due to the RC delay of the data line can be prevented. By using the analog buffer such as a data driver, a gate driver and a common voltage generator of the liquid crystal display, the liquid crystal display according to the exemplary embodiment of the present invention has an effect of improving image quality.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (17)

An input unit for supplying a differential signal; An amplifier for amplifying the differential signal using a current mirror; An output unit for receiving and outputting an amplified signal from the amplifier; And a holding unit connected between the amplifying unit and the output unit to maintain a constant current flowing therein. The method of claim 1, The input unit has an analog buffer, characterized in that it comprises at least two current mirrors for differentially supplying the input signal. delete The method of claim 1, The amplification unit A first amplifier which receives and amplifies a first signal among the differential signals; And a second amplifying part connected to the first amplifying part through the holding part and receiving a second signal among the differential signals to ground a signal flowing through the holding part. The method of claim 4, wherein The first amplification unit A first current mirror connected to the input unit for generating the first signal; And a second current mirror connected to the first current mirror to amplify a current flowing through the first current mirror and to be supplied to the output unit. The method of claim 5, The transistor of the second current mirror The analog buffer, characterized in that 1 to 6 times the size of the transistor constituting the first current mirror. The method of claim 4, wherein The second amplification unit A first current mirror connected to the input unit for generating the second signal; And a second current mirror connected to the first current mirror and connected to the holding unit. The method of claim 1, The holding unit At least one first current mirror connected to an output terminal of the amplifying unit to allow a constant current to flow; And a second current mirror connected to the first current mirrors and maintaining a constant current corresponding to a signal of an input terminal. The method of claim 8, The constant current flowing in the holding portion is And an analog buffer corresponding to the size of a transistor constituting the amplifier. The method of claim 1, The output unit At least one compensation capacitor connected between the amplifying unit and the holding unit; A level shifter connected to the amplifier to shift the signal level from the amplifier; And first and second transistors having gates connected to both ends of the level shifter and whose sources are connected to each other. Generating a differential signal; Amplifying the differential signal using a current mirror; Supplying the amplified differential signal through an output unit; Amplifying the differential signal using a current mirror, Supplying the differential signal to a first current mirror included in an amplifier; And amplifying a signal flowing through the first current mirror using a second current mirror connected to the first current mirror and included in the amplifier. delete The method of claim 11, Amplifying a signal flowing in the first current mirror by using a second current mirror connected to the first current mirror, And amplifying the signal by using the second current mirror having a size of 1 to 6 times the size of a transistor constituting the first current mirror. The method of claim 11, And a holding step of keeping the signal flowing in the amplifying section constant while being connected to the amplifying section. A liquid crystal panel having a pixel matrix; A data driver for driving data lines of the pixel matrix; A gate driver for driving gate lines of the pixel matrix; A common voltage generator supplying a common voltage as a reference voltage to the common electrode of the pixel matrix; An analog buffer included in at least one of the data driver, the gate driver, and the common voltage generator; The analog buffer, An input unit for supplying a differential signal; An amplifier for amplifying the differential signal using a current mirror; An output unit for receiving and outputting an amplified signal from the amplifier; And a holding unit connected between the amplifying unit and the output unit to maintain a constant current flowing therein. The method of claim 15, The data driver supplies a polarized inversion data signal to the data line in response to an input polarity control signal, And the common voltage generator supplying a common voltage driven by the AC to the common electrode. Generating a data signal; Generating a gate signal; Generating a common voltage signal; Generating a differential signal for any one of the data signal, the gate signal, and the common voltage signal; Amplifying the differential signal using a current mirror; Supplying the amplified differential signal to a liquid crystal panel; Amplifying the differential signal using a current mirror, Supplying the differential signal to a first current mirror included in an amplifier; And amplifying a signal flowing in the first current mirror by using a second current mirror connected to the first current mirror and included in the amplifier.

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