TWI475807B - Delay line circuit - Google Patents

Description

Delay line circuit

The present invention relates to a delay line circuit, and more particularly to a delay line circuit implemented by phase interpolation and a phase interpolation module thereof.

The delay line circuit is used in the semiconductor element to adjust the clock delay of signals such as input/output signals and clock signals. A delay line circuit having a phase interpolation circuit is one of delay line circuits and has been widely used to adjust the timing of internal clock signals.

The analog phase interpolation circuit uses analog components (such as adders, multipliers, mixers, amplifiers, etc.) to adjust the phase difference between the two reference clocks. Since the time delay is present in the analog components, it is necessary to use a delay compensation component to adjust the phase between the reference clock and the interpolated clock. In addition, there are different time jitters and variations in the delay compensation component. The time delay of these components is sensitive to changes in the input data rate, process parameters, and temperature.

A digital component (such as an inverter) in the digital phase interpolation circuit is used to adjust the phase difference between the two reference clocks. The digital phase interpolation circuit can be implemented with a simple circuit and can accurately provide a clear phase of the signal. Therefore, digital phase interpolation circuits are widely used in various semiconductor elements and circuits, such as full-digital delay phase locked loop (DLL) circuits. Well-designed digital phase interpolation circuits or mixed-signal phase interpolation circuits are necessary for high-speed circuits or circuits used to generate clock signals.

Figure 1 shows a block diagram of a conventional delay line circuit. Referring to FIG. 1, the delay line circuit 400 includes a plurality of phase interpolation units 401 to 403. The phase interpolating unit 401 includes three inverters 4011 to 4013. The input terminals of the inverters 4011 and 4012 receive a first input signal SI1, and the output terminal is coupled to an input terminal of the inverter 4013. An output of the inverter 4013 outputs a first output signal SO1 which is a delayed signal of the input signal SI1. The phase interpolation unit 403 includes three inverters 4031 to 4033. The input terminals of the inverters 4031 and 4032 receive a second input signal SI2, and the output terminal is coupled to an input terminal of the inverter 4033. An output of the inverter 4033 outputs a second output signal SO2, which is a delayed signal of the input signal SI2.

The phase interpolation unit 402 includes three inverters 4021 to 4023. The input terminals of the inverters 4021 and 4022 individually receive the first input signal SI1 and the second input signal SI2, and the output end is coupled to an input terminal of the inverter 4023. An output of the inverter 4023 outputs a third output signal SO3 whose settling time is between the settling times of the output signals S01 and SO2. The sizes of the inverters 4011 and 4012 are not the same as each other, the sizes of the inverters 4021 and 4022 are not the same as each other, and the sizes of the inverters 4031 and 4032 are not identical to each other, so that the settling time of the output signal SO3 will be The output signals SO1 and SO2 establish an intermediate value of time. Further, when the phases of the input signals SI1 and SI2 are different from each other, a conflicting current is generated between the inverters 4021 and 4022.

The invention discloses a phase interpolation module. In an embodiment of the invention, the phase interpolation module includes first, second, and third phase interpolation units. Each of the first, second, and third phase interpolating units includes a first inverter, a second inverter, a third inverter, a first resistor, and a second resistor . The first electrical group is coupled between an output of the first inverter and an input of the third inverter. The second resistor is coupled between an output of the second inverter and the input of the third inverter. The first and second inverters in the first phase interpolating unit receive a first signal, and the first and second inverters in the third phase interpolating unit receive a second signal, And the first and second inverters in the second phase interpolating unit individually receive the first signal and the second signal.

The invention further discloses a delay line circuit. In an embodiment of the invention, the delay line circuit includes a first phase interpolation module including first, second, and third phase interpolation units. Each of the first, second, and third phase interpolating units includes a first inverter, a second inverter, a third inverter, a first resistor, and a second resistor . The first electrical group is coupled between an output of the first inverter and an input of the third inverter. The second resistor is coupled between an output of the second inverter and the input of the third inverter. The first and second inverters in the first phase interpolating unit receive a first signal, and the first and second inverters in the third phase interpolating unit receive a second signal, The first and second inverters in the second phase interpolating unit individually receive the first signal and the second signal, and the third inverter in the first phase interpolating unit outputs a third The third inverter in the third phase interpolating unit outputs a fifth signal, and the third inverter in the second phase interpolating unit outputs a fourth signal.

The delay line circuit further includes a second phase interpolation module, which includes Fourth, fifth, sixth, seventh and eighth phase interpolation units. Each of the fourth, fifth, sixth, seventh, and eighth phase interpolation units includes a first inverter, a second inverter, a third inverter, and a first a resistor and a second resistor. The first resistor is coupled between an output of the first inverter and an input of the third inverter. The second resistor is coupled between an output of the second inverter and the input of the third inverter. The first and second inverters in the fourth phase interpolating unit receive the third signal, and the first and second inverters in the fifth phase interpolating unit individually receive the third signal And the fourth signal, the first and second inverters in the sixth phase interpolating unit receive the fourth signal, and the first and second inverters in the seventh phase interpolating unit The fourth signal and the fifth signal are individually received, and the first and second inverters in the eighth phase interpolation unit receive the fifth signal. The first and second resistors in the first to the eighth phase interpolating units are arranged in a column, and the first to third phase interpolating units in the first phase interpolating module The circuit layout and the circuit layout of the fourth to the eighth phase interpolating units in the second phase interpolating module are staggered.

The technical features of the present invention have been briefly described above, and the detailed description below will be better understood. Other technical features constituting the subject matter of the patent application of the present invention will be described below. It is to be understood by those of ordinary skill in the art that the present invention may be practiced otherwise. Those of ordinary skill in the art to which the present invention pertains should also be able to understand that such equivalent construction cannot be separated. The spirit and scope of the invention as set forth in the appended claims.

The phase interpolation unit for implementing the delay line circuit of the present invention will be described below. The delay line circuit includes at least one phase interpolation unit, and the phase interpolation units form at least one phase interpolation module. 2 shows a block diagram of a phase interpolation module 1100 in accordance with an embodiment of the present invention.

Referring to FIG. 2, the phase interpolation module 1100 includes three identical phase interpolation units 1110 to 1130. The phase interpolating unit 1110 includes three inverters 1112, 1114, 1116 and two resistors 1118, 1119. The outputs of inverters 1112 and 1114 are individually coupled to one end of resistors 1118 and 1119, while the input of inverter 1116 is coupled to the other ends of resistors 1118 and 1119. The phase interpolating unit 1120 includes three inverters 1122, 1124, 1126 and two resistors 1128, 1129. The outputs of inverters 1122 and 1124 are individually coupled to one ends of resistors 1128 and 1129, while the inputs of inverter 1126 are coupled to the other ends of resistors 1128 and 1129. The phase interpolating unit 1130 includes three inverters 1132, 1134, 1136 and two resistors 1138, 1139. The outputs of inverters 1132 and 1134 are individually coupled to one end of resistors 1138 and 1139, while the input of inverter 1136 is coupled to the other ends of resistors 1138 and 1139.

The inverters 1112 and 1114 receive the input signal S ₁₁ and output an inverted input signal. The inverted signals pass through resistors 1118 and 1119 to form a combined signal I ₁₁ at the input of inverter 1116. The inverter 1116 receives the combined signal I ₁₁ superposed on the inverted signals, and generates an interpolation signal S ₂₁ which is a delayed signal of the signal S ₁₁ . The inverters 1132 and 1134 receive the input signal S ₁₂ and output an inverted input signal. The inverted signals pass through resistors 1138 and 1139 to form a combined signal I ₂₂ at the input of inverter 1136. The inverter 1136 receives the combined signal I ₂₂ superposed from the inverted signals, and generates an interpolation signal S ₂₃ which is a delayed signal of the signal S ₁₂ .

The inverters 1122 and 1124 individually receive the input signals S ₁₁ and S ₁₂ and output inverted input signals. The inverted signals pass through resistors 1128 and 1129 to form a combined signal I ₁₂ at the input of inverter 1126. The inverter 1126 receives the combined signal I ₁₂ superposed from the inverted signals such that the settling time of the interpolated signal S ₂₂ is between the interpolation signals S ₂₁ and S ₂₃ established. The inverters 1112 to 1116, 1122 to 1126, and 1132 to 1136 may be identical to each other. Therefore, the time difference between the input signals S ₁₁ and S ₁₂ is the same as the time difference between the interpolation signals S ₂₁ and S ₂₃ , and the time at which the interpolation signal S _{22 is} established may be the intermediate value of the settling times of the interpolation signals S ₂₁ and S ₂₃ .

3 shows waveform diagrams of input signals S ₁₁ to S ₁₂ and interpolation signals S ₂₁ to S ₂₃ in accordance with an embodiment of the present invention. The input signals S ₁₁ and S _{12 are} individually established at times t ₁ and t ₂ . As previously mentioned, the interpolated signals S ₂₁ and S ₂₃ are delayed signals of the input signals S ₁₁ and S ₁₂ . The time difference (t _{2 -} t ₁ ) between the input signals S ₁₁ and S ₁₂ is the same as the time difference (t _{4 -} t ₃ ) between the interpolation signals S ₂₁ and S ₂₃ . The time t ₅ at which the interpolation signal S _{22 is} established is between times t ₃ and t ₄ . In the present embodiment, time t ₅ is the intermediate value of times t ₃ and t ₄ .

With this configuration, the collision current between inverters 1122 and 1124 is limited by the sum of the resistances of resistors 1128 and 1129. The size of the inverters 1122 and 1124 can be adjusted to be the same by adjusting the ratio of the resistance between the resistors 1128 and 1129. When the sizes of the inverters 1122 and 1124 are the same, the sensitivity to process variation is reduced. Furthermore, since the ratio of the resistance between the resistors 1128 and 1129 is not sensitive to variations in the process, the interpolation signal S _{22 is} not susceptible to process variations. In a similar manner, the sizes of inverters 1112 and 1114 can be adjusted to be the same by adjusting the ratio of the resistance between resistors 1118 and 1119, while the sizes of inverters 1132 and 1134 can be adjusted by adjusting resistors 1138 and 1139. The ratio of resistance values is adjusted to be the same. Therefore, the interpolated signals S ₂₁ and S ₂₃ will not be susceptible to process variations.

Referring to Figure 2, the rise times of the combined signals I ₁₁ , I ₁₂ and I ₂₂ may be the same due to the same bias conditions. Further, the fall times of the interpolation signals S ₂₁ to S ₂₃ may also be the same due to the same bias conditions. Therefore, the interpolation signals S ₂₁ to S ₂₃ may have the same duty cycle. The equal rise times of the combined signals I ₁₁ , I ₁₂ and I ₂₂ can be easily accomplished by adjusting the ratio between the resistors 1128 and 1129 or adjusting the size of the inverters 1122 and 1124 such that the sizes of the inverters 1122 and 1124 are The same as each other, or the resistance of the resistor 1128 and the resistance of the resistor 1129 are identical to each other. Therefore, the duty cycle of the interpolation signals S ₂₁ to S ₂₃ can automatically track the duty cycle of the input signals S ₁₁ and S ₁₂ .

After describing a phase interpolation module composed of at least one phase interpolation unit, a delay line circuit implemented by phase interpolation will be described below. 4 shows a block diagram of a delay line circuit 3000 in accordance with an embodiment of the present invention. The delay line circuit 3000 includes three stages of phase interpolation modules 1100, 1200 and 1300 arranged in series. The delay line circuit 3000 is designed to output nine interpolated signals _S41 to _S49 . However, the invention should not be limited thereto. The phase interpolation module 1110 in FIG. 4 is the same as the phase interpolation module in FIG. The phase interpolation module 1200 has five phase interpolation units 1210 to 1250, the phase interpolation module 1300 has nine phase interpolation units 1310 to 1390, and phase interpolation units 1210 to 1250 and phase interpolation units 1310 to 1390. The detailed circuit in the same is the same as the detailed circuit of one of the phase interpolating units 1110 to 1130.

5 shows waveform diagrams of input signals S ₁₁ to S ₁₂ and interpolation signals S ₂₁ to S ₂₃ , S ₃₁ to S ₃₅ and S ₄₁ to S ₄₉ of the delay line circuit 3000 according to an embodiment of the present invention. Referring to FIGS. 4 and 5, as described above, the phase interpolation module 1100 outputs the interpolation signals S ₂₁ to S ₂₃ after receiving the input signals S ₁₁ to S ₁₂ . The operation of the input signals S ₁₁ to S ₁₂ , the interpolation signals S ₂₁ to S ₂₃ and the phase interpolation module 1110 will not be described again. The operation of the phase interpolation modules 1200 and 1300 and the generation of the interpolation signals S ₃₁ to S ₃₅ and S ₄₁ to S ₄₉ are described below.

The phase interpolation units 1210, 1230 and 1250 individually receive the interpolation signals S ₂₁ , S ₂₂ and S _{23 and} then individually output the interpolation signals S ₃₁ , S ₃₃ and S ₃₅ , wherein the interpolation signals S ₃₁ , S ₃₃ and S ₃₅ is a delayed signal of the interpolation signals S ₂₁ , S ₂₂ and S ₂₃ . The time difference (t _{5 -} t ₃ ) between the interpolation signals S ₂₁ and S ₂₂ is the same as the time difference (t _{9 -} t ₆ ) between the interpolation signals S ₃₁ and S ₃₃ . The time difference (t _{4 -} t ₅ ) between the interpolation signals S ₂₂ and S ₂₃ is the same as the time difference (t _{7 -} t ₉ ) between the interpolation signals S ₃₃ and S ₃₅ . The time t ₈ at which the interpolation signal S _{32 is} established is between times t ₆ and t ₉ . In the present embodiment, time t ₈ is the intermediate value of times t ₆ and t ₉ . The time t ₁₀ at which the interpolation signal S _{34 is} established is between times t ₉ and t ₇ . In the present embodiment, the time t ₁₀ is the intermediate value of the times t ₉ and t ₇ .

The phase interpolation units 1310, 1330, 1350, 1370 and 1390 individually receive the interpolation signals S ₃₁ , S ₃₂ , S ₃₃ , S ₃₄ and S _{35 and} then individually output the interpolation signals S ₄₁ , S ₄₃ , S ₄₅ , S ₄₇ and S ₄₉ , wherein the interpolation signals S ₄₁ , S ₄₃ , S ₄₅ , S ₄₇ and S ₄₉ are delayed signals of the interpolation signals S ₃₁ , S ₃₂ , S ₃₃ , S ₃₄ and S ₃₅ . The time difference (t _{8 -} t ₆ ) between the interpolation signals S ₃₁ and S ₃₂ is the same as the time difference (t _{14 -} t ₁₁ ) between the interpolation signals S ₄₃ and S ₄₁ . The time difference (t _{9 -} t ₈ ) between the interpolation signals S ₃₂ and S ₃₃ is the same as the time difference (t _{16 -} t ₁₄ ) between the interpolation signals S ₄₃ and S ₄₅ . The time difference (t _{10 -} t ₉ ) between the interpolation signals S ₃₃ and S ₃₄ is the same as the time difference (t _{18 -} t ₁₆ ) between the interpolation signals S ₄₅ and S ₄₇ . The time difference (t _{7 -} t ₁₀ ) between the interpolation signals S ₃₄ and S ₃₅ is the same as the time difference (t _{12 -} t ₁₈ ) between the interpolation signals S ₄₉ and S ₄₄ . The time t ₁₃ at which the interpolation signal S _{42 is} established is between times t ₁₁ and t ₁₄ . In the present embodiment, time t ₁₃ is the intermediate value of times t ₁₁ and t ₁₄ . The time t ₁₅ established by the interpolation signal S _{44 is} between time t ₁₄ and t ₁₆ . In the present embodiment, time t ₁₅ is the intermediate value of time t ₁₄ and t ₁₆ . The time t ₁₇ established by the interpolation signal S _{46 is} between times t ₁₆ and t ₁₈ . In the present embodiment, time t ₁₇ is the intermediate value of times t ₁₆ and t ₁₈ . The time t ₁₉ at which the interpolation signal S _{48 is} established is between times t ₁₈ and t ₁₂ . In the present embodiment, time t ₁₉ is the intermediate value of times t ₁₈ and t ₁₂ .

It should be noted that the number of the phase interpolation modules in the foregoing embodiment should not be limited, and the number of the phase interpolation units in the phase interpolation module should not be limited. For example, the phase interpolation module 1300 can be removed from the delay line circuit 3000. For example, the phase interpolation unit 1230 can be removed from the phase interpolation module 1200. That is, the designer can use at least one phase interpolation unit to form at least one phase interpolation module, so that the designed delay line circuit can meet the requirements of different applications.

FIG. 6 shows a schematic diagram of a circuit layout 4000 of the delay line circuit 3000 in accordance with an embodiment of the present invention. Referring to Figures 4 and 6, the circuit layout 400 includes three phase interpolation modules 1100 through 1300. The phase interpolation module 1100 There are three identical phase interpolation units 1110 to 1130, the phase interpolation module 1200 includes five identical phase interpolation units 1210 to 1250, and the phase interpolation module 1300 includes nine identical phase interpolation units. 1310 to 1390. As shown in Figure 6, each solid rectangular block represents a resistor, such as resistors 1118, 1119 or others. The length of each rectangular block may be identical to each other, and the width of each rectangular block may also be identical to each other. That is, the sizes of the resistors are the same as each other. In addition, the resistance of the resistors can be determined by the position between the two metal contacts. For example, the longer the length between the two metal contacts, the greater the resistance of the resistor. Figure 6 shows two columns of resistors with 18 resistors per column. The uppermost and lowermost resistances in the first column (eg, the 1st and 18th resistors in the left column) are not used and may be removed in other embodiments. However, since the circuit layout may be laid out in a symmetrical manner, the first column will have two unused resistors in this embodiment.

The second and third resistors in the first column represent the resistors 1118 and 1119 in the phase interpolating unit 1110. The inverters 1112 and 1114 are connected to the right terminals of the resistors 1118 and 1119, and the inverter 1116 is connected to the left terminals of the resistors 1118 and 1119. The fourth and fifth resistors in the first column represent the resistance in the phase interpolating unit 1210. The two inverters in the phase interpolating unit 1210 are connected to the left terminals of the fourth and fifth resistors in the first column, and the other inverters in the phase interpolating unit 1210 are connected to the first column. The right terminal of the 4th and 5th resistors.

The sixth and seventh resistors in the first column represent the resistance in the phase interpolating unit 1220. The two inverters in the phase interpolating unit 1220 are connected to the left terminals of the sixth and seventh resistors in the first column, and the phase interpolating single The other inverters in element 1210 are connected to the right terminals of the sixth and seventh resistors in the first column. The eighth and ninth resistors in the first column represent the resistors 1128 and 1129 in the phase interpolating unit 1120. The two inverters 1122 and 1124 in the phase interpolating unit 1120 are connected to the right terminals of the eighth and ninth resistors in the first column, and the other inverters 1126 in the phase interpolating unit 1210 are connected to The left terminal of the 8th and 9th resistors in the first column.

The 10th and 11th resistors in the first column represent the resistance in the phase interpolating unit 1230. The two inverters in the phase interpolating unit 1230 are connected to the left terminals of the tenth and eleventh resistors in the first column, and the other inverters in the phase interpolating unit 1230 are connected to the first column. The right terminal of the 10th and 11th resistors. The 12th and 13th resistors in the first column represent the resistance in the phase interpolating unit 1240. The two inverters in the phase interpolating unit 1240 are connected to the left terminals of the 12th and 13th resistors in the first column, and the other inverters in the phase interpolating unit 1240 are connected to the first column. The right terminal of the 12th and 13th resistors.

The 14th and 15th resistors in the first column represent the resistors 1138 and 1139 in the phase interpolating unit 1130. The two inverters 1132 and 1134 in the phase interpolating unit 1130 are connected to the right terminals of the 14th and 15th resistors in the first column, and the other inverters 1136 in the phase interpolating unit 1130 are connected to The left terminal of the 14th and 15th resistors in the first column. The 16th and 17th resistors in the first column represent the resistance in the phase interpolating unit 1250. The two inverters in the phase interpolating unit 1250 are connected to the left terminals of the 16th and 17th resistors in the first column, and the other inverters in the phase interpolating unit 1250 are connected to the first column. Right terminal of the 16th and 17th resistors .

The resistance in the second column represents the resistance in the phase interpolation units 1310 to 1390 in the phase interpolation module 1300. The circuit layouts of the phase interpolation units 1310 to 1390 are identical to each other. Each two consecutive resistances in the second column represent the resistance in the phase interpolating unit. Taking the phase interpolating unit 1310 as an example, the first and second resistances in the second column indicate the resistance in the phase interpolating unit 1310. The two inverters in the phase interpolating unit 1310 are connected to the left terminals of the first and second resistors in the second column, and the other inverters in the phase interpolating unit 1310 are connected to the second column. The right terminal of the first and second resistors. The circuit layout of the phase interpolation units 1320 to 1390 can be obtained in a similar manner.

According to the above configuration, the circuit layout 4000 is solidly formed on the left side of the two-phase interpolation modules 1100 and 1200, and the phase interpolation module 1300 is firmly formed on the right side. The compactness of the circuit layout 4000 is beneficial for reducing the interconnect routing of the circuit and reducing the critical timing of the signal. In addition, the phase interpolation units 1210 to 1220 in the phase interpolation module 1200 are disposed between the phase interpolation units 1110 and 1120 in the phase interpolation module 1100, and the phase in the phase interpolation module 1200 The interpolation units 1230 to 1240 are disposed between the phase interpolation units 1120 and 1130 in the phase interpolation module 1100. The regularity of these unit settings also helps to reduce the critical timing of the signal. In the present embodiment, the circuit layout is applied to the delay line circuit. However, the circuit layout can also be applied to any circuit having a delay line circuit, such as an operational amplifier or other high speed circuit.

Accordingly, embodiments of the present invention provide a phase interpolation module to reduce collision current. In addition, the phase interpolation module includes inverters of the same size, so the phase interpolation module is not sensitive to process variations. The phase interpolation module can form a delay line circuit of the phase interpolation module having the above advantages. In addition, the circuit layout of the delay line circuit is also provided in an embodiment of the invention to reduce the critical timing problem of the signal.

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims

400‧‧‧delay line circuit

401~403‧‧‧ phase interpolation unit

4011~4033‧‧‧Inverter

1100, 1200, 1300‧‧‧ phase interpolation module

1110~1130‧‧‧ phase interpolation unit

1210~1250‧‧‧ phase interpolation unit

1310~1390‧‧‧ Phase Interpolation Unit

1112~1116, 1122~1126, 1132~1136‧‧‧Inverter

1118~1119, 1128~1129, 1138~1139‧‧‧resistance

3000‧‧‧delay line circuit

4000‧‧‧Circuit layout

1 is a block diagram showing a conventional delay line circuit; FIG. 2 is a block diagram showing a phase interpolation module according to an embodiment of the present invention; and FIG. 3 is a diagram showing input signals and interpolation according to an embodiment of the present invention. FIG. 4 is a block diagram showing a delay line circuit according to an embodiment of the present invention; FIG. 5 is a diagram showing waveforms of an input signal and an interpolation signal of the delay line circuit according to an embodiment of the present invention; 6 shows a schematic diagram of a circuit layout of the delay line circuit in accordance with an embodiment of the present invention.

1110~1130‧‧‧ phase interpolation unit

1210~1250‧‧‧ phase interpolation unit

1310~1390‧‧‧ Phase Interpolation Unit

1112~1116, 1122~1126, 1132~1136‧‧‧Inverter

1118~1119, 1128~1129, 1138~1139‧‧‧resistance

4000‧‧‧Circuit layout

Claims (10)

A delay line circuit comprising: a first phase interpolation module comprising first, second and third phase interpolation units, each of the first, second and third phase interpolation units comprising a first inverter; a second inverter; a third inverter; a first resistor coupled to an output of the first inverter and an input of the third inverter And a second resistor coupled between an output of the second inverter and the input of the third inverter; and a second phase interpolation module, including a fourth And a fifth, sixth, seventh and eighth phase interpolation unit, each of the fourth to eighth phase interpolation units comprising: a first inverter; a second inverter; a third resistor; a first resistor coupled between an output of the first inverter and an input of the third inverter; and a second resistor coupled to the second Between an output of the inverter and the input of the third inverter; wherein the first and second inverters in the first phase interpolating unit receive a first signal The third phase interpolation unit and the plurality of first The second inverter receives a second signal, and the first and second inverters in the second phase interpolating unit individually receive the first signal and the second signal, where the first phase interpolating unit is The third inverter outputs a third signal, the third inverter in the third phase interpolating unit outputs a fifth signal, and the third inverter in the second phase interpolating unit And outputting a fourth signal, wherein the first and second inverters in the fourth phase interpolating unit receive the third signal, and the first and second in the fifth phase interpolating unit The phaser individually receives the third signal and the fourth signal, and the first and second inverters in the sixth phase interpolating unit receive the fourth signal, and the seventh phase interpolating unit The first and second inverters individually receive the fourth signal and the fifth signal, and the first and second inverters in the eighth phase interpolating unit receive the fifth signal; and wherein The first and second resistances in the first to the eighth phase interpolating units are arranged in a column, and the first phase Interpolation module of the plurality of the first to the third phase of the interpolation unit and interpolation module circuit layout within the second phase of the fourth to the interpolation circuit layout based interleaving unit disposed within the eighth phase. The delay line circuit of claim 1, wherein the first and second inverters of the first to the eighth phase interpolating units have the same size. A delay line circuit according to claim 1, wherein a time difference between the first and second signals is equal to a time difference between the third and fifth signals. The delay line circuit of claim 1, wherein the settling time of the fourth signal is between the settling times of the third and fifth signals. According to the delay line circuit of claim 4, wherein the time at which the fourth signal is established is an intermediate value of the settling times of the third and fifth signals. The delay line circuit of claim 1, wherein the first and second resistors in the first to the eighth phase interpolating units have the same resistance. The delay line circuit of claim 1, wherein the third inverter in the fourth phase interpolating unit outputs a sixth signal, and the third inverter in the fifth phase interpolating unit outputs a first a seventh signal, the third inverter in the sixth phase interpolating unit outputs an eighth signal, the third inverter in the seventh phase interpolating unit outputs a ninth signal, and the eighth phase The third inverter in the interpolation unit outputs a tenth signal; and wherein a time difference between the first and second signals is equal to a time difference between the sixth and tenth signals. According to the delay line circuit of claim 7, wherein the settling time of the eighth signal is between the settling times of the sixth and tenth signals, and the settling time of the seventh signal is established in the sixth and eighth signals Between times, and the settling time of the ninth signal is between the settling times of the eighth and tenth signals. According to the delay line circuit of claim 8, wherein the time at which the eighth signal is established is an intermediate value of the settling times of the sixth and tenth signals, and the time at which the seventh signal is established is the sixth and eighth signals. An intermediate value of the settling time, and the time at which the ninth signal is established is an intermediate value of the settling times of the eighth and tenth signals. The delay line circuit of claim 1, wherein the first and second resistors in the first phase interpolating unit, the first and second resistors in the fourth phase interpolating unit, and the fifth phase The first and second of the interpolation unit a resistor, the first and second resistors in the sixth phase interpolating unit, the first and second resistors in the seventh phase interpolating unit, and the third of the third phase interpolating units The first and second resistors, the first and second resistors in the first phase interpolating unit, and the first and second resistors in the eighth phase interpolating unit are sequentially arranged in the column.