CN103516334B - Delay line and phase interpolation module thereof - Google Patents
Delay line and phase interpolation module thereof Download PDFInfo
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- CN103516334B CN103516334B CN201210201757.8A CN201210201757A CN103516334B CN 103516334 B CN103516334 B CN 103516334B CN 201210201757 A CN201210201757 A CN 201210201757A CN 103516334 B CN103516334 B CN 103516334B
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Abstract
The present invention discloses a kind of delay line and phase interpolation module thereof.In an embodiment of the present invention, this phase interpolation module comprises first, second, and third phase interpolation unit.Each in these first, second, and third phase interpolation unit comprises one first inverter, one second inverter, one the 3rd inverter, one first resistance and one second resistance.This first electric group is coupled between an output of this first inverter and an input of the 3rd inverter.This second resistance is coupled between an output of this second inverter and this input of the 3rd inverter.These first and second inverters in this first phase interpolation unit receive one first signal, these first and second inverters in this third phase interpolation unit receive a secondary signal, and these first and second inverters in this second phase interpolation unit receive individually this first signal and this secondary signal.
Description
Technical field
The present invention relates to a kind of delay line, relate to a kind of delay line of being implemented by phase interpolation and phase interpolation module thereof.
Background technology
Delay line is used to the clock delay adjusting the signal such as input/output signal, clock signal in the semiconductor element.The delay line with phase interpolation circuit is one of them in delay line, and has been widely used in the sequential adjusting internal clock signal.
Analogue phase interpolating circuit uses analog element (such as adder, multiplier, blender, amplifier etc.) to adjust the phase difference of two reference clocks.Because time delay is present in these analog elements, be necessary to use delay compensation component to adjust the phase place between reference clock and interior interpolated clock.In addition, there is different time jitters and change in delay compensation component.The time delay of these elements is very sensitive for the variation of the data rate inputted, technological parameter and temperature.
Digital element (such as inverter) in digit phase interpolating circuit is in order to adjust the phase difference of two reference clocks.Digit phase interpolating circuit can be implemented with simple circuit, and the phase place that signal one can be provided exactly clear and definite.Therefore, digit phase interpolating circuit is widely used in various semiconductor element and circuit, such as, in digital delay locked loop (DLL) circuit.Design good digit phase interpolating circuit or mixed signal phase interpolation circuit for high speed circuit or be used for clocking circuit for be necessary.
Fig. 1 shows the block schematic diagram of a known delay line.With reference to Fig. 1, this delay line 400 comprises multiple phase interpolation unit 401 to 403.This phase interpolation unit 401 comprises three inverters 4011 to 4013.The input of inverter 4011 and 4012 receives one first input signal SI1, and output is coupled to an input of inverter 4013.One output of inverter 4013 exports one first output signal SO1, and it is the inhibit signal of input signal SI1.Phase interpolation unit 403 comprises three inverters 4031 to 4033.The input of inverter 4031 and 4032 receives one second input signal SI2, and output is coupled to an input of inverter 4033.One output of inverter 4033 exports one second output signal SO2, and it is the inhibit signal of input signal SI2.
Phase interpolation unit 402 comprises three inverters 4021 to 4023.The input of inverter 4021 and 4022 receives individually this first input signal SI1 and this second input signal SI2, and output is coupled to an input of inverter 4023.One output of inverter 4023 exports one the 3rd output signal SO3, and its settling time can between the settling time of output signal SO1 and SO2.Inverter 4011 is not identical each other with the size of 4012, inverter 4021 is not identical each other with the size of 4022, and inverter 4031 is not identical each other with the size of 4032, can be the median outputing signal SO1 and SO2 settling time to make the settling time of output signal SO3.In addition, when the phase place of input signal SI1 and SI2 is differing from each other, the electric current of conflict can between inverter 4021 and 4022, be produced.
Summary of the invention
The present invention discloses a kind of phase interpolation module.In an embodiment of the present invention, this phase interpolation module comprises first, second, and third phase interpolation unit.Each in these first, second, and third phase interpolation unit comprises one first inverter, one second inverter, one the 3rd inverter, one first resistance and one second resistance.This first electric group is coupled between an output of this first inverter and an input of the 3rd inverter.This second resistance is coupled between an output of this second inverter and this input of the 3rd inverter.These first and second inverters in this first phase interpolation unit receive one first signal, these first and second inverters in this third phase interpolation unit receive a secondary signal, and these first and second inverters in this second phase interpolation unit receive individually this first signal and this secondary signal.
The present invention separately discloses a kind of delay line.In an embodiment of the present invention, this delay line comprises a first phase interpose module, and it comprises first, second, and third phase interpolation unit.Each in these first, second, and third phase interpolation unit comprises one first inverter, one second inverter, one the 3rd inverter, one first resistance and one second resistance.This first electric group is coupled between an output of this first inverter and an input of the 3rd inverter.This second resistance is coupled between an output of this second inverter and this input of the 3rd inverter.These first and second inverters in this first phase interpolation unit receive one first signal, these first and second inverters in this third phase interpolation unit receive a secondary signal, these first and second inverters in this second phase interpolation unit receive individually this first signal and this secondary signal, the 3rd inverter in this first phase interpolation unit exports one the 3rd signal, the 3rd inverter in this third phase interpolation unit exports one the 5th signal, and the 3rd inverter in this second phase interpolation unit exports one the 4th signal.
Sketch out technical characteristic of the present invention above, thus make detailed description hereafter be obtained better understanding.Form other technical characteristic of claims target of the present invention will be described in hereafter.Those skilled in the art of the invention should understand, and the concept hereafter disclosed and specific embodiment can be used as basis and revised or design other structure or technique quite easily and realize the object identical with the present invention.Those skilled in the art of the invention also should understand, and the construction of this kind of equivalence also cannot depart from the spirit and scope of the present invention that the claimed scope of appending claims proposes.
Accompanying drawing explanation
Fig. 1 shows the block schematic diagram of a known delay line;
Fig. 2 display is according to the block schematic diagram of the phase interpolation module of one embodiment of the invention;
Fig. 3 display is according to the input signal of one embodiment of the invention and the oscillogram of interpolated signal;
Fig. 4 display is according to the block schematic diagram of the delay line of one embodiment of the invention;
Fig. 5 display is according to the input signal of this delay line of one embodiment of the invention and the oscillogram of interpolated signal; And
Fig. 6 display is according to the schematic diagram of the circuit layout of this delay line of one embodiment of the invention.
[main element symbol description]
400 delay lines
401 ~ 403 phase interpolation unit
4011 ~ 4033 inverters
1100,1200, phase interpolation module
1300
1110 ~ 1130 phase interpolation unit
1210 ~ 1250 phase interpolation unit
1310 ~ 1390 phase interpolation unit
1112 ~ 1116, inverter
1122~1126，
1132~1136
1118 ~ 1119, resistance
1128~1129，
1138~1139
3000 delay lines
4000 circuit layouts
Embodiment
Below illustrate that the present invention is in order to implement the phase interpolation unit of delay line.This delay line comprises at least one phase interpolation unit, and these phase interpolation unit form at least one phase interpolation module.Fig. 2 display is according to the block schematic diagram of the phase interpolation module 1100 of one embodiment of the invention.
With reference to Fig. 2, this phase interpolation module 1100 comprises three identical phase interpolation unit 1110 to 1130.This phase interpolation unit 1110 comprises three inverters, 1112,1114,1116 and two resistance 1118,1119.The output of inverter 1112 and 1114 is connected to individually one end of resistance 1118 and 1119, and the input of inverter 1116 is coupled to the other end of resistance 1118 and 1119.This phase interpolation unit 1120 comprises three inverters, 1122,1124,1126 and two resistance 1128,1129.The output of inverter 1122 and 1124 is connected to individually one end of resistance 1128 and 1129, and the input of inverter 1126 is coupled to the other end of resistance 1128 and 1129.This phase interpolation unit 1130 comprises three inverters, 1132,1134,1136 and two resistance 1138,1139.The output of inverter 1132 and 1134 is connected to individually one end of resistance 1138 and 1139, and the input of inverter 1136 is coupled to the other end of resistance 1138 and 1139.
These inverters 1112 and 1114 receive input signal S
11, and export anti-phase input signal.These anti-phase signals through resistance 1118 and 1119 to form a composite signal I at the input of inverter 1116
11.This inverter 1116 receives from this overlapped composite signal I of these anti-phase signals
11after, produce interpolated signal S
21, it is signal S
11an inhibit signal.These inverters 1132 and 1134 receive input signal S
12, and export anti-phase input signal.These anti-phase signals through resistance 1138 and 1139 to form a composite signal I at the input of inverter 1136
22.This inverter 1136 receives from this overlapped composite signal I of these anti-phase signals
22after, produce interpolated signal S
23, it is signal S
12an inhibit signal.
These inverters 1122 and 1124 Jie Shou input signal S
11and S
12, and export anti-phase input signal.These anti-phase signals through resistance 1128 and 1129 to form a composite signal I at the input of inverter 1126
12.This inverter 1126 receives from this overlapped composite signal I of these anti-phase signals
12, to make interpolated signal S
22settling time can at interpolated signal S
21and S
23between settling time.These inverters 1112 to 1116,1122 to 1126 and 1132 to 1136 may be mutually the same.Therefore, input signal S
11and S
12time difference be same as interpolated signal S
21and S
23time difference, and interpolated signal S
22the time of setting up can be interpolated signal S
21and S
23the median of settling time.
Fig. 3 display is according to the input signal S of one embodiment of the invention
11to S
12and interpolated signal S
21to S
23oscillogram.Input signal S
11and S
12indivedual at time t
1and t
2set up.As previously mentioned, interpolated signal S
21and S
23input signal S
11and S
12inhibit signal.Input signal S
11and S
12between time difference (t
2-t
1) and interpolated signal S
21and S
23between time difference (t
4-t
3) identical.Interpolated signal S
22the time t set up
5at time t
3and t
4between.In the present embodiment, time t
5for time t
3and t
4median.
Configure according to this, the conflict electric current between inverter 1122 and 1124 can by the resistance of resistance 1128 and 1129 with limit.The size of inverter 1122 and 1124 can be adjusted to identical by the ratio of the resistance between adjusting resistance 1128 and 1129.When inverter 1122 with 1124 size identical time, the susceptibility for process variation just can reduce.In addition, because the ratio of the resistance between resistance 1128 and 1129 is insensitive for the variation of technique, interpolated signal S22 is not easy the impact being subject to process variation.According to similar fashion, the size of inverter 1112 and 1114 can be adjusted to identical by the ratio of the resistance between adjusting resistance 1118 and 1119, and the size of inverter 1132 and 1134 can be adjusted to identical by the ratio of the resistance between adjusting resistance 1138 and 1139.Therefore, interpolated signal S
21and S
23the impact being subject to process variation will be not easy.
With reference to Fig. 2, composite signal I
11, I
12and I
22rise time due to identical bias condition may be identical.In addition, due to identical bias condition, interpolated signal S
21to S
23fall time also may be identical.Therefore, interpolated signal S
21to S
23identical responsibility cycle (dutycycle) may be had.Composite signal I
11, I
12and I
22rise time equal can by the ratio between adjusting resistance 1128 and 1129 or adjustment inverter 1122 and 1124 size and complete easily, make the size of inverter 1122 and 1124 mutually the same, or make the resistance of the resistance of resistance 1128 and resistance 1129 mutually the same.Therefore, interpolated signal S
21to S
23responsibility cycle can automatically follow the trail of input signal S
11and S
12responsibility cycle.
After describing the phase interpolation module that is made up of at least one phase interpolation unit, be below described through phase interpolation and the delay line implemented.Fig. 4 display is according to the block schematic diagram of the delay line 3000 of one embodiment of the invention.This delay line 3000 comprises the three grades of phase interpolation modules 1100,1200 and 1300 arranged in a serial fashion.This delay line 3000 is designed to output nine interpolated signal S
41to S
49.But the present invention should as limit.Phase interpolation module 1110 in Fig. 4 is identical with the phase interpolation module in Fig. 2.Phase interpolation module 1200 has five phase interpolation unit 1210 to 1250, phase interpolation module 1300 has nine phase interpolation unit 1310 to 1390, and phase interpolation unit 1210 to 1250 is identical with the thin portion circuit of one of them in phase interpolation unit 1110 to 1130 with the thin portion circuit in phase interpolation unit 1310 to 1390.
Fig. 5 display is according to the input signal S of this delay line 3000 of one embodiment of the invention
11to S
12and interpolated signal S
21to S
23, S
31to S
35and S
41to S
49oscillogram.With reference to Fig. 4 and Fig. 5, as previously mentioned, this phase interpolation module 1100 receives input signal S
11to S
12rear output interpolated signal S
21to S
23.These input signals S
11to S
12, interpolated signal S
21to S
23hereby repeat no more with operating on of this phase interpolation module 1110.Running and these interpolated signals S of these phase interpolation modules 1200 and 1300 are below described
31to S
35and S
41to S
49generation.
These phase interpolation unit 1210,1230 and 1250 Jie Shou interpolated signal S
21, S
22and S
23rear indivedual output interpolated signal S
31, S
33and S
35, wherein interpolated signal S
31, S
33and S
35interpolated signal S
21, S
22and S
23inhibit signal.Interpolated signal S
21and S
22between time difference (t
5-t
3) and interpolated signal S
31and S
33between time difference (t
9-t
6) identical.Interpolated signal S
22and S
23between time difference (t
4-t
5) and interpolated signal S
33and S
35between time difference (t
7-t
9) identical.Interpolated signal S
32the time t set up
8at time t
6and t
9between.In the present embodiment, time t
8for time t
6and t
9median.Interpolated signal S
34the time t set up
10at time t
9and t
7between.In the present embodiment, time t
10for time t
9and t
7median.
These phase interpolation unit 1310,1330,1350,1370 and 1390 Jie Shou interpolated signal S
31, S
32, S
33, S
34and S
35rear indivedual output interpolated signal S
41, S
43, S
45, S
47and S
49, wherein interpolated signal S
41, S
43, S
45, S
47and S
49interpolated signal S
31, S
32, S
33, S
34and S
35inhibit signal.Interpolated signal S
31and S
32between time difference (t
8-t
6) and interpolated signal S
43and S
41between time difference (t
14-t
11) identical.Interpolated signal S
32and S
33between time difference (t
9-t
8) and interpolated signal S
43and S
45between time difference (t
16-t
14) identical.Interpolated signal S
33and S
34between time difference (t
10-t
9) and interpolated signal S
45and S
47between time difference (t
18-t
16) identical.Interpolated signal S
34and S
35between time difference (t
7-t
10) and interpolated signal S
49and S
44between time difference (t
12-t
18) identical.Interpolated signal S
42the time t set up
13at time t
11and t
14between.In the present embodiment, time t
13for time t
11and t
14median.Interpolated signal S
44the time t set up
15at time t
14and t
16between.In the present embodiment, time t
15for time t
14and t
16median.Interpolated signal S
46the time t set up
17at time t
16and t
18between.In the present embodiment, time t
17for time t
16and t
18median.Interpolated signal S
48the time t set up
19at time t
18and t
12between.In the present embodiment, time t
19for time t
18and t
12median.
It is noted that the number of these phase interpolation modules should not be defined in the above-described embodiments, and the number of these phase interpolation unit in this phase interpolation module should not be defined.For example, this phase interpolation module 1300 can remove from this delay line 3000.For example, this phase interpolation unit 1230 can remove from this phase interpolation module 1200.That is designer can use at least one phase interpolation unit to form at least one phase interpolation module, make the delay line designed can meet the demand of different application.
Fig. 6 display is according to the schematic diagram of the circuit layout 4000 of this delay line 3000 of one embodiment of the invention.With reference to Fig. 4 and Fig. 6, this circuit layout 400 comprises three phase interpolation modules 1100 to 1300.This phase interpolation module 1100 comprises three identical phase interpolation unit 1110 to 1130, this phase interpolation module 1200 comprises five identical phase interpolation unit 1210 to 1250, and this phase interpolation module 1300 comprises nine identical phase interpolation unit 1310 to 1390.As shown in Figure 6, each solid rectangle block represents a resistance, such as resistance 1118,1119 or other.The length of each rectangle block may be mutually the same, and the width of each rectangle block also may be mutually the same.That is the size of the layout of these resistance is mutually the same.In addition, the resistance of these resistance can be determined by the position between two Metal Contact.For example, the resistance of longer then this resistance of the length between two Metal Contact is larger.Fig. 6 illustrates two row resistance, and often shows 18 resistance.In first row, the resistance (such as, the 1st and the 18th resistance in left column) of the top and bottom can not be used in other embodiments and may be removed.But because this circuit layout may carry out layout in a symmetrical manner, this first row has two untapped resistance in this embodiment.
In this first row, the 2nd and the 3rd resistance represent the resistance 1118 and 1119 in this phase interpolation unit 1110.These inverters 1112 and 1114 are connected to the right terminal of these resistance 1118 and 1119, and this inverter 1116 is connected to the left terminal of these resistance 1118 and 1119.In this first row, the 4th and the 5th resistance represent the resistance in this phase interpolation unit 1210.Two inverters in this phase interpolation unit 1210 are connected to the left terminal of the 4th and the 5th resistance in this first row, and other inverters in this phase interpolation unit 1210 are connected to the right terminal of the 4th and the 5th resistance in this first row.
In this first row, the 6th and the 7th resistance represent the resistance in this phase interpolation unit 1220.Two inverters in this phase interpolation unit 1220 are connected to the left terminal of the 6th and the 7th resistance in this first row, and other inverters in this phase interpolation unit 1210 are connected to the right terminal of the 6th and the 7th resistance in this first row.In this first row, the 8th and the 9th resistance represent the resistance 1128 and 1129 in this phase interpolation unit 1120.Two inverters 1122 and 1124 in this phase interpolation unit 1120 are connected to the right terminal of the 8th and the 9th resistance in this first row, and other inverters 1126 in this phase interpolation unit 1210 are connected to the left terminal of the 8th and the 9th resistance in this first row.
In this first row, the 10th and the 11st resistance represent the resistance in this phase interpolation unit 1230.Two inverters in this phase interpolation unit 1230 are connected to the left terminal of the 10th and the 11st resistance in this first row, and other inverters in this phase interpolation unit 1230 are connected to the right terminal of the 10th and the 11st resistance in this first row.In this first row, the 12nd and the 13rd resistance represent the resistance in this phase interpolation unit 1240.Two inverters in this phase interpolation unit 1240 are connected to the left terminal of the 12nd and the 13rd resistance in this first row, and other inverters in this phase interpolation unit 1240 are connected to the right terminal of the 12nd and the 13rd resistance in this first row.
In this first row, the 14th and the 15th resistance represent the resistance 1138 and 1139 in this phase interpolation unit 1130.Two inverters 1132 and 1134 in this phase interpolation unit 1130 are connected to the right terminal of the 14th and the 15th resistance in this first row, and other inverters 1136 in this phase interpolation unit 1130 are connected to the left terminal of the 14th and the 15th resistance in this first row.In this first row, the 16th and the 17th resistance represent the resistance in this phase interpolation unit 1250.Two inverters in this phase interpolation unit 1250 are connected to the left terminal of the 16th and the 17th resistance in this first row, and other inverters in this phase interpolation unit 1250 are connected to the right terminal of the 16th and the 17th resistance in this first row.
Resistance in this secondary series represents the resistance in the phase interpolation unit 1310 to 1390 in this phase interpolation module 1300.The circuit layout of these phase interpolation unit 1310 to 1390 is mutually the same.In this secondary series, every two continuous print resistance represent the resistance in this phase interpolation unit.Illustrate for this phase interpolation unit 1310, in this secondary series, the 1st and the 2nd resistance represent the resistance in this phase interpolation unit 1310.Two inverters in this phase interpolation unit 1310 are connected to the left terminal of the 1st and the 2nd resistance in this secondary series, and other inverters in this phase interpolation unit 1310 are connected to the right terminal of the 1st and the 2nd resistance in this secondary series.The circuit layout of these phase interpolation unit 1320 to 1390 can obtain according to similar fashion.
According to above-mentioned configuration mode, this circuit layout 4000 firmly forms two phase place interpose module 1100 and 1200 in left side, and firmly forms this phase interpolation module 1300 on right side.The density of this circuit layout 4000 is of value to the interconnection topology (interconnectrouting) critical sequential (criticaltiming) problem reducing signal that reduce this circuit.In addition, phase interpolation unit 1210 to 1220 in this phase interpolation module 1200 is arranged between the phase interpolation unit 1110 and 1120 in this phase interpolation module 1100, and the phase interpolation unit 1230 to 1240 in this phase interpolation module 1200 is arranged between the phase interpolation unit 1120 and 1130 in this phase interpolation module 1100.The regularity that these unit are arranged also contributes to the marginal timing problems reducing signal.In the present embodiment, this circuit layout is applied to this delay line.Such as, but this circuit layout also can be applicable to anyly have in the circuit of delay line, operational amplifier or other high speed circuits.
Accordingly, embodiments of the invention provide a kind of phase interpolation module to reduce conflict electric current.In addition, this phase interpolation module comprises the inverter with formed objects, and therefore this phase interpolation module is insensitive to process variation.This phase interpolation module can form the delay line of the phase interpolation module with above-mentioned advantage.In addition, also provide the circuit layout of this delay line to reduce the marginal timing problems of signal in an embodiment of the present invention.
Technology contents of the present invention and technical characterstic disclose as above, but those skilled in the art still may do all replacement and the modification that do not deviate from spirit of the present invention based on teaching of the present invention and announcement.Therefore, protection scope of the present invention should be not limited to those disclosed embodiments, and should comprise various do not deviate from replacement of the present invention and modification, and is contained by the scope that appending claims is claimed.
Claims (12)
1. a phase interpolation module, comprises:
First, second, and third phase interpolation unit, each in these first, second, and third phase interpolation unit comprises:
One first inverter;
One second inverter;
One the 3rd inverter;
One first resistance, is coupled between an output of this first inverter and an input of the 3rd inverter; And
One second resistance, is coupled between an output of this second inverter and this input of the 3rd inverter;
Wherein, these first and second inverters in this first phase interpolation unit receive one first signal, these first and second inverters in this third phase interpolation unit receive a secondary signal, and these first and second inverters in this second phase interpolation unit receive individually this first signal and this secondary signal
Wherein these first and second inverters have identical size.
2. phase interpolation module as claimed in claim 1, wherein these first and second resistance have identical resistance.
3. a delay line, comprises:
One first phase interpose module, comprises first, second, and third phase interpolation unit, and each in these first, second, and third phase interpolation unit comprises:
One first inverter;
One second inverter;
One the 3rd inverter;
One first resistance, is coupled between an output of this first inverter and an input of the 3rd inverter; And
One second resistance, is coupled between an output of this second inverter and this input of the 3rd inverter;
Wherein, these first and second inverters in this first phase interpolation unit receive one first signal, these first and second inverters in this third phase interpolation unit receive a secondary signal, these first and second inverters in this second phase interpolation unit receive individually this first signal and this secondary signal, the 3rd inverter in this first phase interpolation unit exports one the 3rd signal, the 3rd inverter in this third phase interpolation unit exports one the 5th signal, and the 3rd inverter in this second phase interpolation unit exports one the 4th signal
Wherein these first and second resistance have identical resistance.
4. delay line as claimed in claim 3, wherein these first and second inverters have identical size.
5. delay line as claimed in claim 3, the time difference wherein between these first and second signals equals the time difference between these the 3rd and the 5th signals.
6. delay line as claimed in claim 3, wherein the settling time of the 4th signal is between the settling time of these the 3rd and the 5th signals.
7. delay line as claimed in claim 6, the time of wherein the 4th signal foundation is the median of the settling time of these the 3rd and the 5th signals.
8. delay line as claimed in claim 3, also comprises:
One second phase interpose module, comprises the 4th, the 5th, the 6th, the 7th and eight-phase interpolation unit, and these the 4th comprise to each in eight-phase interpolation unit:
One first inverter;
One second inverter;
One the 3rd inverter;
One first resistance, is coupled between an output of this first inverter and an input of the 3rd inverter; And
One second resistance, is coupled between an output of this second inverter and this input of the 3rd inverter;
Wherein, these first and second inverters in 4th phase interpolation unit receive the 3rd signal, and the 3rd inverter in the 4th phase interpolation unit exports one the 6th signal, these first and second inverters in 5th phase interpolation unit receive individually the 3rd signal and the 4th signal, and the 3rd inverter in the 5th phase interpolation unit exports one the 7th signal, these first and second inverters in 6th phase interpolation unit receive the 4th signal, and the 3rd inverter in the 6th phase interpolation unit exports one the 8th signal, these first and second inverters in 7th phase interpolation unit receive individually the 4th signal and the 5th signal, and the 3rd inverter in the 7th phase interpolation unit exports one the 9th signal, these first and second inverters in this eight-phase interpolation unit receive the 5th signal, and the 3rd inverter in this eight-phase interpolation unit exports 1 the tenth signal, and
Time difference wherein between these first and second signals equals the time difference between these the 6th and the tenth signals.
9. delay line as claimed in claim 8, wherein the settling time of the 8th signal is between the settling time of these the 6th and the tenth signals, the settling time of the 7th signal is between the settling time of these the 6th and the 8th signals, and the settling time of the 9th signal is between the settling time of these the 8th and the tenth signals.
10. delay line as claimed in claim 9, wherein the time of the 8th signal foundation is the median of the settling time of these the 6th and the tenth signals, the time of the 7th signal foundation is the median of the settling time of these the 6th and the 8th signals, and the time that the 9th signal is set up is the median of the settling time of these the 8th and the tenth signals.
11. delay lines as claimed in claim 8, wherein this first is listed in row to these first and second resistor chains in this eight-phase interpolation unit, and the 4th in first to the circuit layout and this second phase interpose module of this third phase interpolation unit of these in this first phase interpose module to the circuit layout of this eight-phase interpolation unit is staggered setting.
12. delay lines as claimed in claim 11, these first and second resistance wherein in this first phase interpolation unit, these first and second resistance in 4th phase interpolation unit, these first and second resistance in 5th phase interpolation unit, these first and second resistance in 6th phase interpolation unit, these first and second resistance in 7th phase interpolation unit, these first and second resistance in this third phase interpolation unit, these first and second resistance in this first phase interpolation unit and these the first and second resistance sequential in this eight-phase interpolation unit are in these row.
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|---|---|---|---|
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|---|---|---|---|
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7173466B2 (en) * | 2002-02-01 | 2007-02-06 | Fujitsu Limited | Timing signal generating circuit having simple configuration with low supply voltage and generating timing signals with high accuracy |
| US7425858B1 (en) * | 2005-09-16 | 2008-09-16 | Advanced Micro Devices, Inc. | Delay line periodically operable in a closed loop |
| CN101335510A (en) * | 2008-07-28 | 2008-12-31 | 钰创科技股份有限公司 | Long delay circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7173466B2 (en) * | 2002-02-01 | 2007-02-06 | Fujitsu Limited | Timing signal generating circuit having simple configuration with low supply voltage and generating timing signals with high accuracy |
| US7425858B1 (en) * | 2005-09-16 | 2008-09-16 | Advanced Micro Devices, Inc. | Delay line periodically operable in a closed loop |
| CN101335510A (en) * | 2008-07-28 | 2008-12-31 | 钰创科技股份有限公司 | Long delay circuit |
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| CN103516334A (en) | 2014-01-15 |
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