TWI474624B - Dual-loop phase lock loop - Google Patents

Description

Dual-loop controlled phase-locked loop

The invention relates to a two-loop controlled phase-locked loop, in particular to a phase-locked loop for generating a coarse control voltage and a fine-tuning control voltage according to currents of different current sources to adjust the dual-loop control of the feedback clock.

Please refer to FIG. 1 , which is a schematic diagram of the prior art description applied to the dual loop phase locked loop 100 . The dual-loop phase-locked loop 100 utilizes a coarse loop with large oscillator gain to adjust the drift of the oscillator frequency due to fabrication, voltage and temperature variations, and to adjust the double using a fine-tuned loop with small oscillator gain. Parameters of loop-locked loop performance, such as phase noise, random jitter, and loop band-width. Therefore, the dual loop phase locked loop 100 has lower phase noise and random jitter than the single loop phase locked loop.

However, as shown in FIG. 1, in the dual-loop phase-locked loop 100, in order to provide a stable zero (zero), the capacitor C ₂ must be a large capacitor. In addition, the coarse/fine tuning loops of the dual-loop phase-locked loop 100 are respectively adjusted with different control voltages, and the dual-loop phase-locked loop 100 has a very complicated filter. Therefore, the above disadvantages are not easily overcome by the designer.

An embodiment of the invention provides a two-loop controlled phase-locked loop. The phase locked loop includes a phase frequency detecting circuit, a first charge pump, a second charge pump, a first capacitor, a filter, a first adder, a voltage control delay circuit, and a frequency division Device. The phase frequency detecting circuit is configured to generate a switching signal according to a difference between a reference clock and a frequency-dividing feedback clock, the phase frequency detecting circuit having a first input terminal for receiving the reference clock a second input terminal for receiving the frequency division feedback clock, and an output terminal for outputting the switch signal; the first charge pump is configured to generate a coarse control voltage according to the switch signal, The first charge pump has a first end coupled to the output end of the phase frequency detecting circuit for receiving the switching signal, a second end for receiving the first voltage, and a third end, The second charge pump is configured to generate a pre-trimming voltage according to the switching signal, the second charge pump has a first end, and the output end of the phase frequency detecting circuit For receiving the switch signal, a second end for receiving the first voltage, and a third end for outputting the pre-trim voltage; the first capacitor has a first end coupled to the first a third end of a charge pump, and a second end The filter is coupled to the high-frequency portion of the pre-trimming voltage, and has a first end coupled to the third end of the second charge pump and a second end. The first adder is configured to generate a trimming control voltage according to the pre-trimming voltage and the coarse control voltage, the first adder having a first end coupled to the first charge The third end of the pump is configured to receive the coarse control voltage, and a second end is coupled to the third end of the second charge pump for receiving the pre-trim voltage and a third end The voltage control delay line has a first input end coupled to the third end of the first charge pump for receiving the coarse control voltage, a second input end coupled to the third end of the first adder for receiving the trimming control voltage, and an output end for outputting a feedback clock; and the frequency divider is coupled to the voltage control a delay circuit and the phase frequency detecting circuit for dividing the feedback clock to In addition to the frequency of the feedback clock.

The invention provides a double loop controlled phase locked loop. The phase-locked loop utilizes a first current source and a second current source to amplify an equivalent capacitance value of a first capacitor, wherein the first capacitor provides a stable zero point and a coarse control voltage of the phase-locked loop . In addition, the phase-locked loop generates a trimming control voltage by a second capacitor, a resistor, and the coarse control voltage connected in parallel. Thus, the present invention has the following advantages: First, the present invention does not require a digital correction circuit, an LC tank; second, the area of the first capacitor of the present invention is more phase-locked than the conventional analog dual loop control. The area of the capacitor in the loop is small; thirdly, the present invention has a filter of a simple design, and since the coarse voltage control unit and the trimming voltage control unit of the present invention have the same control voltage, the debugging or the test can be reduced. Complexity; Fourth, because the feedforward gain of the trimming voltage control unit is small, the low frequency phase noise generated from the crystal oscillator is not amplified, and the requirement for low noise jitter is achieved.

Please refer to FIG. 2, which is a schematic diagram of a phase-locked loop 200 for dual-loop control according to an embodiment of the present invention. The phase-locked loop circuit 200 includes a phase frequency detecting circuit 202, a first charge pump 204, a second charge pump 206, a first capacitor 208, a filter 210, a first adder 212, and a voltage control circuit. A voltage controlled delay line 214 and a frequency divider 216. The phase frequency detecting circuit 202 has a first input terminal for receiving the reference clock REF, a second input terminal for receiving the frequency-receiving clock pulse DFC, and an output terminal for outputting the switching signal S. The phase frequency detecting circuit 202 is configured to generate the switching signal S according to the difference between the reference clock REF and the frequency-dividing clock DFC. The first charge pump 204 has a first end coupled to the output of the phase frequency detecting circuit 202 for receiving the switching signal S, a second end for receiving the first voltage VDD, and a third end For outputting a coarse control voltage Vcoarse. The second charge pump 206 has a first end coupled to the output end of the phase frequency detecting circuit 202 for receiving the switching signal S, a second end for receiving the first voltage VDD, and a third end For outputting a pre-fine voltage Vpre-fine. The first capacitor 208 has a first end coupled to the third end of the first charge pump 204 and a second end coupled to a ground end. The filter 210 is configured to filter the high frequency portion of the pre-fine voltage Vpre-fine, and the filter 210 has a first end coupled to the third end of the second charge pump 206, and a second end coupled Connected to the ground. The first adder 212 has a first end coupled to the third end of the first charge pump 204 for receiving the coarse control voltage Vcoarse, and a second end coupled to the second charge pump 206 The three ends are configured to receive a pre-fine voltage Vpre-fine and a third end for outputting a trimming control voltage Vfine. The voltage control delay circuit 214 has a first input end coupled to the third end of the first charge pump 204 for receiving the coarse control voltage Vcoarse, and a second input coupled to the first adder 212. The third end is configured to receive the fine adjustment control voltage Vfine, and an output end for outputting a feedback clock FC, wherein the feedback clock FC is a differential clock. The voltage control delay circuit 214 includes a coarse voltage control unit 2142, a trim voltage control unit 2144, and a second adder 2146. The coarse voltage control unit 2142 has a coarse gain function (gr*Kvco)/s for generating a coarse clock control signal CLKcoarse according to the coarse control voltage Vcoarse; the trim voltage control unit 2144 has a fine adjustment gain function Kvco /s, for generating a fine-tuned clock control signal CLKfine according to the fine-tuning control voltage Vfine; the second adder 2146 adds the coarse-tuned clock control signal CLKcoarse and the fine-tuned clock control signal CLKfine, and the voltage-controlled delay circuit 214 is The result of the second adder 2146 outputs a feedback clock FC, wherein the coarse adjustment gain function (gr*Kvco)/s is a first predetermined multiple (gr) of the fine adjustment gain function Kvco/s, where gr is much larger than 1 . The frequency divider 216 is coupled to the voltage control delay circuit 214 and the phase frequency detection circuit 202 for frequency division of the feedback clock FC to output a frequency division feedback clock DFC.

The first charge pump 204 includes a first current source 2042 and a first switch 2044. The first current source 2042 has a first end coupled to the second end of the first charge pump 204 and a second end. The first switch 2044 has a first end coupled to the first charge pump 204. The first end, the second end, is coupled to the second end of the first current source 2042, and the third end is coupled to the third end of the first charge pump 204. When the first charge pump 204 receives the switching signal S, the first current source 2042 charges the first capacitor 208 according to the first current B*IP to determine the coarse control voltage Vcoarse, wherein the coarse control voltage Vcoarse is according to the formula (1) Decide:

Where Cz is the capacitance value of the first capacitor 208.

The second charge pump 206 includes a second current source 2062 and a second switch 2064. The second current source 2062 has a first end coupled to the second end of the second charge pump 206 and a second end. The second switch 2064 has a first end coupled to the second charge pump 206. The first end, the second end is coupled to the second end of the second current source 2062, and the third end is coupled to the third end of the second charge pump 206. The filter 210 includes a second capacitor 2102 and a resistor 2104. The second capacitor 2102 has a first end coupled to the first end of the filter 210 and a second end coupled to the ground end. The resistor 2104 has a first end coupled to the first end of the filter 210. The end, and a second end, are coupled to the ground end. When the second charge pump 206 receives the switching signal S, the second current source 2062 charges the first capacitor 208 according to the second current IP to determine the pre-fine voltage Vpre-fine, wherein the pre-fine voltage Vpre-fine is according to the formula (2) Decide:

Wherein Cp is the capacitance value of the second capacitor 2102, and Rp is the resistance value of the resistor 2104, wherein the capacitance value Cz of the first capacitor 208 is much larger than the capacitance value Cp of the second capacitor 2102.

After receiving the coarse control voltage Vcoarse and the pre-fine voltage Vpre-fine, the first adder 212 generates and outputs a trimming control voltage Vfine according to the coarse control voltage Vcoarse and the pre-fine voltage Vpre-fine, wherein the fine-tuning control voltage Vfine is according to the formula (3) Decide:

Where B is the ratio of the first current B*IP to the second current source 2062, that is, the first current B*IP is a second predetermined multiple (ie, B times) of the second current IP, wherein the second predetermined The multiple B is much smaller than 1, and the second predetermined multiple B and the first predetermined multiple gr are reciprocal to each other.

Therefore, the coarse voltage control unit 2142 of the voltage control delay circuit 214 can generate a first open-loop gain A1 according to the coarse control voltage Vcoarse and the coarse gain function (gr*Kvco)/s, wherein The first open loop gain A1 is determined according to equation (4):

The trimming voltage control unit 2144 of the voltage control delay circuit 214 can generate a second open loop gain A2 according to the trimming control voltage Vfine and the trimming gain function Kvco/s, wherein the second open loop gain A2 is determined according to the formula (5):

The open loop gain A of the phase locked loop 200 is the sum of the first open loop gain A1 and the second open loop gain A2. Therefore, the open loop gain A of the voltage control delay circuit 214 is determined according to equation (6):

According to equations (6), (7) and (8), three poles P1, P2, P3 and zero Z1 of the phase-locked loop 200 are obtained:

Because the first predetermined multiple gr is much larger than 1 and the second predetermined multiple B is reciprocal, and the capacitance Cz of the first capacitor 208 is much larger than the capacitance Cp of the second capacitor 2102, the equation (8) can be Simplified into (9):

Referring to FIG. 3, FIG. 3 is a schematic diagram illustrating a Bode diagram of the open loop gain A of the phase locked loop 200, wherein the longitudinal axis of the Bode diagram of the open loop gain A is corresponding to the open loop gain A. For the logarithmic value, the horizontal axis is ω (the frequency of the feedback clock FC of the phase-locked loop 200). As shown in Fig. 3, since the zero point Z1 is to the left of the zero logarithmic gain point G0 (the logarithm of the open loop gain A is zero), and the pole P3 is to the right of the zero logarithmic gain point G0, the zero logarithmic gain point G0 is On the line segment of -20dB/ten times (-20dB/dec), the phase-locked loop 200 is in a stable state. In addition, since the pole P3 and the zero point Z1 are determined by the equations (7) and (9), respectively, the pole P3 and the zero point can be changed by controlling the capacitance value Cz of the first capacitor 208 and the capacitance value Cp of the second capacitor 2102. The position of Z1 on the third figure.

Please refer to FIG. 4, which is a schematic diagram illustrating the relationship between the coarse control voltage Vcoarse and the trimming control voltage Vfine. As shown in FIG. 4, in order to make the coarse control voltage Vcoarse of the coarse adjustment voltage control unit 2142 equal to the fine adjustment control voltage Vfine of the trimming voltage control unit 2144, the circuit architecture of the coarse adjustment voltage control unit 2142 and the trimming voltage control unit 2144 The circuit architecture is the same, but the component size within the coarse voltage control unit 2142 and the component size within the trim voltage control unit 2144 are different. Therefore, as shown in FIG. 4, the slope of the coarse control voltage Vcoarse curve is a first predetermined multiple gr times the slope of the fine adjustment control voltage Vfine curve. Additionally, the first predetermined multiple gr may vary with the design of the phase locked loop 200.

In summary, the dual-loop controlled phase-locked loop provided by the present invention utilizes a first current source and a second current source to amplify an equivalent capacitance value of the first capacitor, wherein the first capacitor provides a phase-locked loop. Stable zero and coarse control voltage. In addition, the dual-loop controlled phase-locked loop generates a trimming control voltage by a parallel second capacitor, a resistor, and a coarse control voltage. As such, the present invention has the following advantages: First, the present invention does not require a digital correction circuit, an LC tank; and second, the area of the first capacitor of the present invention is smaller than that of a conventional analog-loop dual-loop controlled phase-locked loop. The area of the capacitor is small; thirdly, the invention has a filter with a simple design, and since the coarse voltage control unit and the trimming voltage control unit have the same control voltage, the complexity of debugging or testing can be reduced; Since the feedforward gain of the trimming voltage control unit is small, the low frequency phase noise generated from the crystal oscillator is not amplified, and the low noise jitter is required.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

200. . . Phase-locked loop

202. . . Phase frequency detection circuit

204. . . First charge pump

206. . . Second charge pump

208. . . First capacitor

210. . . filter

212. . . First adder

214. . . Voltage controlled delay circuit

216. . . Frequency divider

2042. . . First current source

2044. . . First switch

2062. . . Second current source

2064. . . Second switch

2102. . . Second capacitor

2104. . . resistance

2142. . . Coarse voltage control unit

2144. . . Fine voltage control unit

2146. . . Second adder

B*IP. . . First current

IP. . . Second current

S. . . Switch signal

Vcoarse. . . Coarse control voltage

Vpre-fine. . . Pre-trim voltage

Vfine. . . Fine-tuning the control voltage

CLKcoarse. . . Coarse clock control signal

CLKfine. . . Fine-tuning the clock control signal

FC. . . Feedback clock

DFC. . . Frequency-receiving clock

REF. . . Reference clock

Z1. . . Zero point

G0. . . Zero logarithmic gain point

P3. . . pole

Figure 1 is a schematic diagram of the prior art description applied to a dual loop phase locked loop.

Fig. 2 is a schematic view showing a phase locked loop of a dual loop control according to an embodiment of the present invention.

Figure 3 is a schematic diagram showing the Bode diagram of the open loop gain of the phase locked loop.

Figure 4 is a schematic diagram showing the relationship between the coarse control voltage and the fine control voltage.

200. . . Phase-locked loop

202. . . Phase frequency detection circuit

204. . . First charge pump

206. . . Second charge pump

208. . . First capacitor

210. . . filter

212. . . First adder

214. . . Voltage controlled delay circuit

216. . . Frequency divider

2042. . . First current source

2044. . . First switch

2062. . . Second current source

2064. . . Second switch

2102. . . Second capacitor

2104. . . resistance

2142. . . Coarse voltage control unit

2144. . . Fine voltage control unit

2146. . . Second adder

B*IP. . . First current

IP. . . Second current

S. . . Switch signal

Vcoarse. . . Coarse control voltage

Vpre-fine. . . Pre-trim voltage

Vfine. . . Fine-tuning the control voltage

CLKcoarse. . . Coarse clock control signal

CLKfine. . . Fine-tuning the clock control signal

FC. . . Feedback clock

DFC. . . Frequency-receiving clock

REF. . . Reference clock

Claims (10)

A dual-loop controlled phase-locked loop includes: a phase frequency detecting circuit for generating a switching signal according to a difference between a reference clock and a frequency-repeating clock, the phase frequency detecting circuit has a first An input terminal for receiving the reference clock, a second input terminal for receiving the frequency division feedback clock, and an output terminal for outputting the switching signal; a first charge pump having a first The end is coupled to the output end of the phase frequency detecting circuit for receiving the switching signal, a second end for receiving a first voltage, and a third end for outputting a coarse control voltage; a second charge pump having a first end coupled to the output of the phase frequency detecting circuit for receiving the switching signal, a second end for receiving the first voltage, and a third The first capacitor has a first end coupled to the third end of the first charge pump, and a second end coupled to a ground end; a filter For filtering the high frequency portion of the pre-trimming voltage, having a first The second end of the second charge pump is coupled to the second end, and the second end is coupled to the ground end, wherein the filter does not generate the pre-trim voltage according to the coarse control voltage; An adder for directly summing the pre-trimming voltage and the coarse control voltage to generate a trimming control voltage, the first adder having a first end coupled to the third end of the first charge pump The second end is coupled to the third end of the second charge pump for receiving the coarse control voltage. Receiving the pre-trimming voltage, and a third terminal for outputting the trimming control voltage; a voltage control delay line having a first input coupled to the first charge pump a third end for receiving the coarse control voltage, a second input coupled to the third end of the first adder for receiving the trim control voltage, and an output for outputting a feedback And a frequency divider coupled to the voltage control delay circuit and the phase frequency detection circuit for frequency division of the feedback clock to output the frequency division feedback clock. The phase-locked loop of claim 1, wherein the voltage-controlled delay circuit comprises: a coarse-tuning voltage control unit having a coarse-tuning gain function for generating a coarse-tuned clock control signal according to the coarse-tuning control voltage And a trimming voltage control unit having a trimming gain function for generating a trimming clock control signal according to the trimming control voltage; wherein the coarse tuning gain function is a first predetermined multiple of the trimming gain function. The phase-locked loop of claim 1, wherein the filter comprises: a second capacitor having a first end coupled to the first end of the filter and a second end coupled to the ground And a first end coupled to the first end of the filter and a second end coupled to the ground end. The phase locked loop of claim 1, wherein the first charge pump comprises: a first current source having a first end coupled to the second end of the first charge pump and a second end; and a first switch having a first end coupled to the first end The first end of the charge pump is coupled to the second end of the first current source, and the third end is coupled to the third end of the first charge pump. The phase-locked loop of claim 1, wherein the second charge pump comprises: a second current source having a first end coupled to the second end of the second charge pump, and a second And a second switch having a first end coupled to the first end of the second charge pump, a second end coupled to the second end of the second current source, and a third The end is coupled to the third end of the second charge pump. A dual-loop controlled phase-locked loop includes: a phase frequency detecting circuit for generating a switching signal according to a difference between a reference clock and a frequency-repeating clock, the phase frequency detecting circuit has a first An input terminal for receiving the reference clock, a second input terminal for receiving the frequency division feedback clock, and an output terminal for outputting the switching signal; a first charge pump having a first The end is coupled to the output end of the phase frequency detecting circuit for receiving the switching signal, a second end for receiving the first voltage, and a third end for outputting a coarse control voltage; a second charge pump having a first end coupled to the output of the phase frequency detecting circuit for receiving the switching signal, and a second end for receiving the a first voltage, and a third end, for outputting a pre-trimming voltage; a first capacitor having a first end coupled to the third end of the first charge pump, and a second end coupled Connected to a ground end; a filter for filtering the high frequency portion of the pre-trimming voltage, having a first end coupled to the third end of the second charge pump, and a second end coupled Connected to the ground; a first adder for generating a trimming control voltage according to the pre-trimming voltage and the coarse control voltage, the first adder having a first end coupled to the first charge The third end of the pump is configured to receive the coarse control voltage, and a second end is coupled to the third end of the second charge pump for receiving the pre-trim voltage and a third end for Outputting the trimming control voltage; a voltage control delay circuit having a first input coupled to the third end of the first charge pump for receiving the coarse control voltage, a second input coupled The third end of the first adder is configured to receive the trimming control voltage, and an output terminal for outputting The voltage control delay circuit includes: a coarse voltage control unit having a coarse gain function for generating a coarse clock control signal according to the coarse control voltage; and a trimming voltage control unit, Having a trimming gain function for generating a trimming clock control signal according to the trimming control voltage; wherein the coarse tuning gain function is a first predetermined multiple of the trimming gain function; a frequency divider coupled to The voltage control delay circuit and the phase frequency detection a channel for dividing the feedback clock to output the frequency-divided feedback clock; wherein a first current provided by the first current source in the first charge pump is a second current in the second charge pump And a second predetermined multiple of a second current provided by the current source, the second predetermined multiple is far less than one, and the first predetermined multiple and the second predetermined multiple are reciprocal of each other. The phase-locked loop of claim 3, wherein the capacitance of the first capacitor is much larger than the capacitance of the second capacitor. The phase-locked loop of claim 1, wherein the feedback clock system is a differential clock. A dual-loop controlled phase-locked loop includes: a phase frequency detecting circuit for generating a switching signal according to a difference between a reference clock and a frequency-repeating clock, the phase frequency detecting circuit has a first An input terminal for receiving the reference clock, a second input terminal for receiving the frequency division feedback clock, and an output terminal for outputting the switching signal; a first charge pump having a first The end is coupled to the output end of the phase frequency detecting circuit for receiving the switching signal, a second end for receiving the first voltage, and a third end for outputting a coarse control voltage, The first charge pump includes: a first current source having a first end coupled to the second end of the first charge pump and a second end; and a first switch having a first End, coupled to the first charge pump One end, a second end, coupled to the second end of the first current source, and a third end coupled to the third end of the first charge pump; a second charge pump having a first One end is coupled to the output end of the phase frequency detecting circuit for receiving the switching signal, a second end for receiving the first voltage, and a third end for outputting a pre-trimming voltage; a first capacitor having a first end coupled to the third end of the first charge pump and a second end coupled to a ground end; a filter for filtering the pre-trimming voltage The high frequency portion has a first end coupled to the third end of the second charge pump, and a second end coupled to the ground end; a first adder for adjusting the pre-fine a voltage and the coarse control voltage to generate a trimming control voltage, the first adder having a first end coupled to the third end of the first charge pump for receiving the coarse control voltage, a second The third end of the second charge pump is coupled to receive the pre-trim voltage, and a third end is configured to output the micro a voltage control delay line having a first input terminal coupled to the third end of the first charge pump for receiving the coarse control voltage and a second input terminal And coupled to the third end of the first adder for receiving the trimming control voltage, and an output terminal for outputting a feedback clock; and a frequency divider coupled to the voltage control delay circuit and The phase frequency detecting circuit is configured to perform frequency division on the feedback clock to output the frequency-divided feedback clock; wherein a first current source is provided by the first current source as the second charge pump The second current source provides a second predetermined multiple of the second current, the second predetermined multiple is far less than one, and the first predetermined multiple and the second predetermined multiple are reciprocal of each other. A dual-loop controlled phase-locked loop includes: a phase frequency detecting circuit for generating a switching signal according to a difference between a reference clock and a frequency-repeating clock, the phase frequency detecting circuit has a first An input terminal for receiving the reference clock, a second input terminal for receiving the frequency division feedback clock, and an output terminal for outputting the switching signal; a first charge pump having a first The end is coupled to the output end of the phase frequency detecting circuit for receiving the switching signal, a second end for receiving the first voltage, and a third end for outputting a coarse control voltage; a second charge pump having a first end coupled to the output of the phase frequency detecting circuit for receiving the switching signal, a second end for receiving the first voltage, and a third The first capacitor has a first end coupled to the third end of the first charge pump, and a second end coupled to a ground end; a filter For filtering the high frequency portion of the pre-trimming voltage, having a first The first end is coupled to the third end of the second charge pump, and the second end is coupled to the ground end; a first adder is configured to generate the voltage according to the pre-trim voltage and the coarse control voltage a trimming control voltage, the first adder having a first end coupled to the third end of the first charge pump for receiving the coarse control voltage, The second end is coupled to the third end of the second charge pump for receiving the pre-trim voltage, and a third end for outputting the trim control voltage, wherein the dual-loop controlled phase-locked loop When the phase is locked, the coarse control voltage is equal to the trimming control voltage; a voltage control delay line has a first input end coupled to the third end of the first charge pump, Receiving the coarse control voltage, a second input end coupled to the third end of the first adder for receiving the trimming control voltage, and an output terminal for outputting a feedback clock; and The frequency divider is coupled to the voltage control delay circuit and the phase frequency detection circuit for frequency division of the feedback clock to output the frequency division feedback clock.