TW201414208A - Phase locked loop with current compensation mechanism and method thereof - Google Patents

Abstract

The present invention discloses a phase locked loop (PLL) with current compensation mechanism and method thereof. The loop comprises an input buffer, charge pump type PLL, detector and lock detector. The input buffer receives a reference signal to generate a first, a second and a third signal. The second signal's phase relay is greater than the first signal but lower than the third signal. The lock detector sends a starting signal to start the detector after determining the phase difference between a feedback signal and the second signal is locked by the charge pump type PLL. The detector samples the feedback signal according to the first and third signals to generate a sampling result and transmits an adjustment signal according to the sampling result to configure the charge pump type PLL to adjust the feedback signal's phase to fall in between the first signal and the third signal.

Description

Phase-locked loop with current compensation mechanism and method thereof

The invention relates to a phase-locked loop with a current compensation mechanism, in particular to a phase adjustment of a phase difference between a reference signal and a feedback signal of a phase-locked loop, and then fine-tuning the phase of the feedback signal to further A phase-locked loop that reduces the phase difference between the reference signal and the feedback signal.

Phase Locked Loop (PLL) is a circuit that is very common today. It is widely used in electronics, communications, etc. The main function of the phase-locked loop is to phase the input reference signal with the output clock signal. The difference can be maintained within a fixed range, thereby achieving the effect of locking the phase difference between the input reference signal and the output clock signal. However, due to the improvement of process technology, the problems faced by technicians are relatively complicated.

Please refer to FIG. 1 , which is a first schematic diagram of a phase locked loop of the prior art. The figure illustrates a common charge pump phase-locked loop, as shown in the figure, the phase-locked loop 1 includes a Phase Frequency Detector (PFD) 11, a Charge Pump 12, Loop Filter 13, Voltage-controlled Oscillator (VCO) and Divider 15.

The feedback signal Fvco is generated by the frequency divider 15. The phase frequency detector 11 determines whether the output signal Fout is leading or falling behind the reference voltage REF according to the phase relationship between the reference signal REF and the feedback signal Fvco, and thereby outputting an Up signal or outputting a Dn signal, thereby adjusting The phase of the feedback signal Fvco is such that the phase difference between the output signal Fout and the reference signal REF is reduced. The charge pump 12 can be composed of a charging current source and a discharge current source. The charge pump 12 can determine the charging current of the internal charging current source according to the Up signal or the Dn signal input by the phase frequency detector 11 or It is the discharge current of the discharge current source, whereby the control current Ic can be generated. The loop filter 13 can convert this control current Ic into a control voltage Vc and input it to the voltage controlled oscillator 14. The voltage controlled oscillator 14 can generate an output signal Fout according to the control voltage Vc, thereby locking the phase of the output signal Fout to be consistent with the reference signal REF.

However, under advanced processes, the effects of the process mismatch in the manufacturing process severely affect the performance of the phase-locked loop 1. For example, due to the inevitable error in the manufacturing process, the charging current source and the discharging current source of the current pump 12 in the phase-locked loop 1 do not match, which causes inconsistency between the charging and discharging currents, thus resulting in phase locking. After the loop 1 is locked, the feedback signal Fvco and the reference signal REF generate a fixed phase difference, which seriously affects the performance of the phase locked loop 1.

Please refer to FIG. 2, which is a second schematic diagram of a phase-locked loop of the prior art. As shown in the figure, when the charging current I1 is smaller than the discharging current I2, the phase of the feedback signal Fvco lags behind the reference signal REF; conversely, when the charging current I1 is greater than the discharging current I2, the phase of the feedback signal Fvco leads the reference signal REF. .

Therefore, how to propose a phase-locked loop, which can effectively improve the phase difference between the output signal of the phase-locked loop and the reference signal caused by the mismatch of the manufacturing process or other reasons, has become an urgent problem.

In view of the above-mentioned problems of the prior art, one of the objects of the present invention is to provide a phase-locked loop with a current compensation mechanism to solve the phase-locked loop of the prior art due to a mismatch in the manufacturing process or other reasons. The problem that the phase difference between the output signal of the loop and the reference signal is too large.

According to one of the objects of the present invention, a phase locked loop with a current compensation mechanism is proposed. The phase locked loop can include an input buffer, a charge pump phase locked loop, and a detector. The input buffer can receive the reference signal to generate the first signal, the second signal and the third signal, and the phase delay of the second signal is greater than the first signal and smaller than the third signal. The charge pump phase-locked loop can receive the second signal and generate a feedback signal according to the output signal, and can lock the phase difference between the second signal and the feedback signal. The detector can receive the first signal, the third signal and the feedback signal. The detector can perform a sampling process on the feedback signal according to the first signal and the third signal after determining that the phase difference between the second signal and the feedback signal is locked, and output the adjustment signal to the charge pump according to the sampling result. The phase-locked loop adjusts the phase of the feedback signal to between the first signal and the third signal.

According to one of the objects of the present invention, a phase locking method is further proposed. The method may include the steps of: receiving the reference signal by the input buffer to generate the first signal, the second signal, and the third signal, wherein the phase delay of the second signal is greater than the first signal and less than the third signal; The phase-locked loop receives the second signal, generates a feedback signal according to the output signal, and locks the phase difference between the second signal and the feedback signal; receives the first signal, the third signal, and the feedback signal through the detector; After determining that the phase difference between the feedback signal and the second signal is locked, the detector performs a sampling procedure on the feedback signal according to the first signal and the third signal, and then outputs an adjustment signal to the charge pump phase-locked loop according to the sampling result. The phase of adjusting the feedback signal falls between the first signal and the third signal.

Preferably, the input buffer further includes a first buffer unit, a second buffer unit, and a third buffer unit, wherein the reference signal generates the first signal through the first buffer unit; the reference signal passes through the first buffer unit and the second buffer unit. And generating a second signal; the reference signal generates a third signal via the first buffer unit, the second buffer unit, and the third buffer unit.

Preferably, the charge pump phase-locked loop can include a charge pump, and the detector can adjust the current of the charge current source or the discharge current source of the charge pump to adjust the phase of the feedback signal.

Preferably, the first buffer unit, the second buffer unit, and the third buffer unit may each include two or more buffers.

Preferably, the detector can sample the feedback signal according to the first signal and the third signal, and determine whether the phase of the feedback signal falls between the first signal and the third signal according to the voltage level value obtained by the sampling. Within the interval.

Preferably, the phase-locked loop may include a lock determiner that activates the signal to activate the detector after detecting the phase difference of the feedback signal and the second signal, so that the detector determines the feedback signal and the first The phase difference of the two signals has been locked and the sampling procedure is performed.

Preferably, the detector determines that the phase difference between the feedback signal and the second signal has been locked after the predetermined time has elapsed, and actively performs the sampling procedure.

In view of the above, the phase-locked loop with current compensation mechanism and method thereof according to the present invention may have one or more of the following advantages:

(1) The present invention uses the detector to finely adjust the phase of the feedback signal after the charge pump phase-locked loop is locked, so that the phase of the output signal is closer to the desired value, so that it can be effectively solved because of the manufacturing process. The mismatch causes the phase difference between the output signal of the charge pump-type phase-locked loop and the reference signal to be too large.

(2) The present invention is simple in construction, so that it is not required to be costly to achieve the desired purpose.

(3) The present invention can adjust the phase difference between the first signal and the third signal and the second signal according to the situation, and change the accuracy of the phase-locked loop, so that the use is extremely flexible.

The embodiments of the phase-locked loop with current compensation mechanism and the phase-locking method thereof according to the present invention will be described with reference to the related drawings. For ease of understanding, the same components in the following embodiments are denoted by the same reference numerals. .

Please refer to FIG. 3, which is a block diagram of a first embodiment of a phase locked loop with a current compensation mechanism of the present invention. As shown, the phase-locked loop 3 can include an input buffer 36, a detector 37, and a charge-pull phase-locked loop A as described in FIG. The charge pump phase-locked loop A can include a PhaseFrequency Detector (PFD) 31, a Charge Pump 32, a Loop Filter 33, and a Voltage-controlled Oscillator. , VCO) 34 and Divider 35.

The input buffer 36 can include a plurality of buffers. The input buffer 36 receives the reference signal REF and can pass the reference signal REF through a different number of buffers to generate the first signal F1, the second signal F2, and the third signal F3. And transmitting the first signal F1 and the third signal F3 to the detector 37. The phase delay amount of the second signal F2 is greater than the first signal F1 and smaller than the third signal F3.

First, the feedback signal Fvco is generated by the frequency divider 35. The phase frequency detector 31 outputs an Up signal according to a phase relationship between the second signal F2 and the feedback signal Fvco, or outputs a Dn signal to adjust the charging current of the charging current source 321 of the charge pump 32 or The discharge current source 322 discharges the magnitude of the discharge current to output the control current Ic, thereby locking the phase difference between the feedback signal Fvco and the reference signal REF. The process is similar to the prior art and will not be described. As described above, due to the process mismatch or other factors generated in the manufacturing process, the charging current source 321 is inconsistent with the discharging current source 322, so that the charge pump-type phase-locked loop A is locked and reaches a steady state, and then feedback The signal Fvco and the second signal F2 still maintain a fixed phase difference.

The detector 37 can determine the phase difference between the feedback signal Fvco and the second signal F2 after a certain preset time (the preset time is sufficient for the charge pump-type phase-locked loop A to be locked to reach a steady state). It is locked, and the sampling signal Fvco is sampled according to the first signal F1 and the third signal F3, and then the phase of the feedback signal Fvco is determined according to the voltage level value obtained by sampling to determine whether the phase of the feedback signal Fvco falls on the preset first signal F1. And within the interval between the third signal F3, and judge whether the feedback signal Fvco is ahead or behind to the second signal F2. Of course, the above is only an example. The phase-locked loop of the present invention may have other mechanisms, so that the detector 37 can determine that the charge pump-type phase-locked loop A has completed locking to reach a steady state, and performs a sampling procedure.

By the above mechanism, the detector 37 can output the adjustment signal Aj to the charge pump 32 to control the magnitude of the charging current of the charging current source 321 of the charge pump 32 or the discharging current of the discharging current source 322. The phase of the feedback signal Fvco is adjusted such that the phase of the output signal Fout falls between the first signal F1 and the third signal F3. Therefore, by the current compensation mechanism described above, the phase-locked loop 3 can be fine-tuned again, so that the phase of the feedback signal Fvco can be locked more accurately.

Please refer to FIG. 4, which is a circuit diagram of a second embodiment of the phase locked loop of the present invention. As shown, the phase locked loop 4 can include an input buffer 46, a detector 47, a lock determiner 48, and a charge pump phase locked loop B as described in FIG. The charge pump phase locked loop B may include a phase frequency detector 41, a charge pump 42, a loop filter 43, a voltage controlled oscillator 44, and a frequency divider 45.

The input buffer 46 may include a first buffer unit 461, a second buffer unit 462, and a third buffer unit 463. The reference signal REF generates the first signal F1 via the first buffer unit 461; the reference signal REF generates the second signal F2 via the first buffer unit 461 and the second buffer unit 462; the reference signal REF passes through the first buffer unit 461, The second buffer unit 463 and the third buffer unit 463 generate a third signal F3. Therefore, the phase delay of the second signal F2 is greater than the first signal F1 and smaller than the third signal F3. Of course, each buffer unit may further include two or more buffers to adjust the interval between the first signal F1 and the third signal F3 to respond to various situations.

Similarly, the charge pump phase-locked loop B first locks the phase difference between the feedback signal Fvco and the second signal F2, however, due to the manufacturing process of the charging current source 421 and the discharge current source 422 of the charge pump 42 or other factors. The resulting mismatch, the phase difference between the feedback signal Fvco and the second signal F2 cannot reach an ideal value close enough.

The lock determiner 48 can detect the feedback signal Fvco and the second signal F2 to determine that the charge pump-type phase-locked loop B completes the lock and reaches a steady state. After the lock determiner 48 determines that the charge pump-type phase-locked loop B has reached a steady state, it sends a start signal En, causing the detector 47 to start performing the sampling process for the second stage of fine-tuning. Of course, this is merely an example, and the present invention can also utilize other mechanisms to enable the detector 37 to determine that the charge pump-type phase-locked loop B has reached a stable state.

Please refer to FIG. 5, which is a timing diagram of a second embodiment of the phase locked loop of the present invention. As shown in the figure, the detector 47 can start the sampling process for the feedback signal Fvco according to the first signal F1 and the third signal F3, and when the level value obtained by the sampling is (0.0), the feedback signal Fvco is displayed. The phase lags behind the second signal F2. At this time, the detector 47 transmits the adjustment signal Aj to the charging current source 421 to increase the charging current I1 (or reduce the discharging current I2); when the sampling is obtained, the level value is (1.1). When the phase of the feedback signal Fvco is ahead of the second signal F2, the detector 47 transmits the adjustment signal Aj to the discharge current source 422 to increase the discharge current I2 (or reduce the charging current I1); finally, when sampling When the obtained level value is (0.1), the phase of the feedback signal Fvco can be closest to the second signal F2. Therefore, after the second stage of the fine adjustment procedure is performed by the detector 37, the phase of the feedback signal Fvco can fall within the interval between the designed first signal F1 and the third signal F3, so that the phase locked loop 4 can be further Indeed.

In addition, the magnitude of the current of the charging current source 421 and the discharging current source 422 of the charge pump 42 can be adjusted using a digital or analogy. These methods should be known to those of ordinary skill in the art to which the present invention pertains. In the narrative.

It is worth mentioning that due to the mismatch or other various factors in the manufacturing process, the error caused by the inconsistency between the charging current source and the discharging current source of the charge pump-type phase-locked loop is achieved. After the steady state, there is still a certain gap between the feedback signal and the reference signal. However, the phase-locked loop proposed by the present invention can use the current compensation mechanism to finely adjust the phase of the feedback signal after the phase-locked loop of the charge-pull phase-locked loop is phase-locked, so that the phase of the feedback signal and the reference signal are more phased. Closely, the error is effectively compensated, so the present invention has progressive patent requirements.

Although the foregoing concept of the phase-locking method of the present invention has been described in the course of explaining the phase-locked loop with current compensation mechanism of the present invention, for the sake of clarity, the following flow chart is further illustrated to explain the present specification in detail. The phase locking method of the invention.

Please refer to FIG. 6 , which is a flowchart of the phase locking method of the present invention. The method includes the following steps:

In step S61, the reference signal is received by the input buffer to generate the first signal, the second signal and the third signal, and the phase delay amount of the second signal is greater than the first signal and smaller than the third signal.

In step S62, the second signal is received by the charge pump phase-locked loop, and the feedback signal is generated according to the output signal, and the phase difference between the second signal and the feedback signal is locked.

In step S63, the first signal, the third signal, and the feedback signal are received via the detector.

In step S64, after the detector determines that the phase difference between the feedback signal and the second signal is locked, the sampling process is performed on the feedback signal according to the first signal and the third signal, and the adjustment signal is output according to the sampling result. The phase of the charge-pull phase-locked loop to adjust the feedback signal falls between the first signal and the third signal.

The detailed description and embodiments of the phase-locking method of the present invention have been described above with respect to the phase-locked loop with current compensation mechanism of the present invention, and will not be repeated here for the sake of brevity.

In summary, the present invention can detect the phase difference between the second signal and the feedback signal again after the charge pump phase-locked loop is locked, thereby adjusting the phase of the output signal to make the same The second signal is more acceptable. Therefore, the present invention can effectively solve the problem that the phase difference between the output signal of the phase-locked loop and the reference signal is too large due to a mismatch in the manufacturing process or other factors. In addition, the design of the present invention is extremely simple and ingenious, and therefore, the object can be achieved without cost. The present invention allows the user to adjust the phase difference between the first signal and the third signal and the second signal as needed, thereby adjusting the phase difference between the feedback signal and the reference signal, so that the use is extremely flexible.

It can be seen that the present invention has achieved the desired effect under the prior art, and is not familiar with the skill of the artist, and its progressiveness and practicability have been met with the patent application requirements.提出 Submit a patent application in accordance with the law, and ask your bureau to approve the application for this invention patent, in order to encourage creation, to the sense of virtue.

The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.

1. . . Phase-locked loop of conventional technology

3, 4. . . Phase locked loop of the invention

11, 31, 41. . . Phase frequency detector

12, 32, 42. . . Charge pump

321,421. . . Charging current source

322, 422. . . Discharge current source

13, 33, 43. . . Loop filter

14, 34, 44. . . Voltage controlled oscillator

15, 35, 45. . . Frequency divider

36, 46. . . Input buffer

461. . . First buffer unit

462. . . Second buffer unit

463. . . Third buffer unit

37, 47. . . Detector

48. . . Lock determiner

A, B. . . Charge pump phase-locked loop

REF. . . Reference signal

Fvco. . . Feedback signal

Fout. . . Output signal

F1. . . First signal

F2. . . Second signal

F3. . . Third signal

I1. . . recharging current

I2. . . Discharge current

En. . . Start signal

Ic. . . Control current

Vc. . . Control voltage

Aj. . . Adjustment signal

S61~S64. . . Step flow

Figure 1 is a first schematic diagram of a phase locked loop of the prior art. Figure 2 is a second schematic diagram of a phase locked loop of the prior art. Figure 3 is a block diagram of a first embodiment of a phase locked loop with current compensation mechanism of the present invention. Figure 4 is a circuit diagram of a second embodiment of a phase locked loop with current compensation mechanism of the present invention. Figure 5 is a timing diagram of a second embodiment of a phase locked loop with current compensation mechanism of the present invention. Figure 6 is a flow chart of the phase lock method of the present invention.

3. . . Phase-locked loop

31. . . Phase frequency detector

32. . . Charge pump

321. . . Charging current source

322. . . Discharge current source

33. . . Loop filter

34. . . Voltage controlled oscillator

35. . . Frequency divider

36. . . Input buffer

37. . . Detector

A. . . Charge pump phase-locked loop

REF. . . Reference signal

Fvco. . . Feedback signal

Fout. . . Output signal

F1. . . First signal

F2. . . Second signal

F3. . . Third signal

Ic. . . Control current

Vc. . . Control voltage

Aj. . . Adjustment signal

Claims (14)

A phase-locked loop with a current compensation mechanism includes: an input buffer for receiving a reference signal to generate a first signal, a second signal, and a third signal, wherein the phase delay of the second signal is greater than the first a signal is smaller than the third signal; a charge pump phase-locked loop receives the second signal and generates a feedback signal according to an output signal, and locks the phase difference between the second signal and the feedback signal; And the detector is configured to receive the first signal, the third signal, and the feedback signal; wherein the detector determines that the phase difference between the second signal and the feedback signal is locked, The first signal and the third signal perform a sampling process on the feedback signal, and output an adjustment signal to the charge pump phase-locked loop according to the sampling result to adjust the phase of the feedback signal to the first signal and the Between the third signal. The phase-locked loop with a current compensation mechanism as claimed in claim 1 , wherein the input buffer further comprises a first buffer unit, a second buffer unit and a third buffer unit, wherein the reference signal passes through the first The first signal is generated by the buffer unit; the reference signal generates the second signal via the first buffer unit and the second buffer unit; the reference signal passes through the first buffer unit, the second buffer unit, and the third The third signal is generated by the buffer unit. A phase-locked loop with a current compensation mechanism as claimed in claim 1, wherein the charge-pull phase-locked loop includes a charge pump, and the detector adjusts a charge current source or a discharge current of the charge pump. The magnitude of the current of the source adjusts the phase of the feedback signal. A phase-locked loop with a current compensation mechanism as described in claim 2, wherein the first buffer unit, the second buffer unit, and the third buffer unit each include two or more buffers. A phase-locked loop with a current compensation mechanism as claimed in claim 1 , wherein the detector samples the feedback signal according to the first signal and the third signal, and obtains a voltage level according to the sampling. The value determines whether the phase of the feedback signal falls within the interval between the first signal and the third signal. The phase-locked loop with the current compensation mechanism as claimed in claim 1 further includes a lock determiner that activates the start signal after detecting the phase difference of the feedback signal and the second signal. The detector causes the detector to determine that the phase difference between the feedback signal and the second signal has been locked, and executes the sampling procedure. A phase-locked loop with a current compensation mechanism as claimed in claim 1 , wherein the detector determines that the phase difference between the feedback signal and the second signal has been locked after a predetermined time has elapsed, and actively performs the Sampling procedure. A phase locking method includes the steps of: receiving a reference signal by using an input buffer to generate a first signal, a second signal, and a third signal, wherein the phase delay of the second signal is greater than the first signal and less than The third signal receives the second signal by a charge pump phase-locked loop, generates a feedback signal according to an output signal, and locks the phase difference between the second signal and the feedback signal; Receiving the first signal, the third signal, and the feedback signal; and determining, by the detector, that the phase difference between the feedback signal and the second signal is locked, according to the first signal and the The three signals perform a sampling process on the feedback signal, and then output an adjustment signal to the charge pump phase locked loop according to the sampling result to adjust the phase of the feedback signal to fall between the first signal and the third signal. The phase lock method of claim 8, wherein the input buffer further comprises a first buffer unit, a second buffer unit and a third buffer unit, wherein the reference signal is generated by the first buffer unit The first signal is generated by the first buffer unit and the second buffer unit; the reference signal is generated by the first buffer unit, the second buffer unit and the third buffer unit Third signal. The phase locking method according to [Recommendation 8] further includes the step of: adjusting, by the detector, a current of a charging current source or a discharging current source of a charge pump in the charge pump phase locked loop. To adjust the phase of the feedback signal. The phase locking method according to [9], wherein the first buffer unit, the second buffer unit, and the third buffer unit each include two or more buffers. The phase locking method as claimed in claim 8 further includes the step of: sampling, by the detector, the feedback signal according to the first signal and the third signal, and obtaining a voltage level according to the sampling. The value determines whether the phase of the feedback signal falls within the interval between the first signal and the third signal. The phase locking method as claimed in claim 8 further includes the steps of: detecting the feedback signal and the second signal by using a lock determiner, and locking the phase difference between the feedback signal and the second signal The detector is then activated by a start signal, so that the detector determines that the phase difference between the feedback signal and the second signal has been locked, and executes the sampling procedure. The phase locking method as claimed in claim 8 further includes the step of: determining, by the detector, that the phase difference between the feedback signal and the second signal has been locked after a predetermined time has elapsed, and actively performing the Sampling procedure.