TWI473095B - Semiconductor device and control method thereof - Google Patents

Description

Semiconductor device and control method thereof

The present invention relates to semiconductor devices, and more particularly to semiconductor devices having non-volatile memory cells capable of storing binary data in a memory cell.

In recent years, the development of large-capacity non-volatile semiconductor devices disposed in semiconductor devices has been promoted. When one of the methods results in a large capacity, a non-volatile memory cell capable of storing two-dimensional data in one memory cell has been developed. Furthermore, a method has been developed for reading data by comparing the threshold voltage of the memory cell with the reference threshold voltage of the two reference memory cells that create the autocorrelation memory cell (hereinafter referred to as A semiconductor device that is a "dynamic reference method".

WO2004-097839 A1 discloses a non-volatile memory for dynamic reference methods with improved data reading in the related art. Japanese Patent Application Publication No. JP-A-2002-334589 discloses a non-volatile memory having a threshold voltage for inspecting a memory cell for checking a reference memory cell to be used as a reference when reading data. Japanese Patent Application Publication No. JP-A-2003-257188 discloses a configuration in which a second reference memory cell is set in accordance with a threshold value of a first reference memory cell in a non-volatile memory in a dynamic reference method. Limit.

In non-volatile memory, it is possible to store two-bit data in one memory cell. One problem is that when reading data using the related technology dynamic reference method, a threshold may occur between the reference memory cell and the memory cell. The voltage does not match, resulting in data reading instability.

In order to solve the above problems, an object of the present invention is to provide a semiconductor device which eliminates a mismatch in threshold voltage between a memory cell and a reference memory cell, thereby improving data reading stability, and providing a method of controlling the semiconductor device.

According to an aspect of the present invention, a semiconductor device has a plurality of memory cells, and stores data of two bits by independently storing data in a storage area isolated in a memory cell; the first reference memory cell corresponds to storing The erasing state of the region is shared by the plurality of memory cells; the second reference memory cell corresponds to the stylized state of the storage region and is shared by the plurality of memory cells; and the control portion is configured by the first reference memory cell The threshold of the second reference memory cell creates a reference threshold and performs data reading by comparing the threshold of the storage area in which the data is to be read in a plurality of memory cells with the reference threshold when reading the data. a fetching operation to verify that the second reference memory cell is programmed with a first threshold to verify that the second reference memory cell is updated with a second threshold value lower than the first threshold value when updating the second reference memory cell Verifying, and when stylizing the plurality of memory cells, in a plurality of memory cells having a threshold value of the second reference memory cell to be programmed to program at least one or more memory cells for verification, and having A plurality of memory cells of the second reference threshold value of the memory cell to be updated to the memory cell to verify the update.

According to another aspect of the present invention, a method for controlling a semiconductor device is provided. The semiconductor device is provided with a plurality of memory cells for storing two bits by independently storing data in an isolated region of a memory cell. In the memory cell, the first reference memory cell corresponds to an erase state of the plurality of memory cells, and the second reference memory cell corresponds to a stylized state of the plurality of memory cells, having the following steps: from the first reference memory cell and The threshold value of the second reference memory cell creates a reference threshold value; the data is read by comparing the threshold value and the reference threshold value of the storage area of the plurality of memory cells to be read; a threshold value stylizes the second reference memory cell to verify; updating the second reference memory cell with a second threshold value lower than the first threshold value to verify; and having a threshold value of the second reference memory cell The plurality of memory cells are to be programmed to program at least one or more memory cells for verification; and to update the memory cells for verification in a plurality of memory cells having a threshold value of the second reference memory cell.

First, the problems solved by the present invention will be explained. Referring to Fig. 1A, the configuration of a non-volatile memory cell MC capable of storing binary data in one memory cell will be explained. The source region 14 and the drain region 12, which are input/output terminals, are formed on the surface of the semiconductor substrate 10 composed of, for example, germanium by a diffusion process. Above the region between the source region 14 and the drain region 12, a gate 16 which is a control terminal is formed. Between the gate 16 and the semiconductor substrate 10, an ONO layer 24 composed of an interlayer insulating film 18, a trapping layer 20, and a gate insulating film 22 is formed (that is, an oxide film, a nitride film, and an oxide film are included). ). The interlayer insulating film 18 and the gate insulating film 22 are oxide films composed of, for example, hafnium oxide, and the trapping layer 20 is a nitride film composed of, for example, tantalum nitride.

Memory is made by injecting a charge into the trap layer 20 (i.e., stylized), or by withdrawing charge (i.e., erasing) from the trapping layer 20 to cause a threshold voltage change. Cell MC stores data. The trapping layer 20 is an insulator, so the injected charge remains in the same place without moving. For this reason, the data can be stored independently in the isolation region in the trap layer 20. Referring to FIG. 1A, the trapping layer 20 has a first storage area 30 and a second storage area 32, each of which can store one bit of data. As for the memory cell MC, it is possible to store two bits of data in one memory cell.

Referring to FIG. 1A, when the first storage region 30 is programmed, although the gate 16 and the drain region 12 are set at a high potential and the source region 14 is set at a low potential, the charge 34 (ie, electron) is Injected in the direction of the arrow by hot electron injection. Referring to FIG. 1B, when the data in the first storage region 30 is erased, although the gate 16 is set to a low potential and the drain region 12 is set to a high potential, the charge 34 is extracted by hot electron injection. In the direction of the arrow.

Reading the first storage by switching the drain region 12 and the source region 14, applying a reverse voltage to the gate region 12 and the source region 14, and applying a lower than a programmed voltage to the gate 16 Information in area 30. Referring to FIG. 1C, when the first storage area 30 is in a stylized state (where charge 34 is injected), the threshold voltage is in a high state and the current flowing in the direction of the arrow is blocked from being marked first in the figure by x. Near the storage area 30, the logical value of "0" is then read. On the contrary, referring to FIG. 1D, when the first storage region 30 is in the erase state (where the charge 34 is not injected), the threshold voltage is in a low state and the current flows in the direction of the arrow, so the logic of reading "1" is read. value.

As described above, stylization, erasing, and reading of data to and from the first storage area 30 of the memory cell MC can be performed. By switching the drain region 12 and the source region 14 and applying the direction of the voltage in the reverse direction, these second storage regions can be implemented in a manner similar to the stylization, erasing and reading of the first storage region 30, respectively. 32 operations.

The memory cell MC independently stores one bit of data to the first storage area 30 and one bit of data in the second storage area 32, thus providing four states as shown in Figures 2A through 2D. Referring to FIG. 2A, in which both the first storage area 30 and the second storage area 32 are in the erased state (ie, the logical value of "1"), it is defined as "11". Referring to FIG. 2B, both the first storage area 30 and the second storage area 32 are in a state of a stylized state (ie, a logical value of "0"), and are defined as "00". Referring to FIG. 2C, the state in which the first storage area 30 is in the erased state and the second storage area 32 is in the stylized state is defined as "10". Referring to FIG. 2D, the state in which the first storage area 30 is in the stylized state and the second storage area 32 is in the erased state is defined as "01".

Here, "programming" means injecting a charge into a storage region of the erase state "1" and raising the voltage of the threshold voltage to the stylized state "0". Meanwhile, "refreshing" explained later means that the refilled charge leaves the storage region which has been in the stylized state "0", to the storage region where the threshold voltage has been lowered to restore the threshold voltage.

Next, the data reading using the dynamic reference method will be explained. Referring to FIG. 3A, a plurality of memory cells MC disposed in the word line WL share the first reference memory cell RC1 and the second reference memory cell RC2 for data read operation. Referring to FIG. 3B, the threshold value of the first reference memory cell RC1 corresponds to the erase state MC "1" of the memory cell MC. The threshold value of the second reference memory cell RC2 corresponds to the stylized state MC "0" of the memory cell MC. The reference threshold REF created by the threshold values of the average first reference memory cell RC1 and the second reference memory cell RC2 is located at the center of MC "1" and MC "0". By comparing the reference threshold REF with the threshold MC "1" and MC "0" of the memory cell MC, it is possible to perform the trickle capture.

In the dynamic reference method, each of the memory cells MC, the first reference memory cell RC1, and the second reference memory cell RC2 coupled to the same word line WL are simultaneously erased each time one of the memory cells is erased. Moreover, each time one of the memory cells is programmed, the memory cell MC and the second reference memory cell RC2 coupled to the same word line WL for all memory cells MC in the stylized state are simultaneously updated. As a result, the characteristics of the memory cell are reconciled, such as the change of the charge loss and the charge gain caused by the degradation of the memory cell MC, the first reference memory cell RC1, and the second reference memory cell RC2, so that the data can be continuously and stably implemented. Read.

Next, a non-volatile memory in the related art dynamic reference method with improved data reading will be explained. Fig. 4A is a cross-sectional view schematically showing an update operation of the "0" side of the memory cell MC in the "10" state. On the second storage region 32, that is, the "0" side, the charge 34 has been injected. When the refresh voltage is applied, the charge is further injected into the direction of the arrow, and the second storage region 32 enters an over-stylized state due to the excess charge. As a result, as indicated by the arrow in FIG. 4B, the threshold voltage MC "1" (which is in the "1" state) rises on the opposite side first storage region 30, thereby causing the reference threshold REF to be present. "Read margin" is 50 small. Get unstable data reading.

Therefore, as shown in Figure 4C, when stylizing new data, the stylized threshold PRGV (ie, the first threshold) is used to verify that when the existing data is updated, the threshold REFV is updated (also That is, a second threshold, which is below the stylized threshold PRGV), is used for verification. As a result, the programmed threshold voltage is distributed as PMC "0" and PRC 2. The updated threshold voltage is distributed as RMC "0" and RRC 2. According to this configuration, when the update is performed, the injected charge is not applied to the storage region where the charge loss is small, so that over-stylization on the "0" side of the second storage region 32 and "1" in the first storage region 30 can be prevented. The rise of the threshold voltage on the side.

Referring to FIG. 5A, in the above configuration, when updating to the "0" side of the memory cell MC in the "10" state, since the verification is performed with the update threshold REFV, the threshold voltage MC on the "1" side" 1" hardly rises, so that a sufficient reading margin of 50 can be ensured. However, referring to FIG. 5B, when stylized (ie, writing new data), one side of the cell MC is in the "11" state because the stylized threshold PRGV is higher than the update threshold REFV. The verification is performed, so the threshold voltage MC "1" on the other "1" side rises (see the arrow in the figure), and a sufficient read margin 50 cannot be ensured. In this case, when the memory cell MC is programmed, the memory cell MC is especially seen after being erased for a long time. A mismatch in the threshold voltage between the reference memory cell RC and the memory cell MC may occur, making data reading unstable.

In order to solve the above problems, according to an aspect of the present invention, a semiconductor device is provided which eliminates a threshold voltage mismatch between a memory cell and a reference memory cell, thereby making data reading stable, and for controlling the semiconductor device. The method.

Embodiments of the present invention will now be described with reference to the drawings.

[First Embodiment]

Fig. 6 is a block diagram showing the configuration of a semiconductor device of a first embodiment of the present invention. The memory cell array 60 including the storage area is composed of a memory cell region 62 for storing data and a dynamic reference region 64 for storing reference materials. The memory cell array 60 is provided with a plurality of bit lines BL in a first direction, and a plurality of word lines WL are disposed in a second direction intersecting the first direction. The individual control terminals of the plurality of memory cells MC are coupled to the memory cell region 62, and the individual control terminals of the first reference memory cell RC1 and the second reference memory cell RC2 are coupled to the single word line WL (eg, WL1). Dynamic reference area 64. In detail, the memory cell MCR composed of a plurality of memory cells MC is provided on the same word line as the first reference memory cell RC1 and the second reference memory cell RC2, sharing RC1 and RC2. The input/output terminals for the memory cell MC and the reference memory cell RC are respectively coupled to two adjacent bit lines BL.

The memory cell MC, the first reference memory cell RC1, and the second reference memory cell RC2 have the same structure as the memory cell MC shown in FIG. 1A, and can be stored in the isolated region of the memory cell by independently storing data (also That is, the first storage area 30 and the second storage area 32) store the data of the two bits in the memory cell. The first reference memory cell RC1 corresponds to the erase state of the memory cell MC, and is set to be equal to the memory region in the "1" state of the memory region in the memory cell MC. The second reference memory cell RC1 corresponds to the stylized state of the memory cell MC and is set to be equal to the memory region in the "0" state of the memory region in the memory cell MC.

Referring to FIG. 6, the bit line BL of the memory cell array 60 is coupled to the row address decoder 66, and the word line WL is coupled to the column address decoder 68. The row address decoder 66 and the column address decoder 68 select the memory cell MC or the reference memory cell RC in accordance with the address signal supplied from the outside through the address bus 72. Furthermore, the row address decoder 66 and the column address decoder 68 apply a voltage to the bit line BL and the word line WL corresponding to the selected memory cell MC or the reference memory cell RC for program, update, erase. And reading the data supplied from the voltage supply circuit 74.

The write/read circuit 76 is read by an internal sense amplifier (not shown) by comparing the signal output from the memory cell region 62 or the dynamic reference region 64 with the reference signal output from the dynamic reference region 64 or the external reference region 79. The data is fetched or verified and the result of the data latch 77 is output. Further, when stylized, the write/read circuit 76 supplies the data input from the material latch 77 to the memory cell array 60. The data latch 77 outputs the data input from the write/read circuit 76 to the I/O circuit 78 and the control unit 70. The I/O circuit 78 exchanges data with the outside.

The control unit 70 controls the stylization, erasing, and data for the memory cell array 60 by controlling the address buffer 72 and the voltage supply circuit 74 corresponding to the commands from the outside and the input data from the data latch 77. Read operation. In particular, when staging and updating the material as will be described later, the control section 70 selects the reference memory cell for verification, and controls the voltage applied to the memory cell in accordance with the verification result in the write/read circuit 76.

On the outside of the memory cell array 60, an external reference area 79 is provided. The external reference region 79 includes a first threshold voltage of the third reference memory cell RC3 setting the programmed threshold PRGV, the fourth reference memory cell RC4 sets the second threshold voltage of the update threshold REFV, and the fifth reference memory cell RC5 sets the third threshold voltage for reading the threshold READV. The outputs from these reference memory cells are supplied to the write/read circuit 76 and are referenced when the second reference memory cell RC2 is programmed or updated.

Referring to Fig. 7, the erasing operation of the semiconductor device of the first embodiment will be explained. First, the control unit 70 collectively erases a plurality of memory cells MC, a first reference memory cell RC1, and a second reference memory cell RC2 coupled to the same word line WL (step S10). In detail, the word line WL coupled to the memory cell MC to be erased is set to a low potential, and all the bit lines BL are set to a high potential, and are removed from the memory cell MC by injecting a thermal hole. The charge is as shown in Figure 1B. As a result, all of the memory cells MC to be erased, the first reference memory cell RC1, and the second reference memory cell RC2 are set to the "11" state.

Next, the control unit 70 programs the second reference memory cell RC2 (step S12). As a result, at least one of the storage areas of the second reference memory cell RC2 enters a "0" state, corresponding to the stylized state of the memory cell MC. At the same time, at least one of the storage areas of the first reference memory cell RC1 is set to a "1" state, corresponding to the erased state of the memory cell MC. The second reference memory cell RC2 is verified by the stylized threshold PRGV set by the stylized third reference memory cell RC3. The stylized threshold PRGV is set higher than the update threshold REFV described later. As described above, in the first embodiment, the stylized second reference memory cell RC2 is implemented during the erase operation.

The stylized operation of the semiconductor device of the first embodiment will be explained. The semiconductor device of the first embodiment uses the same dynamic reference method as that described with reference to FIGS. 3A and 3B. In detail, referring to FIG. 6, when the memory cell MC included in the memory cell NCR in the erase state (ie, the "1" state) is programmed, it is already in the memory state in the memory cell CR (also That is, all the memory cells MC of the "0" state are simultaneously updated. The second reference memory cell RC2 is also updated at the same time. Here, the memory cell MC to be programmed from a plurality of memory cells MC is defined as a memory cell PMC to be programmed. The memory cell MC that has been updated in the stylized state is defined as the memory cell RMC to be updated (refresh the hop cell RMC). When stylized, at least one or more of the memory cells MC become the memory cell PMC to be programmed.

Fig. 8 is a flow chart showing the stylized operation of the semiconductor device of the first embodiment. Referring to Figures 6 and 8, the control unit 70 first inputs new data to be stored in the program memory cell PMC (step S20). In detail, the control unit 70 stores new data in the material latch 77 via the I/O circuit 78. The control section 70 then reads the material that has been stored in the memory cell RMC to be updated (step S22). Here, the read data is implemented by a dynamic reference method as shown in FIG.

Fig. 9 is a flow chart showing the reading operation of the semiconductor device of the first embodiment. Referring to Figures 6 and 9, the control section 70 first obtains the threshold value of the first reference memory cell RC1 (step S30). In detail, from the storage area of the first reference memory cell RC1, the threshold voltage set in the storage area of the erase state "1" is obtained as a current signal or a voltage signal. The control section 70 then obtains the threshold value of the second reference memory cell RC2 (step S32). In detail, the storage area from the second reference memory cell RC2 obtains the threshold voltage of the storage area set in the stylized state “0” as a current signal or a voltage signal.

Then, the control unit 70 determines the reference threshold value REF from the threshold values obtained in steps S30 and S32 (step S34). In the first embodiment, the reference threshold REF is the average of the threshold voltage of the first reference memory cell RC1 and the threshold voltage of the second reference memory cell RC2. The reference threshold REF can be calculated in other ways as long as it is equal to the threshold voltage between the erased state and the stylized state of the memory cell RMC. For example, a weighted average of the threshold voltage of the first reference memory cell RC1 and the threshold voltage of the second reference memory cell RC2 can be used.

Then, the control unit 70 obtains the threshold value of the memory cell MC to be read by the data (step S36). In detail, the storage area of the memory cell MC from which the data is to be read obtains the threshold voltage of the storage area to be read as a current signal or a voltage signal. The control section 70 inputs the threshold value of the memory cell MC and the reference margin REF created in step S34 to the write/read circuit 76 as shown in Fig. 6.

Next, the control unit 70 compares the threshold value of the memory cell MC obtained in step S36 with the reference margin REF created in step S34 for the write/read circuit 76 (step S38). When the threshold of the memory cell MC is greater than the reference threshold REF, the reading result is "0". When the threshold value of the memory cell MC is less than the reference threshold REF, the reading result is "1". Finally, the control unit 70 outputs the comparison result (step S39). In detail, the control section 70 outputs a comparison result to the data latch 77 for the write/read circuit 76. Furthermore, the control unit 70 supplies the material output from the material latch 76 via the input/output circuit 78 to the outside. This completes the data reading operation.

Referring again to FIGS. 6 and 8, in step S22, the control unit 70 stores the data read from the memory cell RMC to be updated into the material latch 77. The control section 70 then updates the second reference memory cell RC2 (step S24). The second reference memory cell RC2 is verified with the update threshold REFV set by the fourth reference memory cell RC4 in the update. The update threshold REFV setting is lower than the stylized threshold PRGV. Therefore, when the charge loss in the storage region (in the "0" state) of the second reference memory cell RC2 is small, no charge is injected, thereby preventing over-staging of the storage region in the "0" state. As a result, the threshold voltage of the second reference memory cell RC2 is maintained at an appropriate level.

Next, the control unit 70 programs the new data to the program memory cell PMC (step S26). In detail, the control unit 70 is configured to use the new data stored in the data latch 77 in step S20, and to program the memory cell PMC to be programmed by applying a voltage to the data latch 77 via the voltage supply circuit 74. . The memory cell PMC to be stylized is verified in the stylization for the threshold value of the second reference memory cell RC2 updated in step S24.

The control unit 70 then updates the existing data in the memory cell RMC to be updated (step S28). In detail, the control unit 70 is used for the data stored in the data latch 77 in step S22, and updates the memory cell RMC to be updated by applying a voltage to the data latch 77 via the voltage supply circuit 74. . The memory cell RMC to be updated is verified in the update for the threshold value of the second reference memory cell RC2 updated in step S24. Step S26 and step S28 can be performed simultaneously. This completes the operation of stylized data.

10A to 10D are diagrams showing changes in the threshold voltage of the memory cell MC and the reference memory cell RC according to the first embodiment. Fig. 10A corresponds to the situation immediately after the erase data operation (i.e., after the end of the flowchart shown in Fig. 7). The threshold voltage of the second reference memory cell RC2 is in a state above the stylized threshold PRGV. The threshold voltage of the first reference memory cell RC1 and the second reference memory cell RC2 is in the erased state.

Fig. 10B corresponds to the situation immediately before the data stylization operation (i.e., before the start of the flowchart shown in Fig. 8). Due to the charge loss over a period of time, the threshold voltage of the second reference memory cell RC2 is lowered, and the threshold voltage sometimes becomes lower than the update threshold REFV (see the physical arrow in the figure). The threshold voltages of the first reference memory cell RC1 and the second reference memory cell RC2 in the "1" state are approximately the same as those shown in FIG. 10A. The reference threshold REF is the average of the threshold voltages of the first reference memory cell RC1 and the second reference memory cell RC2, and the threshold voltage of the second reference memory cell RC2 is decreased (refer to the virtual arrow in the figure) reduce. Therefore, the read margin 50 for the "1" state storage area is smaller than that shown in FIG. 10A. The threshold voltage of the memory cell MC in the "0" state has a similar distribution with the threshold voltage of the second reference memory cell RC2.

The 10Cth map corresponds to the condition immediately after the second reference memory cell RC2 is updated (i.e., the step S24 is completed as shown in Fig. 8). The threshold voltage of the second reference memory cell RC2 is raised by the update, and the threshold voltage is distributed in a region where the update threshold REFV is higher. Furthermore, the reference threshold REF rises according to the updated second reference memory cell RC2 (see the virtual arrow in the figure), and the read margin 50 for the "1" state storage area is greater than that in the 10B chart. Shower.

The 10D map corresponds to the situation immediately after the update of the stylized operation (i.e., the termination of the flowchart shown in Fig. 8). The threshold voltage of the memory cell RMC to be updated in the "0" state shown in Fig. 10C is restored by the update (see the arrow in the figure). Furthermore, the threshold voltage of the memory cell RMC to be programmed in the "1" state shown in Fig. 10C is increased by stylization. Since the memory cell RMC is to be updated and the program memory cell RMC is verified with the threshold voltage of the second reference memory cell RC2 (see step S26 and step S28 shown in FIG. 8), the memory is restored after the stylization or after the update. The threshold voltage of the cell MC "0" is distributed over a region higher than the threshold voltage of the second reference memory cell RC2, thereby preventing over-stylization. As a result, the threshold voltage of the opposite-side storage area MC "1" hardly rises.

Referring to FIG. 8, in accordance with the semiconductor device of the first embodiment, when the new material is programmed, the second reference memory cell RC2 is first updated with an update threshold REFV lower than the programmed threshold PRGV to verify (ie, Step S24), and then verifying with the threshold voltage of the reference memory cell RC2 after the updating step, the memory cell MC is programmed (ie, step S26) and updated (ie, step S28). Therefore, referring to FIG. 10D, in the case where the memory cell PMC and the memory cell RMC are to be updated, it is possible to prevent the overwriting of the storage area MC “0” to be programmed or to be updated, and to prevent the storage area MC of the opposite side. The threshold of "1" has risen. All memory cells MC are verified with the same threshold of the second reference memory cell RC2, thereby preventing a mismatch in the threshold voltage between the memory cell MC and the second reference memory cell RC2. As a result, comparing the example of the related art shown in FIG. 5B, the read margin 50 between the threshold value of the memory cell MC "1" and the reference threshold REF can be made relatively large.

In the erase operation, when the second reference memory cell RC2 is programmed, the programmatic threshold PRGV is used for verification (see step S12 shown in FIG. 7), and in the stylization operation, when updating the When the second memory cell RC2 is referenced, the update threshold REFV (now lower than the stylized threshold PRGV) is used for verification (see step S24 shown in Fig. 8). As a result, referring to FIG. 10C, when the second reference memory cell RC2 is updated, it is possible to prevent the memory area to be updated from being over-stylized, and it is possible to prevent the threshold value of the opposite-side storage area from rising, thereby appropriately setting the second Refer to the threshold voltage of the memory cell RC2.

As described above, according to the semiconductor device of the first embodiment, the threshold voltage of the second reference memory cell RC2 can be appropriately set, and the threshold voltage mismatch between the memory cell MC and the second reference memory cell RC2 is reduced by This improves data reading stability.

In the first embodiment, provided in the external reference area 79 is a third reference memory cell RC3 for setting the programmatic threshold PRGV and the fourth reference memory cell RC4 for setting the update threshold REFV. Therefore, the second reference memory cell RC2 can be verified by either the second reference memory cell RC2 is programmed with the threshold PRGV or the updated threshold REFV.

Referring to FIG. 6, in the first embodiment, the memory cell MC, the first reference memory cell RC1, and the second reference memory cell RC2 are disposed on the same word line WL. According to this configuration, by selecting a single word line WL, all relevant memory cells MC, RC1, and RC2 can be selected, thereby facilitating control. However, the above structure is not an essential constituent of the first embodiment, and other structures may be used as long as the first reference memory cell RC1 and the second reference memory cell RC2 are shared by a plurality of memory cells MC. In detail, when reading data from the memory cell MC, the data will compare the reference threshold REF and the memory cell MC created by the first reference memory cell RC1 and the second reference memory cell RC2. The dynamic reference method is read. For example, a first reference memory cell RC1 and a second reference memory cell RC2 may be provided from outside the memory cell array 60. When the data is read, the threshold voltage on the "1" side is obtained from the first reference memory cell RC1 (that is, step S30 shown in FIG. 9), and the "0" side is obtained from the second reference memory cell RC2. The threshold voltage (that is, step S32 shown in Fig. 9). According to this configuration, the threshold voltage mismatch between the memory cell MC and the reference memory cell RC in the "10" state can be further reduced, thereby further improving the data reading capability.

Referring to FIG. 7, in the erasing operation, when the second reference memory cell RC2 (ie, step S12) is programmed, the whole erase memory cell MC and the reference memory cell RC (ie, step S10) are implemented as part of In the erasing operation, it is preferable to perform a stylizing operation after the entire erasing.

[Second embodiment]

The second embodiment of the present invention is to program the second reference memory cell RC2 for the first stylized memory cell MC after erasing the data (the second reference memory cell RC2 is not programmed when erasing the data). An embodiment. The configuration and data reading operation of the semiconductor device of the second embodiment are the same as those of the first embodiment (i.e., Figs. 6 and 9).

Figure 11 is a flow chart showing the stylized operation of the semiconductor device of the second embodiment. First, the control unit 70 (see Fig. 6) inputs new material to be stored in the program memory cell PMC (step S40). In detail, the control unit 70 stores new data in the material latch 77 via the I/O circuit 78.

The control unit 70 then determines whether or not the memory cell MC is first programmed (step S42). Here, "first time" means that the memory cell MC is programmed for the first time after erasing the memory cell MC and the reference memory cell RC. The erasing operation of the second embodiment is the same as the erasing operation of the first embodiment. In other words, the plurality of memory cells MC, the first reference memory cell RC1, and the second reference memory cell RC2 coupled to the same word line WL are collectively erased (step S10 shown in FIG. 7). Thereafter, the erase operation is completed without programming the reference memory cell RC2.

Figures 12A and 12B show the decision method from step S42 as shown in Fig. 11. The control unit 70 verifies the second reference memory cell RC2 with the read threshold READV lower than the update threshold REFV. The read threshold READV sets a threshold voltage greater than both the memory cell MC of the "1" state and the first reference memory cell RC1, and is smaller than the memory cell MC and the second reference memory having a charge loss in the "0" state The threshold voltage of both cells RC2.

Referring to Fig. 12A, when the first stylized memory cell MC is erased, all memory cells MC are in the "1" state and the first reference memory cell RC1 and the second reference memory cell RC2 are also in the "1" state. . In detail, when the threshold voltage of the second reference memory cell RC2 is lower than the read threshold READV, the control unit 70 determines that the memory cell MC is first programmed, and proceeds to step S44.

On the other hand, referring to Fig. 12B, when the memory cell MC is programmed a second time or more after erasing, the second reference memory cell RC2 and some memory cells MC are in the "0" state. In detail, when the threshold voltage of the second reference memory cell RC2 is higher than the read threshold READV, the control section 70 determines that the memory cell MC is programmed a second time or more, and proceeds to step S46.

Referring again to Figures 6 and 11, in step S42, when the memory cell MC is first programmed, the control unit 70 programs the second reference memory cell RC2 (i.e., step S44). Therefore, at least one of the storage areas in the second reference memory cell RC2 enters a "0" state, corresponding to the stylized state of the memory cell MC. For verifying the second reference memory cell RC2 in the stylization, the stylized threshold PRGV set by the third reference memory cell RC3 is used.

In step S42, when the memory cell MC is not first programmed, that is, when the stylized memory cell MC counts the second or more times after erasing, the control unit 70 reads the existing data (also That is, step S46), and the second reference memory cell RC2 is updated (i.e., step S48). These operations are the same as those of the first embodiment, that is, the same as steps S22 and S24 shown in Fig. 8, respectively. In order to verify the second reference memory cell RC2 in the update, the update threshold REFV set by the fourth reference memory cell RC4 is used. The update threshold REFV is set below the stylized threshold PRGV.

In step S44 or S48, the second reference memory cell RC2 is set to the "0" state. Next, the control unit 70 verifies the threshold voltage of the second reference memory cell RC2, programs the memory cell PMC to be programmed (ie, step S50), and updates the memory cell RMC to be updated (ie, Step S52). These operations are the same as those of the first embodiment, that is, the same as steps S26 and S28 shown in Fig. 8, respectively, thus completing the stylized operation of the semiconductor device of the second embodiment. When the memory cell MC is first programmed, since there is no memory cell RMC to be updated, no re-update is performed (i.e., step S52).

Figures 13A to 13C show changes in the threshold voltage of the memory cell MC and the reference memory cell RC in the stylized operation according to the second embodiment. Fig. 13A corresponds to the situation after the data is erased (i.e., step S10 shown in Fig. 7). All of the memory cells MC, the first reference memory cell RC1, and the second reference memory cell RC2 are in the "1" state, and the threshold voltage is lower than the read threshold READV.

Fig. 13B corresponds to the situation after the second reference memory cell RC2 is being programmed (i.e., step S44 shown in Fig. 11). All memory cells MC are in the "1" state. The second reference memory cell RC2 is verified by the programmatic threshold PRGV, and therefore, the second reference memory cell RC2 is set above the threshold of the stylized threshold PRGV. The reference threshold REF is set at the center of the first reference memory cell RC1 and the second reference memory cell RC2.

Fig. 13C corresponds to the situation after the memory cell MC is being programmatically operated (i.e., the end of the flowchart shown in Fig. 11). The threshold voltage of the "0" state memory cell MC (i.e., the memory cell PMC to be programmed) is distributed over the region of the second reference memory cell RC2 that is verified above the stylized threshold PRGV. Therefore, the threshold value of the storage area MC "1" in the opposite side in the "1" state can be raised. However, in the second embodiment, since the second reference memory cell RC2 is verified by the stylized threshold PRGV in the stylization, the reference threshold REFV is higher than in the first embodiment (ie, the 10D picture). By. As a result, as in the first embodiment, the reading margin 50 of the "1" side can be sufficiently maintained.

Figures 13A through 13C correspond to changes in the threshold voltage of the memory cell when the memory cell MC is first programmed after erasing the data. When the memory cell MC is programmed a second or more times after erasing the data, the application shows the same pattern as shown in FIGS. 10B to 10D.

According to the second embodiment, as in the first embodiment, the threshold voltage mismatch between the memory cell MC and the second reference memory cell RC2 can be reduced, thereby improving the data reading operation capability. The second reference memory cell RC2 is not programmed in the erase operation, so that the time required for the erase operation is shortened compared to the erase operation of the first embodiment.

In the second embodiment, the state of the second reference memory cell RC2 is determined by the read threshold READV lower than the update threshold REFV (see FIGS. 12A to 12B). Therefore, even when the threshold of the reference memory cell RC2 becomes lower than the update threshold REFV, the second reference memory cell RC2 can be correctly determined by the charge loss after a period of time after the second reference memory cell RC2 is programmed. Whether the state is in the "1" or "0" state.

In the second embodiment, provided in the external reference area 79 is a third reference memory cell RC3 setting stylized threshold PRGV, a fourth reference memory cell RC4 setting update threshold REFX, and a fifth reference memory cell RC5 setting. Read the threshold REFV. Therefore, referring to Fig. 11, after verification by the read threshold READV (i.e., as shown in step S42 of Fig. 12), the stylized threshold PRGV verification can be continuously performed (i.e., step S44). Or verify with the update threshold REFV (ie, step S8).

Finally, several aspects of the invention are summarized below.

According to an aspect of the present invention, a semiconductor device is provided with a plurality of memory cells for storing data of two bits by independently storing data in a storage area isolated in a memory cell; the first reference memory cell corresponding to the storage The erasing state of the region is shared by a plurality of memory cells; the second reference memory cell corresponds to the stylized state of the storage region and is shared by the plurality of memory cells; and the control portion, by using the first reference memory cell and The threshold of the second reference memory cell creates a reference threshold and performs data reading by comparing the threshold of the storage area in which the data is to be read in a plurality of memory cells with the reference threshold when reading the data. a fetching operation to verify that the second reference memory cell is programmed with a first threshold to verify that the second reference memory cell is updated with a second threshold value lower than the first threshold value when updating the second reference memory cell Verifying, and when stylizing the plurality of memory cells, in a plurality of memory cells having a threshold value of the second reference memory cell to be programmed to program at least one or more memory cells for verification, and having A plurality of reference memory cells of the memory cell of the threshold value to be updated to the memory cell to verify the update. With this configuration, the threshold voltage of the second reference memory cell can be appropriately set, and the threshold voltage mismatch between the memory cell and the second reference memory cell can be reduced, thereby improving data reading stability.

In the above structure, the control unit may be configured to erase a plurality of memory cells, the first reference memory cell, and the second reference memory cell when erasing the data, and then program the second threshold with the first threshold. Refer to the memory cell for verification. According to this configuration, the time required for the stylized operation can be shortened.

In the above structure, the control unit may be configured to erase a plurality of memory cells, the first reference memory cell, and the second reference memory cell when erasing the data, and then program the plurality of memories for the first time after erasing The second reference memory cell is programmed with the first threshold to verify. According to this configuration, the time required for the erase operation can be shortened.

In the above structure, the control unit may be configured to verify the second reference memory cell with a third threshold value lower than the second threshold value when the data is programmed, when the threshold value of the second reference memory cell is lower than the When the threshold is three, the second reference memory cell is programmed with the first threshold to verify, and when the threshold of the second reference memory cell is higher than the third threshold, the second threshold is updated. Two reference memory cells are verified. According to this configuration, the time required for the erase operation can be shortened.

In the above structure, a third reference memory cell that sets the first threshold, a fourth reference memory cell that sets the second threshold, and a fifth reference memory cell that sets the third threshold may be further provided. According to this configuration, after the verification of the third threshold is performed, the first threshold or the second threshold can be continuously verified.

In the above structure, a plurality of memory cells, the first reference memory cell, and the second reference memory cell are disposed on the same word line.

In the above structure, the first reference memory cell and the second reference memory cell can be separately stored in the two isolated storage areas of the memory cell to store the data of the two bits in the memory cell, and can be configured. One of the two storage areas goes to the stylized state and the other to the erased state. According to this configuration, the threshold voltage mismatch between the memory cell and the reference memory cell can be further reduced, thereby further improving the stability of the data reading operation.

According to an aspect of the present invention, a method for controlling a semiconductor device is provided. The semiconductor device is provided with a plurality of memory cells, and the two-bit data is stored by independently storing data in an isolated region of the memory cell. In the memory cell, the first reference memory cell corresponds to an erase state of the plurality of memory cells, and the second reference memory cell corresponds to a stylized state of the plurality of memory cells, having the following steps: from the first reference memory cell and the The threshold value of the second reference memory cell creates a reference threshold value; the data is read by comparing the threshold value with the reference threshold value of the storage area of the plurality of memory cells to be read; Limiting the second reference memory cell to verify; updating the second reference memory cell with a second threshold below the first threshold to verify; having a threshold value of the second reference memory cell A plurality of memory cells are to be programmed to program at least one or more memory cells for verification; and in a plurality of memory cells having a threshold of the second reference memory cell to be updated to update the memory cells for verification. With this configuration, the threshold voltage of the second reference memory cell can be appropriately set, and the threshold voltage mismatch between the memory cell and the second reference memory cell can be reduced, thereby improving data reading stability.

The above configuration may further provide an erasing step of collectively erasing the plurality of memory cells, the first reference memory cell, and the second reference memory cell, and may be configured to implement the first threshold stylized when performing the erasing step Two reference memory cells to verify the steps. According to this configuration, the time required for the stylized operation can be shortened.

The foregoing configuration may further provide an erasing step of collectively erasing the plurality of memory cells, the first reference memory cell, and the second reference memory cell, and configured to program the second reference memory cell with the first threshold to verify Step, performing the first stylization of a plurality of memory cells after the erasing step. According to this configuration, the time required for the erase operation can be shortened.

While the preferred embodiments of the present invention have been described hereinabove, the present invention is not limited to the specific embodiments, and various modifications may be made within the spirit and scope of the invention as defined by the scope of the claims. change.

10. . . Semiconductor substrate

12. . . Bungee area

14. . . Source area

16. . . Gate

18. . . Interlayer insulating film

20. . . Trapped layer

twenty two. . . Gate insulating film

twenty four. . . ONO layer

30. . . First storage area

32. . . Second storage area

34. . . Electric charge

50. . . Read margin

60. . . Memory cell array

62. . . Memory cell area

64. . . Dynamic reference area

66. . . Row address decoder

68. . . Column address decoder

70. . . Control department

72. . . Address bus (address buffer)

74. . . Voltage supply circuit

76. . . Write/read circuit

77. . . Data latch

78. . . I/O circuit

79. . . External reference area

BL. . . Bit line

MC. . . Memory cell

MCR. . . Memory cell

PMC. . . Stylize memory cells

PMC "0", PRC2. . . Threshold voltage after stylization (updated)

PRGV. . . Stylized threshold (first threshold)

RC1. . . First reference memory cell

RC2. . . Second reference memory cell

RC3. . . Third reference memory cell

RC4. . . Fourth reference memory cell

RC5. . . Fifth reference memory cell

READV. . . Read threshold

REF. . . Reference threshold

REFV. . . Update threshold (second threshold)

RMC. . . To update the memory cell

RMC "0", RRC 2. . . Updated threshold voltage

S10, S12. . . step

S20, S22, S24, S26, S28. . . step

S30, S32, S34, S36, S38, S39. . . step

S40, S42, S44, S46, S48, S50, S52. . . step

WL. . . Word line

1A to 1D are cross-sectional views (Part 1) schematically showing the configuration of the memory cell of the related art and the configuration of the memory cell of the embodiment of the present invention;

2A to 2D are cross-sectional views (Part 2) schematically showing the configuration of the memory cell of the related art and the configuration of the memory cell of the embodiment of the present invention;

3A is a circuit diagram showing a configuration of a semiconductor device in the related art, and FIG. 3B is a diagram showing a threshold voltage of each memory cell shown in FIG. 3A;

4A is a cross-sectional view schematically showing the configuration of the related art semiconductor device, and FIGS. 4B and 4C are diagrams showing the threshold voltage of each memory cell shown in FIG. 4A;

5A and 5B are diagrams showing the threshold voltages of the respective memory cells in the related art;

Figure 6 is a block diagram showing the configuration of a semiconductor device according to a first embodiment of the present invention;

Figure 7 is a flow chart showing the erasing operation of the semiconductor device of the first embodiment;

Figure 8 is a flow chart showing the stylized operation of the semiconductor device of the first embodiment;

Figure 9 is a flow chart showing a reading operation of the semiconductor device of the first embodiment;

10A to 10D are diagrams showing changes in the threshold voltage of each memory cell in the stylized operation according to the first embodiment;

Figure 11 is a flow chart showing the stylized operation of the semiconductor device of the second embodiment of the present invention;

Figures 12A and 12B show the operation from the operation of step S42 as shown in Fig. 11;

Figures 13A to 13C show changes in the threshold voltage of the respective memory cells in the stylized operation of the second embodiment.

60. . . Memory cell array

62. . . Memory cell area

64. . . Dynamic reference area

66. . . Row address decoder

68. . . Column address decoder

70. . . Control department

72. . . Address bus (address buffer)

74. . . Voltage supply circuit

76. . . Write/read circuit

77. . . Data latch

78. . . I/O circuit

79. . . External reference area

BL. . . Bit line

MC. . . Memory cell

PRGV. . . Stylized threshold (first threshold)

RC1. . . First reference memory cell

RC2. . . Second reference memory cell

RC3. . . Third reference memory cell

RC4. . . Fourth reference memory cell

RC5. . . Fifth reference memory cell

READV. . . Read threshold

REFV. . . Update threshold (second threshold)

WL. . . Word line

Claims (10)

A semiconductor device comprising: a plurality of memory cells, wherein two bits of data are stored into the memory cell by independently storing data in an isolated storage area of the memory cell; the first reference memory cell corresponding to the storage area a erased state and shared by the plurality of memory cells; a second reference memory cell corresponding to the stylized state of the storage region and shared by the plurality of memory cells; and a control portion by using the first reference The threshold of the memory cell and the second reference memory cell creates a reference threshold and the reference value of the storage region to be read by comparing the data in the plurality of memory cells with the reference when the data is read Controlling the read operation by thresholding, stylizing with the first threshold when the second reference memory cell is programmed, and verifying that the second reference memory cell is lower than the first threshold when updating the second reference memory cell a threshold update to verify, and when stylizing the plurality of memory cells, program the threshold of the second reference memory cell in the plurality of memory cells to program at least one or more memory cells Verify, and in A plurality of memory cells to the threshold updating the second reference memory cell in the memory cell to verify the update. The semiconductor device of claim 1, wherein the control unit erases the plurality of memory cells, the first reference memory cell, and the second reference memory cell together when erasing the data, and thereafter First pro The limit stylizes the second reference memory cell for verification. The semiconductor device of claim 1, wherein the control unit collectively erases the plurality of memory cells, the first reference memory cell, and the second reference memory cell when the data is erased, and after the erasing The second reference memory cell is programmed with the first threshold to verify when the plurality of memory cells are first programmed. The semiconductor device of claim 3, wherein the control unit, when stylizing the data, verifying the second reference memory cell with a third threshold value lower than the second threshold value, when the second When the threshold of the reference memory cell is lower than the third threshold, the second reference memory cell is programmed with the first threshold to verify, and when the threshold of the second reference memory cell is high At the third threshold, the second reference memory cell is updated with the second threshold to verify. The semiconductor device of claim 4, further comprising: setting a third reference memory cell of the first threshold; setting a fourth reference memory cell of the second threshold; and setting the third threshold The fifth reference memory cell. The semiconductor device of claim 1, wherein the plurality of memory cells, the first reference memory cell, and the second reference memory cell are disposed on the same word line. The semiconductor device of claim 1, wherein the first reference memory cell and the second reference memory cell store the data of the two bits by independently storing data in two isolated storage areas of the memory cell. In the memory cell, and One of the two storage areas is set to the stylized state and the other is set to the erased state. A method for controlling a semiconductor device, the semiconductor device comprising a plurality of memory cells, wherein two bits of data are stored in the memory cell by independently storing data in an isolated region of the memory cell, the first reference memory cell Corresponding to the erase state of the plurality of memory cells, and the second reference memory cell corresponding to the stylized state of the plurality of memory cells, the method comprising the steps of: from the first reference memory cell and the second reference memory cell The threshold value creates a reference threshold value; the data is read by comparing the threshold value of the storage area of the plurality of memory cells to which the data is to be read and the reference threshold value; using the first threshold program The second reference memory cell is verified to be updated; the second reference memory cell is updated with a second threshold value lower than the first threshold value; and the second reference memory cell is used in the plurality of memory cells The threshold is stylized to program at least one or more memory cells for verification; and the threshold value of the second reference memory cell is updated in the plurality of memory cells to update the memory cell for verification. The method for controlling a semiconductor device according to claim 8 of the patent application, further comprising: collectively erasing the plurality of memory cells, the first reference memory cell, and the second reference memory cell; Wherein, after performing the erasing, the second reference memory cell is programmed with the first threshold to verify. The method for controlling a semiconductor device according to claim 8 , further comprising: collectively erasing the plurality of memory cells, the first reference memory cell, and the second reference memory cell; wherein, after the erasing step, the first When the plurality of memory cells are stylized, the second reference memory cell is programmed to verify with the first threshold.