JP4005522B2 - Nonvolatile semiconductor memory and operation control method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory.
[0002]
[Prior art]
A nonvolatile semiconductor memory such as a flash memory stores data by injecting electrons into a charge storage layer of a memory cell and changing a threshold voltage of the memory cell. In general, a state in which the threshold voltage is high and no current flows in the memory cell during the read operation is a state in which “data 0” is written (“0 state” = program state), and the threshold voltage is low and the read operation is in progress. A state in which a current flows through the memory cell is a state in which “data 1” is written (“1 state” = erased state). The “0 state” and “1 state” are detected by comparing the current (memory cell current) flowing through the memory cell during the read operation with the reference current flowing through the reference memory cell.
[0003]
The memory cell current flows by applying a gate voltage to the memory cell. When the gate voltage changes depending on the power supply voltage, the memory cell current changes according to the power supply voltage. When the memory cell current changes, the difference from the read reference current to be compared during the read operation varies, so that the data read margin decreases. In the worst case, the data stored in the memory cell is erroneously read.
[0004]
In order to prevent this kind of read margin from being lowered, a nonvolatile semiconductor memory is disclosed in which an erase verify operation is executed twice using two types of gate voltages during an erase operation (see, for example, Patent Document 1). . Here, the erase verify operation is an operation in which in the erase operation, the memory cell current is compared with the erase reference current flowing through the reference memory cell for erasure to confirm that the memory cell has changed to the erased state.
[0005]
Further, in order to improve a data read margin, a nonvolatile semiconductor memory has been developed that forms a pair of reference memory cells (erase dynamic reference and program dynamic reference) for each memory cell column composed of a predetermined number of memory cells. . The erase dynamic reference is erased together when an erase operation is performed on the corresponding memory cell. At this time, the program dynamic reference is also deleted. The program dynamic reference is programmed together when a program operation is performed on the corresponding memory cell column.
[0006]
In the read operation, the average current of the currents flowing through both dynamic references is used as the read reference current, and the logic level of the data held in the memory cell is determined. A method of erasing and programming each dynamic reference together with erasing and programming of a memory cell is called a dynamic reference method.
[0007]
FIG. 1 shows a distribution of threshold voltages of memory cells in a nonvolatile semiconductor memory employing a dynamic reference method.
The erase operation of the memory cell is executed until the threshold voltage of the memory cell becomes lower than the threshold voltage VEREF of the erase reference memory cell. For this reason, the threshold voltage of the erased memory cell EMC is distributed in a region lower than the threshold voltage VEREF. The erase dynamic reference EDRMC corresponding to each memory cell column is erased together with the erase operation of the memory cell using the memory cell current flowing through the erase reference memory cell (threshold voltage VEREF) as the erase reference current. For this reason, the threshold voltage of the erase dynamic reference EDRMC in the erased state is distributed in a region lower than the threshold voltage VEREF.
[0008]
On the other hand, the program operation of the memory cell is executed until the threshold voltage of the memory cell becomes higher than the threshold voltage VPREF of the program reference memory cell. For this reason, the threshold voltage of the memory cell PMC in the programmed state is distributed in a region higher than the threshold voltage VPREF. The program dynamic reference PDRMC corresponding to each memory cell column is programmed together with the memory cell program operation using the memory cell current flowing through the program reference memory cell (threshold voltage VPREF) as the program reference current. For this reason, the threshold voltage of the program dynamic reference PDRMC in the program state is distributed in a region higher than the threshold voltage VPREF.
[0009]
In the read operation of the memory cell, an average current between the memory cell current of the erase dynamic reference EDRMC and the memory cell current of the program dynamic reference PDRMC is used as the read reference current. In FIG. 1, for ease of explanation, the read reference current is expressed as a threshold voltage VRREF. Since the threshold voltages of the erase dynamic reference EDRMC and the program dynamic reference PDRMC are distributed, the threshold voltage VRREF is also distributed.
[0010]
As described above, in the non-volatile semiconductor memory of the dynamic reference system, the erase dynamic reference EDRMC or the program dynamic reference PDRMC is also written for each erase operation or program operation of each memory cell column. Therefore, the same gate voltage is applied to the memory cells and the dynamic references EDRMC and PDRMC, and the memory cells in the memory cell column and the dynamic references EDRMC and PDRMC corresponding to the memory cell column are always accessed together. . Therefore, the charge gain characteristic and charge loss characteristic of the memory cell and the dynamic references EDRMC and PDRMC can be matched, and the read margin is improved.
[0011]
Here, the charge gain is a phenomenon that a threshold voltage is increased by unexpectedly injecting electrons into the charge storage layer when a relatively high voltage is repeatedly applied to the control gate of the memory cell. The charge gain is generated by repeatedly reading data from the memory cell. The charge gain decreases the read margin of “1 state (erased state)”. The charge loss is a phenomenon in which a relatively low voltage is repeatedly applied to the control gate of the memory cell, whereby unexpected electrons are emitted from the charge storage layer and the threshold voltage is lowered. The charge loss occurs when data is repeatedly written into the memory cell. The charge loss reduces the read margin of “0 state (program state)”.
[0012]
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-60395 (FIG. 2)
[0013]
[Problems to be solved by the invention]
In FIG. 1, when the threshold voltages of the dynamic references EDRMC and PDRMC corresponding to a certain memory cell column are located at black square marks, the threshold voltage VRREF corresponding to the read reference current is located at a black triangle mark. At this time, when the threshold voltage (black circle) of the programmed memory cell in the memory cell column is close to the threshold voltage VPREF of the program reference memory cell, the read margin MRG0 of “0 state (program state)” decreases. .
[0014]
Similarly, when the threshold voltages of the dynamic references EDRMC and PDRMC corresponding to a certain memory cell column are located in white square marks, the threshold voltage VRREF corresponding to the read reference current is located in a white triangle mark. At this time, when the threshold voltage (white circle) of the programmed memory cell in the memory cell column is close to the threshold voltage VEREF of the erase reference memory cell, the read margin MRG1 of “1 state (erased state)” decreases. .
[0015]
In other words, the read margins MRG0 and MRG1 of the memory cell MC in each memory cell column MCR are half of the difference between the memory cell current IPREF of the program dynamic memory cell PDRMC and the memory cell current IEREF of the erase dynamic memory cell EDRMC. May be smaller.
As described above, the conventional dynamic reference method can reduce the influence of the charge gain and the charge loss, but the read margin may be lowered depending on the threshold voltage of the memory cell.
[0016]
An object of the present invention is to improve the read margin of a nonvolatile semiconductor memory. In particular, the read margin of a dynamic reference type nonvolatile semiconductor memory is improved.
[0017]
[Means for Solving the Problems]
  The nonvolatile semiconductor memory of claim 1 andClaim 7In the nonvolatile semiconductor memory operation control method, in the read operation for reading data from the memory cell, the average value of the memory cell currents flowing through the nonvolatile first and second reference memory cells is selected as the read reference current. The first and second reference memory cells have different threshold voltages. Then, the memory cell current flowing through the nonvolatile memory cell is compared with the read reference current, and the logical value stored in the memory cell is determined.
[0018]
The write operation for writing data to the memory cell includes a first write operation and a second write operation following the first write operation. The reference current is switched by, for example, a reference switching circuit between the read operation and the first and second write operations or between the first write operation and the second write operation.
[0019]
First, in the first write operation, the memory cell current flowing through the write reference memory cell is selected as a write reference current for write verification. Then, data is written to the memory cell and one of the first and second reference memory cells while determining the writing state based on the writing reference current. That is, the threshold voltage of the memory cell and the threshold voltage of the first or second reference memory cell are distributed in one region with the threshold voltage of the write reference memory cell as a boundary.
[0020]
In the second write operation, one of the memory cell currents flowing through the first and second reference memory cells is selected as a write reference current for write verification. Then, data is written into the memory cell while determining the write state based on the write reference current. For this reason, after the second write operation, the threshold voltage of the memory cell is distributed on one side with the first or second reference memory cell as a boundary.
[0021]
  By executing a write operation (for example, an erase operation) using the first reference memory cell and a write operation (for example, a program operation) using the second reference memory cell, the threshold voltages of all the memory cells are set. The first and second reference memory cells can be distributed outside the region sandwiched between the threshold voltages. Therefore, the difference between the read reference current generated from the first and second reference memory cells and the memory cell current of the memory cell can be increased. As a result, data can be reliably read in the subsequent read operation. That is, the read margin can be improved.Further, in the first write operation, the write control circuit writes write data to the memory cell, and writes write data to one of the first or second reference memory cells according to the logical value of the write data. The write control circuit writes write data to the memory cell without writing write data to the first and second reference memory cells. Therefore, the first write operation and the second write operation can be reliably executed by the write control circuit.
[0022]
According to another aspect of the nonvolatile semiconductor memory of the present invention, the comparison circuit compares the memory cell current flowing through each memory cell with either the read reference current or the write reference current selected by the reference switching circuit. The switching control circuit controls the selection operation of the reference switching circuit to switch the reference current in accordance with the comparison result in the comparison circuit. For this reason, for example, in the first write operation, when the magnitude relationship between the memory cell current and the write reference current is reversed, the memory for quickly flowing the reference current for write verification to the first and second reference memory cells. Switching to one of the cell currents can start the second write operation. As a result, even when the write operation is executed separately for the first and second write operations, it is possible to prevent the write operation time from significantly increasing.
[0024]
  Claim 3Non-volatile semiconductor memory andClaim 8In the nonvolatile semiconductor memory operation control method, the first and second write operations are first and second erase operations for erasing data in the memory cells. That is, the write reference memory cell is an erase reference memory cell for erase verify. The threshold voltage of the first reference memory cell is lower than the threshold voltage of the second reference memory cell.
[0025]
The first erase operation is executed until the threshold voltage of the memory cell and the first reference memory cell becomes lower than the threshold voltage of the erase reference memory cell. Then, the first logical value is written into the memory cell and the first reference memory cell. The second erase operation is executed until the threshold voltage of all the memory cells becomes lower than the threshold voltage of the first reference memory cell. Then, the first logic value is strongly written into the memory cell. For this reason, the erase level (threshold voltage) of the memory cell can always be lower than the erase level (threshold voltage) of the first reference memory cell. As a result, the erasing operation can be reliably executed, and the data can be reliably read in the subsequent reading operation. That is, the read margin can be improved.
[0026]
  Claim 4Non-volatile semiconductor memory andClaim 9In the nonvolatile semiconductor memory operation control method, the first and second write operations are first and second program operations for programming data in the memory cells. That is, the write reference memory cell is a program reference memory cell for program verification. The threshold voltage of the second reference memory cell is higher than the threshold voltage of the first reference memory cell.
[0027]
The first program operation is executed until the threshold voltage of the memory cell and the second reference memory cell becomes higher than the threshold voltage of the program reference memory cell. Then, the second logical value is written into the memory cell and the second reference cell. The second program operation is executed until the threshold voltage of all the memory cells becomes higher than the threshold voltage of the second reference memory cell. Then, the second logical value is strongly written into the memory cell. For this reason, the program level (threshold voltage) of the memory cell can always be higher than the program level (threshold voltage) of the second reference memory cell. As a result, the program operation can be reliably executed, and the data can be reliably read in the subsequent read operation. That is, the read margin can be improved.
[0028]
  Claim 5In the nonvolatile semiconductor memory, the first and second reference memory cells are formed for each memory cell column. In one read operation or one first and second write operation, one of the memory cell columns formed of a predetermined number of memory cells and the first and second reference memory cells corresponding to the memory cell columns are Accessed. For this reason, the number of accesses of the first and second reference memory cells can be made the same as the number of accesses of the memory cell column. Therefore, the characteristic variation of the first and second reference memory cells can be matched with the characteristic variation of the memory cells in the memory cell column. For example, the charge gain characteristics and the charge loss characteristics of the first and second reference memory cells and the memory cells in the memory cell column can be matched. For this reason, even if the nonvolatile semiconductor memory is used for a long time, it is possible to prevent the read margin from being reduced.
[0029]
  Claim 6In the non-volatile semiconductor memory, the memory cells in each memory cell column and the first and second reference memory cells corresponding to each memory cell column include a charge storage layer for storing charges and a control gate connected to a word line have. These memory cells are connected in series via input / output nodes to which bit lines are respectively connected. That is, a nonvolatile semiconductor memory generally called a virtual ground type is configured.
[0030]
As described above, in the second write operation, data is written only in the memory cells in the memory cell column, and data is not written in the first and second reference memory cells. Control for writing data to only a part of a plurality of memory cells connected to the same word line can be easily achieved by a virtual ground nonvolatile semiconductor memory. As a result, when the present invention is applied to a virtual ground nonvolatile semiconductor memory, the present invention can be easily realized with a control circuit similar to the conventional one. That is, the present invention can be realized with a simple control circuit.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the figure, the signal lines indicated by bold lines are composed of a plurality of lines. Double circles in the figure indicate external terminals. A signal preceded by “/” is a negative logic signal.
FIG. 2 shows a first embodiment of the nonvolatile semiconductor memory of the present invention.
The nonvolatile semiconductor memory is formed as a flash memory on a silicon substrate using a CMOS process. The flash memory includes a state control circuit 10, a voltage switching circuit 12, a program control circuit 14, an erase control circuit 16, an address latch 18, an input / output control circuit 20, a switching control circuit 22, an input / output buffer 24, a data latch 26, and a comparison circuit. 28, a reference switching circuit 30, a row address decoder 32, a column address decoder 34, a cell array unit 36, a dynamic reference unit 38, and an external reference unit 40. The program control circuit 14 and the erase control circuit 16 operate as a write control circuit. The row address decoder 32, the column address decoder 34, the cell array unit 36, and the dynamic reference unit 38 constitute a memory core CORE.
[0032]
The state control circuit 10 determines the operating state of the flash memory according to the chip enable signal / CE, the write enable signal / WE supplied from the outside of the flash memory, and the data signal DATA supplied together with these command signals, A control signal corresponding to the determined operation state is output.
The voltage switching circuit 12 switches the voltage supplied to the memory core CORE according to the control signal from the state control circuit 10 and the logical information signal LINF from the data latch 26. For example, in a program operation (a kind of write operation), the row address decoder 32 is supplied with a program voltage (gate voltage of the memory cell MC; for example, 9 V) applied to the word line WL, and the column address decoder 34 is supplied with a bit line. A program voltage (drain voltage of the memory cell MC; for example, 5 V) to be supplied to BL is supplied. In the verify operation after the program operation, the row address decoder 32 is supplied with a verify voltage (for example, 5 V) applied to the gate of the memory cell MC, and the column address decoder 34 is supplied with a verify voltage (for example, applied to the drain of the memory cell MC). 1.0V) is supplied. In an erase operation (another kind of write operation), an erase voltage (for example, −6V) applied to the gate of the memory cell MC is supplied, and an erase voltage (for example, 6V) applied to the drain of the memory cell MC is supplied to the column address decoder 34. Is supplied. In the read operation, the row address decoder 32 is supplied with a read voltage (for example, 5 V) applied to the gate of the memory cell MC, and the column address decoder 34 is supplied with a read voltage (voltage 1.0 V) applied to the drain of the memory cell MC. Is supplied. The voltage switching circuit 12 performs these switching controls.
[0033]
The program control circuit 14 operates to write “data 0” to the memory cell MC selected by the address signal ADD when a program command is supplied. The program control circuit 14 reliably executes a first program operation and a second program operation described later.
The erase control circuit 16 operates to write “data 1” to the memory cell MC when an erase command is supplied. The erase control circuit 16 reliably executes a first erase operation and a second erase operation described later.
[0034]
The address latch 18 latches an address signal ADD supplied from the outside via an address terminal, and outputs the latched address signal ADD to the row address decoder 32 and the column address decoder 34.
The input / output control circuit 20 switches the data input / output direction of the input / output buffer 24 in accordance with the chip enable signal / CE and the output enable signal / OE.
[0035]
The switching control circuit 22 outputs a switching signal SW for controlling the operation of the reference switching circuit 30 in accordance with the logical information signal LINF (comparison result in the comparison circuit 28) from the data latch 26.
The input / output buffer 24 outputs the data read from the cell array unit 36 and latched by the data latch 26 to the data terminal DATA during the read operation. The input / output buffer 24 receives write data via the data terminal DATA and outputs the received data to the data latch 26 during a program operation. The input / output buffer 24 receives a command data signal via the data terminal DATA.
[0036]
The data latch 26 latches the logic level corresponding to the comparison result output from the comparison circuit 28 during the read operation, and outputs the latched logic level to the input / output buffer 24. The data latch 26 latches the write data supplied from the input / output buffer 24 during the program operation, and uses the latched write data as an expected value for write verification.
[0037]
The comparison circuit 28 compares the memory cell current flowing through the accessed memory cell MC with the reference current during the read operation and the verify operation during the erase operation and the program operation, and outputs the comparison result to the data latch 26. . The read operation is executed in response to a read command supplied from the outside. The erase operation is executed in response to an erase command supplied from the outside. The program operation is executed in response to a program command supplied from the outside. The verify operation is executed to determine whether or not the write data (“logic 0” or “logic 1”) has been correctly written in the memory cell MC in the write operation (erase operation and program operation).
[0038]
In response to the switching signal SW from the switching control circuit 22, the reference switching circuit 30 selects one of the read reference current for read operation, the erase reference current IEREF, and the program reference current IPREF, which is an average value of the reference currents IREF 1 and IREF 0. The selected reference current is output to the comparison circuit 28. The reference switching circuit 30 has a function of obtaining an average value of the reference currents IREF1 and IREF0 in order to perform a read operation.
[0039]
The row address decoder 32 selects one of the word lines WL according to the address signal ADD (upper bit) from the address latch 18. The row address decoder 32 supplies a program voltage, a verify voltage, a read voltage, or an erase voltage to the selected word line WL.
The column address decoder 34 selects a predetermined bit line BL according to the address signal ADD (lower bit) from the address latch 18. Specifically, the bit lines BL on both sides of the memory cell MC to be accessed are selected according to the address signal ADD. The selected bit line BL is set to a predetermined voltage.
[0040]
The cell array unit 36 includes a plurality of memory cells MC arranged in a matrix, a plurality of word lines WL wired in the horizontal direction in the figure, and a plurality of bit lines wired along the vertical direction in the figure. Yes. The memory cells MC arranged in the horizontal direction in the figure are connected in series via an input / output node ND. The control gates of the memory cells MC arranged in the horizontal direction in the figure are connected to the same word line WL.
[0041]
A memory cell column MCR is formed by the memory cells MC connected to the same word line WL. The input / output nodes ND of the memory cells MC arranged in the vertical direction in the figure are connected to each other via a bit line BL. Each bit line BL is shared by adjacent memory cells MC on the left and right sides of the figure. This type of cell array is generally referred to as a virtual ground type.
[0042]
Each memory cell MC is composed of a transistor (cell transistor) having a trap gate TG (charge storage layer) for storing charges (electrons). The trap gate TG is formed of an insulating film such as a nitride film. For this reason, the charges trapped in the trap gate TG do not move in the trap gate TG. Using this, the threshold voltage of the cell transistor can be locally changed.
[0043]
In this embodiment, data is written in only one of a pair of trap regions (white squares in the figure) in the trap gate TG. That is, one memory cell MC can store 1-bit data.
The basic structure of the dynamic reference unit 38 is the same as that of the cell array unit 36. That is, the dynamic reference unit 38 has a virtual ground type cell array structure. The dynamic reference unit 38 is connected to an erase dynamic reference EDRMC (first reference memory cell) and a program dynamic reference PDRMC (second reference memory cell) having the same structure (same characteristics) as the memory cell MC, and these dynamic references EDRMC and PDRMC. A word line WL and a bit line BL.
[0044]
A pair of erase dynamic reference EDRMC and program dynamic reference PDRMC arranged in the horizontal direction in the figure are connected in series via an input / output node ND. The control gates of the memory cells MC arranged in the horizontal direction in the figure are connected to the same word line WL as the cell array portion 36. That is, the pair of erase dynamic reference EDRMC and program dynamic reference PDRMC are formed corresponding to the memory cell column MCR of the cell array unit 34, and their control gates are connected to a common word line WL. The average value of the memory cell currents IREF1 and IREF0 flowing through the dynamic references EDRMC and PDRMC is used as a read reference current during a read operation.
[0045]
In this flash memory, the memory cell MC is accessed by selecting the word line WL. At this time, the dynamic references EDRMC and PDRMC connected to the same word line WL are also accessed. In other words, when a voltage is applied to the control gates of the memory cells MC in the memory cell column MCR, the same voltage is applied to the control gates of the corresponding dynamic references EDRMC and PDRMC. That is, the number of accesses of the dynamic references EDRMC and PDRMC is the same as the number of accesses of the memory cell column MCR.
[0046]
Specifically, when the memory cell column MCR of the cell array unit 36 is erased to “logic 1”, the first reference memory cell EDRMC is also erased to “logic 1”. When the memory cell column MCR of the cell array unit 36 is programmed to “logic 0”, the second reference memory cell PDRMC is also programmed to “logic 0”. That is, the flash memory according to the present embodiment employs a dynamic reference method. Therefore, the characteristic variation of the dynamic references EDRMC and PDRMC coincides with the characteristic variation of the memory cell MC of the memory cell column MCR.
[0047]
Thus, by forming the dynamic references EDRMC and PDRMC for each memory cell column MCR, the charge gain characteristics and the charge loss characteristics of the memory cells MC of the memory cell column MCR and the dynamic references EDRMC and PDRMC can be matched. . As a result, it is possible to mitigate the decrease in the read margin due to the charge gain and charge loss of the memory cell, and the read margin does not decrease even when the nonvolatile semiconductor memory is used for a long time.
[0048]
The external reference unit 40 has a pair of write reference cells (erase reference memory cell EREF and program reference memory cell PREF). The erase reference memory cell EREF and the program reference memory cell PREF are composed of nonvolatile memory cells having a size larger than that of the memory cell MC. A memory cell current IEREF (erase reference current, write reference current) flowing through the erase reference memory cell EREF is used for a verify operation during the erase operation. A memory cell current IPREF (program reference current, write reference current) flowing in the program reference memory cell PREF is used for a verify operation during a program operation. The erase reference current IEREF and the program reference current IPREF are output to the reference switching circuit 30.
[0049]
FIG. 3 shows the flow of the program operation in the first embodiment. The program operation includes a first program operation in steps S10 to S14 and a second program operation in steps S15 to S17.
First, in step S10, the switching control circuit 22 shown in FIG. 2 controls the reference switching circuit 30 to set the program reference current IPREF as a reference current for program verification.
[0050]
Next, in step S11, the comparison circuit 28 compares the memory cell current IMC flowing in each memory cell MC selected by the address signal ADD with the program reference current IPREF. The comparison result is latched in the data latch 26. The switching control circuit 22 receives the logic information signal LINF from the data latch 26 and determines whether or not “logic 0” is written in the memory cell MC. Specifically, when the memory cell current IMC is larger than the program reference current IPREF, it is determined that the program to the memory cell MC is insufficient, and the process proceeds to step S12. If the memory cell current IMC is less than or equal to the program reference current IPREF, it is determined that the program to the memory cell MC is sufficient, and the process proceeds to step S13.
[0051]
In step S12, the program control circuit 14 executes a program operation for writing “logic 0” to the memory cell MC. Thereafter, the process proceeds to step S11 again.
In step S13, the comparison circuit 28 compares the memory cell current IREF0 flowing through the program dynamic reference PDRMC corresponding to the memory cell column MCR selected by the address signal ADD with the program reference current IPREF. The comparison result is latched in the data latch 26. The switching control circuit 22 receives the logical information signal LINF from the data latch 26 and determines whether or not “logic 0” is written in the program dynamic reference PDRMC. Specifically, when the memory cell current IREF0 is larger than the program reference current IPREF, it is determined that the program to the program dynamic reference PDRMC is insufficient, and the process proceeds to step S14. If the memory cell current IREF0 is less than or equal to the program reference current IPREF, it is determined that the program to the program dynamic reference PDRMC is sufficient, and the process proceeds to step S15.
[0052]
In step S14, the program control circuit 14 executes a program operation for writing "logic 0" to the program dynamic reference PDRMC. Thereafter, the process proceeds to step S13 again.
As shown in FIG. 1 described above by the processing of steps S10-S14 (first program operation, first write operation), the threshold voltages of the memory cell MC to be programmed and the program dynamic reference PDRMC are both program reference memory cells. Higher than the threshold voltage VPREF. At this time, the threshold voltage distributions of the memory cell MC and the program dynamic reference PDRMC overlap.
[0053]
Next, in step S15, the switching control circuit 22 controls the reference switching circuit 30 to set the memory cell current IREF0 of the program dynamic reference PDRMC as a reference current for program verification. Since the reference current is quickly switched by the switching control circuit 22, the program operation time does not increase significantly even when the program operation is divided into the first and second program operations.
[0054]
Next, in step S16, the comparison circuit 28 compares the memory cell current IMC flowing in the memory cell MC selected by the address signal ADD with the memory cell current IREF0. The comparison result is latched in the data latch 26. The switching control circuit 22 receives the logical information signal LINF from the data latch 26, and determines whether or not the threshold voltage of the memory cell MC is higher than the threshold voltage of the program dynamic reference PDRMC. Specifically, when the memory cell current IMC is equal to or greater than the memory cell current IREF0, it is determined that the program to the memory cell MC is insufficient, and the process proceeds to step S17. When the memory cell current IMC is smaller than the memory cell current IREF0, it is determined that the program to the memory cell MC is sufficient, and the program operation ends.
[0055]
In step S17, the program control circuit 14 executes a program operation for writing “logic 0” to the memory cell MC. Thereafter, the process proceeds to step S16 again.
The threshold voltages of all the memory cells MC to be programmed are higher than the threshold voltages of the program dynamic memory cells PDRMC by the processing of Steps S15 to S17 (second program operation, second write operation).
[0056]
FIG. 4 shows the erase operation in the first embodiment. The erasing operation includes a first erasing operation in steps S20 to S22 and a second erasing operation in steps S23 to S25.
First, in step S20, the switching control circuit 22 controls the reference switching circuit 30 to set the erase reference current IEREF as a verification reference current.
[0057]
Next, in step S21, the comparison circuit 28 uses the memory cell current IMC flowing in each memory cell MC selected by the address signal ADD and the memory flowing in the erase dynamic reference EDRMC corresponding to the memory cell column MCR selected by the address signal ADD. The cell current IREF1 is compared with the erase reference current IEREF, respectively. The comparison result is latched in the data latch 26. The switching control circuit 22 receives the logical information signal LINF from the data latch 26 and determines whether or not “logic 1” is written in the memory cell MC. Specifically, when the memory cell current IMC is smaller than the erase reference current IEREF, it is determined that the erase of the memory cell MC is insufficient, and the process proceeds to step S22. Similarly, when the memory cell current IREF0 is smaller than the erase reference current IEREF, it is determined that the erase dynamic reference PDRMC is not sufficiently erased, and the process returns to step S22.
[0058]
If the memory cell current IMC is greater than or equal to the erase reference current IEREF, it is determined that the erase to the memory cell MC is sufficient, and the process proceeds to step S23. Similarly, when the memory cell current IREF0 is equal to or larger than the erase reference current IEREF, it is determined that the erase dynamic reference PDRMC is sufficiently erased, and the process proceeds to step S23.
[0059]
In step S22, the program control circuit 14 executes an erase operation for erasing the memory cell MC and the erase dynamic reference EDRMC to “logic 1”. Thereafter, the process proceeds to step S21 again.
As shown in FIG. 1 described above by the processing of steps S20 to S22 (first erase operation and first write operation), the threshold voltages of the memory cell MC to be erased and the erase dynamic reference EDRMC are both erase reference memory cells. Lower than the threshold voltage VEREF. At this time, the threshold voltage distributions of the memory cell MC and the erase dynamic reference EDRMC overlap.
[0060]
Next, in step S23, the switching control circuit 22 controls the reference switching circuit 30 to set the memory cell current IREF1 of the erase dynamic reference EDRMC as a reference current for erase verification. Since the reference current is quickly switched by the switching control circuit 22, even when the erase operation is executed separately for the first and second erase operations, the erase operation time does not increase significantly.
[0061]
Next, in step S24, the comparison circuit 28 compares the memory cell current IMC flowing in the memory cell MC selected by the address signal ADD with the memory cell current IREF1 of the erase dynamic reference EDRMC. The comparison result is latched in the data latch 26. The switching control circuit 22 receives the logical information signal LINF from the data latch 26 and determines whether or not the threshold voltage of the memory cell MC is higher than the threshold voltage of the erase dynamic reference EDRMC. Specifically, when the memory cell current IMC is equal to or greater than the memory cell current IREF1, it is determined that writing to the memory cell MC is insufficient, and the process proceeds to step S25. When the memory cell current IMC is smaller than the memory cell current IREF1, it is determined that writing to the memory cell MC is sufficient, and the erase operation is finished.
[0062]
In step S25, the program control circuit 14 executes an erasing operation for erasing the memory cell MC to “logic 1”. Thereafter, the process proceeds to step S24 again.
The threshold voltages of all memory cells MC to be programmed become lower than the threshold voltages of the erase dynamic memory cells EDRMC by the processes of Steps S23 to S25 (second erase operation, second write operation).
[0063]
FIG. 5 shows the threshold voltage distribution of the memory cell after the program operation and the erase operation shown in FIGS.
By the second program operation shown in steps S15 to S17 of FIG. 3 described above, the threshold voltage of the memory cell MC (PMC) in each memory cell column MCR becomes higher than the threshold voltage of the program dynamic memory cell PDRMC. Further, the threshold voltage of the memory cell MC (EMC) in each memory cell column MCR becomes lower than the threshold voltage of the erase dynamic memory cell EDRMC by the second erase operation shown in steps S23 to S25 of FIG. 4 described above.
[0064]
FIG. 6 shows details of the threshold voltage distribution of FIG.
The threshold voltage of the memory cell MC of the memory cell column MCR connected to the word line WLm is necessarily higher than the threshold voltage of the program dynamic memory cell PDRMC by the second program operation. The threshold voltage of the memory cell MC of the memory cell column MCR connected to the word line WLm is necessarily lower than the threshold voltage of the erase dynamic memory cell EDRMC by the second erase operation. The same applies to memory cell columns MCR connected to other word lines WLn.
[0065]
In the dynamic reference type flash memory, the read reference current IRREF of each memory cell column MCR is set to an average value of memory cell currents flowing through the program dynamic memory cell PDRMC and the erase dynamic memory cell EDRMC. Therefore, in the read operation, the read margin MRG0 of the programmed memory cell MC (PMC) is necessarily larger than the difference between the memory cell current IPREF of the program dynamic memory cell PDRMC and the read reference current IRREF.
[0066]
Similarly, in the read operation, the read margin MRG1 of the erased memory cell MC (EMC) is necessarily larger than the difference between the memory cell current IEREF of the erase dynamic memory cell EDRMC and the read reference current IRREF. In other words, the read margins MRG0 and MRG1 are always larger than one half of the difference between the memory cell current IPREF of the program dynamic memory cell PDRMC and the memory cell current IEREF of the erase dynamic memory cell EDRMC. Improving the read margins MRG0 and MRG1 prevents read data from being erroneously read, that is, data destruction.
[0067]
As described above, in this embodiment, in the second erase operation, the threshold voltage of the memory cell MC can always be lower than the threshold voltage of the corresponding erase dynamic reference EDRMC (first reference memory cell). In the second program operation, the threshold voltage of the memory cell MC can always be higher than the threshold voltage of the corresponding program dynamic reference PDRMC (second reference memory cell). Therefore, the difference between the read reference current IRREF generated from the dynamic references EDRMC and PDRMC and the memory cell current IMC of the memory cell MC can be increased. As a result, data can be reliably read in the subsequent read operation. That is, the read margin can be improved.
[0068]
The switching control circuit 22 controls the selection operation of the reference switching circuit in order to switch the reference current according to the comparison result in the comparison circuit 28. Therefore, in the first program operation, when the memory cell current IMC and the second reference current IREF0 of the program dynamic reference PDRMC are smaller than the program reference current IPREF, the reference current for program verification is quickly supplied to the second reference. The second program operation can be started by switching to the current IREF0. As a result, it is possible to prevent the program operation time from significantly increasing even when the program operation is executed by dividing it into the first and second program operations.
[0069]
Similarly, in the first erase operation, when the memory cell current IMC and the first reference current IREF1 of the erase dynamic reference EDRMC are larger than the erase reference current IEREF, the reference current for erase verification is quickly changed to the first reference. The second erase operation can be started by switching to the current IREF1. As a result, it is possible to prevent the erase operation time from significantly increasing even when the erase operation is executed separately for the first and second erase operations.
[0070]
Since the dynamic references EDRMC and PDRMC are formed for each memory cell column MCR, the number of accesses of the dynamic references EDRMC and PDRMC can be made the same as the number of accesses of the memory cell column MCR. Therefore, the characteristic variation of the dynamic references EDRMC and PDRMC can be matched with the characteristic variation of the memory cell MC of the memory cell column MCR. For example, the charge gain characteristics and the charge loss characteristics of the dynamic references EDRMC and PDRMC and the memory cells MC of the memory cell column MCR can be matched. As a result, it is possible to prevent the read margin from being reduced even when the nonvolatile semiconductor memory is used for a long time.
[0071]
In the virtual ground type flash memory, it is possible to easily control writing data into a part of the memory cells MC, EDRMC, and PDRMC connected to the same word line WL. Therefore, by applying the present invention to a virtual ground type flash memory, the second erase operation and the second program operation can be realized by a control circuit similar to the conventional one. The first program operation composed of steps S10 to S14 shown in FIG. 3 can also be realized by a control circuit similar to the conventional one. In other words, the present invention can be easily realized by applying the present invention to a virtual ground type flash memory.
[0072]
FIG. 7 shows a second embodiment of the nonvolatile semiconductor memory of the present invention. The same circuits / signals as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
In the flash memory, the voltage switching circuit 12B, the cell array unit 36B, the dynamic reference unit 38B, and the external reference unit 40B are used instead of the voltage switching circuit 12, the cell array unit 36, the dynamic reference unit 38, and the external reference unit 40 of the first embodiment. have. The memory cell MC in the cell array part 36B and the dynamic reference part is composed of a transistor (cell transistor) having a floating gate FG (charge storage layer) for storing charges (electrons). Other configurations are substantially the same as those of the first embodiment. The floating gate FG is formed of a conductive film such as polysilicon.
[0073]
Also in this embodiment, the same effect as that of the first embodiment described above can be obtained.
In the first embodiment described above, an example in which the memory cell MC and the program dynamic memory cell PDRMC of the memory cell column MCR are independently programmed in the first program operation of the program operation has been described (FIG. 3). Steps S10-S14). However, the present invention is not limited to such an embodiment. For example, the memory cell MC and the program dynamic memory cell PDRMC may be programmed simultaneously.
[0074]
In the first embodiment described above, an example in which the trap gate TG is formed in the memory cell MC and data is held in only one of the pair of trap regions in the trap gate TG has been described. However, the present invention is not limited to such an embodiment. For example, data may be held in both trap areas, and 1-bit data may be held in two trap areas. In this case, the reliability of data retention can be improved and the read margin can be further improved.
[0075]
In the above-described embodiment, the example in which the present invention is applied to a virtual ground type flash memory has been described. However, the present invention is not limited to such an embodiment. The present invention can be applied to a NOR type or NAND type flash memory. Furthermore, the present invention can be applied to an electrically rewritable nonvolatile multilevel semiconductor memory such as an EEPROM.
[0076]
The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1) A plurality of nonvolatile memory cells;
Non-volatile first and second reference memory cells having different threshold voltages,
A write reference memory cell for determining a write state of the memory cell;
An average value of memory cell currents flowing through the first and second reference memory cells during a read operation is selected as a read reference current, and a memory cell current flowing through the write reference memory cell during a first write operation is selected. One of the memory cell currents flowing in the first and second reference memory cells is selected as a write reference current for write verification, and a write current for write verification is selected during the second write operation executed following the first write operation. A non-volatile semiconductor memory comprising a reference switching circuit that is selected as a reference current.
[0077]
(Appendix 2) In the nonvolatile semiconductor memory according to Appendix 1,
A comparison circuit that compares the memory cell current flowing through each memory cell with either the read reference current or the write reference current selected by the reference switching circuit;
A non-volatile semiconductor memory comprising: a switching control circuit that controls a selection operation of the reference switching circuit in order to switch a reference current according to a comparison result in the comparison circuit.
[0078]
(Supplementary note 3) In the nonvolatile semiconductor memory according to supplementary note 1,
In the first write operation, the write data is written into one of the first and second reference memory cells in accordance with the logical value of the write data together with the memory cell, and only in the memory cell in the second write operation. A non-volatile semiconductor memory comprising a write control circuit for writing the write data.
[0079]
(Supplementary Note 4) In the nonvolatile semiconductor memory according to Supplementary Note 1,
The first and second write operations are first and second erase operations for erasing data of the memory cell,
The write reference memory cell is an erase reference memory cell for erase verify,
The threshold voltage of the first reference memory cell is lower than the threshold voltage of the second reference memory cell,
The write control circuit includes:
In the first erase operation, a threshold voltage of the memory cell and the first reference memory cell is lower than a threshold voltage of the erase reference memory cell in order to write a first logic value to the memory cell and the first reference cell. Execute the erase operation until
In the second erasing operation, the erasing operation is executed until a threshold voltage of the memory cell becomes lower than a threshold voltage of the first reference memory cell in order to strongly write a first logical value in the memory cell. Nonvolatile semiconductor memory.
[0080]
(Supplementary Note 5) In the nonvolatile semiconductor memory according to Supplementary Note 1,
The first and second write operations are first and second program operations for programming data in the memory cell,
The write reference memory cell is a program reference memory cell for program verification,
The threshold voltage of the second reference memory cell is higher than the threshold voltage of the first reference memory cell,
The write control circuit includes:
In the first program operation, a threshold voltage of the memory cell and the second reference memory cell is higher than a threshold voltage of the program reference memory cell in order to write a second logic value to the memory cell and the second reference cell. Execute the program operation until
In the second write operation, in order to strongly write a second logical value to the memory cell, a program operation is executed until a threshold voltage of the memory cell becomes higher than a threshold voltage of the second reference memory cell. Nonvolatile semiconductor memory.
[0081]
(Supplementary note 6) In the nonvolatile semiconductor memory according to supplementary note 1,
A plurality of memory cell columns each comprising a predetermined number of the memory cells;
The first and second reference memory cells are formed for each memory cell column,
In one read operation or one first and second write operations, one of the memory cell columns and at least one of the first and second reference memory cells corresponding to the memory cell column are accessed. A nonvolatile semiconductor memory.
[0082]
(Supplementary note 7) In the nonvolatile semiconductor memory according to supplementary note 6,
The memory cells in the memory cell column and the first and second reference memory cells corresponding to the memory cell columns each have a charge storage layer for storing charges and a control gate connected to a word line. A nonvolatile semiconductor memory, wherein bit lines are connected in series via input / output nodes to which bit lines are respectively connected.
[0083]
(Supplementary note 8) In the nonvolatile semiconductor memory according to supplementary note 7,
The non-volatile semiconductor, wherein the charge storage layer of each of the memory cells and the first and second reference memory cells is a trap insulating film that traps charges locally according to a logical value of write data memory.
(Supplementary note 9) In the nonvolatile semiconductor memory according to supplementary note 7,
2. The nonvolatile semiconductor memory according to claim 1, wherein the charge storage layer of each of the memory cells and the first and second reference memory cells is a floating gate that stores a charge corresponding to a logical value of write data.
[0084]
(Supplementary note 10) In the nonvolatile semiconductor memory according to supplementary note 6,
The memory cell of each memory cell column and the first and second reference memory cells corresponding to each memory cell column are composed of transistors having control gates,
The non-volatile semiconductor memory, wherein the control gate is connected to a common word line.
[0085]
(Supplementary Note 11) In a read operation for reading data from a memory cell, an average value of memory cell currents flowing through the first and second reference memory cells is selected as a read reference current, and the memory cell current flowing through the memory cell is selected as the read reference. By comparing with the current, the logical value stored in the memory cell is determined,
In a write operation for writing data to the memory cell,
A memory cell current flowing through a write reference memory cell to determine a write state of the memory cell is selected as a write reference current for write verification, and the memory cell and one of the first and second reference memory cells are selected. Perform a first write operation to write data;
Subsequent to the first write operation, one of the memory cell currents flowing through the first and second reference memory cells is selected as a write reference current for write verification, and a second write operation for writing data into the memory cell is executed. A method for controlling the operation of a nonvolatile semiconductor memory.
[0086]
(Supplementary Note 12) In the nonvolatile semiconductor memory operation control method according to Supplementary Note 11,
The first and second write operations are first and second erase operations for erasing data of the memory cell,
The write reference memory cell is an erase reference memory cell for erase verify,
The threshold voltage of the first reference memory cell is lower than the threshold voltage of the second reference memory cell,
In the first erase operation, a threshold voltage of the memory cell and the first reference memory cell is lower than a threshold voltage of the erase reference memory cell in order to write a first logic value to the memory cell and the first reference cell. Execute the erase operation until
In the second erasing operation, the erasing operation is executed until a threshold voltage of the memory cell becomes lower than a threshold voltage of the first reference memory cell in order to strongly write a first logical value in the memory cell. An operation control method for a nonvolatile semiconductor memory.
[0087]
(Supplementary note 13) In the nonvolatile semiconductor memory operation control method according to supplementary note 11,
The first and second write operations are first and second program operations for programming data in the memory cell,
The write reference memory cell is a program reference memory cell for program verification,
The threshold voltage of the second reference memory cell is higher than the threshold voltage of the first reference memory cell,
In the first program operation, a threshold voltage of the memory cell and the second reference memory cell is higher than a threshold voltage of the program reference memory cell in order to write a second logic value to the memory cell and the second reference cell. Execute the program operation until
In the second write operation, in order to strongly write a second logical value to the memory cell, a program operation is executed until a threshold voltage of the memory cell becomes higher than a threshold voltage of the second reference memory cell. An operation control method for a nonvolatile semiconductor memory.
[0088]
As mentioned above, although this invention was demonstrated in detail, said embodiment and its modification are only examples of this invention, and this invention is not limited to this. Obviously, modifications can be made without departing from the scope of the present invention.
[0089]
【The invention's effect】
In the nonvolatile semiconductor memory of claim 1 and the nonvolatile semiconductor memory operation control method of claim 8, the threshold voltages of all the memory cells are set to the threshold voltages of the first and second reference memory cells by the second write operation. It can be distributed outside the region. For this reason, the difference between the read reference current generated from the first and second reference memory cells and the memory cell current of the memory cell can be increased. As a result, data can be reliably read in the subsequent read operation. That is, the read margin can be improved.
[0090]
In the nonvolatile semiconductor memory according to the second aspect, even when the write operation is executed by the first and second write operations, it is possible to prevent the write operation time from significantly increasing.
In the nonvolatile semiconductor memory according to the third aspect, the first write operation and the second write operation can be reliably executed by the write control circuit.
[0091]
In the operation control method of the nonvolatile semiconductor memory according to claim 4 and the nonvolatile semiconductor memory according to claim 9, the erase level (threshold voltage) of the memory cell is set to the erase level (threshold value) of the first reference memory cell by the second erase operation. Voltage) can always be lower. As a result, the erasing operation can be reliably executed, and the data can be reliably read in the subsequent reading operation. That is, the read margin can be improved.
[0092]
In the nonvolatile semiconductor memory according to claim 5 and the operation control method of the nonvolatile semiconductor memory according to claim 10, the program level (threshold voltage) of the memory cell is changed to the program level (threshold value) of the second reference memory cell by the second program operation. Voltage) can always be higher. As a result, the program operation can be reliably executed, and the data can be reliably read in the subsequent read operation. That is, the read margin can be improved.
[0093]
In the nonvolatile semiconductor memory according to the sixth aspect, the number of accesses of the first and second reference memory cells can be made the same as the number of accesses of the memory cell column. Therefore, the characteristic variation of the first and second reference memory cells can be matched with the characteristic variation of the memory cells in the memory cell column. As a result, it is possible to prevent the read margin from being reduced even when the nonvolatile semiconductor memory is used for a long time.
[0094]
In the nonvolatile semiconductor memory according to the seventh aspect, when the present invention is applied to a virtual ground nonvolatile semiconductor memory, the present invention can be easily realized by a control circuit similar to the conventional one. That is, the present invention can be realized with a simple control circuit.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a threshold voltage distribution of memory cells in a nonvolatile semiconductor memory employing a dynamic reference method.
FIG. 2 is a block diagram showing a first embodiment of a nonvolatile semiconductor memory of the present invention.
FIG. 3 is a flowchart showing a program operation in the first embodiment.
FIG. 4 is a flowchart showing an erasing operation in the first embodiment.
FIG. 5 is an explanatory diagram showing threshold voltage distributions after a program operation and an erase operation in the first embodiment.
6 is an explanatory diagram showing details of threshold voltage distribution in FIG. 5; FIG.
FIG. 7 is a block diagram showing a second embodiment of a nonvolatile semiconductor memory of the present invention.
[Explanation of symbols]
10 State control circuit
12 Voltage switching circuit
14 Program control circuit
16 Erase control circuit
18 Address latch
20 I / O control circuit
22 Switching control circuit
24 I / O buffer
26 Data latch
28 Comparison circuit
30 Reference switching circuit
32 row address decoder
34 Column address decoder
36 Cell array section
38 Dynamic reference section
40 External reference section
BL bit line
CORE memory core
EDRMC First Reference Memory Cell, Erase Dynamic Reference
EREF Erase reference memory cell
IEREF Write reference current, erase reference current
IMC memory cell current
IPREF Write reference current, Program reference current
IREF0 Second reference current
IREF1 First reference current
IRREF Read reference current
LINF logic information signal
MC memory cell
MCR memory cell column
PDRMC Second reference memory cell, program dynamic reference PREF Program reference memory cell
SW switching signal
WL word line

Claims (9)

A plurality of nonvolatile memory cells;
Non-volatile first and second reference memory cells having different threshold voltages,
A write reference memory cell for determining a write state of the memory cell and the first and second reference memory cells ;
An average value of memory cell currents flowing through the first and second reference memory cells during a read operation is selected as a read reference current, and a memory cell current flowing through the write reference memory cell during a first write operation is selected. One of the memory cell currents flowing in the first and second reference memory cells is selected as a write reference current for write verification, and a write current for write verification is selected during the second write operation executed following the first write operation. In the first switching operation, a reference switching circuit that is selected as a reference current, and in the first write operation, the write data is written to one of the first and second reference memory cells according to a logical value of write data, 2 writing In operation, without writing the write data to the first and second reference memory cell, a write control circuit for writing said write data to said memory cell,
A non-volatile semiconductor memory comprising: The nonvolatile semiconductor memory according to claim 1,
During the first write operation , the memory cell current that flows through each of the memory cells and one of the first reference memory cell and the second reference memory cell is used. During the second write operation, the memory cell current that flows through the memory cell. and a comparator circuit for comparing with any of the read reference current and the write reference current selected by said reference switching circuit,
A non-volatile semiconductor memory comprising: a switching control circuit that controls a selection operation of the reference switching circuit in order to switch a reference current in accordance with a comparison result in the comparison circuit. The nonvolatile semiconductor memory according to claim 1 ,
The first write operation is a first erase operation for erasing data in the memory cell and the first reference memory cell,
The second write operation is a second erase operation for erasing data in the memory cell,
The write reference memory cell is an erase reference memory cell for erase verify,
The threshold voltage of the first reference memory cell is lower than the threshold voltage of the second reference memory cell,
The write control circuit includes:
In the first erase operation, a threshold voltage of the memory cell and the first reference memory cell is lower than a threshold voltage of the erase reference memory cell in order to write a first logic value to the memory cell and the first reference cell. Execute the erase operation until
In the second erasing operation, the erasing operation is executed until a threshold voltage of the memory cell becomes lower than a threshold voltage of the first reference memory cell in order to strongly write a first logical value in the memory cell. Nonvolatile semiconductor memory. The nonvolatile semiconductor memory according to claim 1 ,
The first write operation is a first program operation for programming data in the memory cell and the second reference memory cell,
The second write operation is a second program operation for programming data into the memory cell,
The write reference memory cell is a program reference memory cell for program verification,
The threshold voltage of the second reference memory cell is higher than the threshold voltage of the first reference memory cell,
The write control circuit includes:
In the first program operation, a threshold voltage of the memory cell and the second reference memory cell is higher than a threshold voltage of the program reference memory cell in order to write a second logic value to the memory cell and the second reference cell. Execute the program operation until
In the second write operation, in order to strongly write a second logical value to the memory cell, a program operation is executed until a threshold voltage of the memory cell becomes higher than a threshold voltage of the second reference memory cell. Nonvolatile semiconductor memory. The nonvolatile semiconductor memory according to claim 1,
A plurality of memory cell columns each comprising a predetermined number of the memory cells;
The first and second reference memory cells are formed for each memory cell column,
In one read operation or one first and second write operations, one of the memory cell columns and at least one of the first and second reference memory cells corresponding to the memory cell column are accessed. A nonvolatile semiconductor memory. The nonvolatile semiconductor memory according to claim 5 , wherein
The memory cells in the memory cell column and the first and second reference memory cells corresponding to the memory cell columns each have a charge storage layer for storing charges and a control gate connected to a word line. A nonvolatile semiconductor memory, wherein bit lines are connected in series via input / output nodes to which bit lines are respectively connected. In a read operation of reading data from a memory cell, an average value of memory cell currents flowing through first and second reference memory cells having different threshold voltages is selected as a read reference current, and the memory cell current flowing through the memory cell is read out. By comparing with a reference current, the logical value stored in the memory cell is determined,
In a write operation for writing data to the memory cell,
A memory cell current flowing through a write reference memory cell to determine a write state of the memory cell and the first and second reference memory cells is selected as a write reference current for write verification, and the memory cell and the first reference memory cell are selected. And a first write operation for writing data to one of the second reference memory cells,
Subsequent to the first write operation, one of the memory cell currents flowing through the first and second reference memory cells is selected as a write reference current for write verification, and a second write operation for writing data into the memory cell is executed. A method for controlling the operation of a nonvolatile semiconductor memory. The operation control method for a nonvolatile semiconductor memory according to claim 7 ,
The first write operation is a first erase operation for erasing data in the memory cell and the first reference memory cell,
The second write operation is a second erase operation for erasing data in the memory cell,
The write reference memory cell is an erase reference memory cell for erase verify,
The threshold voltage of the first reference memory cell is lower than the threshold voltage of the second reference memory cell,
In the first erase operation, a threshold voltage of the memory cell and the first reference memory cell is lower than a threshold voltage of the erase reference memory cell in order to write a first logic value to the memory cell and the first reference cell. Execute the erase operation until
In the second erasing operation, the erasing operation is executed until a threshold voltage of the memory cell becomes lower than a threshold voltage of the first reference memory cell in order to strongly write a first logical value in the memory cell. An operation control method for a nonvolatile semiconductor memory. The operation control method for a nonvolatile semiconductor memory according to claim 7 ,
The first write operation is a first program operation for programming data in the memory cell and the second reference memory cell,
The second write operation is a second program operation for programming data in the memory cell,
The write reference memory cell is a program reference memory cell for program verification,
The threshold voltage of the second reference memory cell is higher than the threshold voltage of the first reference memory cell,
In the first program operation, a threshold voltage of the memory cell and the second reference memory cell is higher than a threshold voltage of the program reference memory cell in order to write a second logic value to the memory cell and the second reference cell. Execute the program operation until
In the second write operation, in order to strongly write a second logical value to the memory cell, a program operation is executed until a threshold voltage of the memory cell becomes higher than a threshold voltage of the second reference memory cell. An operation control method for a nonvolatile semiconductor memory.

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