CN107644666B

CN107644666B - Self-adaptive flash memory write-in operation control method and circuit

Info

Publication number: CN107644666B
Application number: CN201710986267.6A
Authority: CN
Inventors: 洪亮
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2017-10-20
Filing date: 2017-10-20
Publication date: 2020-09-18
Anticipated expiration: 2037-10-20
Also published as: CN107644666A

Abstract

The invention discloses a self-adaptive flash memory write-in operation control method and a circuit, wherein the method comprises the following steps: step one, when processing write operation, detecting threshold voltages of two reference units; and step two, comparing the detected threshold voltage with different reference thresholds, judging the threshold range of the current row according to the comparison result, thereby obtaining the state of the current row, and then judging the corresponding operations of preprogramming, erasing, progressive erasing or programming.

Description

Self-adaptive flash memory write-in operation control method and circuit

Technical Field

The present invention relates to the field of flash memory technology, and in particular, to a method and a circuit for controlling write operation of a self-adaptive flash memory.

Background

Flash memory, also known as Flash, is the most common type of non-volatile memory at present, and is a reliable data retention method, and is characterized in that data can be repeatedly read for a long time by once writing, and is not affected by chip reset or power failure. Because of the reliability characteristics of Flash, Flash has been widely applied to the fields of bank cards and MCU processors, and is used for storing data with high reliability requirements, such as chip start programs.

The threshold voltage Vt of the Flash memory cell is a characteristic value of the state of Flash. The Flash cell structure determines that the operation of writing data into Flash includes two steps of erasing (Erase) and programming (Program), wherein Erase is used for reducing the Vt of the memory cell to a certain negative voltage, and Program is used for increasing the Vt to different negative or positive voltages according to the written value on the basis of the Vt of Erase, so that different data can be obtained through the operation of a reading circuit. According to the operation state, the threshold voltage of Flash can be divided into 3 types: (1) a 1 state is written, which is characterized by a threshold voltage exceeding a certain positive threshold voltage and a read value of "1"; (2) writing a 0 state, which is embodied as a negative threshold voltage with a threshold voltage close to a relatively small value, and reading a value of "0"; (3) the erase state, specifically, the negative threshold voltage with a threshold voltage much lower than the threshold voltage when writing the 0 state, is also "0" in the read value.

Erase is the basis of the whole programming process of the Flash device, the result of Erase operation is firstly related to the initial Vt of the current cell, and the change amount of Vt is delta V_tAnd operation ofIs related to the duration and can be approximately characterized using equation (1). For the user, Erase voltage V_eraseIs determined during chip testing, the factors that influence the result of each write are mainly the Vt before operation and the operation time Δ t.

ΔVt∝V_eraseΔt (1)

Two failure models may occur for normal abnormal Erase operation: the failed cells are classified according to their Vt characteristics: vt too high and Vt too low. A condition where Vt is too low is an excessive Erase condition, also known as supersaturation: the "oversaturation" of SONOS nonvolatile memory cells is characterized by the inability of reprogramming the Vt of a memory cell to increase when the Vt is erased to below some negative value that is too low. From a system level, the cell cannot rewrite "1", thereby causing a functional failure, which is usually caused by too long erase time or too many times, and is therefore also referred to as "over-erase phenomenon". This phenomenon is usually caused by faulty operation of the memory cell after the process problem is eliminated, and in practice, this phenomenon needs to be avoided. The other failure is represented by a Vt that is too high, which can be regarded as an Erase deficiency, i.e., the Vt after Erase does not reach a desired Vt value, and has a large correlation with the device characteristic shift. This situation can be solved by increasing the Erase time.

In general, to prevent Vt from being too low, Flash IP designers use a method called pre-programming, which first uniformly pulls Vt to a positive threshold and then erases it to ensure that Vt is not operated too low. This approach can pull the initial Vt of each program operation closer, making the post Erase Vt only related to Δ Vt, which can be relatively close because the operation time is fixed. This approach can avoid inter-cell Vt differences after Erase, but still suffers from the following drawbacks: (1) if the Vt itself has exceeded the preprogrammed target Vt, the preprogrammed operation is meaningless, wasting system operating time; (2) the method can not avoid the possibility of over erasure caused by abnormal operation of the user system; (3) this approach does not address the case of Vt being too high. In the case where Vt is too high, it is generally considered as a characteristic in terms of process, and it is ensured by process reliability.

Disclosure of Invention

To overcome the above-mentioned deficiencies of the prior art, the present invention provides a method and a circuit for controlling a write operation of an adaptive flash memory, so as to prevent the Vt (threshold voltage) after Erase from being abnormal.

To achieve the above and other objects, the present invention provides a method for controlling write operation of an adaptive flash memory, comprising the steps of:

step one, when processing write operation, detecting threshold voltages of two reference units;

and step two, comparing the detected threshold voltage with different reference thresholds, judging the threshold range of the current row according to the comparison result so as to obtain the state of the current row, and then judging the corresponding operations of preprogramming, erasing, progressive erasing or programming.

Further, the second step further comprises:

step S1, determining whether the detected threshold voltages of the two reference cells are both greater than the positive voltage first reference threshold Vtp, if yes, proceeding to step S2;

step S2, erasing the current row;

step S3, continuing to detect the threshold voltages of the two reference cells for one time;

step S4, determining whether the detected threshold voltages of the two reference cells are both smaller than the third reference threshold Vte, if yes, entering step S5;

step S5, the current row is programmed or preprogrammed.

Further, in step S1, if the determination result is negative, it is determined whether the detected threshold voltages of the two reference cells are both smaller than the third reference threshold Vte, if so, the method proceeds to step S5 to perform a programming operation; if not, judging whether the detected threshold voltages of the two reference cells are both smaller than a second reference threshold Vtpi and larger than a third reference threshold Vte, if so, performing incremental erasing on the current row, returning to the step S3, otherwise, entering the step S5, and performing pre-programming operation.

Further, in step S4, if the determination result is negative, the current row is incrementally erased, and the process returns to step S3.

Further, the first reference threshold is greater than the second reference threshold and greater than the third reference threshold.

To achieve the above object, the present invention further provides an adaptive flash memory write control circuit, including:

the top layer controller is responsible for overall control and configures other modules;

the timing module is responsible for realizing a timing function;

the address configuration is used for configuring the address of the flash memory;

the threshold voltage detection module is used for detecting the threshold voltage in the configuration flash memory through the threshold detection interface, realizing the reading operation of the flash memory, judging the specific threshold voltage Vt condition of the reference memory cell by checking the read data and feeding back the specific threshold voltage Vt condition to the top layer controller;

the write-in operation module sends a specific time sequence command to the flash memory through the write-in operation interface according to the instruction provided by the top layer controller, and determines the specific operation time of the flash memory according to the signal of the timing module;

and a clock generator for sending clock pulses to the flash memory according to the threshold voltage detection module and the enable signal of the write operation module.

Further, the threshold voltage detection module includes:

the detection controller is responsible for controlling the internal state machine switching of threshold voltage Vt detection, controlling the clock of threshold voltage Vt reading operation, setting an enable signal Tm _ conf and an MDAC of margin read of the threshold voltage Vt corresponding to the flash memory, and judging the read comparison result of the flash memory;

an MDAC setting selector for selecting an MDAC value corresponding to the threshold voltage Vt to be detected through the enable signal Msel [1:0] of the detection controller;

the read clock enable signal generation unit is used for generating an enable signal clk _ gen _ reg to enable the clock generator to generate a flash memory read clock pulse.

And the flash memory output comparator is used for obtaining the flash memory output data, obtaining the read comparison result of the flash memory and sending the read comparison result to the detection controller.

Further, the control circuit judges the state of the target row by detecting the threshold voltages of two reference units of the flash memory so as to adaptively perform corresponding operations on the corresponding rows of the flash memory.

Further, the control circuit detects the threshold voltages of the two reference units, and judges the threshold range of the current row according to the comparison result of the detected threshold voltages and different reference thresholds, so as to obtain the state of the current row, and then judge the required operations of preprogramming, erasing, progressive erasing or programming.

Further, the threshold voltage detection module sequentially performs detection operations on the first reference threshold Vtp/the second reference threshold Vtpi/the third reference threshold Vte, obtains required threshold voltage Vt information, and returns to the top controller, which determines the required flash memory operation according to the threshold voltage Vt information and configures a timer) and the flash memory operation interface to implement corresponding pre-programming/erasing/programming operations on the flash memory.

Compared with the prior art, the self-adaptive Flash memory write-in operation control method and the self-adaptive Flash memory write-in operation control circuit judge the state of a target line by detecting the threshold voltage Vt of a Flash memory (Flash) reference unit, carry out self-adaptive write-in operation on the Flash memory (Flash), effectively prevent supersaturation failure caused by excessive erasure of a storage unit, simultaneously prevent Flash failure caused by insufficient erasure through a progressive erasure mechanism aiming at an insufficiently erased line, and improve the usability of the Flash.

Drawings

FIG. 1 is a flow chart illustrating steps of a method for controlling write operations of an adaptive flash memory according to the present invention;

FIG. 2 is a schematic diagram of a write operation control circuit of an adaptive flash memory according to the present invention;

FIG. 3 is a circuit diagram of a threshold voltage detection module according to an embodiment of the present invention;

FIG. 4 is a detailed block diagram of a timing module according to an embodiment of the present invention;

FIG. 5 is a detailed block diagram of an address configuration module according to an embodiment of the present invention;

FIG. 6 is a detailed block diagram of a clock generator according to an embodiment of the present invention.

Detailed Description

Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.

The on-chip detection method of the threshold voltage of the Flash unit is generally realized by adopting a voltage approximation detection mode (MarginMode), and the principle is that the switching characteristics of the SONOS unit and an NMOS pipe are utilized, when the external voltage Vvrg of a grid is larger than Vt, the unit is conducted with the current, the read value is 0, when the Vvrg is smaller than the Vt, the unit is turned off, the read value is 1, and therefore the Vt condition can be judged accurately by utilizing the critical value of the Vvrg. The present invention determines the range of Vt in this manner.

To characterize the state, the invention marks with a threshold voltage representative value, defined herein as the cell being written to the 1 state when Vt exceeds a positive voltage Vtp; when the Vt is less than Vte, the cell is said to be in the erased state, and when the Vt is less than Vtpi and greater than Vte, the cell is said to be in the written "0" state.

As can be seen from the foregoing, the threshold voltage Vt after Erase is determined by Erase time Δ T, and in normal operation, Erase time is a fixed value and is set to Δ T_oriThe corresponding threshold voltage Vt shift is set as Δ Vt_oriThen equation (1) can be equated with equation (2).

ΔVt_ori+ΔVt_diff∝V_erase(ΔT_ori+ΔT_diff) (2)

Wherein Δ Vt_diffAnd Δ T_diffSeparately identifying the variation of the threshold voltage Vt and the variation of the Erase (Erase) time。

By detecting the threshold voltage Vt, it can be seen that: when it is detected that Vt has become smaller than Erase monitor voltage, i.e. Δ Vt_diffIf the current cell is more than 0, the current cell has undergone Erase operation; when the threshold voltage Vt is detected to be still higher than Erase monitor voltage, i.e. Δ Vt_diffIf < 0, the current cell has not yet undergone Erase operation, then the Erase operation time Δ t needs to be increased_diff。

In conjunction with the programming effect on Vt, 2 data monitor points are set, writing only 0 and only 1, referred to as data 0 cells and data 1 cells, respectively. In different states, the Vt states of the two monitor points can be referenced as shown in Table 1:

TABLE 1 reference unit vt vs. State LUT

FIG. 1 is a flowchart illustrating steps of a method for controlling write operations of an adaptive flash memory according to the present invention. As shown in fig. 1, a method for controlling write operation of an adaptive flash memory according to the present invention includes:

in step 101, when a write operation is processed, the threshold voltages (Vt0/Vt1) of two reference cells are first sensed.

Step 102, determining whether the detected threshold voltages (Vt0/Vt1) of the two reference cells are both greater than a positive voltage first reference threshold Vtp, if so, indicating that the current row is pre-programmed (Preprogram), and going to step 103; if not, go to step 107;

step 103, erasing (Erase) the current row;

step 104, continuing to detect the threshold voltages (Vt0/Vt1) of the two reference cells once;

step 105, determining whether the detected threshold voltages (Vt0/Vt1) of the two reference cells are both smaller than a third reference threshold Vte, if yes, entering step 109, otherwise, entering step 106;

step 106, performing incremental erasing on the current row, and returning to step 104;

step 107, determining whether the detected threshold voltages (Vt0/Vt1) of the two reference cells are both smaller than a third reference threshold Vte, if yes, entering step 109, performing a programming operation, and if no, entering step 108;

step 108, judging whether the detected threshold voltages of the two reference units are both smaller than a second reference threshold Vtpi and larger than a third reference threshold Vte, if so, indicating that the erasing time is insufficient, and returning to step 106; otherwise, entering step 109, and performing pre-programming operation;

step 109, the current row is programmed or preprogrammed.

FIG. 2 is a schematic diagram of a write operation control circuit of an adaptive flash memory according to the present invention. As shown in fig. 2, the present invention provides an adaptive flash memory write operation control circuit, which includes: a top-level Controller (Controller)20, a timing module 21, an address configuration module 22, a threshold voltage detection module 23, a write operation module 24, and a clock generator 25.

Wherein, the top Controller (Controller)20 is responsible for global control and configuring other modules; a timing (Timer) module 21 is responsible for implementing timing functions; an Address configuration (Address IF) module 22 for configuring an Address of a Flash memory (Flash); a threshold voltage detection module 23, which detects the threshold voltage (Vt) in the configuration Flash (Flash) through a threshold detection interface (Margin-Read IF), realizes the Read operation of the Flash (Flash), judges the specific threshold voltage Vt condition of the reference memory cell by checking the Read data, and feeds back the result to the top Controller (Controller) 20; a Write-in Operation module 24, which sends a specific timing command to the Flash memory (Flash) through a Write-in Operation interface (Write-Operation IF) according to an instruction provided by the top Controller (Controller)20, and determines the specific Operation time of the Flash memory (Flash) according to a signal of the timing (Timer) module 21; the clock generator 25 issues a clock pulse to a Flash memory (Flash) according to the enablement of the threshold voltage detection block 23 and the write operation block 24. Table 2 is a description of each structural module in the specific embodiment of the present invention:

table 2 modular description

Fig. 3 is a circuit diagram of a threshold voltage detection module according to an embodiment of the invention. As shown in fig. 3, the threshold voltage detection module 23 includes: a detection controller (margin _ ctrl)231, an MDAC setting selector (MUX)232, a read clock enable signal (clk _ gen _ reg) generation unit 233, a Flash memory (Flash) output comparator (Do _ comp)234, a test mode register (Tm _ reg)235, and an MDAC setting register (MDAC _ reg)236, where the detection controller (margin _ ctrl)231 is responsible for controlling internal state machine switching of threshold voltage Vt detection, controlling a clock of threshold voltage Vt read operation, setting an enable signal Tm _ conf and a threshold configuration MDAC of a threshold read circuit module (margin read) of a threshold voltage Vt corresponding to the Flash memory (Flash), determination of a Flash read comparison result, and the like; the MDAC setting selector (MUX)232 selects an MDAC value corresponding to the threshold voltage Vt to be detected by the enable signal Msel [1:0] of the detection controller (margin _ ctrl)231 and stores the MDAC value in an MDAC setting register (MDAC _ reg) 236; after the MDAC value is set, the detection controller (margin _ ctrl)231 instructs the Clock generator (Clock _ IF) to generate a Flash read Clock pulse by the read Clock enable signal clk _ gen _ reg generated by the read Clock enable signal clk _ gen _ reg generation unit 233.

The logic of the Margin Read design is illustrated by taking the operation logic for reading the positive threshold voltage Vtp as an example, and is shown in the following table. And the MDAC is a configuration signal for detecting Vt by the Flash, and the Flash is enabled to enter a threshold voltage Vt detection mode by configuring the MDAC to a value corresponding to the Vtp. By reading, a reading result is obtained by outputting data DOUT through Flash. When the read value is 00, it indicates that the Vt of both reference cells is less than Vtp, so Vtpi continues to be detected; when the read value is 11, which indicates that Vt of both reference cells is greater than Vtp, the Vt configuration information is set to Vtp _ DAC +1, so as to ensure that the Controller (Controller) can obtain the corresponding logic result; similarly, when the read value is 10 or 01, the known cell VT is configured as VTP _ DAC +1, respectively, while the corresponding VTPI result continues to be detected.

The threshold reading circuit module (margin read) sequentially executes the detection operation of Vtp/Vtpi/Vte, obtains the required threshold voltage Vt information, and returns to the Controller. And the Controller (Controller) judges the required Flash operation according to the Vt information, and configures a Timer (Timer) and a Flash operation interface to realize the operation of the corresponding Preprogram/Erase/Program and the like of the Flash. The logic code for Margin Read Vtp is shown in Table 3 below:

TABLE 1 Margin Read vtp logic

Table 4 is a logical pseudo-code representation of a controller in an embodiment of the present invention, where curr _ operator represents the current operation. And performing Vt detection before the current row is operated each time, and judging the next operation according to the Vt result. When the Program operation is completed, the write operation is ended.

TABLE 4 control pseudo code of the controller

Fig. 4 is a detailed structure diagram of the timing module according to an embodiment of the present invention, in which a clock configuration signal Timer config under different operations is transmitted to the internal configuration queue FIFO through the multiplexer, and is transmitted to the Counter register Counter _ reg according to the operation, and a timing end signal is output to the write operation module when the count-down is ended until the Counter _ reg is equal to 0.

Fig. 5 is a detailed structure diagram of an address configuration module according to an embodiment of the present invention. Wherein Conf _ sel is an internal multiplexer selection signal for controlling whether the address Ca is derived from the reference cell address or the external normal read operation address, and transmitting to the flash memory circuit

Fig. 6 is a detailed structure diagram of the clock generator according to an embodiment of the present invention, when the external clock is input, the inverted clock is obtained through the inverter, and when the read threshold operation enable signal clk _ en _ read or the flash memory control operation clk _ en _ operator enable signal is enabled, the inverted clock is transmitted to the flash memory through the and gate to trigger the specific operation.

In summary, the adaptive Flash write operation control method and circuit of the present invention determine the target row state by detecting the threshold voltage Vt of the Flash reference cell, perform adaptive write operation on the Flash, effectively prevent oversaturation failure caused by over-erase of the memory cell, and simultaneously prevent Flash failure due to under-erase by a progressive erase mechanism for an under-erase row, thereby improving the usability of Flash.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.

Claims

1. A self-adaptive flash memory write operation control method comprises the following steps:

step two, comparing the detected threshold voltage with different reference thresholds, judging the threshold range of the current row according to the comparison result, thereby obtaining the state of the current row, and then judging the corresponding operations of preprogramming, erasing, progressive erasing or programming;

wherein the second step further comprises:

step S2, erasing the current row;

step S5, the current row is programmed or preprogrammed.

2. The adaptive flash memory write operation control method of claim 1, wherein: in step S1, if the determination result is negative, it is determined whether the detected threshold voltages of the two reference cells are both smaller than the third reference threshold Vte, if so, the process proceeds to step S5 to perform a programming operation, if not, it is determined whether the detected threshold voltages of the two reference cells are both smaller than the second reference threshold Vtpi and larger than the third reference threshold Vte, if so, the current row is incrementally erased, and the process returns to step S3, and if not, the process proceeds to step S5 to perform a pre-programming operation.

3. The adaptive flash write operation control method of claim 2, wherein: if the determination result in step S4 is negative, the current row is incrementally erased, and the process returns to step S3.

4. The adaptive flash write operation control method of claim 3, wherein: the first reference threshold is greater than the second reference threshold and greater than the third reference threshold.

5. An adaptive flash write control circuit, comprising:

the timing module is responsible for realizing a timing function;

the clock generator sends clock pulses to the flash memory according to the enabling signals of the threshold voltage detection module and the write-in operation module;

wherein, this threshold voltage detection module includes:

a read clock enable signal generating unit for generating an enable signal clk _ gen _ reg to make the clock generator generate a flash memory read clock pulse;

6. The adaptive flash write control circuit of claim 5, wherein: the control circuit judges the state of the target row by detecting the threshold voltages of two reference units of the flash memory so as to adaptively perform corresponding operation on the corresponding row of the flash memory.

7. The adaptive flash write control circuit of claim 6, wherein: the control circuit detects the threshold voltages of the two reference units, judges the threshold range of the current row according to the comparison result of the detected threshold voltages and different reference thresholds, thereby obtaining the state of the current row and then judging the operations of preprogramming, erasing, gradual erasing or programming.

8. The adaptive flash write control circuit of claim 6, wherein: the threshold voltage detection module sequentially executes detection operations on a first reference threshold Vtp/a second reference threshold Vtpi/a third reference threshold Vte, obtains required threshold voltage Vt information, returns to the top layer controller, judges required flash memory operations according to the threshold voltage Vt information, and configures a timer and a flash memory operation interface to realize corresponding pre-programming/erasing/programming operations on the flash memory.