KR101750077B1 - Non-volatile Memory Apparatus and Determining Method of Read Bias Therefor - Google Patents

Abstract

A voltage supply unit for generating an operating voltage according to an operation mode and providing the memory cell array with a memory cell array, and a voltage supply unit for increasing the read bias to a first offset value until the error bit number after the read operation satisfies a predetermined first threshold value, And a read bias setting unit for increasing the read bias to a second offset value and providing the read bias to the voltage supply unit when the number of error bits after the read operation satisfies a predetermined first threshold value and a read bias setting for the nonvolatile memory device We suggest a method.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a nonvolatile memory device and a read bias setting method therefor,

The present invention relates to a semiconductor device, and more particularly, to a nonvolatile memory device and a method of setting a read bias for the same.

A nonvolatile memory device represented by a flash memory device has been inverted from a single level cell to a multi level cell.

In a flash memory device, a program is page-wise, and in a flash memory device composed of multi-level cells, the threshold voltages of memory cells included in each page are programmed to be equal to or higher than a predetermined verification voltage. Further, when reading data stored in the memory cell, the read voltage is determined by the verify voltage used in programming the page to which the cell belongs.

However, in the flash memory device, the charge injected into the floating gate may leak due to the influence of the surrounding environment, for example, the temperature. If the charge of the floating gate leaks, the threshold voltage fluctuates. Therefore, when data is read by applying a predetermined read bias, an error may occur.

Accordingly, a read bias setting method adaptable to a threshold voltage variation of a memory cell has been proposed.

1 is a diagram for explaining a general read bias setting method for a nonvolatile memory device.

The read bias setting method for the memory cells having the state ST1 programmed by the specific verify voltage will be described as an example.

In order to set the read bias for the memory cells having the state ST1, the initial read bias Vint is applied to read the data of the memory cells belonging to the state ST1. Then, the result of reading is compared with the expected data to check the number of error bits.

If the number of error bits is larger than the preset number of bits, the read bias is increased by a predetermined offset value (? V), and cell data readout, comparison with predicted data, and error bit number check process are repeated.

Also in this case, when the number of error bits is larger than the preset number of bits, the process repeats the process of increasing the read bias by a predetermined offset value (? V) and checking the number of error bits. Then, the voltage when the number of error bits becomes equal to or less than a predetermined number of bits is determined as the read bias Vdtm.

As described above, a method of increasing the read bias from the initial bias Vint by a preset offset value? V is used for determining the read bias, and the offset value? V is set to a fixed value.

The offset value? V is generally set to 40 mV. Considering that the difference between the finally determined lead bias Vdtm and the initial bias Vint is 200 to 300 mV, the range of the offset value? V is somewhat You can see a wide range.

Therefore, the accuracy of the read bias is lowered, which may cause malfunction of the memory device. To solve this problem, it is possible to determine the offset value to be small. However, as the offset value becomes smaller, it takes much time to set the read bias.

The present invention provides a nonvolatile memory device capable of precisely controlling a read bias and a lead bias setting method therefor.

Another aspect of the present invention is to provide a nonvolatile memory device capable of detecting a more accurate lead bias while shortening a time required for setting a read bias, and a method of setting a read bias for the nonvolatile memory device.

According to an aspect of the present invention, there is provided a nonvolatile memory device including: a memory cell array; A voltage supplier for generating an operating voltage according to an operating mode and providing the operating voltage to the memory cell array; And providing the read bias to the voltage supply unit until the error bit number after the read operation satisfies a predetermined first threshold value and providing the read bias to the voltage supply unit when the error bit number after the read operation satisfies the predetermined first threshold value, And a read bias setting unit for increasing the bias to a second offset value and providing the bias to the voltage supply unit.

According to another aspect of the present invention, there is provided a read bias setting method including: a first read step of applying a first read bias to perform a read operation; A first determination step of comparing the read result with the expected data to check the number of error bits; Increasing the read bias by a first offset value when the number of error bits is greater than a predetermined first threshold value, performing a read operation and proceeding to the first determination step; And a second read step of increasing the read bias by a second offset value when the number of error bits is less than or equal to a predetermined first threshold value, thereby performing a read operation.

According to the present invention, if a predetermined number of error bits are detected by increasing the read bias to a first offset value, the read bias is increased by increasing the read bias to a second offset smaller than the first offset.

That is, the read bias can be determined more precisely by increasing the read bias to a large extent with respect to the initial read bias and reducing the read bias increase range when approaching the substantial read bias. Therefore, the reliability of the nonvolatile memory device can be improved.

In addition, since the initial increase width of the read bias is set to be large, the read bias can be detected at a high speed, and the operation performance of the nonvolatile memory device can be improved.

1 is a diagram for explaining a general read bias setting method of a nonvolatile memory device,
2 is a configuration diagram of a nonvolatile memory device according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a read bias setting method according to an embodiment of the present invention. FIG.
4 is a conceptual diagram for explaining a read bias setting method according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described more specifically with reference to the accompanying drawings.

2 is a configuration diagram of a nonvolatile memory device according to an embodiment of the present invention.

2, the nonvolatile memory device 10 includes a controller 160 for controlling the overall operation, a memory cell array 110, a page buffer unit 120, a Y decoder 130, an X decoder 140 A voltage supply unit 150, and a read bias setting unit 170.

In the memory cell array 110, a plurality of memory cells for storing data, for example, a word line WL for selecting and activating a memory cell and a bit line BL for inputting / outputting data of the memory cell, Respectively.

The page buffer unit 120 may include a plurality of page buffers connected to the memory cell array 110 through bit lines BL to provide program data to selected memory cells of the memory cell array 110, And reads and stores data from the selected memory cell of the array 110. [

Y decoder 130 provides a data input / output path to page buffers of the page buffer unit 120 under the control of the controller 160. The X decoder 140 controls the page buffers of the page buffer unit 120 according to the control of the controller 160, The word line WL of the word line WL is selected.

The voltage supply unit 150 generates an operation voltage corresponding to an operation mode (program, erase, read) under the control of the controller 160 and outputs the generated operation voltage to the word line WL or page And supplies it to the buffer unit 120.

The read bias setting unit 170 determines a bias to be supplied to the selected word line of the memory cell array 110 in the read operation. More specifically, the read bias setting unit 170 increases the read bias from the initial read bias to the voltage supply unit 150 by a first offset value, and performs a read operation under the control of the controller 160. In addition, the read bias setting unit 170 receives the result of performing the read operation according to the read bias increased by the first offset value, and when the error bit number is less than the predetermined first threshold value, 2 Change to the offset value. In addition, the read bias increased by the second offset value is supplied to the voltage supplier 150 so that the read operation is performed under the control of the controller 160. The read bias setting unit 170 receives the result of performing the read operation according to the read bias increased by the second offset value, and when the number of error bits is less than a predetermined second threshold value, And determines it as the final read bias and provides it to the voltage supplier 150.

FIG. 3 is a flow chart for explaining a read bias setting method according to an embodiment of the present invention, and FIG. 4 is a conceptual diagram for explaining a lead bias setting method according to an embodiment of the present invention.

Referring to FIGS. 3 and 4, a predetermined initial read bias Vint is applied to determine a read bias (S10), and a read operation is performed on the memory cells connected to the selected word line (S20).

The read result is compared with the expected data to check the number of error bits (S30). If it is determined in step S30 that the number of error bits is larger than the predetermined first threshold value N1, the read bias setting unit 170 increases the read bias by a predetermined first offset value? V1 and then performs a read operation The process proceeds to step S20.

If the error bit number is equal to or less than the predetermined first threshold value N1 as a result of the determination in step S30, the read bias setting unit 170 sets the read bias Va at that time to the lead bias (S50) and performs the read operation (S60).

Then, the read result is compared with the expected data to check the number of error bits (S70). If it is determined in step S70 that the number of error bits is larger than the predetermined second threshold value N2, the process proceeds to step S50 where the read bias is increased by the second offset value? V2. If not, that is, if the number of error bits is equal to or less than the predetermined second threshold value N2, the read bias at that time is determined as the final read bias Vdtm (S80).

As described above, according to the present invention, the read bias is increased by the first offset value? V1 until the error bit number becomes larger than the predetermined first threshold value N1, and the error bit number is increased by the predetermined first threshold value N1, The read bias is increased by the second offset value? V2. Then, when the read bias is increased by the second offset value? V2 and the number of error bits becomes equal to or less than the predetermined second threshold value N2, the bias at that time is determined as the final read bias.

In one embodiment of the present invention, the first offset value? V1 may be set to 50 to 70 mV, and the second offset value? V2 may be set to 10 to 30 mV.

Therefore, if the read bias is increased to a large extent with respect to the initial read bias and approaches the substantial read bias, the read bias increase width is reduced and the read bias is determined more precisely. Accordingly, not only the read bias can be set at a high speed, but also a precise read bias can be applied according to the state of the memory cell, thereby improving the operational reliability of the nonvolatile memory device.

Thus, those skilled in the art will appreciate that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

10: nonvolatile memory device
110: memory cell array
120:
130: Y decoder
140: X decoder
150:
160: Controller
170: Read bias setting unit

Claims (6)

A memory cell array;
A voltage supplier for generating an operating voltage according to an operating mode and providing the operating voltage to the memory cell array; And
The read bias is increased by the first offset value until the error bit number after the read operation satisfies the predetermined first threshold value and supplied to the voltage supply unit so as to be supplied to the memory cell array, A read bias setting unit for increasing the read bias by a second offset value and providing the read bias to the voltage supply unit and supplying the read voltage to the memory cell array;
Volatile memory device. [Claim 2 is abandoned upon payment of the registration fee.] The method according to claim 1,
Wherein the read bias setting unit determines the bias at the time point as a read bias when the number of error bits after the read operation satisfies a predetermined second threshold value and provides the read bias to the voltage supply unit. [Claim 3 is abandoned upon payment of the registration fee.] The method according to claim 1,
Wherein the first offset value is set to a value larger than the second offset value. A first read step of applying an initial read bias to the memory cell array to perform a read operation for the memory cell array;
A first determination step of comparing the read result with the expected data to check the number of error bits;
Increasing the read bias by a first offset value when the number of error bits is larger than a predetermined first threshold value, performing a read operation for the memory cell array, and proceeding to the first determination step; And
A second read step of increasing a read bias by a second offset value and performing a read operation for the memory cell array when the number of error bits is less than the first threshold value;
And setting a read bias. [Claim 5 is abandoned upon payment of registration fee.] 5. The method of claim 4,
A second determination step of comparing the read result with the expected data after the second read step to check the number of error bits;
If the number of error bits according to the second determination step is greater than a predetermined second threshold value, proceeding to a second read step; And
Determining a bias at the time point as a final read bias when the number of error bits according to the second determination step is less than or equal to the second threshold value;
And setting a read bias. [Claim 6 is abandoned due to the registration fee.] The method according to claim 4 or 5,
Wherein the first offset value is set to a value larger than the second offset value.

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