JP2013125575A - Nonvolatile semiconductor storage device, and operation condition control method in nonvolatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which can detect deterioration states of characteristics of memory cells for individual blocks of a flash memory, and can set an operation condition of the flash memory according to the deterioration states of the individual blocks.SOLUTION: A nonvolatile semiconductor storage device 1 includes monitoring erase time (tERS) of individual blocks in a flash memory 20, storing a block address of the block when the erase time (tERS) exceeds a determination reference value, and changing an operation condition of the flash memory 20 to a predetermined operation condition when the block is accessed.

Description

  The present invention relates to a nonvolatile semiconductor memory device including a flash memory, and an operation condition control method in the nonvolatile semiconductor memory device.

There is a related nonvolatile semiconductor memory device (see Patent Document 1). The nonvolatile semiconductor memory device described in Patent Document 1 can perform optimum erasure according to the number of write and erase operations, and can suppress an increase in erase time as the number of erase times increases. The purpose is to provide.
In the nonvolatile semiconductor memory device described in Patent Document 1, the number of erase operations performed in the past is stored in the erase number storage unit, and the readout time is controlled by the readout time setting circuit according to the number of erases. The read time can be set based on the number of erases.

  There is also a related nonvolatile semiconductor memory device (see Patent Document 2). An object of the nonvolatile semiconductor memory device described in Patent Document 2 is to provide a nonvolatile semiconductor memory device having a built-in function for managing the number of times of data erasing for each sub-block. In this nonvolatile semiconductor memory device, each sub-block of the cell array stores the number of data erasures updated every time the sub-block data is erased, and the maximum allowable number of data erasures stored in a predetermined block of the cell array is referred to. Thus, the number of data erases is limited for each sub-block.

  There is also a method for managing data on a related storage medium (see Patent Document 3). In the method for data management described in Patent Document 3, when the first block is to be erased, it is determined whether the consumption level of the first block is acceptable for erasing. If acceptable, the data on the first block is erased. Otherwise, a second block having a lower wear level than the first block is selected, and the data in the second block is copied to the first block. Each block has an associated counter that monitors the number of times it has been erased. Since blocks that have hardly been erased in the past are unlikely to be erased in the future, the first block is not erased very often, thus extending its lifetime. The second block can be used to store new data and is used more frequently.

  There is also a related terminal device (see Patent Document 4). The terminal device described in Patent Document 4 can prevent rewriting from being concentrated on a specific area on the NAND flash memory, and can distribute the rewriting frequency over the entire NAND flash memory. An object of the present invention is to provide a terminal device that can reduce the number of times of block rewriting as much as possible and improve the processing speed related to product data rewriting.

  There is also a related nonvolatile semiconductor memory device (see Patent Document 5). An object of the nonvolatile semiconductor memory device described in Patent Document 5 is to reduce unnecessary verification and shorten the total writing time in the nonvolatile semiconductor memory device of multi-value storage.

Japanese Patent No. 394649 JP 2005-122800 A Special table 2003-532222 gazette JP 2002-32256 A JP 2000-163976 A

  In the NAND flash memory, when cycling such as programming and erasing operations is repeated, the oxide film of the memory cell deteriorates, a charge trap is generated in the oxide film, and the distribution of the threshold value Vt of the programmed cell tends to widen. is there. For example, FIG. 10 is a diagram showing a distribution of threshold level Vt of SLC (Single Level Cell), FIG. 10A shows a distribution of threshold value Vt before cycling, and FIG. The distribution of the threshold value Vt is shown. In this figure, Vpgmv indicates the voltage applied to the word line at the time of program verification, and Vread indicates the voltage of the unselected word line at the time of reading. As shown in this figure, by repeating the cycling, the distribution range of the threshold value Vt after the cycling is expanded as compared with that before the cycling.

  When the distribution of the threshold value Vt of the programmed cell is widened, the following problem may occur. For example, when the NAND flash memory is SLC, there is a possibility that a column read failure due to over programming (Over Programming) may occur, and in the case of MLC (Multiple Level Cell), each of a plurality of threshold values Vt May cause a read failure due to overlapping with the adjacent state. These are serious problems in the reliability of the NAND flash memory.

  Conventionally, in order to avoid such a problem, for example, the ECC (Error Checking and Correction) function is expanded, and the number of cycles of each block (the number of times of execution of program and erase operations) is averaged as much as possible. Therefore, there is a method of managing the average cycling number of the whole NAND flash memory and changing the operating condition of the NAND flash memory according to the average cycling number.

  However, when the ECC is expanded, a memory area for storing ECC information is required, which increases the chip area of the NAND flash memory. In addition, since processing for calculating the ECC is required for reading and writing data, a burden is imposed on the system side. In addition, when averaging the number of cycles of each block, a large number of registers (registers that hold the number of cycles for each block) are required on the system side, which is also a burden. In addition, when changing the operating conditions of the NAND flash memory depending on the number of cycles, the operating conditions are managed based on the number of cycling times of the entire NAND flash memory. The condition is applied, and there is a drawback that the performance of the NAND flash memory is reduced.

  The present invention has been made in view of such circumstances, and an object of the present invention is to change the operating conditions of the flash memory according to the deterioration state of the characteristics of the memory cell for each block of the flash memory. It is an object of the present invention to provide a nonvolatile semiconductor memory device and an operation condition control method for the nonvolatile semiconductor memory device that can be set in accordance with the above.

  The present invention has been made in order to solve the above-described problems. The nonvolatile semiconductor memory device of the present invention has a memory in the block from the start of erasing when performing an erase operation on the block in the flash memory. A function for measuring the erase time until the erase of the cell is completed, a function for comparing the erase time with a predetermined criterion value, and when the erase time exceeds the criterion value in the block, And a function of accessing the block by changing the operating condition of the flash memory to a predetermined operating condition.

In the nonvolatile semiconductor memory device of the present invention, the erase time in the block to be erased is determined (measured), and when this erase time exceeds the determination reference value, the next time the block is accessed, The operating condition of the flash memory is changed to a predetermined operating condition.
As a result, the deterioration state of the characteristics of the memory cell can be detected for each individual block of the flash memory, and the operation condition corresponding to this characteristic deterioration can be set for the flash memory for each individual block. For this reason, the reliability of the flash memory can be improved.

1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. 1 is a diagram showing a configuration of a NAND flash memory. It is a figure which shows the structure of a memory cell array. It is a figure which shows the change characteristic of program time tPROG with respect to cycling frequency, and erase time tERS. It is a figure which shows the change of the operating condition in flash memory, and the change of program time tPROG. It is a figure which shows the example of a condition table. It is a block diagram which shows the structure of the non-volatile semiconductor memory device concerning 2nd Embodiment of this invention. It is a figure which shows the structure of the NAND type flash memory in 2nd Embodiment. It is a figure which shows the example of the condition table in 2nd Embodiment. It is a figure which shows distribution of the threshold value Vt of SLC.

Embodiments of the present invention will be described below with reference to the accompanying drawings.
[Overview]
In the nonvolatile semiconductor memory device of this embodiment, the erase time is monitored not for the number of cycles but for each block (a block that becomes a unit for accessing (eg, programming) the memory cell array). The block address when the value exceeds the criterion value is stored, and the operating condition of the NAND flash memory is changed when the block is next accessed.

  That is, in the NAND flash memory, a charge trap is generated due to deterioration of the oxide film of the memory cell due to repeated cycling, and electrons are captured in the charge trap, so that the programming time of the memory cell is increased. (Easier to program) On the contrary, the erase time becomes longer (it becomes difficult to erase).

  Therefore, in the nonvolatile semiconductor memory device, when the erase time exceeds the determination reference value in the block to be erased, the block address is stored, and when the block address is accessed next time, a new predetermined operation condition is applied. Request for NAND flash memory. The operating conditions are, for example, operating conditions for program / program verify / read / erase (Program / Program Verify / Read / Erase). The erase time determination reference value is updated (increased) every time the operating condition of the NAND flash memory is changed.

[First Embodiment]
(Configuration of nonvolatile semiconductor memory device)
FIG. 1 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to the first embodiment of the present invention. A non-volatile semiconductor memory device 1 shown in FIG. 1 is a non-volatile semiconductor memory device having a NAND flash memory (also simply referred to as “flash memory” in this specification) 20, and only a portion directly related to the present invention is included. It is shown. As shown in FIG. 1, the nonvolatile semiconductor memory device 1 of the present embodiment includes a NAND flash memory 20 in which memory cells are arranged in an array, and a controller 10 that controls the flash memory 20. Configured. The NAND flash memory 20 has a memory cell array 21 in which memory cells are arranged in an array.

  The controller 10 issues a command such as a program execution command to a block in the NAND flash memory 20 (a block serving as a unit for accessing the memory cell array 21 in the flash memory 20), and at the same time, the flash memory 20 A command (operation condition change setting command CMD) for setting the operation condition is issued. The NAND flash memory 20 sets operating conditions such as a program voltage and a read voltage according to the operating condition change setting information included in the command CMD input from the controller 10. The NAND flash memory 20 outputs a signal of a flag F_ERS (erase completion information) described later to the controller 10.

  Based on the flag F_ERS input from the flash memory 20, the controller 10 causes the erase time (tERS) determination unit 13 to measure the time tERS from the start of erase in the block to be erased until the flag F_ERS is output, It is determined whether the time tERS exceeds a predetermined determination reference value (for example, 3 ms).

  When the erase time determination unit 13 determines that the time tERS in the block to be erased exceeds a predetermined determination reference value (for example, 3 ms), the block address storage unit 12 The number of times the time tERS has been exceeded in the block is stored.

  In the nonvolatile semiconductor memory device 1 configured as described above, when accessing a block in the NAND flash memory 20, the controller 10 first refers to the block address storage unit 12 and the condition table 11. In the condition table 11, as will be described later, the determination reference value of the erase time tERS, the number of times the erase time tERS exceeded the determination reference value (the number of corrections), and the number of times that exceeded this time The operation conditions of the flash memory 20 to be applied to the block in the operation are stored in association with each other (see FIG. 6). When the block address of the block is stored in the block address storage unit 12, the controller 10 obtains the number of times (the number of times that the time tERS has exceeded the determination reference value) and the corresponding operation condition from the condition table 11. read out. The controller 10 sets the operation condition read from the condition table 11 to the NAND flash memory 20, and then performs a desired operation (read / program / erase).

  The NAND flash memory 20 has a function capable of changing the operation condition in accordance with the operation condition change setting command (operation condition change setting command CMD) requested from the controller 10. As an example of changing the operating condition, for example, the flash memory 20 changes (lowers) the start voltage (Vipgm) of program stress (Program stress). In addition, for example, the flash memory 20 changes the voltage step width (Vstep) in an incremental step pulse-program (ISPP) cycle in which programming is performed while increasing the gate voltage of the memory cell by a constant voltage Vstep ( Make it smaller). Thereby, in the flash memory 20, the program speed is suppressed and overwriting (overprogramming) is prevented.

  Alternatively, the flash memory 20 changes (increases) the voltage (Vread) of the unselected word line at the time of reading. Accordingly, the flash memory 20 can have a margin (margin) so that data can be normally read when data is read from the memory cell even if the memory cell is overwritten somewhat. Alternatively, the flash memory 20 changes (increases) the voltage (Vsel) of the selected word line during program verification. If the memory cell is cycled, it becomes easier to program, but at the same time, the charge retention characteristics deteriorate. Therefore, the flash memory 20 changes (increases) the voltage (Vsel) of the selected word line at the time of program verification. Thus, a margin can be provided so that data can be read normally.

  FIG. 2 is a diagram showing a configuration of the NAND flash memory 20, and shows a portion related to the present invention. As shown in FIG. 2, the NAND flash memory 20 includes a memory cell array 21, a page buffer 22 including a page buffer decoder 22A, and a row decoder 23. The NAND flash memory 20 includes a memory control circuit 31 that controls the overall operation of the NAND flash memory 20, an operating condition change setting unit 32, an output data buffer 33, and an input data buffer 34. , A flag generation unit 35, an erase completion detection unit 36, and an operating voltage controller 37.

  In the NAND flash memory 20 configured as described above, the memory cell array 21 includes a plurality of blocks shown in FIG. As shown in FIG. 3, each block includes N + 1 bit lines BL0 to BLN (generically referred to as bit line BL), n + 1 word lines WL0 to WLn (generically referred to as word line WL), a common source line CSL, , N + 1 memory strings ST0 to STN (collectively referred to as memory string ST) connected between each bit line BL and the common source line CSL. Each memory string ST includes n + 1 number of electrically rewritable nonvolatile memory cells MC0 to MCn having a floating gate structure connected in series with each other, and the memory cell MCn on the drain side corresponds via a selection gate transistor SS1. The memory cell MC0 on the source side connected to the bit line BL is connected to the common source line CSL via the selection gate transistor GS1. The control gates of the memory cells in the same row are connected to a common word line WL.

  In the block shown in FIG. 3, erasing of the memory cell is performed, for example, by applying a high voltage to the semiconductor substrate and applying 0 V to the word lines WL0 to WLn. As a result, electrons are extracted from the floating gate, which is a charge storage layer made of polysilicon, for example, and the threshold voltage of the memory cell MC is set to the erase threshold voltage VtL (for example, −1 V). On the other hand, in writing (programming), for example, by applying 0 V to the source and drain and applying a high voltage to the control gate (selected word line WL), electrons are injected into the floating gate to raise the threshold voltage. To set the write threshold voltage VtH. When the threshold voltage of the memory cells MC0 to MCn is the threshold voltage VtL, the data value of the memory cell is “1”, and when the threshold voltage is the threshold voltage VtH, the data value of the memory cell is “0”. .

  When data is read from the memory cell, all the bit lines BL are precharged with a predetermined voltage, and then the read voltage between the thresholds VtL and VtH is set to the word line WL commonly connected to the memory cell MC to be read. And applied to each control gate of the selected memory cell. Further, a high voltage is applied to the control gates of the memory cells MC other than the selected memory cell and the selection transistors SS1 and GS1, and the memory cells MC other than the selected memory cell and the selection gate transistors SS1 and GS1 are turned on. Accordingly, when the data value of the selected memory cell is “1”, a cell current flows through the selected memory cell, whereas when the data value of the selected memory cell is “0”, no cell current flows through the selected memory cell. The data written in each selected memory cell can be read based on whether the cell current flows.

  In the NAND flash memory 20 shown in FIG. 2, the operation condition change setting unit 32 operates according to the operation condition instructed by the command (operation condition change setting command) CMD input from the controller 10. Set. The output data buffer 33 is a buffer circuit for externally outputting data read from the memory cell array 21, and outputs data to data input / output lines (I / Os) serving as connection lines with external devices. The input data buffer 34 is a buffer circuit that is also connected to data input / output lines (I / Os) and used for inputting data from an external device, inputting an address signal, and inputting an operation control command.

  The erase completion detection unit 36 flags information (erase completion information) indicating that the erase of this block is completed when all the memory cells in this block are erased in the erase operation in the block to be erased. Output to the generator 35. When the erase completion information is input from the erase completion detection unit 36, the flag generation unit 35 generates a flag F_ERS indicating that the erase has been completed in the block to be erased, and outputs the flag F_ERS to the controller 10.

  The operating voltage controller 37 generates a boosted high voltage or intermediate voltage used during operations such as data rewriting (programming), erasing (erasing), and reading (reading). The voltage signal generated by the operating voltage controller 37 is output to the row decoder 23 and the page buffer 22 as signals Vread, Vpgm, Vers, and the like. The operation of the voltage signal generation in the operation voltage controller 37 is performed by the memory control circuit 31 and the operation condition change setting unit in accordance with data read (read), rewrite (program), erase (erase) operation, etc. from the memory cell MC. This is carried out based on the control command output from 32.

[Description of Operation of Nonvolatile Semiconductor Memory Device of this Embodiment]
As described above, in the NAND flash memory 20, the charge trap is generated in the oxide film of the memory cell by repeating the cycling, and the programming time of the memory cell is shortened (programming becomes easy). On the other hand, the erase time becomes longer (it becomes difficult to erase).

  Therefore, the nonvolatile semiconductor memory device 1 measures the erase time tERS in the block to be erased, stores the block address when the erase time tERS exceeds the determination reference value, and accesses the block address from the next time. When doing so, the NAND flash memory 20 is requested to apply a new operating condition. The operating conditions are, for example, operating conditions for program / program verify / read / erase (Program / Program Verify / Read / Erase). The erase time tERS is defined as the time from the start of erase in the block to be erased until the flag F_ERS is output.

  FIG. 4 is a diagram showing the change characteristics of the program time tPROG and the erase time tERS with respect to the number of cyclings. In FIG. 4, the horizontal axis represents the number of cycling (log scale), and the vertical axis represents time. In addition, the time shown on the vertical axis represents A.D. according to the respective characteristic curves of tPROG and tERS. U. (arbitrary unit).

  As shown in FIG. 4, each of the program time tPROG and the erase time tERS changes substantially constant between the number of cycling times 0 and N1. After the cycling number N1, the flash memory 20 is repeatedly cycled to generate a charge trap in the oxide film of the memory cell, and the programming time tPROG of the memory cell becomes shorter (easier to program). On the contrary, the erase time tERS becomes longer (it becomes difficult to erase).

  When the time tERS becomes longer and exceeds the determination reference value (reference value 1) (when the number of times of cycling is N2), the controller 10 issues a command CMD to the flash memory 20, and the operation conditions in the flash memory 20 are changed. change. The reference value 2 will be described with reference to FIG.

FIG. 5 is a diagram showing changes in operating conditions and changes in program time tPROG in the flash memory. In FIG. 5, as in FIG. 4, the horizontal axis indicates the number of cycles (log scale), and the vertical axis indicates time (AU).
As shown in FIG. 5, each of the program time tPROG and the erase time tERS changes substantially constant between the number of cycling times 0 and N1. Then, after the number of cycles N1, in the flash memory 20, by cycling, a charge trap is generated in the oxide film of the memory cell, and the programming time tPROG of the memory cell is shortened (programming becomes easier). Conversely, the erase time tERS becomes longer.

  When the time tERS becomes longer and exceeds the determination reference value (reference value 1) at the number of times of cycling N2, the controller 10 issues a command CMD to the flash memory 20 and changes the operating condition in the flash memory 20. . Further, the controller 10 updates the determination reference value from the reference value 1 to the reference value 2 (reference value 2> reference value 1). Then, by changing the operating condition in the flash memory 20, the program time tPROG is temporarily restored to the original time (time of tPROG equal to or less than the cycling count N1).

  After changing the operating condition at the number of times of cycling N2, by further repeating the number of times of cycling, the program time tPROG of the memory cell is gradually shortened and the erase time tERS is further lengthened. When the time tERS becomes longer and exceeds the determination reference value (reference value 2) at the number of times of cycling N3, the controller 10 issues a command CMD to the flash memory 20 and changes the operating condition in the flash memory 20 again. To do. Then, by changing the operating condition in the flash memory 20, the program time tPROG returns to the original time. As described above, the controller 10 monitors the flag F_ERS output from the NAND flash memory 20 and operates in the NAND flash memory 20 every time the erase time tERS exceeds the determination reference value (the determination reference value to be updated). Change the condition.

  In order to change the operation condition in the flash memory 20, the condition table 11 in the controller 10 includes a determination reference value for the time tERS, the number of times the erase time tERS exceeds the determination reference value (the number of corrections), and this The operation conditions of the flash memory 20 to be applied to the block in the next operation corresponding to the number of times stored are associated and stored.

  FIG. 6 is a diagram illustrating an example of the condition table. The table shown in FIG. 6 shows the determination reference value, the number of corrections (the number of times the erase time tERS has exceeded the determination reference value), and the operating conditions of the NAND flash memory 20 corresponding to this correction number (when reading, programming Operating conditions at the time of program, verify program, and erase). In this table, the voltage Vread at the time of reading indicates the initial voltage of the non-selected word line at the time of reading, and the voltage Vipgm at the time of programming indicates the initial voltage at the time of programming. The voltage Vpass at the time of program verification indicates the initial voltage of the non-selected word line at the time of program verification, and the voltage Vsel indicates the initial voltage of the selected word line. The voltage Vers at the time of erasing indicates the erase voltage (initial voltage) at the time of erasing the memory cell.

  As shown in FIG. 6, when the erase time tERS is longer than the first determination reference time (3 ms) (when the number of times of cycling N2 shown in FIG. 5), the first operating condition is corrected. . In the first correction, the voltage Vread of the unselected word line at the time of reading is increased by 0.1 V from the initial voltage Vread to Vread1 (Vread1 = Vread + 0.1V). This is because the oxide film of the flash memory is deteriorated, so that the program speed is increased (the program voltage is decreased), and the memory cell may be overprogrammed (the threshold value Vt is increased). The voltage Vread of the line is raised to cope with it.

  In the first correction, the initial voltage Vipgm at the time of programming is decreased by 1.0 V from the initial voltage Vipgm to be Vipgm1 (Vippm1 = Vippm−1.0 V). This is done by lowering the program voltage Vipgm to prevent the flash memory oxide film from degrading to increase the program speed and to over-program the memory cells.

  In the first correction, the step voltage Vstep1 in the incremental pulse program (ISPP) cycle is kept at the initial voltage Vstep (Vstep1 = Vstep). Note that the incremental pulse program (ISPP) is a method of performing writing by increasing the voltage applied to the gate of the memory cell in a stepped manner. In the NAND flash memory 20, the program voltage is increased by a constant value for each loop. Thus, data is written to a desired memory cell.

  In the first correction, the voltage Vpass of the non-selected word line at the program verify is increased by 0.1 V from the initial voltage Vpass to Vpass1 (Vpass1 = Vpass + 0.1V). This is because the threshold value Vt may decrease due to deterioration of the oxide film of the flash memory, and conversely, the voltage Vpass of the non-selected word line at the time of verification is increased. Further, the voltage Vsel at the time of program verification is increased by 0.1 V from the initial voltage Vsel to Vsel1 (Vsel1 = Vsel + 0.1V), and the voltage Vers1 at the time of erasing is kept at the initial voltage Vers (Vers1 = Vers). . In this example, the voltage Vers1 at the time of erasing is kept at the initial voltage Vers. However, the voltage Vers1 may be increased in consideration of the possibility that the memory cell is overprogrammed.

  Next, when the erase time tERS becomes longer and shorter than the second determination reference value (4 ms) (when the number of times of cycling N3 shown in FIG. 5), the second operating condition is corrected. In the second correction, the voltage Vread of the unselected word line at the time of reading is increased by 0.2V from the initial voltage Vread to Vread2 (Vread2 = Vread + 0.2V). Further, the program voltage Vipgm is reduced by −1.5 V from the initial voltage Vipgm to be Vipgm2 (Vipgm2 = Vippm−1.5 V). Further, the step voltage Vstep in the ISPP cycle is reduced by 0.1 V from the initial voltage Vstep to Vstep2 (Vstep2 = Vstep−0.1 V).

  In the second correction, the voltage Vpass of the non-selected word line at the program verify is increased by 0.2 V from the initial voltage Vpass to Vpass2 (Vpass2 = Vpass + 0.2V). Further, the voltage Vsel at the time of program verify is increased by 0.1 V from the initial voltage Vsel to Vsel2 (Vsel2 = Vsel + 0.1V). Note that the voltage Vers2 at the time of erasing remains the initial voltage Vers (Vers2 = Vers).

  Similarly, every time the controller 10 detects that the time tERS exceeds the determination reference value (5 ms,...), The correction is repeated in order of the third time, the fourth time,.

  As described above, the nonvolatile semiconductor memory device 1 using the NAND flash memory 20 determines the time tERS when the flag F_ERS is output from the flash memory 20, and if the time tERS exceeds the determination reference value, the controller 10 Updates (decreases) the determination reference value to a predetermined value, and stores the block address and the number of times that the erase time tERS exceeds the determination reference value (correction count) in the block address storage unit 12 (if it is the first time) 1st, 2nd, 2nd, 3rd, 3 ...)

  Then, when accessing the block next time, the controller 10 of the nonvolatile semiconductor memory device 1 reads the number of corrections stored in the condition table 11 and the operation condition corresponding thereto, and the read operation condition is first set to the NAND type. The flash memory 20 is set, and then a desired operation (read / program / erase) is performed.

Note that the setting value of the operating condition in the condition table shown in FIG. 6 can be determined by experimental data, for example. The condition table 11 shown in FIG. 6 shows an example, and the set value can be changed according to the type and configuration of the nonvolatile semiconductor memory device.
Further, when the number of corrections in a certain block increases (characteristic deterioration progresses), the block can be prevented from being used. Thereby, the lifetime of the flash memory 20 can be extended and the reliability of the flash memory 20 can be improved.

  As described above, in the nonvolatile semiconductor memory device of this embodiment, the erase time tERS of each block is monitored instead of the number of cycles, and when the erase time tERS exceeds the determination reference value, the block Store the address and change the operating condition only for that block.

  That is, in the NAND flash memory 20, the charge trap is generated in the oxide film of the memory cell by cycling, and the programming time of the memory cell is shortened (programming becomes easy). On the contrary, the erase time becomes longer (it becomes difficult to erase). Therefore, in the nonvolatile semiconductor memory device 1, when the erase time exceeds the determination reference value in the block to be erased, the block address and the operation condition to be applied to the block from the next time are stored. When accessing, the NAND flash memory 20 is instructed to apply a new operating condition.

  As described above, in the nonvolatile semiconductor memory device 1 according to the present embodiment, it is not necessary to store the number of cycles of each block on the NAND flash memory 20, so that the register area can be reduced. Further, since the deterioration state of the characteristics of the memory cell can be managed for each individual block, the NAND flash memory can be compared with the case where the operating condition of the NAND flash memory 20 is changed using the average number of cycles. Therefore, the reliability of the NAND flash memory 20 can be improved without causing deterioration of the overall characteristics of the NAND flash memory 20.

[Second Embodiment]
Next, as a second embodiment of the present invention, instead of the method in which the NAND flash memory 20 outputs the flag F_ERS to the controller 10 in the first embodiment, the flash memory 20 has a determination reference value (an updated determination reference value). ) Will be described. Thereby, the controller 10 does not need to determine (measure) the erase time, and the control in the controller 10 is simplified.

  FIG. 7 is a diagram showing a configuration of a nonvolatile semiconductor memory device 1A according to the second embodiment of the present invention. Compared with the nonvolatile semiconductor memory device 1 shown in FIG. 1, the nonvolatile semiconductor memory device 1A shown in FIG. 7 omits the erase time (tERS) 13 in the controller 10 shown in FIG. The difference is that the condition table 11 and block address storage unit 12 shown are changed to the condition table 11A and block address storage unit 12A shown in FIG. Further, the difference is that the flag value RnB is output from the NAND flash memory 20A shown in FIG. 7 instead of outputting the flag F_ERS from the NAND flash memory 20 shown in FIG. Other configurations are the same as those of the nonvolatile semiconductor memory device 1 shown in FIG.

  FIG. 8 is a diagram showing a configuration of a NAND flash memory 20A according to the second embodiment of the present invention. The NAND flash memory 20A shown in FIG. 8 differs from the NAND flash memory 20 shown in FIG. 2 in that the flag generator 35 shown in FIG. 2 is changed to a flag value generator 35A shown in FIG. .

That is, in the NAND flash memory 20 of the first embodiment shown in FIG. 2, when the erase is completed in the block to be erased, the flag generator 35 generates the flag F_ERS indicating that the erase is completed. And output to the controller 10.
On the other hand, in the NAND flash memory 20A shown in FIG. 8, when the erase is completed in the block to be erased, the flag value generation unit 35A generates a flag value RnB corresponding to the erase time tERS and outputs it to the controller 10A. Is configured to do.

  When the flag value generation unit 35A receives the erase completion information from the erase completion detection unit 36, the flag value generation unit 35A determines (measures) the erase time tERS in the block based on the erase completion information. Further, the flag value generation unit 35A includes a plurality of determination reference values “determination reference value 1, determination reference value 2 (> determination reference value 1), determination reference value 3 (> determination reference value 2),. The reference value n ”is held in advance, and the determined (measured) erase time tERS is compared with each determination reference value, and a flag value RnB is generated based on the comparison result.

  For example, when the erase time tERS is larger than the determination reference value 1 and smaller than the determination reference value 2 (determination reference value 1 <tERS <determination reference value 2), the flag value generation unit 35A sets the flag value “01”. Generate and output to the controller 10A. The flag value generation unit 35A sets the flag value “02” when the erase time tERS is larger than the determination reference value 2 and smaller than the determination reference value 3 (determination reference value 2 <tERS <determination reference value 3). Generate and output. Thus, when the erase time tERS exceeds the determination reference value 1, the flag value generation unit 35A generates a flag value corresponding to the size of the determination reference value and outputs the flag value to the controller 10A.

  When the controller 10A receives the flag value RnB from the flash memory 20 after erasing the block to be erased, the controller 10A associates the block address of the block with the flag value RnB and stores them in the block address storage unit 12A. To do. Further, the controller 10A includes a condition table 11A shown in FIG. The condition table 11A shown in FIG. 9 shows the number of corrections (1, 2, 3,..., N) in the table shown in FIG. 6 as compared with the condition table 11 shown in FIG. The difference is that the flag values (01, 02, 03,..., FF) are changed. The other items are the same as in FIG. In this condition table 11A, the erase time tERS, the flag value RnB, and the operation condition of the flash memory 20A corresponding to the flag value RnB are stored in association with each other.

When starting access to a block in the NAND flash memory 20A, the controller 10A first refers to the block address storage unit 12A, and whether the block address of the block is stored in the block address storage unit 12A. Determine whether or not. When the block address of the block to be accessed is stored in the block address storage unit 12A, the controller 10A reads the flag value RnB stored corresponding to this block address, and based on this flag value RnB With reference to the condition table 11A, the operating conditions to be applied to the flash memory 20A are read. The controller 10A requests the flash memory 20A to apply the operation condition read from the condition table 11A to this block.
Then, the controller 10A starts access to the block of the flash memory 20A after the requested operating condition is set in the flash memory 20A.

  As described above, in the nonvolatile semiconductor memory device 1A of the second embodiment, the flash memory 20A compares the erase time tERS with the determination reference value (a plurality of determination reference values), and sets the comparison result as the flag value RnB to the controller 10A. Therefore, it is not necessary to determine the erase time tERS on the controller 10 side, and it is not necessary to compare the erase time tERS with the determination reference value, thereby simplifying the control in the controller 10A.

  Although the embodiment of the present invention has been described above, the correspondence between the present invention and the above embodiment will be supplementarily described here. In the above embodiment, the nonvolatile semiconductor memory device of the present invention corresponds to the nonvolatile semiconductor memory device 1 shown in FIG. 1, and the flash memory in the present invention is a NAND flash memory (also simply referred to as “flash memory”) 20. Corresponds. The controller 10 in the present invention corresponds to the controller 10 shown in FIG. 1, the condition table in the present invention corresponds to the condition table 11, and the block address storage unit in the present invention corresponds to the block address storage unit 12. The erase time determination unit in the present invention corresponds to the erase time determination unit 13.

(1) In the above embodiment, when the nonvolatile semiconductor memory device 1 performs the erase operation on the block in the flash memory 20, the erase from the erase start until the erase of the memory cell in the block is completed. A function for measuring the time tERS, a function for comparing the erase time tERS with a predetermined determination reference value, and when the erase time tERS exceeds the determination reference value in the block, the next time the block is accessed And a function of changing the operating condition of the flash memory 20 to a predetermined operating condition and accessing it.
In the nonvolatile semiconductor memory device 1 having such a configuration, the erase time tERS in the block to be erased is determined (measured), and when the erase time tERS exceeds the determination reference value, the block address of the block is stored. The next time the block is accessed, the operating condition of the flash memory 20 is changed to a predetermined operating condition.
Thereby, the characteristic deterioration state of the memory cell can be detected for each individual block in the flash memory, and the operating condition corresponding to the characteristic deterioration can be set for the flash memory 20 for each individual block. Also, normal operating conditions can be set for blocks where the memory cells are not degraded. Furthermore, it is possible not to use a block having a large degree of deterioration (deteriorated). Therefore, the overall characteristics of the flash memory 20 are not deteriorated, the life of the flash memory can be extended, and the reliability of the flash memory 20 can be improved.

  (2) In the above embodiment, the nonvolatile semiconductor memory device 1 includes the flash memory 20 having a memory region in which memory cells are arranged in an array, and a control unit (controller 10) that controls the operation of the flash memory 20. The flash memory 20 outputs erase completion information (flag F_ERS) indicating the completion of the erase to the outside (the controller 10) when the erase of the memory cell in the block to be erased is completed. And a function of changing the operating condition in the flash memory 20 in response to a request from the outside (controller 10). The control unit (controller 10) has erase completion information (flag) output from the flash memory 20 F_ERS) to monitor the block to be erased. A function for determining the erase time tERS required from the start of the erase to the completion of the erase, a function for comparing the erase time tERS with the determination reference value, and the erase time tERS in the block to be erased is the determination reference value The function of storing the block address of the block in the case of exceeding the threshold and requesting the flash memory 20 to change the operating condition of the flash memory 20 to a predetermined operating condition when accessing the block from the next time And comprising.

In the nonvolatile semiconductor memory device 1 having such a configuration, the flash memory 20 outputs erase completion information (flag F_ERS) to the outside when the erase of the memory cells in the block to be erased is completed. Further, the flash memory 20 can change operating conditions in response to a request from the outside (controller 10).
The control unit (controller 10) monitors the erase completion information (flag F_ERS) output from the flash memory 20, and determines the erase time tERS (time from the start of erase until the flag F_ERS is set). When the time tERS exceeds the determination reference value, the control unit (controller 10) stores the block address and the operation condition to be applied to the block from the next time, and when accessing the block from the next time, the new operation condition is set. The flash memory 20 is requested to apply. The operating conditions are, for example, operating conditions for program / program verify / read / erase (Program / Program Verify / Read / Erase).
Thereby, without storing the number of cycles of each block in the flash memory, the deterioration of the characteristics of the memory cell is detected for each block, and the operating condition of the flash memory is set according to the deterioration state of each block. be able to. For this reason, the lifetime of the flash memory can be extended and the reliability of the flash memory can be improved.

  (3) In the above embodiment, each time the erase time tERS exceeds the determination reference value in the block in the flash memory 20, the control unit (controller 10) updates the determination reference value for the block by increasing the predetermined time. At the same time, when the block is accessed next, different operating conditions are set for the flash memory 20.

In the nonvolatile semiconductor memory device 1 configured as described above, when the erase time tERS exceeds the determination reference value in one block, the time of the determination reference value is extended and updated. The operating condition of the flash memory 20 is changed. Then, after the determination reference value is updated, when the race time tERS again exceeds the determination reference value in the one block, the determination reference value for the one block is further extended and updated, and the flash The operating condition of the memory 20 is extended again and updated. Thereafter, every time the erase time tERS exceeds the determination reference value in the one block, the determination reference value is extended and updated, and the operation conditions set (held) in advance according to the number of times of the increase are updated. Set for.
As a result, when the characteristic deterioration of the memory cell progresses in a certain block, it is possible to set an operation condition according to the state of the characteristic deterioration of the memory cell for this block. For this reason, the reliability of the flash memory can be improved.

  (4) In the above embodiment, the nonvolatile semiconductor memory device 1 determines the erase time tERS from the start of erase to the completion of erase in the block to be erased, and uses the erase time tERS and the determination reference value. In addition, when the erase time tERS exceeds the determination reference value, the erase time determination unit 13 that updates the determination reference value for the block by extending the time, and the erase time tERS in the block to be erased is the determination reference A block address storage unit 12 that stores the block address of the block and the correction count that is the number of times the erase time tERS exceeded the criterion value in the block in association with each other, and the correction count And the criterion value that is updated according to the number of corrections Similarly, a condition table 11 for associating and storing operating conditions to be applied to the flash memory 20 in accordance with the number of corrections, and the control unit (controller 10) stores blocks in the flash memory 20 Before starting access to the block address storage unit 12 and the condition table 11, if the block address of the block is stored in the block address storage unit 12, it corresponds to the correction count of the block. The operation condition is extracted from the condition table 11, and after setting the extracted operation condition for the flash memory 20, access to the block is started.

In the nonvolatile semiconductor memory device 1 configured as described above, the erase time determination unit 13 determines (measures) the erase time tERS from the start of erase in the block to be erased until the erase completion information (flag F_ERS) is output. At the same time, the erase time tERS is compared with a criterion value. In addition, the erase time determination unit 13 extends and updates the time of the determination reference value for a block in which the erase time tERS exceeds the determination reference value. Further, the block address storage unit 12 stores the block address of the block in which the erase time tERS exceeds the determination reference value, together with the number of times (correction count) that the erase time tERS exceeds the determination reference value in the block. The condition table 11 associates and stores the number of corrections, the determination reference value that is updated according to the number of corrections, and the operating condition that should be applied to the flash memory 20 according to the number of corrections. To do.
The control unit (controller 10) refers to the block address storage unit 12 and the condition table 11 before starting access to the block in the flash memory 20, and the block address of the block is stored in the block address storage unit 12. If stored, an operation condition corresponding to the number of corrections of the block is extracted, and after setting the extracted operation condition to the flash memory 20, access to the block is started.
As a result, when the characteristics of the memory cell in a certain block deteriorate, the block address of this block is stored, and the operating condition corresponding to the characteristic deterioration of the memory cell in this block is set for the flash memory 20 Can do.

(5) In the above-described embodiment, the operating condition to be changed when accessing is an operating condition when performing any one of the program, program verify, read, erase, or all the processing on the block of the flash memory 20 As a result, when the characteristics of a memory cell deteriorate in a certain block, the operating conditions at the time of programming, program verifying, reading and erasing according to the deterioration state of the memory cell (for example, programming Voltage conditions such as voltage, read voltage and verify voltage) can be set appropriately.

  Although the embodiments of the present invention have been described above, the nonvolatile semiconductor memory device of the present invention is not limited to the above illustrated examples, and various modifications are made within the scope not departing from the gist of the present invention. Of course you get.

For example, in the above-described embodiments, an example in which the flash memory is a NAND flash memory has been described. However, the flash memory may be a NOR flash memory.
The present invention is not limited to the nonvolatile semiconductor memory device described above, and can be effectively applied to various systems incorporating a flash memory.

DESCRIPTION OF SYMBOLS 1,1A ... Nonvolatile semiconductor memory device, 10, 10A ... Controller, 11, 11A ... Condition table, 12, 12A ... Block address memory | storage part, 13 ... Erase time determination part, 20, 20A ... Flash memory, 21 ... Memory cell array , 22 ... page buffer, 22A ... page buffer decoder, 23 ... row decoder, 31 ... memory control circuit, 32 ... operating condition change setting unit, 33 ... output data buffer, 34 ... input data buffer, 35 ... flag generation unit, 35A ... Flag value generation unit, 36 ... Erase completion detection unit, 37 ... Operating voltage controller

Claims (6)

When performing an erase operation on a block in the flash memory, a function for measuring the erase time from the start of erase until completion of the erase,
A function of comparing the erase time with a predetermined criterion value;
When the erase time exceeds the determination reference value in the block, when accessing the block from the next time, the function of accessing the flash memory by changing the operation condition to a predetermined operation condition;
A non-volatile semiconductor memory device comprising: A flash memory having memory areas in which memory cells are arranged in an array, and a control unit for controlling the operation of the flash memory;
The flash memory is
When the erase of the memory cells in the block to be erased is completed, the function of outputting erase completion information indicating that the erase is completed to the outside,
A function to change the operating conditions in the flash memory in response to an external request;
With
The controller is
A function of measuring the erase time required from the start of the erase to the completion of the erase in the block to be erased by monitoring the erase completion information output from the flash memory;
A function of comparing the erase time with the criterion value;
When the erase time of the block to be erased exceeds the determination reference value, the block address of the block is stored, and when the block is accessed next time, the operation condition of the flash memory is set to the predetermined value. A function that requests the flash memory to change to the operating conditions of
The nonvolatile semiconductor memory device according to claim 1, comprising: The controller is
Each time the erase time exceeds the determination reference value in the block in the flash memory, the determination reference value for the block is updated to be longer by a predetermined time, and the next time the block is accessed, Set different operating conditions for flash memory,
The nonvolatile semiconductor memory device according to claim 2. The erase time from the start of erasure to the completion of erasure in the block to be erased is measured, and the erase time is compared with the determination reference value, and when the erase time exceeds the determination reference value, An erase time determination unit that updates the determination reference value for a block by extending the time;
When the erase time exceeds the determination reference value in the block to be erased, the block address of the block, and the number of corrections that is the number of times the erase time exceeds the determination reference value in the block, A block address storage unit for storing the information in association with each other;
A condition table for associating and storing the number of corrections, the determination reference value updated and set according to the number of corrections, and the operating condition to be applied to the flash memory according to the number of corrections ,
With
The controller is
Before starting access to the block in the flash memory, refer to the block address storage unit and the condition table,
When the block address of the block is stored in the block address storage unit,
An operation condition corresponding to the number of corrections of the block is extracted from the condition table, and after the extracted operation condition is set for the flash memory, access to the block is started. Item 4. The nonvolatile semiconductor memory device according to Item 3. The operation condition to be changed when accessing is an operation condition for performing any one of program, program verify, read, erase, or all processing on a block. 5. The nonvolatile semiconductor memory device according to claim 4. A procedure for measuring the erase time from the start of erasing to the completion of erasing of the memory cells in the block when performing an erase operation on the block in the flash memory; and
A procedure for comparing the erase time with a predetermined criterion value;
When the erase time in the block exceeds the determination reference value, the procedure for accessing the block by changing the operation condition of the flash memory to a predetermined operation condition when accessing the block next;
An operation condition control method for a nonvolatile semiconductor memory device, comprising:

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