WO2009073221A1 - Semiconductor device and control method thereof - Google Patents

Semiconductor device and control method thereof Download PDF

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Publication number
WO2009073221A1
WO2009073221A1 PCT/US2008/013441 US2008013441W WO2009073221A1 WO 2009073221 A1 WO2009073221 A1 WO 2009073221A1 US 2008013441 W US2008013441 W US 2008013441W WO 2009073221 A1 WO2009073221 A1 WO 2009073221A1
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WO
WIPO (PCT)
Prior art keywords
reference cell
threshold value
cell
memory cells
programming
Prior art date
Application number
PCT/US2008/013441
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French (fr)
Inventor
Satoshi Takahashi
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Spansion Llc
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Publication of WO2009073221A1 publication Critical patent/WO2009073221A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0491—Virtual ground arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure

Definitions

  • the present invention relates to semiconductor devices and, more particularly, to a semiconductor device having a non-volatile memory cell capable of storing two bits of data in a cell.
  • WO2004-097839 Al discloses a non-volatile memory used in the dynamic reference method in related art with an improved data reading.
  • Japanese Patent Application Publication No. JP-A-2002-334589 discloses a non-volatile memory provided with an inspection cell inspecting a threshold voltage of a reference cell that is referenced when reading data.
  • Japanese Patent Application Publication No. JP-A-2003-257188 discloses a configuration, in a nonvolatile memory in dynamic reference method, to set a threshold value of a second reference cell in accordance with a threshold value of a first reference cell.
  • a semiconductordevice having a plurality of memory cells storing two bits of data in a cell by independently storing data in isolated storage regions in the cell; a first reference cell corresponding to an erased state of the storage region and being shared by the plurality of memory cells; a second reference cell corresponding to a programmed state of the storage region and being shared by the plurality of memory cells; and a control section carrying out data read operations by creating a reference threshold value from threshold values of the first reference cell and the second reference cell and by comparing a threshold value of the storage region subject to data reading in the plurality of memory cells with the reference threshold value when reading data, programming with a first threshold value to verify when programming the second reference cell, refreshing with a second threshold value lower than the first threshold value to verify when refreshing the second reference cell, and programming at least one or more cells subject to programming in the plurality of memory cells with the threshold value of the second reference cell to verify and refreshing a cell subject to refresh in the plurality of memory cells with the
  • a method for controlling a semiconductor device provided with a plurality of memory cells storing two bits of data in a memory cell by independently storing data in isolated regions in the memory cell, a first reference cell corresponding to an erased state of the plurality of memory cells, and a second reference cell corresponding to a programmed state of the plurality of memory cells, having the steps of creating a reference threshold value from threshold values of the first reference cell and the second reference cell, reading data by comparing a threshold value of the storage region subject to data read in the plurality of memory cells with the reference threshold value, programming the second reference cell with a first threshold value to verify, refreshing the second reference cell with a second threshold value lower than the first threshold value to verify, programming at least one or more cells subject to programming in the plurality of memory cells with the threshold value of the second reference cell to verify, and refreshing a cell subject to refresh in the plurality of memory cells with the threshold value of the second reference cell to verify.
  • FIGS. IA to ID are cross-sectional views (part 1) schematically showing the configuration of a memory cell in related art and that in embodiments of the present invention
  • FIGS. 2 A to 2D are cross-sectional views (part 2) schematically showing the ⁇ configuration of the memory cell in related art and that in the embodiments of the present invention;
  • FIG. 3A is a schematic circuit diagram showing the configuration of a semiconductor device in related art
  • FIG. 3B is a graph showing threshold voltages of each cell shown in FIG. 3A;
  • FIG. 4A is a cross-sectional view schematically showing the configuration of the semiconductor device in related art
  • FIGS. 4B and 4C are graphs showing threshold voltages of each cell shown in FIG. 4A
  • FIGS. 5 A and 5B are graphs showing threshold voltages of each cell of the semiconductor device in related art
  • FIG. 6 is a block diagram showing the configuration of a semiconductor device of a first embodiment of the present invention.
  • FIG. 7 is a flowchart showing an erasing operation of the semiconductor device of the first embodiment
  • FIG. 8 is a flowchart showing programming operation of the semiconductor device of the first embodiment
  • FIG. 9 is a flowchart showing reading operation of the semiconductor device of the first embodiment.
  • FIGS. 1OA to 1OD show changes in threshold voltages of each of cells according to the programming operation of the first embodiment;
  • FIG. 11 is a flowchart showing programming operation of a semiconductor device of a second embodiment of the present invention.
  • FIGS. 12A and 12B show operation determination from step S42, as shown in FIG. 11;
  • FIGS. 13A to 13C show the changes in threshold voltages of each of cells in programming operation of the second embodiment.
  • FIG. IA the configuration of a non-volatile memory cell MC capable of storing two bits of data in a cell will be described.
  • a source region 14 and a drain region 12 that are input/output terminals are formed.
  • a gate 16 that is a control terminal is formed. Between the gate 16 and the semiconductor
  • an ONO film 24 i.e., a multilayered film including an oxide film, a nitride film, • and an oxide film
  • an interlayer insulating film 18, a trap layer 20, and a gate insulating film 22 is formed.
  • the interlayer insulating film 18 and the gate insulating film 22 are oxide films composed of, e.g., silicon oxide
  • the trap layer 20 is a nitride film composed of, e.g., silicon nitride.
  • the memory cell MC stores data by changes in threshold voltage caused by injecting electrical charges into the trap layer 20 (i.e., programming), or withdrawing the electrical charges from the trap layer 20 (i.e., erasing).
  • the trap layer 20 is an insulator, thus the injected electrical charges remain in the same place without moving. Therefore, data can be independently stored in isolated regions in the trap layer 20.
  • the trap layer 20 has a first storage region 30 and a second storage region 32, and each region can store one bit data each.
  • the memory cell MC two bits of data in a cell can be stored.
  • electrical charges 34 i.e., electrons
  • FIG. IA when programming the first storage region 30, while the gate 16 and the drain region 12 are set to a high potential and the source region 14 is set to a low potential, electrical charges 34 (i.e., electrons), are injected in a direction of an arrow by hot electron injection.
  • FIG. IB when erasing data in the first storage region 30, while the gate 16 is set to a low potential and the drain region 12 to a high potential, the electrical charges 34 are withdrawn in a direction of an arrow by hot hole injection.
  • the data in the first storage region 30 is read out by switching around the drain region 12 and the source region 14, applying voltages thereto in a reverse direction, and applying a voltage lower than that used in programming to the gate 16.
  • the threshold voltage is in a high state and the current flowing towards an arrow direction is blocked in the vicinity of the first storage region 30 where marked x in the drawing, thus a logic value of "0" is read.
  • the threshold voltage is in a low stage and the current flows in an arrow direction, thus a logic value of "1" is read.
  • programming, erasing and reading data to or from the first storage region 30 of the memory cell MC can be carried out.
  • These operations for the second storage region 32 can be carried out in similar manners to the respective operations of programming, erasing and reading the first storage region 30, by switching around the drain region 12 and the source region 14 and reversing the direction of the voltages applied.
  • the memory cell MC independently stores one bit of data to the first storage region 30 and one bit of data in the second storage region 32, thus providing four states as shown in FIGS. 2A to 2D.
  • FIGS. 2A to 2D With reference to FIG. 2A, the state in which both the first storage region 30 and the
  • AF02584WO second storage region 32 are in erased state, i.e., a logic value of "1", is defined as "11".
  • the state in which both the first storage region 30 and the second storage region 32 are in programmed state i.e., a logic value of "0" is defined as "00".
  • the state in which the first storage region 30 is in the erased state and the second storage region 32 is in the programmed state is defined as "10".
  • the state in which the first storage region 30 is in the programmed state and the second storage region 32 is in the erased state is defined as "01".
  • “Programming” herein means to inject electrical charges to the storage region in the erased state "1" and to raise the threshold voltage to that of the programmed state "0". Meanwhile, a later described “refreshing” means to inject electrical charges again, out of the storage regions in the programmed state "0" already, to the storage region in which the threshold voltage is lowered so as to restore the threshold voltage.
  • a plurality of memory cells MC provided on a word line WL shares a first reference cell RCl and a second reference cell RC2 for data read operations.
  • the threshold value of the first reference cell RCl corresponds to the erased state MC "1" of the memory cell MC.
  • the threshold value of the second reference cell RC2 corresponds to the programmed state MC "0" of the memory cell MC.
  • the reference threshold value REF created by averaging the threshold values of the first reference cell RCl and the second reference cell RC2 is situated in the middle of MC "1" and MC "0".
  • the dynamic reference method whenever one of the memory cells MC is erased, all of the memory cells MC, the first reference cell RCl, and the second reference cell RC2 coupled on the same word line WL are simultaneously erased. Further, whenever one of the memory cells MC is programmed, the memory cell MC in the programmed state out of all of the memory cells MC, and the second reference cell RC2 coupled on the same word line WL are refreshed. Consequently, characteristics of cells, such as changes in characteristics of charge loss and charge gain from deterioration, of the memory cells MC, the first reference cell RCl, and the second reference cell RC2 can be coordinated, thus data reading can be stably carried out continuously.
  • FIG.4A is a cross-sectional view schematically showing the refreshing operation of the "0" side of the memory cell MC in the "10" state.
  • the electrical charges 34 are already injected.
  • AF02584WO electrical charges are further injected in an arrow direction by the voltage applied in refreshing, ' 'the second storage region 32 enters an over-programmed state due to excess electrical charges.
  • the threshold voltage MC "1" of the first storage region 30 on the opposite side, which is in the "1" state rises, thereby making a "read margin" 50 with the reference threshold value REF small.
  • the result is unstable data reading.
  • a program threshold value PRGV i.e., a first threshold value
  • a refresh threshold value REFV i.e., a second threshold value
  • the threshold voltages after programming are distributed as PMC “0" and PRC 2.
  • the threshold voltages after refreshing are distributed as RMC “0" and RRC 2.
  • FIG. 6 is a block diagram showing the configuration of a semiconductor device of a first embodiment of the present invention.
  • a memory cell array 60 containing storage regions is composed of a memory cell area 62 for storing data, and a dynamic reference area 64 for storing
  • the memory cell array 60 is provided with a plurality of bit lines BL in a first ⁇ direction and a plurality of word lines WL in a second direction crossing the first direction.
  • a single word line WL e.g., WLl
  • respective control terminals of a plurality of memory cells MC are coupled in the memory cell area 62
  • respective control terminals of a first reference cell RCl and a second reference cell RC2 are coupled in the dynamic reference area 64.
  • a memory cell row MCR composed of the plurality of memory cells MC are provided on the same word line as the first reference cell RCl and the second reference cell RC2, sharing the RCl and the RC2.
  • Input/output terminals for the memory cells MC and the reference cells RC are respectively coupled with two adjacent bit lines BL.
  • the memory cells MC, the first reference cell RCl , and the second reference cell RC2 are structured the same as the memory cell MC shown in FIG. IA, and are capable of storing two bits of data in a cell by independently storing data in isolated regions, i.e. the first storage region 30 and the second storage region 32, in the cell.
  • the first reference cell RCl corresponds to the erased state of the memory cell MC and is set to a threshold voltage equivalent to the storage region in the "1" state of the storage regions in the memory cell MC.
  • the second reference cell RC2 corresponds to the programmed state of the memory cell MC and is set to a threshold voltage equivalent to the storage region in the "0" state of the storage regions in the memory cell MC.
  • the bit lines BL of the memory cell array 60 are coupled with a column address decoder 66, and the word lines WL are coupled with a row address decoder 68.
  • the column address decoder 66 and the row address decoder 68 select the memory cells MC or the reference cells RC according to an address signal provided from the outside via an address buffer 72. Further, the column address decoder 66 and the row address decoder 68 apply voltages for programming, refreshing, erasing and data reading supplied from a voltage supply circuit 74 to the bit lines BL and the word line WL corresponding to the selected memory cells MC and the reference cells RC.
  • a write/read circuit 76 via an internal sense amplifier (not shown), reads or verifies data by comparing a signal output from the memory cell area 62 or the dynamic reference area 64 with a reference signal output from the dynamic reference area 64 or an external reference area 79, and outputs the result to a data latch 77. Further, when programming, the write/read circuit 76 feeds data entered from the data latch 77 to the memory cell array 60. The data latch 77 outputs data entered from the write/read circuit 76 to the I/O circuit 78 and the control section 70. The I/O circuit 78 exchanges data with the outside.
  • the control section 70 controls operations of programming, erasing and data reading for the memory cell array 60 by controlling the address buffer 72 and the voltage supply circuit 74
  • the control section 70 selects the reference cell used to verify and, based on the result of verification in the write/read circuit 76, controls voltages to be applied to the cells.
  • the external reference area 79 is provided outside the memory cell array 60.
  • the external reference area 79 includes a third reference cell RC3 setting a first threshold voltage of the program threshold value PRGV, a fourth reference cell RC4 setting a second threshold voltage of the refresh threshold value REFV, and a fifth reference cell RC5 setting a third threshold voltage of a read threshold value READV.
  • the outputs from these reference cells are fed to the write/read circuit 76 and are referenced when programming or refreshing the second reference cell RC2.
  • the control section 70 collectively erases the plurality of memory cells MC, the first reference cell RCl, and the second reference cell RC2 coupled on the same word line WL (step SlO). More specifically, the word line WL coupled with the memory cells MC subject to erase is set to a low potential and all bit lines BL are set to a high potential to withdraw electrical charges from the memory cells MC by injecting hot holes as shown in FIG. IB. Consequently, all of the memory cells MC subject to erase, the first reference cell RCl, and the second reference cell RC2 are set in the "1 1" state. Next, the control section 70 programs the second reference cell RC2 (step S 12).
  • At least one of the storage regions of the second reference cell RC2 enters the "0" state, corresponding to the programmed state of the memory cell MC. Meanwhile, at least one of the storage regions of the first reference cell RCl is set to be in the "1" state, corresponding to the erased state of the memory cell MC.
  • the second reference cell RC2 is verified with the program threshold value PRGV set by the third reference cell RC3 in programming.
  • the program threshold value PRGV is set higher than the later described refresh threshold value REFV. As described above, in the first embodiment, programming to the second reference cell RC2 is carried out in the course of the erasing operation.
  • the semiconductor device of the first embodiment employs the same dynamic reference method as that in related art described with reference to FIGS. 3A and 3B. More specifically, with reference to FIG. 6, when programming the memory cell MC in the erased state (i.e., the "1" state), included in the memory cell row MCR, all of the memory cells MC already in the programmed state (i.e., the "0" state), in the memory cell row MCR are simultaneously refreshed. The second reference cell RC2 is also refreshed at the same time.
  • FIG. 8 is a flowchart showing the programming operation of the semiconductor device of the first embodiment.
  • the control section 70 first enters new data to be stored in the program subjected cell PMC (step S20). More specifically, the control section 70 stores the new data in the data latch 77 via the I/O circuit 78. The control section 70 then reads data already stored in the refresh subjected cell RMC (step S22). Here, reading data is carried out by the dynamic reference method shown in FIG. 9.
  • FIG. 9 is a flowchart showing a reading operation of the semiconductor device of the first embodiment.
  • the control section 70 first obtains the threshold value of the first reference cell RCl (step S30). Specifically, out of the storage regions of the first reference cell RCl, the threshold voltage of the storage region set in the erased state "1" is obtained as a current signal or a voltage signal.
  • the control section 70 then obtains the threshold value of the second reference cell RC2 (step S32). Specifically, out of the storage regions of the second reference cell RC2, the threshold voltage of the storage region set in the programmed state "0" is obtained as a current signal or a voltage signal.
  • the control section 70 determines, from the threshold values obtained in steps S30 and S32, the reference threshold value REF (step S34).
  • the reference threshold value REF in the first embodiment is an average value of the threshold voltage of the first reference cell RCl and the threshold voltage of the second reference cell RC2.
  • the reference threshold value REF may be calculated in other ways so long as it is equivalent to the threshold voltage between the erased state and the programmed state of the memory cell MC. For example, a weighted mean average of the threshold voltage of the first reference cell RCl and the threshold voltage of the second reference cell RC2 may be used.
  • the control section 70 then obtains the threshold value of the memory cell MC subject to data reading (step S36). Specifically, out of the storage regions of the memory cell MC subject to data reading, the threshold voltage of the storage region subject to read is obtained as a current signal or a voltage signal.
  • the control section 70 inputs both the threshold value of the memory cell MC and the reference threshold value REF created in step S34 to the write/read circuit 76 shown in FIG. 6.
  • control section 70 directs the write/read circuit 76 to compare the threshold value of the memory cell MC obtained in step S36 with the reference threshold value REF created in step S34 (step S38). When the threshold value of the memory cell MC is greater than
  • the control section 70 outputs the comparison result (step S39). More specifically, the control section 70 directs the write/read circuit 76 to output the comparison result to the data latch 77. Further, the control section 70 provides data output to the outside from the data latch 76 via the I/O circuit 78. This completes the data reading operation.
  • the control section 70 stores the data read from the refresh subjected cell RMC in the data latch 77.
  • the control section 70 then refreshes the second reference cell RC2 (step S24).
  • the second reference cell RC2 is verified with the refreshing threshold value REFV set by the fourth reference cell RC4 in refreshing.
  • the refresh threshold value REFV is set lower than the program threshold value PRGV. Therefore, when the charge loss in the storage region (in the "0" state) of the second reference cell RC2 is small, electrical charges are not injected again, thereby preventing the storage region in the "0" state from over-programming. Consequently, the threshold voltage of the second reference cell RC2 can be maintained at an appropriate level.
  • control section 70 programs the new data to the program subjected cell PMC (step S26). Specifically, the control section 70 programs the program subjected cell PMC, with the new data stored in the data latch 77 in step S20, by applying a voltage thereto via the voltage supply circuit 74. The program subjected cell PMC is verified with the threshold value of the second reference cell RC2 refreshed in step S24 in programming.
  • the control section 70 then refreshes existing data in the refresh subjected cell RMC (step S28). Specifically, the control section 70 refreshes the refresh subjected cell RMC, with the existing data stored in the data latch 77 in step S22, by applying a voltage thereto via the voltage supply circuit 74. The refresh subjected cell RMC is verified with the threshold value of the second reference cell RC2 refreshed in step S24 in refreshing. Steps S26 and S28 may be carried out at the same time. This completes the operation of programming data.
  • FIGS. 1OA to 1OD show changes in threshold voltages of the memory cells MC and the reference cells RC in accordance with the programming operation of the first embodiment.
  • FIG. 1OA corresponds to a condition immediately after the operation of erasing data, i.e., the end of the flowchart shown in FIG. 7.
  • the threshold voltage of the second reference cell RC2 is in a state higher than the program threshold value PRGV.
  • the threshold voltages of both the first reference cell RCl and the memory cells MC are in the erased state.
  • FIG. 1OB corresponds to a condition immediately before the data programming operation, i.e., the start of the flowchart shown in FIG. 8.
  • the threshold voltage of the second reference cell RC2 is lowered by the charge loss with elapsed time, and may sometimes become
  • the threshold voltages of the first reference cell RCl and the memory cell MC in the "1" state are about the same as those shown in FIG. 1OA.
  • the reference threshold value REF is the average of the threshold voltages of the first reference cell RCl and the second reference cell RC2, and is lowered in accordance with the lowering of the threshold voltage of the second reference cell
  • the read margin 50 for the storage region in the "1" state is smaller than that shown in FIG. 1OA.
  • the threshold voltage of the memory cell MC in the "0" state is similarly distributed to that of the second reference cell RC2.
  • FIG. 1OC corresponds to a condition immediately after refreshing the second reference cell RC2, i.e., the completion of step S24 shown in FIG. 8.
  • the threshold voltage of the second reference cell RC2 is raised by refreshing, and is distributed in a higher area than the refresh threshold value REFV (see a solid arrow in the drawing). Further, the reference threshold value REF is raised in accordance with the refreshing of the second reference cell RC2, see a broken arrow in the drawing, and the read margin 50 for the storage region in the "1" state is greater than that shown in FIG. 1 OB .
  • FIG. 1OD corresponds to a condition immediately after the programming operation, i.e., the end of the flowchart shown in FIG. 8.
  • the threshold voltage of the refresh subjected cell RMC in the "0" state shown in FIG. 1OC is restored by refreshing, see an arrow in the drawing.
  • the threshold voltage of the program subjected cell PMC in the "1" state shown in FIG. 1OC is raised by the programming. Since both the refresh subjected cell RMC and the program subjected cell PMC are verified with the threshold voltage of the second reference cell RC2 (see steps S26 and S28 shown in FIG.
  • the threshold voltages of the memory cells MC "0" after programming or after refreshing are distributed in areas higher than the threshold voltage of the second reference cell RC2, thereby preventing over-programming. Consequently, the threshold voltage of the storage region MC "1" on the opposite side is hardly raised.
  • the second reference cell RC2 when programming new data, the second reference cell RC2 is first refreshed with the refresh threshold value REFV lower than the program threshold value PRGV to verify, i.e. step S24, and then, with the threshold voltage of the reference cell RC2 after the refresh step to verify, the memory cells MC are programmed, i.e., step S26, and refreshed, i.e., step S28. Therefore, with reference to FIG. 10D, in the program subjected cell PMC and the refresh subjected cell RMC, the storage regions MC "0" subject to program or subject to refresh can be prevented from over programming, and the threshold value of the storage region MC "1" on opposite side can be prevented from being raised. All of the memory cells MC are verified with the same threshold value of the second reference cell RC2, thereby preventing a mismatch of the threshold voltages
  • the read margin 50 between the threshold value of the memory cell MC "1" in the "1" state and the reference threshold value REF can be made greater.
  • the program threshold value PRGV is used to verify when programming the second reference cell RC2 (see step S12, as shown in FIG. 7), and in the programming operation, the refresh threshold value REFV, now lower than the program threshold value PRGV, is used to verify when refreshing the second reference cell RC2 (see step S24 as shown in FIG. 8). Consequently, with reference to FIG. 1OC, when refreshing the second reference cell RC2, the storage region subject to refresh can be prevented from over- programming and the threshold value of the storage region on the opposite side can be prevented from being raised, thereby appropriately setting the threshold voltage of the second reference cell RC2.
  • the threshold voltage of the second reference cell RC2 can be appropriately set and the mismatch of the threshold voltages between the memory cell MC and the second reference cell RC2 reduced, thereby improving data reading stability.
  • the second reference cell RC2 can be verified with either the program threshold value PRGV or the refresh threshold value REFV.
  • the memory cells MC, the first reference cell RCl, and the second reference cell RC2 are provided on the same word line WL. According to this structure, by selecting a single word line WL, all related cells MC, RCl and RC2 can be selected, thereby facilitating the control.
  • the above structure is not an essential constituent factor of the first embodiment and, as long as the first reference cell RCl and the second reference cell RC2 are shared by a plurality of memory cells MC, other structures may be used.
  • the data is to be read in the dynamic reference method by comparing the reference threshold value REF created from the first reference cell RC 1 and the second reference cell RC2 with the threshold value of the memory cell MC.
  • REF the reference threshold value created from the first reference cell RC 1 and the second reference cell RC2
  • both the first reference cell RCl and the second reference cell RC2 are set in the "10" state, see FIG. 2C.
  • the threshold voltage of the "1" side is obtained from the first reference cell RCl, i.e., step S30 as shown in
  • step S12 the programming operation is to be carried out after collectively erasing the memory cells MC and the reference cells RC, i.e., step SlO, as a part of the erasing operation, it is preferable that the programming operation be carried out immediately after the collective erasing.
  • a second embodiment of the present invention is an embodiment for programming the second reference cell RC2 at the same time as the memory cell MC is programmed for the first time after erasing data, not programming the second reference cell RC2 at the time of erasing data.
  • the configuration and data reading operation of the semiconductor device of the second embodiment are the same as those, i.e., FIGS. 6 and 9, of the first embodiment.
  • FIG. 11 is a flowchart showing a programming operation of the semiconductor device of the second embodiment.
  • the control section 70 enters new data to be stored in the program subjected cell PMC (step S40). More specifically, the control section 70 stores the new data in the data latch 77 via the I/O circuit 78.
  • the control section 70 determines whether programming to the memory cell MC is the first time or not (step S42).
  • first time means when the memory cell MC is programmed for the first time counting from after erasing the memory cells MC and the reference cells RC.
  • the erasing operation of the second embodiment is the same as that of the first embodiment. In other words, a plurality of memory cells MC, the first reference cell RCl, and the second reference cell RC2 coupled on the same word line WL are collectively erased (see step SlO, as shown in FIG. 7). Thereafter, the erasing operation is finished without programming the second reference cell RC2.
  • FIGS. 12A and 12B show a determining method for step S42, as shown in FIG. 11.
  • the control section 70 verifies the second reference cell RC2 with a read threshold value READV that is lower than the refresh threshold value REFV.
  • the read threshold value READV is set to be greater than the threshold voltages of both the memory cell MC in the "1" state, and the first reference cell RCl, and smaller than the threshold voltages of both the memory cell MC in the "0" state with a charge loss, and the second reference cell RC2.
  • step S44 is proceeded to.
  • step S42 when the memory cell MC is to be programmed for the first time, the control section 70 programs the second reference cell RC2, i.e. step S44.
  • the program threshold value PRGV set by the third reference cell RC3 is used.
  • step S42 when the memory cell MC is not programmed for the first time, i.e. when programming the memory cell MC for the second time or more counting from after erasing, the control section 70 reads existing data, i.e. step S46, and refreshes the second reference cell RC2, i.e. step S48.
  • steps S22 and S24 respectively, as shown in FIG. 8.
  • the refresh threshold value REFV set by the fourth reference cell RC4 is used for the verification of the second reference cell RC2 in refreshing.
  • the refresh threshold value REFV is set lower than the program threshold value PRGV.
  • the second reference cell RC2 is set to the "0" state.
  • the control section 70 programs the program subjected cell PMC, i.e., step S50, and refreshes the refresh subjected cell RMC, i.e., step S52.
  • steps S44 or S48 the second reference cell RC2 is set to the "0" state.
  • the control section 70 programs the program subjected cell PMC, i.e., step S50, and refreshes the refresh subjected cell RMC, i.e., step S52.
  • FIGS. 13A to 13C show the changes in threshold voltages of the memory cells MC and the reference cells RC in accordance with the programming operation of the second embodiment.
  • FIG. 13A corresponds to a condition immediately after erasing data, i.e., completion of step SlO, as shown in FIG. 7. All of the memory cells MC, the first reference cell
  • FIG. 13B corresponds to a condition immediately after programming the second reference cell RC2, i.e., step S44, as shown in FIG. 11. All of the memory cells MC are in the "1" state.
  • the second reference cell RC2 is verified by the program threshold value PRGV and, therefore, is set higher than the threshold value of the program threshold value PRGV.
  • the reference threshold value REF is set in the middle of the first reference cell RCl and the second reference cell RC2.
  • FIG. 13C corresponds to a condition immediately after the programming operation of the memory cell MC, i.e., the end of the flowchart as shown in FIG. 11.
  • the threshold voltage of the memory cell MC in the "0" state i.e., the program subjected cell PMC
  • the threshold voltage of the storage region MC "1" in the "1" state on opposite side may be raised.
  • the reference threshold value REFV is higher than that of the first embodiment, i.e. FIG. 10D. Consequently, the read margin 50 of the "1" side can be sufficiently maintained, the same as in the first embodiment.
  • FIGS. 13A to 13C correspond to changes in the threshold voltages of the cells when programming the memory cell MC for the first time after erasing data.
  • FIGS. 13A to 13C correspond to changes in the threshold voltages of the cells when programming the memory cell MC for the first time after erasing data.
  • FIGS. 1OB to 1OD apply.
  • the mismatch of the threshold voltages between the memory cell MC and the second reference cell RC2 can be reduced, thereby improving the stability of data reading operations.
  • RC2 is not programmed in the erasing operation, thus the time required for the erasing operation can be cut down compared with that of the first embodiment.
  • the status of the second reference cell RC2 is determined with a read threshold value READV lower than the refresh threshold value REFV to verify (see FIGS. 12A and 12B). Therefore, even when the threshold value of the reference cell RC2 becomes lower than the refresh threshold value REFV, by a charge-loss over elapsed time after the second reference cell RC2 is programmed, the status of the second reference cell RC2, whether in the
  • the third reference cell RC3 setting the program threshold value PRGV
  • the fourth reference cell RC4 is provided in the external reference area 79.
  • step S42 the verification with the read threshold value READV
  • step S44 the verification with the program threshold value PRGV, i.e., step S44, or with the refresh threshold value REFV, i.e., step S48, can be continuously carried out.
  • a semiconductor device having a plurality of memory cells storing two bits of data in a cell by independently storing data in isolated storage regions in the cell; a first reference cell corresponding to an erased state of the storage region and being shared by the plurality of memory cells; a second reference cell corresponding to a programmed state of the storage region and being shared by the plurality of memory cells; and a control section carrying out data reading by creating a reference threshold value from threshold values of the first reference cell and the second reference cell and by comparing a threshold value of the storage region subject to data reading operations in the plurality of memory cells with the reference threshold value when reading data, programming with a first threshold value to verify when programming the second reference cell, refreshing with a second threshold value lower than the first threshold value to verify when refreshing the second reference cell, and programming at least one or more cells subject to programming in the plurality of memory cells with the threshold value of the second reference cell to verify and refreshing a cell subject to refresh in the pluralit
  • control section may be configured, when erasing data, to collectively erase the plurality of memory cells, the first reference cell, and the second reference cell and, thereafter, to program the second reference cell with the first threshold value to verify. According to this configuration, the time required for programming operation can be cut down.
  • control section may be configured to collectively erase the plurality of memory cells, the first reference cell, and the second reference cell when erasing data, and then to program the second reference cell with the first threshold value to verify when programming the plurality of memory cells for the first time
  • control section may be configured, when programming data, to verify the second reference cell with a third threshold value lower than the second threshold value, to program the second reference cell with the first threshold value to verify when the threshold value of the second reference cell is lower than the third threshold value, and to refresh the second reference cell with the second threshold value to verify when the threshold value of the second reference cell is higher than the third threshold value.
  • a third reference cell setting the first threshold value a fourth reference cell setting the second threshold value, and a fifth reference cell setting the third threshold value may be further provided.
  • the verification with the third threshold value can be carried out followed by the verification with the first threshold value or the second threshold value continuously.
  • the plurality of memory cells, the first reference cell, and the second reference cell may be structured to be provided on the same word line.
  • the first reference cell and the second reference cell may be structured to store two bits of data in a cell by independently storing data in two isolated storage regions in the cell, and configured to set one of the two storage regions to the programmed state and the other to the erased state. According to this configuration, the mismatch of threshold voltages between the memory cell and the reference cell can be further reduced, thereby further improving the stability of data reading operations.
  • a method for controlling a semiconductor device provided with a plurality of memory cells storing two bits of data in a memory cell by independently storing data in isolated regions in the memory cell, a first reference cell corresponding to an erased state of the plurality of memory cells, and a second reference cell corresponding to a programmed state of the plurality of memory cells, having the steps of creating a reference threshold value from threshold values of the first reference cell and the second reference cell, reading data by comparing a threshold value of the storage region subject to data reading in the plurality of memory cells with the reference threshold value, programming the second reference cell with a first threshold value to verify, refreshing the second reference cell with a second threshold value lower than the first threshold value to verify, programming at least one or more cells subject to programming in the plurality of memory cells with the threshold value
  • the threshold voltage of the second reference cell can be appropriately set and the mismatch of threshold voltages between the memory cell and the second reference cell can be reduced, thereby improving data reading stability.
  • the above-mentioned configuration may be further provided with an erasing step of collectively erasing the plurality of memory cells, the first reference cell, and the second reference cell, and the step of programming the second reference cell with the first threshold value to verify may be configured to be carried out when the erasing step is carried out. According to this configuration, the time required for a programming operation can be cut down.
  • the above-mentioned configuration may be further provided with an erasing step of collectively erasing the plurality of memory cells, the first reference cell, and the second reference cell, and the step of programming the second reference cell with the first threshold value to verify may be configured to be carried out when programming the plurality of memory cells for the first time after the erasing step. According to this configuration, the time required for an erasing operation can be cut down.

Abstract

A semiconductor device has a plurality of memory cells storing two bits of data in a cell, and a first reference cell (RCl) and a second reference cell (RC2) being shared by the plurality of memory cells. When programming the memory cell, programming a program subjected cell and refreshing a refresh subjected cell are both verified with a threshold value of the second reference cell corresponding to a programmed state of the memory cell. The second reference cell is programmed with a first threshold value (PRGV) to verify when programming, and is refreshed with a second threshold value (REFV) lower than the first threshold value to verify when refreshing.

Description

DESCRIPTION
SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF
TECHNICAL FIELD
The present invention relates to semiconductor devices and, more particularly, to a semiconductor device having a non-volatile memory cell capable of storing two bits of data in a cell.
BACKGROUND ART
In recent years, the development of a non- volatile semiconductor memory of a large capacity installed in a semiconductor device has been propelled. As one of the ways to make the capacity larger, a non-volatile memory cell capable of storing two bits of data in a cell has been developed. Further, a semiconductor device adopting a method for reading data by comparing a threshold voltage of a memory cell with a reference threshold voltage created from two reference cells related to the memory cell, hereinafter referred to as "dynamic reference method", has been developed.
WO2004-097839 Al discloses a non-volatile memory used in the dynamic reference method in related art with an improved data reading. Japanese Patent Application Publication No. JP-A-2002-334589 discloses a non-volatile memory provided with an inspection cell inspecting a threshold voltage of a reference cell that is referenced when reading data. Japanese Patent Application Publication No. JP-A-2003-257188 discloses a configuration, in a nonvolatile memory in dynamic reference method, to set a threshold value of a second reference cell in accordance with a threshold value of a first reference cell.
In a non-volatile memory capable of storing two bits of data in a cell, there has been a problem in that, when reading data with the dynamic reference method in related art, a mismatch of threshold voltages between a reference cell and a memory cell may occur, resulting in data read instability.
SUMMARY OF THE INVENTION
In order to solve the problem described above, it is an object of the present invention to provide a semiconductor device which eliminates the mismatch of the threshold voltages between the memory cell and the reference cell, thereby improving data reading stability, and a method for controlling the same.
AF02584WO According to an aspect of the present invention, there is provided a semiconductordevice having a plurality of memory cells storing two bits of data in a cell by independently storing data in isolated storage regions in the cell; a first reference cell corresponding to an erased state of the storage region and being shared by the plurality of memory cells; a second reference cell corresponding to a programmed state of the storage region and being shared by the plurality of memory cells; and a control section carrying out data read operations by creating a reference threshold value from threshold values of the first reference cell and the second reference cell and by comparing a threshold value of the storage region subject to data reading in the plurality of memory cells with the reference threshold value when reading data, programming with a first threshold value to verify when programming the second reference cell, refreshing with a second threshold value lower than the first threshold value to verify when refreshing the second reference cell, and programming at least one or more cells subject to programming in the plurality of memory cells with the threshold value of the second reference cell to verify and refreshing a cell subject to refresh in the plurality of memory cells with the threshold value of the second reference cell to verify when programming the plurality of the memory cells.
According to another aspect of the present invention, there is provided a method for controlling a semiconductor device provided with a plurality of memory cells storing two bits of data in a memory cell by independently storing data in isolated regions in the memory cell, a first reference cell corresponding to an erased state of the plurality of memory cells, and a second reference cell corresponding to a programmed state of the plurality of memory cells, having the steps of creating a reference threshold value from threshold values of the first reference cell and the second reference cell, reading data by comparing a threshold value of the storage region subject to data read in the plurality of memory cells with the reference threshold value, programming the second reference cell with a first threshold value to verify, refreshing the second reference cell with a second threshold value lower than the first threshold value to verify, programming at least one or more cells subject to programming in the plurality of memory cells with the threshold value of the second reference cell to verify, and refreshing a cell subject to refresh in the plurality of memory cells with the threshold value of the second reference cell to verify.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. IA to ID are cross-sectional views (part 1) schematically showing the configuration of a memory cell in related art and that in embodiments of the present invention;
AF02584WO FIGS. 2 A to 2D are cross-sectional views (part 2) schematically showing the ■configuration of the memory cell in related art and that in the embodiments of the present invention;
FIG. 3A is a schematic circuit diagram showing the configuration of a semiconductor device in related art, and FIG. 3B is a graph showing threshold voltages of each cell shown in FIG. 3A;
FIG. 4A is a cross-sectional view schematically showing the configuration of the semiconductor device in related art, and FIGS. 4B and 4C are graphs showing threshold voltages of each cell shown in FIG. 4A; FIGS. 5 A and 5B are graphs showing threshold voltages of each cell of the semiconductor device in related art;
FIG. 6 is a block diagram showing the configuration of a semiconductor device of a first embodiment of the present invention;
FIG. 7 is a flowchart showing an erasing operation of the semiconductor device of the first embodiment;
FIG. 8 is a flowchart showing programming operation of the semiconductor device of the first embodiment;
FIG. 9 is a flowchart showing reading operation of the semiconductor device of the first embodiment; FIGS. 1OA to 1OD show changes in threshold voltages of each of cells according to the programming operation of the first embodiment;
FIG. 11 is a flowchart showing programming operation of a semiconductor device of a second embodiment of the present invention;
FIGS. 12A and 12B show operation determination from step S42, as shown in FIG. 11; and
FIGS. 13A to 13C show the changes in threshold voltages of each of cells in programming operation of the second embodiment.
DETAILED DESCRIPTION First, the problem to be solved by the present invention will be clarified. With reference to FIG. IA, the configuration of a non-volatile memory cell MC capable of storing two bits of data in a cell will be described. On a surface of a semiconductor substrate 10 composed of e.g., silicon, by a diffusion process, a source region 14 and a drain region 12 that are input/output terminals are formed. Above the region in between the source region 14 and the drain region 12, a gate 16 that is a control terminal is formed. Between the gate 16 and the semiconductor
AF02584WO substrate 10, an ONO film 24 (i.e., a multilayered film including an oxide film, a nitride film, • and an oxide film), composed of an interlayer insulating film 18, a trap layer 20, and a gate insulating film 22 is formed. The interlayer insulating film 18 and the gate insulating film 22 are oxide films composed of, e.g., silicon oxide, and the trap layer 20 is a nitride film composed of, e.g., silicon nitride.
The memory cell MC stores data by changes in threshold voltage caused by injecting electrical charges into the trap layer 20 (i.e., programming), or withdrawing the electrical charges from the trap layer 20 (i.e., erasing). The trap layer 20 is an insulator, thus the injected electrical charges remain in the same place without moving. Therefore, data can be independently stored in isolated regions in the trap layer 20. With reference to FIG. IA, the trap layer 20 has a first storage region 30 and a second storage region 32, and each region can store one bit data each. As for the memory cell MC, two bits of data in a cell can be stored.
With reference to FIG. IA, when programming the first storage region 30, while the gate 16 and the drain region 12 are set to a high potential and the source region 14 is set to a low potential, electrical charges 34 (i.e., electrons), are injected in a direction of an arrow by hot electron injection. With reference to FIG. IB, when erasing data in the first storage region 30, while the gate 16 is set to a low potential and the drain region 12 to a high potential, the electrical charges 34 are withdrawn in a direction of an arrow by hot hole injection.
The data in the first storage region 30 is read out by switching around the drain region 12 and the source region 14, applying voltages thereto in a reverse direction, and applying a voltage lower than that used in programming to the gate 16. With reference to FIG. 1C, when the first storage region 30 is in a programmed state in which the electrical charges 34 are injected, the threshold voltage is in a high state and the current flowing towards an arrow direction is blocked in the vicinity of the first storage region 30 where marked x in the drawing, thus a logic value of "0" is read. On the contrary, with reference to FIG. ID, when the first storage region 30 is in an erased state in which the electrical charges 34 are being not injected, the threshold voltage is in a low stage and the current flows in an arrow direction, thus a logic value of "1" is read.
As described above, programming, erasing and reading data to or from the first storage region 30 of the memory cell MC can be carried out. These operations for the second storage region 32 can be carried out in similar manners to the respective operations of programming, erasing and reading the first storage region 30, by switching around the drain region 12 and the source region 14 and reversing the direction of the voltages applied.
The memory cell MC independently stores one bit of data to the first storage region 30 and one bit of data in the second storage region 32, thus providing four states as shown in FIGS. 2A to 2D. With reference to FIG. 2A, the state in which both the first storage region 30 and the
AF02584WO second storage region 32 are in erased state, i.e., a logic value of "1", is defined as "11". With •reference to FIG. 2B, the state in which both the first storage region 30 and the second storage region 32 are in programmed state, i.e., a logic value of "0", is defined as "00". With reference to FIG. 2C, the state in which the first storage region 30 is in the erased state and the second storage region 32 is in the programmed state is defined as "10". With reference to FIG. 2D, the state in which the first storage region 30 is in the programmed state and the second storage region 32 is in the erased state is defined as "01".
"Programming" herein means to inject electrical charges to the storage region in the erased state "1" and to raise the threshold voltage to that of the programmed state "0". Meanwhile, a later described "refreshing" means to inject electrical charges again, out of the storage regions in the programmed state "0" already, to the storage region in which the threshold voltage is lowered so as to restore the threshold voltage.
Next, data reading with the dynamic reference method will be described. With reference to FIG. 3A, a plurality of memory cells MC provided on a word line WL shares a first reference cell RCl and a second reference cell RC2 for data read operations. With reference to FIG. 3B, the threshold value of the first reference cell RCl corresponds to the erased state MC "1" of the memory cell MC. The threshold value of the second reference cell RC2 corresponds to the programmed state MC "0" of the memory cell MC. The reference threshold value REF created by averaging the threshold values of the first reference cell RCl and the second reference cell RC2 is situated in the middle of MC "1" and MC "0". By comparing the reference threshold value REF with the threshold values of MC "1" and MC "0" of the memory cell MC, data reading can be carried out.
In the dynamic reference method, whenever one of the memory cells MC is erased, all of the memory cells MC, the first reference cell RCl, and the second reference cell RC2 coupled on the same word line WL are simultaneously erased. Further, whenever one of the memory cells MC is programmed, the memory cell MC in the programmed state out of all of the memory cells MC, and the second reference cell RC2 coupled on the same word line WL are refreshed. Consequently, characteristics of cells, such as changes in characteristics of charge loss and charge gain from deterioration, of the memory cells MC, the first reference cell RCl, and the second reference cell RC2 can be coordinated, thus data reading can be stably carried out continuously.
Next, a non-volatile memory in the dynamic reference method in related art with an improved data reading will be described. FIG.4A is a cross-sectional view schematically showing the refreshing operation of the "0" side of the memory cell MC in the "10" state. In the second storage region 32, i.e., the "0" side, the electrical charges 34 are already injected. When
AF02584WO electrical charges are further injected in an arrow direction by the voltage applied in refreshing, ''the second storage region 32 enters an over-programmed state due to excess electrical charges. As a result, as shown by an arrow in FIG. 4B, the threshold voltage MC "1" of the first storage region 30 on the opposite side, which is in the "1" state rises, thereby making a "read margin" 50 with the reference threshold value REF small. The result is unstable data reading.
Therefore, as shown in FIG. 4C, when programming new data, a program threshold value PRGV, i.e., a first threshold value, is used to verify and, when refreshing existing data, a refresh threshold value REFV (i.e., a second threshold value), lower than the program threshold value PRGV is used to verify. Consequently, the threshold voltages after programming are distributed as PMC "0" and PRC 2. The threshold voltages after refreshing are distributed as RMC "0" and RRC 2. According to this configuration, when refreshing, the injection of electrical charges is not carried out to the storage regions where charge loss is small, thus over-programming on the "0" side of the second storage region 32 and the resultant rise in the threshold voltage on the "1" side of the first storage region 30 can be prevented. With reference to FIG. 5 A, in the above-mentioned configuration, when refreshing the
"0" side of the memory cell MC in the "10" state, since verification is carried out with the refresh threshold value REFV, the threshold voltage MC "1" on the "1" side is hardly raised, thus a sufficient read margin 50 can be ensured. However, with reference to FIG. 5B, when programming (i.e., writing new data), one side of the memory cell MC in the "11" state, since verification is carried out with the program threshold value PRGV higher than the refresh threshold value REFV, the threshold voltage MC "1" of the other "1" side is raised (see an arrow in the drawing), and a sufficient read margin 50 may not be ensured. This is particularly seen when programming a memory cell MC which has been left standing for a long time after erasure. A mismatch of the threshold voltages between the reference cells RC and the memory cell MC is likely to occur, making data reading unstable.
In order to solve the problems described above, according to an aspect of the present invention, there is provided a semiconductor device which eliminates the mismatch of the threshold voltages between the memory cell and the reference cell, thereby making data reading stable, and a method for controlling the same. Now, with reference to accompanying drawings, embodiments of the present invention will be described below. [First Embodiment]
FIG. 6 is a block diagram showing the configuration of a semiconductor device of a first embodiment of the present invention. A memory cell array 60 containing storage regions is composed of a memory cell area 62 for storing data, and a dynamic reference area 64 for storing
AF02584WO references. The memory cell array 60 is provided with a plurality of bit lines BL in a first ■ direction and a plurality of word lines WL in a second direction crossing the first direction. On a single word line WL, e.g., WLl, respective control terminals of a plurality of memory cells MC are coupled in the memory cell area 62, and respective control terminals of a first reference cell RCl and a second reference cell RC2 are coupled in the dynamic reference area 64. More specifically, a memory cell row MCR composed of the plurality of memory cells MC are provided on the same word line as the first reference cell RCl and the second reference cell RC2, sharing the RCl and the RC2. Input/output terminals for the memory cells MC and the reference cells RC are respectively coupled with two adjacent bit lines BL. The memory cells MC, the first reference cell RCl , and the second reference cell RC2 are structured the same as the memory cell MC shown in FIG. IA, and are capable of storing two bits of data in a cell by independently storing data in isolated regions, i.e. the first storage region 30 and the second storage region 32, in the cell. The first reference cell RCl corresponds to the erased state of the memory cell MC and is set to a threshold voltage equivalent to the storage region in the "1" state of the storage regions in the memory cell MC. The second reference cell RC2 corresponds to the programmed state of the memory cell MC and is set to a threshold voltage equivalent to the storage region in the "0" state of the storage regions in the memory cell MC.
With reference to FIG. 6, the bit lines BL of the memory cell array 60 are coupled with a column address decoder 66, and the word lines WL are coupled with a row address decoder 68. The column address decoder 66 and the row address decoder 68 select the memory cells MC or the reference cells RC according to an address signal provided from the outside via an address buffer 72. Further, the column address decoder 66 and the row address decoder 68 apply voltages for programming, refreshing, erasing and data reading supplied from a voltage supply circuit 74 to the bit lines BL and the word line WL corresponding to the selected memory cells MC and the reference cells RC.
A write/read circuit 76, via an internal sense amplifier (not shown), reads or verifies data by comparing a signal output from the memory cell area 62 or the dynamic reference area 64 with a reference signal output from the dynamic reference area 64 or an external reference area 79, and outputs the result to a data latch 77. Further, when programming, the write/read circuit 76 feeds data entered from the data latch 77 to the memory cell array 60. The data latch 77 outputs data entered from the write/read circuit 76 to the I/O circuit 78 and the control section 70. The I/O circuit 78 exchanges data with the outside.
The control section 70 controls operations of programming, erasing and data reading for the memory cell array 60 by controlling the address buffer 72 and the voltage supply circuit 74
AF02584WO corresponding to commands from the outside and input data from the data latch 77. Particularly, when programming and refreshing data as described later, the control section 70 selects the reference cell used to verify and, based on the result of verification in the write/read circuit 76, controls voltages to be applied to the cells. Outside the memory cell array 60, the external reference area 79 is provided. The external reference area 79 includes a third reference cell RC3 setting a first threshold voltage of the program threshold value PRGV, a fourth reference cell RC4 setting a second threshold voltage of the refresh threshold value REFV, and a fifth reference cell RC5 setting a third threshold voltage of a read threshold value READV. The outputs from these reference cells are fed to the write/read circuit 76 and are referenced when programming or refreshing the second reference cell RC2.
With reference to FIG. 7, an erasing operation of the semiconductor device of the first embodiment will be described. First, the control section 70 collectively erases the plurality of memory cells MC, the first reference cell RCl, and the second reference cell RC2 coupled on the same word line WL (step SlO). More specifically, the word line WL coupled with the memory cells MC subject to erase is set to a low potential and all bit lines BL are set to a high potential to withdraw electrical charges from the memory cells MC by injecting hot holes as shown in FIG. IB. Consequently, all of the memory cells MC subject to erase, the first reference cell RCl, and the second reference cell RC2 are set in the "1 1" state. Next, the control section 70 programs the second reference cell RC2 (step S 12).
Consequently, at least one of the storage regions of the second reference cell RC2 enters the "0" state, corresponding to the programmed state of the memory cell MC. Meanwhile, at least one of the storage regions of the first reference cell RCl is set to be in the "1" state, corresponding to the erased state of the memory cell MC. The second reference cell RC2 is verified with the program threshold value PRGV set by the third reference cell RC3 in programming. The program threshold value PRGV is set higher than the later described refresh threshold value REFV. As described above, in the first embodiment, programming to the second reference cell RC2 is carried out in the course of the erasing operation.
A programming operation of the semiconductor device of the first embodiment will be described. The semiconductor device of the first embodiment employs the same dynamic reference method as that in related art described with reference to FIGS. 3A and 3B. More specifically, with reference to FIG. 6, when programming the memory cell MC in the erased state (i.e., the "1" state), included in the memory cell row MCR, all of the memory cells MC already in the programmed state (i.e., the "0" state), in the memory cell row MCR are simultaneously refreshed. The second reference cell RC2 is also refreshed at the same time.
AF02584WO Here, out of the plurality of memory cells MC, the memory cell MC subject to programming is ■ defined as a program subjected cell PMC. The memory cell MC subject to refresh that is already in the programmed state is defined as a refresh subjected cell RMC. When programming, at least one or more of the memory cells MC become a program subjected cell PMC. FIG. 8 is a flowchart showing the programming operation of the semiconductor device of the first embodiment. With reference to FIGS. 6 and 8, the control section 70 first enters new data to be stored in the program subjected cell PMC (step S20). More specifically, the control section 70 stores the new data in the data latch 77 via the I/O circuit 78. The control section 70 then reads data already stored in the refresh subjected cell RMC (step S22). Here, reading data is carried out by the dynamic reference method shown in FIG. 9.
FIG. 9 is a flowchart showing a reading operation of the semiconductor device of the first embodiment. With reference to FIGS. 6 and 9, the control section 70 first obtains the threshold value of the first reference cell RCl (step S30). Specifically, out of the storage regions of the first reference cell RCl, the threshold voltage of the storage region set in the erased state "1" is obtained as a current signal or a voltage signal. The control section 70 then obtains the threshold value of the second reference cell RC2 (step S32). Specifically, out of the storage regions of the second reference cell RC2, the threshold voltage of the storage region set in the programmed state "0" is obtained as a current signal or a voltage signal.
Then, the control section 70 determines, from the threshold values obtained in steps S30 and S32, the reference threshold value REF (step S34). The reference threshold value REF in the first embodiment is an average value of the threshold voltage of the first reference cell RCl and the threshold voltage of the second reference cell RC2. The reference threshold value REF may be calculated in other ways so long as it is equivalent to the threshold voltage between the erased state and the programmed state of the memory cell MC. For example, a weighted mean average of the threshold voltage of the first reference cell RCl and the threshold voltage of the second reference cell RC2 may be used.
The control section 70 then obtains the threshold value of the memory cell MC subject to data reading (step S36). Specifically, out of the storage regions of the memory cell MC subject to data reading, the threshold voltage of the storage region subject to read is obtained as a current signal or a voltage signal. The control section 70 inputs both the threshold value of the memory cell MC and the reference threshold value REF created in step S34 to the write/read circuit 76 shown in FIG. 6.
Next, the control section 70 directs the write/read circuit 76 to compare the threshold value of the memory cell MC obtained in step S36 with the reference threshold value REF created in step S34 (step S38). When the threshold value of the memory cell MC is greater than
AF02584WO the reference threshold value REF, the reading result is "0". When the threshold value of the memory cell MC is smaller than the reference threshold value REF, the reading result is "1". Finally, the control section 70 outputs the comparison result (step S39). More specifically, the control section 70 directs the write/read circuit 76 to output the comparison result to the data latch 77. Further, the control section 70 provides data output to the outside from the data latch 76 via the I/O circuit 78. This completes the data reading operation.
With reference to FIGS. 6 and 8 again, in step S22, the control section 70 stores the data read from the refresh subjected cell RMC in the data latch 77. The control section 70 then refreshes the second reference cell RC2 (step S24). The second reference cell RC2 is verified with the refreshing threshold value REFV set by the fourth reference cell RC4 in refreshing. The refresh threshold value REFV is set lower than the program threshold value PRGV. Therefore, when the charge loss in the storage region (in the "0" state) of the second reference cell RC2 is small, electrical charges are not injected again, thereby preventing the storage region in the "0" state from over-programming. Consequently, the threshold voltage of the second reference cell RC2 can be maintained at an appropriate level.
Next, the control section 70 programs the new data to the program subjected cell PMC (step S26). Specifically, the control section 70 programs the program subjected cell PMC, with the new data stored in the data latch 77 in step S20, by applying a voltage thereto via the voltage supply circuit 74. The program subjected cell PMC is verified with the threshold value of the second reference cell RC2 refreshed in step S24 in programming.
The control section 70 then refreshes existing data in the refresh subjected cell RMC (step S28). Specifically, the control section 70 refreshes the refresh subjected cell RMC, with the existing data stored in the data latch 77 in step S22, by applying a voltage thereto via the voltage supply circuit 74. The refresh subjected cell RMC is verified with the threshold value of the second reference cell RC2 refreshed in step S24 in refreshing. Steps S26 and S28 may be carried out at the same time. This completes the operation of programming data.
FIGS. 1OA to 1OD show changes in threshold voltages of the memory cells MC and the reference cells RC in accordance with the programming operation of the first embodiment. FIG. 1OA corresponds to a condition immediately after the operation of erasing data, i.e., the end of the flowchart shown in FIG. 7. The threshold voltage of the second reference cell RC2 is in a state higher than the program threshold value PRGV. The threshold voltages of both the first reference cell RCl and the memory cells MC are in the erased state.
FIG. 1OB corresponds to a condition immediately before the data programming operation, i.e., the start of the flowchart shown in FIG. 8. The threshold voltage of the second reference cell RC2 is lowered by the charge loss with elapsed time, and may sometimes become
10 AF02584WO lower than the refresh threshold value REFV (see a solid arrow in the drawing). The threshold voltages of the first reference cell RCl and the memory cell MC in the "1" state are about the same as those shown in FIG. 1OA. The reference threshold value REF is the average of the threshold voltages of the first reference cell RCl and the second reference cell RC2, and is lowered in accordance with the lowering of the threshold voltage of the second reference cell
RC2 (see a broken arrow in the drawing). Therefore, the read margin 50 for the storage region in the "1" state is smaller than that shown in FIG. 1OA. The threshold voltage of the memory cell MC in the "0" state is similarly distributed to that of the second reference cell RC2.
FIG. 1OC corresponds to a condition immediately after refreshing the second reference cell RC2, i.e., the completion of step S24 shown in FIG. 8. The threshold voltage of the second reference cell RC2 is raised by refreshing, and is distributed in a higher area than the refresh threshold value REFV (see a solid arrow in the drawing). Further, the reference threshold value REF is raised in accordance with the refreshing of the second reference cell RC2, see a broken arrow in the drawing, and the read margin 50 for the storage region in the "1" state is greater than that shown in FIG. 1 OB .
FIG. 1OD corresponds to a condition immediately after the programming operation, i.e., the end of the flowchart shown in FIG. 8. The threshold voltage of the refresh subjected cell RMC in the "0" state shown in FIG. 1OC is restored by refreshing, see an arrow in the drawing. Further, the threshold voltage of the program subjected cell PMC in the "1" state shown in FIG. 1OC is raised by the programming. Since both the refresh subjected cell RMC and the program subjected cell PMC are verified with the threshold voltage of the second reference cell RC2 (see steps S26 and S28 shown in FIG. 8), the threshold voltages of the memory cells MC "0" after programming or after refreshing are distributed in areas higher than the threshold voltage of the second reference cell RC2, thereby preventing over-programming. Consequently, the threshold voltage of the storage region MC "1" on the opposite side is hardly raised.
With reference to FIG. 8, according to the semiconductor device of the first embodiment, when programming new data, the second reference cell RC2 is first refreshed with the refresh threshold value REFV lower than the program threshold value PRGV to verify, i.e. step S24, and then, with the threshold voltage of the reference cell RC2 after the refresh step to verify, the memory cells MC are programmed, i.e., step S26, and refreshed, i.e., step S28. Therefore, with reference to FIG. 10D, in the program subjected cell PMC and the refresh subjected cell RMC, the storage regions MC "0" subject to program or subject to refresh can be prevented from over programming, and the threshold value of the storage region MC "1" on opposite side can be prevented from being raised. All of the memory cells MC are verified with the same threshold value of the second reference cell RC2, thereby preventing a mismatch of the threshold voltages
11 AF02584WO between the memory cells MC and the second reference cell RC2. Consequently, compared with the example in related art shown in FIG. 5B, the read margin 50 between the threshold value of the memory cell MC "1" in the "1" state and the reference threshold value REF can be made greater. In the erasing operation, the program threshold value PRGV is used to verify when programming the second reference cell RC2 (see step S12, as shown in FIG. 7), and in the programming operation, the refresh threshold value REFV, now lower than the program threshold value PRGV, is used to verify when refreshing the second reference cell RC2 (see step S24 as shown in FIG. 8). Consequently, with reference to FIG. 1OC, when refreshing the second reference cell RC2, the storage region subject to refresh can be prevented from over- programming and the threshold value of the storage region on the opposite side can be prevented from being raised, thereby appropriately setting the threshold voltage of the second reference cell RC2.
As described above, according to the semiconductor device of the first embodiment, the threshold voltage of the second reference cell RC2 can be appropriately set and the mismatch of the threshold voltages between the memory cell MC and the second reference cell RC2 reduced, thereby improving data reading stability.
In the first embodiment, provided in the external reference area 79, are the third reference cell RC3 for setting the program threshold value PRGV and the fourth reference cell RC4 for setting the refresh threshold value REFV. Therefore, the second reference cell RC2 can be verified with either the program threshold value PRGV or the refresh threshold value REFV.
With reference to FIG. 6, in the first embodiment, the memory cells MC, the first reference cell RCl, and the second reference cell RC2 are provided on the same word line WL. According to this structure, by selecting a single word line WL, all related cells MC, RCl and RC2 can be selected, thereby facilitating the control. However, the above structure is not an essential constituent factor of the first embodiment and, as long as the first reference cell RCl and the second reference cell RC2 are shared by a plurality of memory cells MC, other structures may be used. More specifically, when reading data from the memory cell MC, the data is to be read in the dynamic reference method by comparing the reference threshold value REF created from the first reference cell RC 1 and the second reference cell RC2 with the threshold value of the memory cell MC. For example, it is possible to provide the first reference cell RCl and the second reference cell RC2 outside the memory cell array 60.
It is preferable to be configured so that both the first reference cell RCl and the second reference cell RC2 are set in the "10" state, see FIG. 2C. When reading data, the threshold voltage of the "1" side is obtained from the first reference cell RCl, i.e., step S30 as shown in
12 AF02584WO FIG. 9, and the threshold voltage of the "0" side is obtained from the second reference cell RC2, ■ i.e., step S32 as shown in FIG. 9. According to this configuration, the mismatch of the threshold voltages between the memory cell MC in the "10" state and the reference cells RC can be further reduced, thereby further improving data reading stability. With reference to FIG. 7, in the erasing operation, while programming the second reference cell RC2, i.e., step S12, is to be carried out after collectively erasing the memory cells MC and the reference cells RC, i.e., step SlO, as a part of the erasing operation, it is preferable that the programming operation be carried out immediately after the collective erasing. [Second Embodiment] A second embodiment of the present invention is an embodiment for programming the second reference cell RC2 at the same time as the memory cell MC is programmed for the first time after erasing data, not programming the second reference cell RC2 at the time of erasing data. The configuration and data reading operation of the semiconductor device of the second embodiment are the same as those, i.e., FIGS. 6 and 9, of the first embodiment. FIG. 11 is a flowchart showing a programming operation of the semiconductor device of the second embodiment. First, the control section 70 (see FIG. 6), enters new data to be stored in the program subjected cell PMC (step S40). More specifically, the control section 70 stores the new data in the data latch 77 via the I/O circuit 78.
The control section 70 then determines whether programming to the memory cell MC is the first time or not (step S42). Here, "first time" means when the memory cell MC is programmed for the first time counting from after erasing the memory cells MC and the reference cells RC. The erasing operation of the second embodiment is the same as that of the first embodiment. In other words, a plurality of memory cells MC, the first reference cell RCl, and the second reference cell RC2 coupled on the same word line WL are collectively erased (see step SlO, as shown in FIG. 7). Thereafter, the erasing operation is finished without programming the second reference cell RC2.
FIGS. 12A and 12B show a determining method for step S42, as shown in FIG. 11. The control section 70 verifies the second reference cell RC2 with a read threshold value READV that is lower than the refresh threshold value REFV. The read threshold value READV is set to be greater than the threshold voltages of both the memory cell MC in the "1" state, and the first reference cell RCl, and smaller than the threshold voltages of both the memory cell MC in the "0" state with a charge loss, and the second reference cell RC2.
With reference to FIG. 12A, when programming the memory cell MC for the first time after erasing, all of the memory cells MC are in the "1" state and both the first reference cell RCl and the second reference cell RC2 are also in the "1" state. More specifically, when the
13 AF02584WO threshold voltage of the second reference cell RC2 is lower than the read threshold value READV, the control section 70 determines that the memory cell MC is programmed for the first time, and step S44 is proceeded to.
On the contrary, with reference to FIG. 12B, when the memory cell MC is to be programmed for the second time or more after erasing, the second reference cell RC2 and some of the memory cells MC are in the "0" state. More specifically, when the threshold voltage of the second reference cell RC2 is higher than the read threshold value READV, the control section 70 determines that the memory cell MC is to be programmed for the second time or more, and step S46 is proceeded to. With reference to FIGS. 6 and 11 again, in step S42, when the memory cell MC is to be programmed for the first time, the control section 70 programs the second reference cell RC2, i.e. step S44. Therefore, at least one of the storage regions in the second reference cell RC2 enters the "0" state, corresponding to the programmed state of the memory cell MC. For the verification of the second reference cell RC2 in programming, the program threshold value PRGV set by the third reference cell RC3 is used.
In step S42, when the memory cell MC is not programmed for the first time, i.e. when programming the memory cell MC for the second time or more counting from after erasing, the control section 70 reads existing data, i.e. step S46, and refreshes the second reference cell RC2, i.e. step S48. These operations are the same as those of the first embodiment, i.e. the same as steps S22 and S24 respectively, as shown in FIG. 8. For the verification of the second reference cell RC2 in refreshing, the refresh threshold value REFV set by the fourth reference cell RC4 is used. The refresh threshold value REFV is set lower than the program threshold value PRGV.
In steps S44 or S48, the second reference cell RC2 is set to the "0" state. Next, the control section 70, with the threshold voltage of the second reference cell RC2 to verify, programs the program subjected cell PMC, i.e., step S50, and refreshes the refresh subjected cell RMC, i.e., step S52. These operations are the same as those of the first embodiment, i.e., the same as steps S26 and S28 respectively, as shown in FIG. 8. This completes the programming operation of the semiconductor device of the second embodiment. When the memory cell MC is programmed for the first time, since no refresh subjected cell RMC exists, the refreshing, i.e., step S52, is not carried out.
The FIGS. 13A to 13C show the changes in threshold voltages of the memory cells MC and the reference cells RC in accordance with the programming operation of the second embodiment. FIG. 13A corresponds to a condition immediately after erasing data, i.e., completion of step SlO, as shown in FIG. 7. All of the memory cells MC, the first reference cell
14 AF02584WO RCl, and the second reference cell RC2 are in the "1" state, and the threshold voltages are lower than the read threshold value READV.
FIG. 13B corresponds to a condition immediately after programming the second reference cell RC2, i.e., step S44, as shown in FIG. 11. All of the memory cells MC are in the "1" state. The second reference cell RC2 is verified by the program threshold value PRGV and, therefore, is set higher than the threshold value of the program threshold value PRGV. The reference threshold value REF is set in the middle of the first reference cell RCl and the second reference cell RC2.
FIG. 13C corresponds to a condition immediately after the programming operation of the memory cell MC, i.e., the end of the flowchart as shown in FIG. 11. The threshold voltage of the memory cell MC in the "0" state (i.e., the program subjected cell PMC), is distributed to an area higher than the second reference cell RC2 being verified with the program threshold value
PRGV. Therefore, the threshold voltage of the storage region MC "1" in the "1" state on opposite side may be raised. However, in the second embodiment, since the second reference cell RC2 is verified with the program threshold value PRGV in programming, the reference threshold value REFV is higher than that of the first embodiment, i.e. FIG. 10D. Consequently, the read margin 50 of the "1" side can be sufficiently maintained, the same as in the first embodiment.
FIGS. 13A to 13C correspond to changes in the threshold voltages of the cells when programming the memory cell MC for the first time after erasing data. When programming the memory cell MC for the second time or more after erasing data, the same drawings shown in
FIGS. 1OB to 1OD apply.
According to the second embodiment, as in the first embodiment, the mismatch of the threshold voltages between the memory cell MC and the second reference cell RC2 can be reduced, thereby improving the stability of data reading operations. The second reference cell
RC2 is not programmed in the erasing operation, thus the time required for the erasing operation can be cut down compared with that of the first embodiment.
In the second embodiment, the status of the second reference cell RC2 is determined with a read threshold value READV lower than the refresh threshold value REFV to verify (see FIGS. 12A and 12B). Therefore, even when the threshold value of the reference cell RC2 becomes lower than the refresh threshold value REFV, by a charge-loss over elapsed time after the second reference cell RC2 is programmed, the status of the second reference cell RC2, whether in the
"1" or "0" state, can be correctly determined.
In the second embodiment, provided in the external reference area 79 are the third reference cell RC3 setting the program threshold value PRGV, the fourth reference cell RC4
15 AF02584WO setting the refresh threshold value REFV, and the fifth reference cell RC5 setting the read ' threshold value READV. Therefore, with reference to FIG. 11, following the verification with the read threshold value READV (i.e., step S42, as shown in FIG. 12), the verification with the program threshold value PRGV, i.e., step S44, or with the refresh threshold value REFV, i.e., step S48, can be continuously carried out.
Finally, several aspects of the present invention are summarized below. According to an aspect of the present invention, there is provided a semiconductor device having a plurality of memory cells storing two bits of data in a cell by independently storing data in isolated storage regions in the cell; a first reference cell corresponding to an erased state of the storage region and being shared by the plurality of memory cells; a second reference cell corresponding to a programmed state of the storage region and being shared by the plurality of memory cells; and a control section carrying out data reading by creating a reference threshold value from threshold values of the first reference cell and the second reference cell and by comparing a threshold value of the storage region subject to data reading operations in the plurality of memory cells with the reference threshold value when reading data, programming with a first threshold value to verify when programming the second reference cell, refreshing with a second threshold value lower than the first threshold value to verify when refreshing the second reference cell, and programming at least one or more cells subject to programming in the plurality of memory cells with the threshold value of the second reference cell to verify and refreshing a cell subject to refresh in the plurality of memory cells with the threshold value of the second reference cell to verify when programming the plurality of the memory cells. With this structure, the threshold voltage of the second reference cell can be appropriately set and the mismatch of the threshold voltages between the memory cell and the second reference cell can be reduced, thereby improving data reading stability.
In the above-mentioned structure, the control section may be configured, when erasing data, to collectively erase the plurality of memory cells, the first reference cell, and the second reference cell and, thereafter, to program the second reference cell with the first threshold value to verify. According to this configuration, the time required for programming operation can be cut down.
In the above-mentioned structure, the control section may be configured to collectively erase the plurality of memory cells, the first reference cell, and the second reference cell when erasing data, and then to program the second reference cell with the first threshold value to verify when programming the plurality of memory cells for the first time
16 AF02584WO after the erasing. According to this configuration, the time required for an erasing operation can be cut down.
In the above mentioned structure, the control section may be configured, when programming data, to verify the second reference cell with a third threshold value lower than the second threshold value, to program the second reference cell with the first threshold value to verify when the threshold value of the second reference cell is lower than the third threshold value, and to refresh the second reference cell with the second threshold value to verify when the threshold value of the second reference cell is higher than the third threshold value. According to this configuration, the time required for an erasing operation can be cut down.
In the above-mentioned structure, a third reference cell setting the first threshold value, a fourth reference cell setting the second threshold value, and a fifth reference cell setting the third threshold value may be further provided. According to this structure, the verification with the third threshold value can be carried out followed by the verification with the first threshold value or the second threshold value continuously.
In the above-mentioned structure, the plurality of memory cells, the first reference cell, and the second reference cell may be structured to be provided on the same word line.
In the above-mentioned structure, the first reference cell and the second reference cell may be structured to store two bits of data in a cell by independently storing data in two isolated storage regions in the cell, and configured to set one of the two storage regions to the programmed state and the other to the erased state. According to this configuration, the mismatch of threshold voltages between the memory cell and the reference cell can be further reduced, thereby further improving the stability of data reading operations.
According to another aspect of the present invention, there is provided a method for controlling a semiconductor device provided with a plurality of memory cells storing two bits of data in a memory cell by independently storing data in isolated regions in the memory cell, a first reference cell corresponding to an erased state of the plurality of memory cells, and a second reference cell corresponding to a programmed state of the plurality of memory cells, having the steps of creating a reference threshold value from threshold values of the first reference cell and the second reference cell, reading data by comparing a threshold value of the storage region subject to data reading in the plurality of memory cells with the reference threshold value, programming the second reference cell with a first threshold value to verify, refreshing the second reference cell with a second threshold value lower than the first threshold value to verify, programming at least one or more cells subject to programming in the plurality of memory cells with the threshold value
17 AF02584WO of the second reference cell to verify, and refreshing a cell subject to refresh in the plurality of memory cells with the threshold value of the second reference cell to verify. With this structure, the threshold voltage of the second reference cell can be appropriately set and the mismatch of threshold voltages between the memory cell and the second reference cell can be reduced, thereby improving data reading stability.
The above-mentioned configuration may be further provided with an erasing step of collectively erasing the plurality of memory cells, the first reference cell, and the second reference cell, and the step of programming the second reference cell with the first threshold value to verify may be configured to be carried out when the erasing step is carried out. According to this configuration, the time required for a programming operation can be cut down.
The above-mentioned configuration may be further provided with an erasing step of collectively erasing the plurality of memory cells, the first reference cell, and the second reference cell, and the step of programming the second reference cell with the first threshold value to verify may be configured to be carried out when programming the plurality of memory cells for the first time after the erasing step. According to this configuration, the time required for an erasing operation can be cut down.
While preferred embodiments of the present invention are described in detail above, the present invention is not limited to those specific embodiments and, within the spirit and scope of the present invention as defined in the appended claims, various modifications and alterations may be made.
18 AF02584WO

Claims

1. A semiconductor device comprising: a plurality of memory cells storing two bits of data in a cell by independently storing data in isolated storage regions in the cell; a first reference cell corresponding to an erased state of the storage region and being shared by the plurality of memory cells; a second reference cell corresponding to a programmed state of the storage region and being shared by the plurality of memory cells; and a control section for controlling read operations, by creating a reference threshold value from threshold values of the first reference cell and the second reference cell and by comparing a threshold value of the storage region subject to data reading in the plurality of memory cells with the reference threshold value when reading data, programming with a first threshold value to verify when programming the second reference cell, refreshing with a second threshold value lower than the first threshold value to verify when refreshing the second reference cell, and programming at least one or more cells subject to programming in the plurality of memory cells with the threshold value of the second reference cell to verify and refreshing a cell subject to refresh in the plurality of memory cells with the threshold value of the second reference cell to verify when programming the plurality of memory cells.
2. The semiconductor device according to claim 1, wherein the control section collectively erases the plurality of memory cells, the first reference cell, and the second reference cell when erasing data and thereafter programs the second reference cell with the first threshold value to verify.
3. The semiconductor device according to claim 1 , wherein the control section collectively erases the plurality of memory cells, the first reference cell, and the second reference cell when erasing data, and programs the second reference cell with the first threshold value to verify when programming the plurality of memory cells for the first time after the erasing.
4. The semiconductor device according to claim 3, wherein the control section, when programming data, verifies the second reference cell with a third threshold value lower than the second threshold value, programs the second reference cell with the first threshold value to verify when the threshold value of the second reference cell is lower than the third threshold
19 AF02584WO value, and refreshes the second reference cell with the second threshold value to verify when the threshold value of the second reference cell is higher than the third threshold value.
5. The semiconductor device according to claim 4, further comprising: a third reference cell setting the first threshold value; a fourth reference cell setting the second threshold value; and a fifth reference cell setting the third threshold value.
6. The semiconductor device according to claim 1, wherein the plurality of memory cells, the first reference cell, and the second reference cell are provided on the same word line.
7. The semiconductor device according to claim 1 , wherein the first reference cell and the second reference cell stores two bits of data in a cell by independently storing data in two isolated storage regions in the cell, and one of the two storage regions is set to the programmed state and the other is set to the erased state.
8. A method for controlling a semiconductor device that includes a plurality of memory cells storing two bits of data in a memory cell by independently storing data in isolated regions in the memory cell, a first reference cell corresponding to an erased state of the plurality of memory cells, and a second reference cell corresponding to a programmed state of the plurality of memory cells, the method comprising: creating a reference threshold value from threshold values of the first reference cell and the second reference cell; reading data by comparing a threshold value of the storage region subject to data reading in the plurality of memory cells with the reference threshold value; programming the second reference cell with a first threshold value to verify; refreshing the second reference cell with a second threshold value lower than the first threshold value to verify; programming at least one or more cells subject to programming in the plurality of memory cells with the threshold value of the second reference cell to verify; and refreshing a cell subject to refresh in the plurality of memory cells with the threshold value of the second reference cell to verify.
20 AF02584WO
9. The method for controlling a semiconductor device according to claim 8, further comprising: erasing collectively the plurality of memory cells, the first reference cell, and the second reference cell; wherein the programming of the second reference cell with the first threshold value to verify is carried out following the erasing.
10. The method for controlling a semiconductor device according to claim 8, further comprising: erasing collectively the plurality of memory cells, the first reference cell, and the second reference cell; wherein the programming of the second reference cell with the first threshold value to verify is carried out when programming the plurality of memory cells for the first time after the erasing.
21 AF02584WO
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