TWI472898B - Charge pump system and charge pump method thereof - Google Patents

Description

Booster system and boosting method thereof

This invention relates to charge booster systems and charge booster clocks.

The four-phase charge booster system is a power supply efficiency design that can effectively address critical voltages. Such four-phase charge booster systems require relatively long setup times, while set-up times typically require higher demands at faster operating speeds.

An important functional requirement of the memory volume circuit is that the time interval between the command to receive a read operation and the actual execution of this read operation must be short. After the self-assembly circuit receives a read operation command, it takes the setup time of the four-phase charge booster system and the additional setup time to start the active booster. The setup time of the multiphase clock almost eliminates the available setup time of the active booster. Moreover, the settling time required for the effective booster is further due to the leakage current from the internal node of an active booster.

The present invention discloses an apparatus including a first charge booster and a second charge booster.

The first charge booster includes a plurality of series-arranged charge booster stages and inter-stage nodes between adjacent charge booster stages. A plurality of series-arranged charge booster stages of the first charge booster are arranged to boost the first charge booster from a first phase to a final phase to a first voltage level.

The second charge booster is coupled to one or more of the plurality of inter-stage nodes of the first charge booster. The second charge booster is arranged to boost one or more of the plurality of inter-stage nodes of the first charge booster to one or more voltage levels. The second charge booster includes a plurality of series-arranged charge booster stages to schedule boosting of the second charge booster from the first stage to the last stage to a second voltage level.

In one embodiment, the first charge booster is driven by a two-phase clock including a first clock signal and a second clock signal, wherein the first clock signal and the second clock signal are a non-specific charge. Different delayed versions of the input clock signal used by the booster.

In one embodiment, the first charge booster is driven by a plurality of clock signals that are not overlapped such that portions of the clock signals that initiate the plurality of charge booster stages are non-overlapping.

In one embodiment, the first charge booster is driven by a plurality of clock signals having a duty cycle of less than one-half, such that portions of the clock signals that initiate the plurality of charge booster stages are less than two One of them.

In one embodiment, the first charge booster is driven by a different delayed version of the clock signal of the input clock signal, and the input clock signal has a duty cycle of less than one-half, such that the plurality of charge boosts are enabled The portion of the clock signals at the stage is less than one-half.

In one embodiment, the first charge booster is driven by a two-phase clock including a first clock signal and a second clock signal, wherein the first clock signal and a second clock signal are not exclusive. Different delayed versions of the input clock signal for the charge booster, and wherein the second charge booster is driven by a four phase clock. This second charge booster can be driven by a standby charge booster generated by an internal four-phase clock because this second charge booster does not need to face settling time as a first booster as an active booster Requirements.

An embodiment further includes the control circuit using the second charge booster to charge boost the one or more inter-stage nodes to compensate for leakage current from the one or more inter-stage nodes.

In one embodiment, an output of the first charge booster provides a word line read voltage.

In one embodiment, the boost frequency of the first charge booster is determined by an input clock signal that is not dedicated to the charge booster.

In various embodiments, the input clock signal can be, for example, an external command clock that communicates with an external command data provided by the integrated circuit including the charge booster.

Another object of the present invention is to provide a method comprising:

Using a second charge booster having a second plurality of series arrangement of charge booster stages to place one or more stages between a plurality of adjacent stages of a series arrangement in a first charge booster The internode is boosted to one or more voltage levels.

In one embodiment, the first charge booster is driven by a two-phase clock including a first clock signal and a second clock signal, wherein the first clock signal and the second clock signal are a non-specific charge. Different delayed versions of the input clock signal used by the booster. For example, the input clock signal can be an external command clock that provides a clock for the integrated circuit including the charge booster to communicate with an external command data.

In one embodiment, the first charge booster is driven by a two-phase clock including a first clock signal and a second clock signal, wherein the first clock signal and a second clock signal are not exclusive. Different delayed versions of the input clock signal for the charge booster, and wherein the second charge booster is driven by a four phase clock.

An embodiment further includes:

The one or more inter-stage nodes are charge boosted using the second charge booster to compensate for leakage current from the one or more inter-stage nodes.

In one embodiment, an output of the first charge booster provides a word line read voltage.

In one embodiment, the boost frequency of the first charge booster is determined by an input clock signal that is not dedicated to the charge booster.

In various embodiments, the input clock signal can be, for example, an external command clock that communicates with an external command data provided by the integrated circuit including the charge booster.

Still another object of the present invention is to provide an apparatus comprising an integrated circuit. The integrated circuit includes an electrical connector and a charge booster.

The electrical connector transmits a signal between the integrated circuit and an external circuit. The signals include a command clock and command data. The command clock provides a clock for the command material. The charge booster includes a plurality of series-arranged charge booster stages to boost from a first stage to a final stage to a voltage level, wherein timing of the charge booster stage is controlled by at least the command clock signal .

It is still another object of the present invention to provide a method comprising: transmitting a signal between an integrated circuit and an external circuit through an electrical connector of an integrated circuit, the signals including a command clock and a clock provided by the command clock Command data; and timing of controlling the charge booster stage of a charge booster in the integrated circuit by at least the command clock signal.

Figure 1 shows a block diagram of a circuit of a charge booster system.

The standby charge booster system is selectively enabled to stop the active charge booster when there are no other pending operations, such as a read operation in response to a read command. Standby leakage is the output from the standby charge booster, the output of the active charge booster, and the output of the integrated charge booster that combines the output of the standby charge booster with the output of the active charge booster.

If the voltage at the output of the overall charge booster is reduced due to leakage, it will be detected by the booster detection circuit. In response to this detection, the boost detection circuit periodically sends an "enable booster" control signal to the standby charge booster. The standby charge booster can be enabled or disabled in various embodiments when setting a response to a read command. In an embodiment where an active charge booster is also enabled in response to a read command, the active charge booster and the standby charge booster are enabled by an "enable booster" in response to a read command. A control signal is enabled to activate the active charge booster and the standby charge booster. The output of this standby charge booster is combined with the output of the active charge booster to form the output of the overall charge booster. After this read command, the active charge booster and standby charge booster are disabled by a "disable booster" control signal.

When this read command of N clock cycles is executed, the active charge booster consumes the energy stored in the standby charge booster during the previous N clock cycles. After this read command, the standby charge booster stores energy for use in the N clock cycles of the next read command.

Figure 2 shows a schematic diagram of the source of the external clock signal for this active charge booster.

The effective charge booster in this integrated circuit is clocked by an external command clock. The external command clock is a signal that also provides a clock signal for the command data signal. The command clock signal and the command data signal are transmitted between the integrated circuit and an external circuit (outside the integrated circuit). Since the effective charge booster in the integrated circuit is clocked by an external command clock, the settling time effective to generate a clock signal for the active charge booster can be omitted in response to the read command.

Figure 3 shows the non-overlapping clock signal for this active charge booster.

This effective charge booster is clocked by a non-overlapping clock signal. The first clock signal CLK1 of this active charge booster is an external command clock signal. The second clock signal CLK2 of this active charge booster is a delayed version of the external command clock signal. In another embodiment, the first clock signal CLK1 and the second clock signal CLK2 of the active charge booster are both delayed versions of the external command clock signal.

When the active charge booster is disabled, both the first clock signal CLK1 and the second clock signal CLK2 of the active charge booster are turned off.

The setting of this non-overlapping clock signal is relatively fast, also because the clock period of the two-phase clock signal is shorter than the clock period of the four-phase clock signal.

Figure 4 shows a block diagram of this active charge booster with an intermediate node supported by a standby charge booster.

The active charge booster has a plurality of charge booster stages arranged in series, booster stage 0, booster stage 1, ..., to booster stage n. The inter-stage nodes V0, V1, etc. are between adjacent stages. The inter-stage node V0 is the output located in booster stage 0. The inter-stage node V0 is also the input at the booster stage 1. The inter-stage node V1 is the output located in booster stage 1. The inter-stage node V1 is also the input at booster stage 2 (not shown). In general, the inter-stage node Vx is the output located in the booster stage x. The inter-stage node Vx is also the input at booster stage x+1. The output of the last booster stage is the active booster output.

The inter-stage nodes of this active charge booster have a leakage current path that reduces their voltage level, which causes the voltage level of the nodes to drop between these stages. To ensure that the active booster will operate with this external clock signal control, the voltage level of the internal node of this active charge booster is supported by the standby charge booster. The frequency of the different read command modes is close to DC and occurs no more than every N clock cycles.

In order to counter this leakage current, the standby charge booster is connected to the inter-stage nodes V0, V1, ... of the effective charge booster. The weaker pull-up transistor between the standby charge booster and the interstage node forms a "weak path" which pulls up the voltage level of the interstage node. The weak pull-up transistor has a gate and a drain terminal coupled to the standby charge booster output, and a source terminal coupled to the inter-stage node. The inter-stage nodes V0, V1, etc. of this effective charge booster are boosted to the output of the standby charge booster which is reduced by a threshold voltage by the diode-connected transistor. These interstage nodes are internal to the active charge booster and are supported by the level of the standby charge booster output that is close to the diode connected transistor to reduce a threshold voltage. This diode connection ensures that the interstage nodes supported by the standby charge booster are internal to the active charge booster while ensuring that the interstage nodes of these active charge boosters do not affect standby rise. Pressure.

Figure 5 shows a detailed schematic of this active charge booster with an intermediate node supported by a standby charge booster.

This effective charge booster stage has a triple well transistor. In an embodiment with a triple well NMOS transistor, the N ⁺ source and the N ⁺ drain are formed in the P well region. This P well area is formed in an n well area. The n well region is formed in a p-type substrate. A more detailed information can be found in U.S. Patent No. 6,100,557, the disclosure of which is incorporated herein by reference.

The interleaving phase of the active charge booster is to alternately provide a clock signal from the first clock signal CLK1 and the second clock signal CLK2. For example, in the "even" active booster phase, booster phase 0 (pump stage 0), booster phase 2 (pump stage 2) is clocked by the first clock signal CLK1, and "odd number" In the stage of the active booster, the boost stage 1 and the pump stage 3 are clock signals supplied by the second clock signal CLK2. In another embodiment, the "even" active booster stage is clocked by the second clock signal CLK2, and the "odd" active booster stage is clocked by the first clock signal CLK1.

This active charge intermediate stage node has a pull up transistor to provide a supply voltage VDD. The pull-up transistor has a gate and a drain terminal coupled to the standby charge booster output, and a source terminal coupled to the inter-stage node.

Figure 6 shows a schematic of this standby charge booster. Figure 7 is a schematic diagram of the clock signal of the standby charge booster in Figure 6.

The phase interleaved switch that changes the interleaving phase of the active charge booster interleaves one of the clock signals P2 and P4. For example, an "even" phase interleaved switch, M0s, M2s, etc. are clock signals provided by the clock signal P2, and an "odd" phase interleaved switch, M1s, M3s, etc. are clock signals provided by the clock signal P4.

The staggered interstage phase and gate boost transistor system of the active charge booster interleaves one of the clock signals P2 and P4. For example, "even" interstage nodes and gate boost transistors, M0g, M2g, etc. are clock signals provided by clock signal P3, and "odd" phase nodes and gate boost transistors, M1g, M3g The clock signal is supplied from the clock signal P1.

These transistors M1x and M2x prevent the booster stage from shifting the voltage level due to the transistors M1s and M2s.

Figure 8 shows a block diagram of an integrated circuit having a charge booster system as described herein in accordance with an embodiment of the present invention.

An integrated circuit 850 including a memory array 800 is shown. A column (word line) decoder 801 is coupled to and electrically communicates with a plurality of word lines 802 arranged along the column direction of the memory array 800. A row (bit line) decoder 803 is coupled and electrically coupled to a plurality of bit lines 804 arranged along the row direction of the memory array 800. The address is supplied to the column decoder 801 and the row decoder 803 via the bus 805. The sensing circuit (sense amplifier) and data input structure in block 806, including voltage and/or current sources, are coupled to bit line decoder 803 via data bus 807. The data is supplied to the data input line 811 by the input/output port on the integrated circuit 850, or is input to the data input structure in block 806 by other internal/external data sources of the integrated circuit 850. Other circuits may be included within integrated circuit 850, such as a general purpose processor or special purpose application circuit, or a combination of modules to provide system single chip functionality supported by memory array 800. The data is provided by the sense amplifier in block 806, via data output line 815, to an input/output port on integrated circuit 850, or to other data terminals internal/external to integrated circuit 850.

The controller 809 used in this embodiment uses a bias adjustment state mechanism to provide signals to control the application of the charge booster circuit, the bias circuit voltage, and the current source 808 to provide, for example, read, program, Wipe, erase verify, and programmatically verify the bias voltage and/or current to the word line and bit line. The charge booster is supported by a standby charge booster to support an inter-stage node of an active charge booster. The controller 809 can be utilized with special purpose logic circuitry as is well known to those skilled in the art. In an alternate embodiment, the controller 809 includes a general purpose processor that can be used in the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, the controller 809 is a combination of special purpose logic circuitry and a general purpose processor.

An external command circuit 860 communicates with a command clock signal and command data signals via bus 862. An example command data signal is a read command that reads a memory address. By using the command clock signal to provide the clock for the active booster, this active booster can eliminate the setup time for generating a clock signal for this active charge booster.

In one embodiment, a command code on bus 826 (e.g., a serial peripheral interface bus) aligns integrated circuit 850 with a command clock signal transmitted on bus 826.

Although the present invention has been described with reference to the embodiments, the present invention is not limited by the detailed description thereof. Alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, all combinations of components that are substantially identical to the invention can achieve substantially the same results as the present invention without departing from the spirit of the invention. therefore, All such alternatives and modifications are intended to fall within the scope of the invention as defined by the appended claims and their equivalents.

850‧‧‧ integrated circuit

800‧‧‧ memory array

801‧‧‧ column decoder

802‧‧‧ character line

803‧‧‧ line decoder

804‧‧‧ bit line

805‧‧‧ busbar

807‧‧‧ data bus

809‧‧‧ Controller

808‧‧‧ bias adjustment supply voltage and charge booster

811‧‧‧ data input line

815‧‧‧ data output line

860‧‧‧External command circuit

862‧‧ ‧ busbar

The invention is defined by the scope of the patent application. These and other objects, features, and embodiments will be described in conjunction with the drawings in the sections of the following embodiments, wherein: FIG. 1 is a schematic block diagram of a charge booster system.

Figure 2 shows a schematic diagram of the source of the external clock signal for this active charge booster.

Figure 3 shows the non-overlapping clock signal for this active charge booster.

Figure 4 shows a block diagram of this active charge booster with an intermediate node supported by a standby charge booster.

Figure 5 shows a detailed schematic of this active charge booster with an intermediate node supported by a standby charge booster.

Figure 6 shows a schematic of this standby charge booster.

Figure 7 is a schematic diagram of the clock signal of the standby charge booster in Figure 6.

Figure 8 shows a block diagram of an integrated circuit having a charge booster system as described herein in accordance with an embodiment of the present invention.

Claims (18)

A booster system device comprising: a first charge booster comprising: a plurality of series-connected charge boosters of the first charge booster to arrange for boosting a first voltage level from the first a charge booster from a first phase to a last phase; and a plurality of inter-stage nodes between the plurality of series-arranged adjacent charge booster stages; and a second charge booster, One or more of the plurality of inter-stage nodes of a charge booster, the second charge booster being arranged to one or more of the plurality of inter-stage nodes of the first charge booster Boosting to one or more voltage levels, comprising: a plurality of series-connected charge boosters of the second charge booster to arrange for boosting a second voltage level from the second charge booster From the first stage to the last stage. The booster system of claim 1, wherein the first charge booster is driven by a two-phase clock including a first clock signal and a second clock signal, wherein the first clock signal and A second clock signal is a different delayed version of the input clock signal that is not used by the dedicated charge booster. The booster system of claim 1, wherein the first charge booster is driven by a plurality of clock signals that are not overlapped such that portions of the plurality of clock stages that initiate the plurality of charge booster stages are It does not overlap. The booster system of claim 1, wherein the first charge booster is driven by a plurality of clock signals having a duty cycle of less than one-half The portion of the clock signals that initiate the plurality of charge booster stages is less than one-half. The booster system of claim 1, wherein the first charge booster is driven by a different delayed version of the input clock signal, and the input clock signal has a duty cycle less than two-thirds First, the portion of the clock signals that initiate the plurality of charge booster stages is less than one-half. The booster system of claim 1, wherein the first charge booster is driven by a two-phase clock including a first clock signal and a second clock signal, wherein the first clock signal and A second clock signal is a different delayed version of the input clock signal that is not dedicated to the charge booster, and wherein the second charge booster is driven by a four phase clock. The booster system of claim 1, further comprising a control circuit for performing charge boosting on the one or more inter-stage nodes by the second charge booster to compensate for the one or more Leakage current of the nodes between stages. The booster system of claim 1, wherein an output of the first charge booster provides a word line read voltage. The booster system of claim 1, wherein the boost frequency of the first charge booster is determined by an input clock signal that is not dedicated to the charge booster. A boosting method for a booster system, comprising: using a second charge booster having a second plurality of series-arranged charge booster stages to place a first plurality of first charge boosters Series The one or more interstage nodes between adjacent phases are stepped up to one or more voltage levels. The method of claim 10, wherein the first charge booster is driven by a two-phase clock including a first clock signal and a second clock signal, wherein the first clock signal and a second The clock signal is a different delayed version of the input clock signal that is not dedicated to the charge booster. The method of claim 10, wherein the first charge booster is driven by a plurality of clock signals that are not overlapped such that portions of the plurality of clock signals that initiate the plurality of charge booster stages do not overlap. of. The method of claim 10, wherein the first charge booster is driven by a plurality of clock signals having a duty cycle of less than one-half, such that the plurality of clocks of the plurality of charge booster stages are activated The portion of the signal is less than one-half. The method of claim 10, wherein the first charge booster is driven by a different delayed version of a clock signal of the input clock signal, and the input clock signal has a duty cycle of less than one-half, such that The portion of the clock signals that initiate the plurality of charge booster stages is less than one-half. The method of claim 10, wherein the first charge booster is driven by a two-phase clock including a first clock signal and a second clock signal, wherein the first clock signal and a second The clock signal is a different delayed version of the input clock signal that is not dedicated to the charge booster, and wherein the second charge booster is driven by a four phase clock. The method of claim 10, further comprising: using the second charge booster to charge boost the one or more inter-stage nodes to compensate for leakage from the one or more inter-stage nodes Current. The method of claim 10, wherein an output of the first charge booster provides a word line read voltage. The method of claim 10, wherein the boosting frequency of the first charge booster is determined by an input clock signal that is not dedicated to the charge booster.