CN103326578A - Voltage booster system - Google Patents
Voltage booster system Download PDFInfo
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- CN103326578A CN103326578A CN2012100722352A CN201210072235A CN103326578A CN 103326578 A CN103326578 A CN 103326578A CN 2012100722352 A CN2012100722352 A CN 2012100722352A CN 201210072235 A CN201210072235 A CN 201210072235A CN 103326578 A CN103326578 A CN 103326578A
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Abstract
The invention discloses a charge voltage booster device which comprises a first charge voltage booster. The first charge voltage booster has a plurality of charge voltage booster stages which are arranged in series. A between-stage node between adjacent stages carries out voltage boosting through a second charge voltage booster. The invention further discloses a method, and the time sequence of the charge voltage booster stages is controlled by at least one order clock signal. An order clock and order data are transmitted between an integrated circuit with the charge voltage boosters and an external circuit.
Description
Technical field
The invention relates to electric charge stepup transformer system and electric charge stepup transformer clock.
Background technology
Four phase charge stepup transformer systems a kind ofly can effectively solve the power-efficient relevant with critical voltage design.So four phase charge stepup transformer systems need relatively long setup times, but and setup times is needing higher requirement under the service speed usually faster.
A kind of critical function demand of memory integrated circuit is must be very short in the order that receives a read operation and the actual time interval of carrying out this read operation.Receive the order of a read operation from integrated circuit after, need to take the setup times of this four phase charges stepup transformer system and start the extra setup times of effective stepup transformer.The setup times of multi-phase clock has almost been used up the available setup times of effective stepup transformer.And effectively the required setup times of stepup transformer again because longer from the electric leakage rheology of an effective stepup transformer internal node.
Summary of the invention
The present invention provides a kind of device, and it comprises one first electric charge stepup transformer and one second electric charge stepup transformer.
This first electric charge stepup transformer comprises the electric charge stepup transformer stage of a plurality of series connection arrangements and the stage intermediate node between the adjacent electric charge stepup transformer stage.The electric charge stepup transformer stage of a plurality of series connection arrangements of this first electric charge stepup transformer is to arrange and will boost to one first voltage level from phase I to last stage in this first electric charge stepup transformer.
One or more coupling in a plurality of stage intermediate node of this of this second electric charge stepup transformer and this first electric charge stepup transformer.This second electric charge stepup transformer is arranged to one or more in these a plurality of stage intermediate node of this first electric charge stepup transformer is boosted to one or more voltage levels.This second electric charge stepup transformer comprises that the electric charge stepup transformer stage of a plurality of series connection arrangements is to arrange and will boost to a second voltage level from phase I to last stage in this second electric charge stepup transformer.
In one embodiment, this the first electric charge stepup transformer is driven by a two phase clock that comprises one first clock signal and a second clock signal, and wherein this first clock signal and a second clock signal are the difference delay versions of the input clock signal of not exclusive electric charge stepup transformer use.
In one embodiment, this first electric charge stepup transformer is nonoverlapping by there not being overlapping a plurality of clock signals to drive so that start the part of these clock signals in these a plurality of electric charge stepup transformer stages.
In one embodiment, this first electric charge stepup transformer is driven by a plurality of clock signals that have less than 1/2nd work periods, so that the part of these clock signals that starts these a plurality of electric charge stepup transformer stages is less than 1/2nd.
In one embodiment, this the first electric charge stepup transformer is driven by the clock signal of the difference delay version of an input clock signal, and this input clock signal has the work period less than 1/2nd, so that the part of these clock signals that starts these a plurality of electric charge stepup transformer stages is less than 1/2nd.
In one embodiment, this the first electric charge stepup transformer comprises that by one the two phase clock of one first clock signal and a second clock signal drives, wherein this first clock signal and a second clock signal are that a difference that is not specific to the input clock signal of electric charge stepup transformer use postpones version, and wherein this second electric charge stepup transformer is driven by four phase clocks.This second electric charge stepup transformer can be driven by the standby electric charge stepup transformer that inner four phase clocks produce, because this second electric charge stepup transformer does not need as the requirement of facing setting-up time as the first stepup transformer of effective stepup transformer.
One embodiment also comprises the control circuit use and by this second electric charge stepup transformer these one or more stage intermediate node is carried out the leakage current that electric charge boosts to compensate oneself these one or more stage intermediate node.
In one embodiment, an output of this first electric charge stepup transformer provides a word line read voltage.
In one embodiment, the frequency of boosting of this first electric charge stepup transformer is decided by an input clock signal that is not specific to the use of electric charge stepup transformer.
In different embodiment, this input clock signal can be for example to link up the external command clock that clock is provided at the integrated circuit that comprises this electric charge stepup transformer and external command data.
Another object of the present invention comprises for a kind of method is provided:
Use has the one second electric charge stepup transformer in the electric charge stepup transformer stage of a plurality of series connection arrangements, and the one or more stage intermediate node between the adjacent phases of a plurality of series connection arrangements in one first electric charge stepup transformer are boosted to one or more voltage levels.
In one embodiment, this the first electric charge stepup transformer is driven by a two phase clock that comprises one first clock signal and a second clock signal, and wherein this first clock signal and a second clock signal are the difference delay versions of the input clock signal of not exclusive electric charge stepup transformer use.For example, this input clock signal can be to link up the external command clock that clock is provided in the integrated circuit that comprises this electric charge stepup transformer and external command data.
In one embodiment, this the first electric charge stepup transformer comprises that by one the two phase clock of one first clock signal and a second clock signal drives, wherein this first clock signal and a second clock signal are that a difference that is not specific to the input clock signal of electric charge stepup transformer use postpones version, and wherein this second electric charge stepup transformer is driven by four phase clocks.
One embodiment also comprises:
Use this second electric charge stepup transformer that these one or more stage intermediate node are carried out electric charge and boost to compensate the certainly leakage current of these one or more stage intermediate node.
In one embodiment, an output of this first electric charge stepup transformer provides a word line read voltage.
In one embodiment, the frequency of boosting of this first electric charge stepup transformer is decided by an input clock signal that is not specific to the use of electric charge stepup transformer.
In different embodiment, this input clock signal can be for example to link up the external command clock that clock is provided in the integrated circuit that comprises this electric charge stepup transformer and external command data.
A further object of the present invention provides a kind of device, comprises integrated circuit.This integrated circuit comprises electric connector and electric charge stepup transformer.
This electric connector transmits signal between this integrated circuit and an external circuit.These signals comprise order clock and an order data.This order clock provides clock for this order data.This electric charge stepup transformer comprises the electric charge stepup transformer stage of a plurality of series connection arrangements to boost to a voltage level from phase I to last stage, and wherein the sequential in this electric charge stepup transformer stage is at least by this order clock signal control.
Another purpose of the present invention comprises for a kind of method is provided:
Electric connector by an integrated circuit transmits signal between this integrated circuit and an external circuit, and these signals comprise an order clock and the order data of clock is provided by this order clock; And
At least control the sequential in the electric charge stepup transformer stage of the electric charge stepup transformer in this integrated circuit by this order clock signal.
Description of drawings
The present invention is defined by claim.These and other objects, feature, and embodiment can cooperate accompanying drawing to be described in the chapters and sections of following execution mode, wherein:
Fig. 1 shows the circuit box schematic diagram of an electric charge stepup transformer system.
Fig. 2 shows the schematic diagram in the external timing signal source of this effective charge stepup transformer.
Fig. 3 shows the non-overlapping clock signal of this effective charge stepup transformer.
Fig. 4 shows the block schematic diagram of this effective charge stepup transformer, and it has the intermediate node of being supported by standby electric charge stepup transformer.
Fig. 5 shows the detailed maps of this effective charge stepup transformer, and it has the intermediate node of being supported by standby electric charge stepup transformer.
Fig. 6 shows the schematic diagram of this standby electric charge stepup transformer.
Fig. 7 is the clock signal schematic diagram of standby electric charge stepup transformer among Fig. 6.
Fig. 8 shows the integrated circuit block schematic diagram have according to an embodiment of the invention electric charge stepup transformer described herein system.
[main element symbol description]
850: integrated circuit;
800: Nonvolatile storage array;
801: column decoder;
802: the word line;
803: row decoder;
804: bit line;
805: bus;
807: data/address bus;
809: programme, wipe with the bias voltage of read operation and adjust state machine;
808: bias voltage adjustment supply voltage and electric charge stepup transformer;
811: Data In-Line;
815: DOL Data Output Line;
860: the external command circuit;
862: the bus of carrying order clock and order data.
Embodiment
Fig. 1 shows the circuit box schematic diagram of an electric charge stepup transformer system.
When not having the operation of other waits, for example respond the read operation of a reading order, this standby electric charge stepup transformer system is enabled by selectivity and the electric charge stepup transformer of ceasing to have effect.Standby leakage is from the output of the output of standby electric charge stepup transformer, effective charge stepup transformer and in conjunction with the output of the total charge stepup transformer of the output of the output of standby electric charge stepup transformer and effective charge stepup transformer.
If when the voltage of the output of total charge stepup transformer caused reducing because of electric leakage, the stepup transformer circuit for detecting detected thus.Respond this detecting, this circuit for detecting that boosts can be sent so far standby electric charge stepup transformer of " enabling stepup transformer " control signal termly.When setting response one reading order, this standby electric charge stepup transformer can be enabled or anergy in different embodiment.Also be enabled to respond among the embodiment of reading order at an effective charge stepup transformer,
In order to respond a reading order, this effective charge stepup transformer and standby electric charge stepup transformer are enabled to start this effective charge stepup transformer and standby electric charge stepup transformer by one " enabling stepup transformer " control signal.The output of this standby electric charge stepup transformer and the output of effective charge stepup transformer are combined into the output of total charge stepup transformer.After this reading order, this effective charge stepup transformer and standby electric charge stepup transformer are by " anergy stepup transformer " control signal and by anergy.
When carrying out this reading order of N frequency period, this effective charge stepup transformer can consume formerly and be stored in the interior energy of standby electric charge stepup transformer in the top n frequency period.After this reading order, standby electric charge stepup transformer meeting storage power is used for N frequency period of next reading order.
Fig. 2 shows the schematic diagram in the external timing signal source of this effective charge stepup transformer.
Effective charge stepup transformer in this integrated circuit is to provide clock signal by the external command clock.This outside order clock is a signal that clock signal also is provided for the order data signal.This order clock signal and order data signal transmit between this integrated circuit and an external circuit (outside integrated circuit).Because the effective charge stepup transformer in this integrated circuit is to provide clock signal by the external command clock, when the response reading order, can save for this reason setup times of effective charge stepup transformer clocking.
Fig. 3 shows the non-overlapping clock signal of this effective charge stepup transformer.
This effective charge stepup transformer provides clock by the non-overlapping clock signal.The first clock signal clk 1 of this effective charge stepup transformer is the external command clock signal.The second clock signal CLK2 of this effective charge stepup transformer is the delay version of external command clock signal.In another embodiment, the first clock signal clk 1 of this effective charge stepup transformer and second clock signal CLK2 are the delay version of external command clock signal.
When this effective charge stepup transformer during by anergy, the first clock signal clk 1 and the second clock signal CLK2 of this effective charge stepup transformer are closed.
The setting of this non-overlapping clock signal is relatively fast, also is because the frequency period cause shorter than the frequency period of four phase clock signals of two phase clock signal.
Fig. 4 shows the block schematic diagram of this effective charge stepup transformer, and it has the intermediate node of being supported by standby electric charge stepup transformer.
This effective charge stepup transformer has the electric charge stepup transformer stage that a plurality of series windings arrange, stepup transformer stage 0, stepup transformer stage 1 ..., to stepup transformer stage n.Stage intermediate node V0, V1... etc. are between the adjacent stage.Stage intermediate node V0 is the output that is positioned at the stepup transformer stage 0.Stage intermediate node V0 also is the input that is positioned at the stepup transformer stage 1.Stage intermediate node V1 is the output that is positioned at the stepup transformer stage 1.Stage intermediate node V1 also is the input that is positioned at stepup transformer stages 2 (not shown).Generally speaking, stage intermediate node Vx is the output that is positioned at stepup transformer stage x.Stage intermediate node Vx also is the input that is positioned at stepup transformer stage x+1.The output in last stepup transformer stage is effective stepup transformer output.
These stage intermediate node of this effective charge stepup transformer exist a meeting to reduce the drain current path of its voltage level, and it can cause the voltage level of these stage intermediate node to descend.In order to ensure the thus external timing signal control and working of effective stepup transformer, the voltage level of this effective charge stepup transformer internal node is supported by standby electric charge stepup transformer.The frequency of different read command patterns is near direct current, can not occur above under every N frequency period.
In order to suppress this leakage current, standby electric charge stepup transformer is connected with stage intermediate node V0, the V1... etc. of effective charge stepup transformer.Between between standby electric charge stepup transformer and stage intermediate node a little less than pull up transistor and consist of one " weak path " it can draw on the voltage level with the stage intermediate node.This pulls up transistor a little less than and has grid and drain terminal and the output of standby electric charge stepup transformer and couple, and source terminal and stage intermediate node couple.Stage intermediate node V0, the V1... of this effective charge stepup transformer etc. can be boosted to connecting the output that transistor reduces the standby electric charge stepup transformer of a critical voltage by diode-type.These stage intermediate node are the inside that belongs to the effective charge stepup transformer, and it is to support near the level that diode-type connects the standby electric charge stepup transformer output of a critical voltage of transistor reduction in meeting.This diode-type connects guarantees that these stage intermediate node that standby electric charge stepup transformer is supported are the inside that belongs to the effective charge stepup transformer, and the while can guarantee that the stage intermediate node of the inside of these effective charge stepup transformers can not affect standby and boost.
Fig. 5 shows the detailed maps of this effective charge stepup transformer, and it has the intermediate node of being supported by standby electric charge stepup transformer.
This effective charge stepup transformer stage has triple well transistor (triple well transistors).Has among the embodiment of triple well nmos pass transistor N one
+Source electrode and N
+Drain electrode is to be formed in the P well region.This P well region is to be formed in the n well region.And this n well region is to be formed in the p-type substrate.More detailed information can be consulted United States Patent (USP) No. 6100557, draws at this to be reference data.
The staggered stage of this effective charge stepup transformer is to provide clock signal by the first clock signal clk 1 and second clock signal CLK2 alternately.For example, " even number " be the stage of stepup transformer effectively, stepup transformer stage 0 (pump stage 0), stepup transformer stage 2 (pump stage 2) are to provide clock signal by the first clock signal clk 1, and the stage of " odd number " effective stepup transformer, stepup transformer stage 1 (pump stage 1), stepup transformer stage 3 (pump stage 3) they are to provide clock signal by second clock signal CLK2.In another embodiment, the stage of " even number " effective stepup transformer is to provide clock signal by second clock signal CLK2, and the stage of " odd number " effective stepup transformer then is to provide clock signal by the first clock signal clk 1.
This effective charge interstage node has and pulls up transistor to provide supply voltage VDD.This pulls up transistor and has grid and drain terminal and the output of standby electric charge stepup transformer couples, and source terminal and stage intermediate node couple.
Fig. 6 shows the schematic diagram of this standby electric charge stepup transformer.Fig. 7 is the clock signal schematic diagram of standby electric charge stepup transformer among Fig. 6.
Change the staggered diverter switch of stage in the staggered stage of this effective charge stepup transformer, be staggered one of clock signal P2 and P4 of using.For example, the stage of " even number " diverter switch of interlocking, M0s, M2s etc. provides clock signal by clock signal P2, and staggered diverter switch of " odd number " stage, M1s, M3s etc. provides clock signal by clock signal P4.
Staggered one of clock signal P2 and the P4 of using of the staggered stage intermediate node of this effective charge stepup transformer and grid boost transistor.For example, the stage intermediate node of " even number " and grid boost transistor, M0g, M2g etc. provides clock signal by clock signal P3, and " odd number " stage intermediate node and grid boost transistor, M1g, M3g etc. provides clock signal by clock signal P1.
The movement that these transistors M1x and M2x prevent the stepup transformer stage and produce voltage level because of transistor M1s and M2s.
Fig. 8 shows the integrated circuit block schematic diagram have according to an embodiment of the invention electric charge stepup transformer described herein system.
Show the integrated circuit 850 that comprises a storage array 800 among the figure.One row (word line) decoder 801 couples and electrically links up with many word lines 802 along storage array 800 column direction arrangements.Delegation's (bit line) decoder 803 couples and electrically links up with multiple bit lines 804 along storage array 800 line direction arrangements.The address offers column decoder 801 and row decoder 803 via bus 805.Sensing circuit in the square 806 (sensing amplifier) and data input structure comprise that voltage and/or current source couple via data/address bus 807 and bit line decoder 803.Data offer Data In-Line 811 by the input/output end port on the integrated circuit 850, perhaps by the data source of integrated circuit 850 other inner/outer, input to the data input structure in the square 806.Other circuit can be contained within the integrated circuit 850, for example general purpose processor or specific purposes application circuit, or module combinations is to provide the system single chip function of being supported by storage array 800.Data are by the sensing amplifier in the square 806, via DOL Data Output Line 815, the input/output end port to the integrated circuit 850 is provided, or provides to other data terminals of integrated circuit 850 inner/outer.
One external command circuit 860 is by bus 862 and order clock signal and an order data signal communicating.The order data signal of an example is the reading order of a read memory address.Be provided as the clock of effective stepup transformer by the utility command clock signal, this effective stepup transformer can save for this reason setup times of effective charge stepup transformer clocking.
In one embodiment, in the command code on the bus 826 (for example go here and there order peripheral interface bus) the order clock signal that transmits on integrated circuit 850 and the bus 826 is aimed at.
Although the present invention is described with reference to embodiment, the present invention is not subject to its detailed description.Substitute mode and revise pattern and in previous description, advise, and other substitute modes and modification pattern will can be expected for those skilled in the art.Particularly, all have be same as in fact member of the present invention in conjunction with and reach the technical scheme of identical result in fact with the present invention, do not break away from spiritual category of the present invention.Therefore, all these substitute modes and revise pattern and all drop on the present invention and enclose among the category that claim and equivalent way thereof define.
Claims (20)
1. stepup transformer system and device comprises:
One first electric charge stepup transformer comprises:
The electric charge stepup transformer of a plurality of series connection arrangements of this first electric charge stepup transformer with arrange to boost one first voltage level from this first electric charge stepup transformer from the phase I to last stage; And
A plurality of stage intermediate node are between the adjacent electric charge stepup transformer stage that these a plurality of series connection arrange; And
One second electric charge stepup transformer, with one or more the coupling in these a plurality of stage intermediate node of this first electric charge stepup transformer, this the second electric charge stepup transformer is arranged to one or more in these a plurality of stage intermediate node of this first electric charge stepup transformer is boosted to one or more voltage levels, comprising:
The electric charge stepup transformer of a plurality of series connection arrangements of this second electric charge stepup transformer with arrange to boost a second voltage level from this second electric charge stepup transformer from the phase I to last stage.
2. stepup transformer according to claim 1 system, wherein this first electric charge stepup transformer is driven by a two phase clock that comprises one first clock signal and a second clock signal, and wherein this first clock signal and a second clock signal are the difference delay versions of the input clock signal of not exclusive electric charge stepup transformer use.
3. stepup transformer according to claim 1 system, wherein this first electric charge stepup transformer is nonoverlapping by there not being overlapping a plurality of clock signals to drive so that start the part of these clock signals in these a plurality of electric charge stepup transformer stages.
4. stepup transformer according to claim 1 system, wherein this first electric charge stepup transformer is driven by a plurality of clock signals that have less than 1/2nd work periods, so that the part of these clock signals that starts these a plurality of electric charge stepup transformer stages is less than 1/2nd.
5. stepup transformer according to claim 1 system, wherein this first electric charge stepup transformer is driven by the clock signal of the difference delay version of an input clock signal, and this input clock signal has the work period less than 1/2nd, so that the part of these clock signals that starts these a plurality of electric charge stepup transformer stages is less than 1/2nd.
6. stepup transformer according to claim 1 system, wherein this first electric charge stepup transformer comprises that by one the two phase clock of one first clock signal and a second clock signal drives, wherein this first clock signal and a second clock signal are that a difference that is not specific to the input clock signal of electric charge stepup transformer use postpones version, and wherein this second electric charge stepup transformer is driven by four phase clocks.
7. stepup transformer according to claim 1 system also comprises control circuit and uses and by this second electric charge stepup transformer these one or more stage intermediate node are carried out electric charge and boost to compensate leakage current from these one or more stage intermediate node.
8. stepup transformer according to claim 1 system, wherein an output of this first electric charge stepup transformer provides a word line read voltage.
9. stepup transformer according to claim 1 system, wherein the frequency of boosting of this first electric charge stepup transformer decides by not being specific to the input clock signal that the electric charge stepup transformer uses.
10. the step-up method of a stepup transformer system comprises:
Use has the one second electric charge stepup transformer in the electric charge stepup transformer stage of a plurality of series connection arrangements, and the one or more stage intermediate node between the adjacent phases of more than first series connection arrangements in one first electric charge stepup transformer are boosted to one or more voltage levels.
11. method according to claim 10, wherein this first electric charge stepup transformer comprises that by one the two phase clock of one first clock signal and a second clock signal drives, and wherein this first clock signal and a second clock signal are that a difference that is not specific to the input clock signal of electric charge stepup transformer use postpones version.
12. method according to claim 10, wherein this first electric charge stepup transformer is nonoverlapping by there not being overlapping a plurality of clock signals to drive so that start the part of these clock signals in these a plurality of electric charge stepup transformer stages.
13. method according to claim 10, wherein this first electric charge stepup transformer is driven by a plurality of clock signals that have less than 1/2nd work periods, so that the part of these clock signals that starts these a plurality of electric charge stepup transformer stages is less than 1/2nd.
14. method according to claim 10, wherein this first electric charge stepup transformer is driven by the clock signal of the difference delay version of an input clock signal, and this input clock signal has the work period less than 1/2nd, so that the part of these clock signals that starts these a plurality of electric charge stepup transformer stages is less than 1/2nd.
15. method according to claim 10, wherein this first electric charge stepup transformer comprises that by one the two phase clock of one first clock signal and a second clock signal drives, wherein this first clock signal and a second clock signal are that a difference that is not specific to the input clock signal of electric charge stepup transformer use postpones version, and wherein this second electric charge stepup transformer is driven by four phase clocks.
16. method according to claim 10 also comprises:
Use this second electric charge stepup transformer that these one or more stage intermediate node are carried out electric charge and boost to compensate the certainly leakage current of these one or more stage intermediate node.
17. method according to claim 10, wherein an output of this first electric charge stepup transformer provides a word line read voltage.
18. method according to claim 10, wherein the frequency of boosting of this first electric charge stepup transformer is decided by an input clock signal that is not specific to the use of electric charge stepup transformer.
19. a stepup transformer system and device comprises:
One integrated circuit comprises:
Electric connector between this integrated circuit and an external circuit is to transmit signal, and these signals comprise order clock and an order data; And
One stepup transformer comprises:
The electric charge stepup transformer stage of a plurality of series connection arrangements, wherein the sequential in this electric charge stepup transformer stage was at least by this order clock signal control to boost to a voltage level from phase I to last stage.
20. the step-up method of a stepup transformer system comprises:
Electric connector by an integrated circuit transmits signal between this integrated circuit and an external circuit, and these signals comprise an order clock and the order data of clock is provided by this order clock; And
At least order the sequential in the electric charge stepup transformer stage of the electric charge stepup transformer in this integrated circuit of clock control by this.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210072235.2A CN103326578B (en) | 2012-03-19 | 2012-03-19 | Booster system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210072235.2A CN103326578B (en) | 2012-03-19 | 2012-03-19 | Booster system |
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| CN103326578A true CN103326578A (en) | 2013-09-25 |
| CN103326578B CN103326578B (en) | 2016-03-02 |
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|---|---|---|---|
| CN201210072235.2A Active CN103326578B (en) | 2012-03-19 | 2012-03-19 | Booster system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104682701A (en) * | 2013-11-26 | 2015-06-03 | 旺宏电子股份有限公司 | Boosted circuit |
| CN109804326A (en) * | 2016-10-12 | 2019-05-24 | 赛普拉斯半导体公司 | Fast slope low-power-supply charge pump circuit |
| TWI776765B (en) * | 2022-01-04 | 2022-09-01 | 華邦電子股份有限公司 | Power-on read circuit |
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| JP3258923B2 (en) * | 1997-02-26 | 2002-02-18 | 株式会社東芝 | Semiconductor integrated circuit device |
| CN101002275A (en) * | 2004-05-11 | 2007-07-18 | 斯班逊有限公司 | Nonvolatile semiconductor memory, semiconductor device and charge pump circuit |
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| US5734290A (en) * | 1996-03-15 | 1998-03-31 | National Science Council Of R.O.C. | Charge pumping circuit having cascaded stages receiving two clock signals |
| CN1173023A (en) * | 1996-05-28 | 1998-02-11 | 冲电气工业株式会社 | Booster circuit and method of driving the same |
| JP3258923B2 (en) * | 1997-02-26 | 2002-02-18 | 株式会社東芝 | Semiconductor integrated circuit device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104682701A (en) * | 2013-11-26 | 2015-06-03 | 旺宏电子股份有限公司 | Boosted circuit |
| CN104682701B (en) * | 2013-11-26 | 2017-04-26 | 旺宏电子股份有限公司 | Boosted circuit |
| CN109804326A (en) * | 2016-10-12 | 2019-05-24 | 赛普拉斯半导体公司 | Fast slope low-power-supply charge pump circuit |
| TWI776765B (en) * | 2022-01-04 | 2022-09-01 | 華邦電子股份有限公司 | Power-on read circuit |
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| Publication number | Publication date |
|---|---|
| CN103326578B (en) | 2016-03-02 |
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