TWI470741B - Nonvolatile memory with intermittent isolation structure and SONOS memory cell and its operation method, production method - Google Patents

Description

Non-volatile memory with discontinuous isolation structure and SONOS memory cell, operation method thereof, and manufacturing method thereof

The present invention relates to a non-volatile memory, and more particularly to a non-volatile memory having a discontinuous isolation structure and a SONOS memory cell, an operation method thereof, and a fabrication method.

With the development of semiconductor integrated circuit manufacturing technology, the number of memory cells contained in non-volatile memory has been increasing, and the size of components has been continuously reduced due to the increase in the degree of integration.

However, no matter how small the size of the component is, it is necessary to properly insulate or isolate each memory cell in the non-volatile memory to ensure the stability of the memory cell during operation and achieve good memory. characteristic.

Figure 1 is a top plan view of a conventional non-volatile memory array. Figure 1 shows a portion of a non-volatile memory array having a plurality of gate structures 102 as SONOS memory cells connected by control gates 102d into horizontally arranged characters. line. A gate structure 102 is adjacent to a drain region 106 and a source region 104 that are parallel to the word line. As shown in FIG. 1 , the source region 104 between adjacent two-character lines has a source line contact window 122. The source line contact window 122 fills the barrier plug and passes through a source line. (not shown) are connected together, so that the source regions 104 separated by the isolation structures 110 can be electrically connected into a strip of source lines. The drain region 106 has a bit line contact window 124. The bit line contact window 124 fills the barrier plug and passes through a bit line (not shown). Connected together, the drain regions 106 separated by the isolation structures 110 can be connected as a strip of bit lines above.

However, due to the arrangement of the contact windows 122, 124 and the barrier plug, it is difficult to process and reduce the yield of the product for the target of the size of the miniature component.

It is an object of the present invention to simplify the spatial arrangement of non-volatile memory and thereby contribute to the miniaturization of the memory.

To achieve the above and other objects, the present invention provides a non-volatile memory having a discontinuous isolation structure and a SONOS memory cell, comprising: a semiconductor substrate having an array region, the array region comprising a plurality of isolation structures The isolation structures are parallel to each other and each of the isolation structures has a plurality of voids that cut the isolation structure, the voids forming a plurality of channels exposing the semiconductor substrate in a direction perpendicular to the isolation structure; a plurality of source lines Is perpendicular to the arrangement direction of the isolation structures, the source lines are located in the channels of the semiconductor substrate; a plurality of SONOS memory cells are located on the semiconductor substrate between the adjacent two isolation structures; And the plurality of drain regions are located in the semiconductor substrate between the adjacent two isolation structures, wherein the drain regions of each SONOS memory cell and the connected source lines are located parallel to the source lines In the semiconductor substrate on different sides of the word line.

In an embodiment, the isolation structure is a shallow trench isolation structure.

In an embodiment, in the semiconductor substrate, the source line passes each time Two intermittent isolation structures are connected to a source line contact source line contact window.

In one embodiment, in the semiconductor substrate, the source line is connected to a source line contact window for each of the 64 intermittent isolation structures. In addition, the regions between the isolation structures and the adjacent isolation structures in the semiconductor substrate may have a width of 0.16 μm in a direction parallel to the word lines. Further, the source lines have a width in a direction of a vertical word line, and a distance between each source line and a word line on the semiconductor substrate is 0.1 μm.

In one embodiment, the material of the source lines is one of cobalt telluride, nickel telluride and titanium telluride.

In one embodiment, in the semiconductor substrate, every two intermittent isolation structures have a complete isolation structure that is not cut, and is adjacent to the two isolated isolation structures. The intersection of the polar region and the source line has a source line contact window. In addition, the straight line parallel to the isolation structures having the source line contact window may also be a discontinuous isolation structure, and the straight line and the adjacent isolation structure form a larger block isolation structure region.

The present invention further provides a method for operating a non-volatile memory as described above, comprising: a programming step of applying a positive voltage to one of a gate, a source region and a drain region of a SONOS memory cell to be programmed. a wiping step of applying a positive voltage to one of the source region and the drain region of the SONOS memory cell to be erased, and applying a negative voltage to the gate of the SONOS memory cell to be erased; a reading step of applying a positive voltage to one of the gate, the drain region and the source region of the SONOS memory cell to be read, wherein The voltage applied in the reading step is lower than the voltage applied in the programming step.

To achieve the above and other objects, the present invention provides a method for fabricating a non-volatile memory having a discontinuous isolation structure and a SONOS memory cell, comprising the steps of: forming a plurality of intermittent isolations in a semiconductor substrate. a structure, wherein each of the isolation structures has a plurality of voids that cut the isolation structure, the voids forming a plurality of channels exposing the semiconductor substrate in a direction perpendicular to the isolation structure; performing a source ion implantation process to Forming a plurality of source lines in the channels of the semiconductor substrate; forming an ONO structure on the semiconductor substrate; depositing a control gate and patterning the control gate to form a plurality of word lines; and forming a source line contact window.

Therefore, in the special configuration when the isolation structure is formed, the isolation structure is not formed in the channel through which the source line on the semiconductor substrate passes, so that the non-volatile memory of the present invention does not need to be as conventional technology. A large number of source line contact windows are generally required to electrically connect the source regions separated by the isolation structure into a strip of source lines.

On the other hand, the entire isolation structure can be left to the subsequent process and then excavated. However, the pre-formed isolation structure can eliminate the need to dig the isolation structure on the source line area in the subsequent process. In addition to the steps. If the above-mentioned isolation structure excavation step is not excavated, the isolation structure that is not excavated will hinder the formation of the implantation area, which will increase the resistance of the source area, thereby causing the entire action area to fail.

Therefore, the intermittent isolation structure of the present invention can simplify the process and avoid the risk that the memory cells fail due to the uncleaned isolation structure.

In order to fully understand the objects, features and advantages of the present invention, the present invention will be described in detail by the following specific embodiments and the accompanying drawings. The formed isolation structure is discontinuous, and the gaps of the isolation structures are interrupted to form a complete source region in a direction perpendicular to the isolation structure, so as to avoid a source line contact window corresponding to each gate structure. Shortcomings.

First, please refer to FIG. 2, which is a plan view of a non-volatile memory having a discontinuous isolation structure and a SONOS memory cell in an embodiment of the present invention. 2 is a partial non-volatile memory array having a plurality of gate structures 202 as SONOS memory cells, the gate structures 202 being connected by control gates 202d into horizontally arranged words. Yuan line. A gate structure 202 is adjacent to a drain region 206 and a source region 204 that are parallel to the word line. The isolation structure 210 of the present invention is discontinuous. As shown in Fig. 2, there is no isolation structure 210 between the source regions 104 separated in the prior art, that is, an entire source can be implanted when the source regions are implanted. In the polar region, the fabrication steps of the source line contact window and its corresponding barrier plug are eliminated, thereby simplifying the spatial arrangement in the non-volatile memory.

In the structure of the embodiment of the present invention, a source-region contact window for externally electrically connected and its corresponding barrier plug can be set at every predetermined number of SONOS memory cells. , greatly simplifying the space arrangement within the component, thereby contributing to the miniaturization of the memory. For example, at least A barrier plug is set up between two SONOS memory cells. As for the number of SONOS memory cells to be separated, it is necessary to set a barrier plug depending on the driving capability of the entire component, that is, the system can be designed according to actual needs.

As for the drain region 206, there is still a bit line contact window 224. The bit line contact window 224 is filled with a barrier plug and is connected to the top through a bit line (not shown). The drain regions 206 separated by the isolation structure 210 can be connected as a strip of bit lines above.

Next, please refer to FIGS. 3-7, which are perspective cross-sectional views of a non-volatile memory having a discontinuous isolation structure and SONOS memory cells in different process steps according to an embodiment of the present invention. It is only a three-dimensional cross-sectional view of a portion of the non-volatile memory, and the components in the figures are for illustrative purposes only.

Referring first to FIG. 3, a plurality of intermittent isolation structures 210 are first formed in a semiconductor substrate 200 in a mask or other equivalent manner. Each of the isolation structures 210 has a plurality of voids 210a that cut the isolation structure 210. The voids 210a may form a plurality of channels exposing the semiconductor substrate 200 in a direction perpendicular to the isolation structure 210. Then, a source ion implantation process is performed, which is used for implanting the source region, so that the implanted ion cloth is implanted into the semiconductor substrate 200 at the channel to form a source region 204, and the source region 204 After the subsequent process is performed, it is placed in the semiconductor substrate 200 on the side of the gate structure 202 (see FIG. 7). The material of the semiconductor substrate 200 may be bismuth (Si), germanium (SiGe), silicon on insulator (SOI), and overlying insulating layer (Silicon Germanium On). Insulator, SGOI), Germanium On Insulator (GOI).

Accordingly, the present invention integrates the source region and other well regions into the semiconductor substrate 200 at the beginning of the process, using a special arrangement of the discontinuous isolation structure. Among them, the value of other well areas is a customary means of those familiar with the technology, and will not be described here.

Next, referring to FIG. 4, a tunnel oxide layer 202a is formed on the semiconductor substrate 200 by, for example, a thermal oxidation method. The tunnel oxide layer 202a is, for example, a hafnium oxide layer. The tantalum nitride layer 202b is deposited by, for example, Low Pressure Chemical Vapor Deposition (LPCVD). Subsequent to the deposition of the yttrium oxide layer 202c (i.e., the cladding oxide layer) by, for example, thermal oxidation, an ONO (Oxide-Nitride-Oxide) structure is formed (see Figure 5).

Next, referring to FIG. 6, a control gate 202d (eg, deposited polysilicon poly) is formed. The control gate 202d is deposited on the ONO structure, and then formed by a patterning process such as a photoresist mask and etching. A plurality of gate structures 202 (see FIG. 7), wherein the stacked structure without the isolation structure 210 becomes the gate structure 202 (as indicated by the figure in FIG. 7), and the lateral gate structure 202 The word lines WL are connected in a strip. In addition, as shown, the arrangement direction of the control gate 202d on the semiconductor substrate 200 is perpendicular to the isolation structures 210.

Next, please refer to FIG. 8, which is a first exemplary diagram of the arrangement relationship between the isolation structure and the source line contact window of the present invention. In the figure, a single cell "Unit Cell" is the UC area in the drawing. In the semiconductor substrate, on the map In the lateral direction, the source line SL is connected to a source line contact window 226 for each of the two intermittent isolation structures 210. In a preferred embodiment, the source line SL is connected to a source line contact window 226 for every 64 intermittent isolation structures 210, that is, every 64 bit lines are connected to have a reference potential. Vss pickup. Further, the regions between the isolation structures 210 and the adjacent isolation structures 210 in the semiconductor substrate have a width (ie, "X") of 0.16 μm in a direction parallel to the word line WL; The polar line SL has a width in the direction of the vertical word line WL, and the distance between each source line SL and the word line WL on the semiconductor substrate (ie, "Y") is 0.1 μm.

Next, please refer to FIG. 9, which is a second exemplary diagram of the arrangement relationship between the isolation structure and the source line contact window of the present invention. In the semiconductor substrate, every two intermittent isolation structures 210 have an intact isolation structure 210 that is not cut, and is adjacent to the drain region 206 between the two isolated isolation structures 210. A source line contact window 226 is formed at the intersection with the source line SL.

Next, please refer to FIG. 10, which is a third exemplary diagram of the arrangement relationship between the isolation structure and the source line contact window of the present invention. Wherein, the line "L" having the source line contact window 226 parallel to the isolation structures 210 is a discontinuous isolation structure 210, and the straight line and the adjacent isolation structure form a larger block isolation structure. region.

In another aspect, the method for operating the non-volatile memory may include: a programming step of one of a gate, a source region, and a drain region of a SONOS memory cell to be programmed. Apply a positive voltage; The erasing step applies a positive voltage to one of the source region and the drain region of the SONOS memory cell to be erased, and applies a negative voltage to the gate of the SONOS memory cell to be erased; The reading step is one of a gate, a drain region and a source region of the SONOS memory cell to be read, and both apply a positive voltage, wherein the voltage applied in the reading step is low The voltage applied during this programming step, therefore, is only read in the read step of low applied voltage.

In summary, the structure disclosed in the present invention can greatly reduce the spatial arrangement in the non-volatile memory, thereby contributing to the miniaturization of the memory, for example, the gate structure under the two adjacent character lines. It will be designed to be closer, and if it is known in the art, the space of the source line contact window needs to be considered.

The invention has been described above in terms of the preferred embodiments, and it should be understood by those skilled in the art that the present invention is not intended to limit the scope of the invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of protection of the present invention is defined by the scope of the patent application.

102‧‧‧ gate structure

102d‧‧‧Control gate

104‧‧‧ source area

106‧‧‧Bungee Area

110‧‧‧Isolation structure

122‧‧‧Source line contact window

124‧‧‧ bit line contact window

200‧‧‧Semiconductor substrate

202‧‧‧ gate structure

202a‧‧‧ Tunneling Oxidation Layer

202b‧‧‧ layer of tantalum nitride

202c‧‧‧Oxide layer

202d‧‧‧Control gate

204‧‧‧ source area

206‧‧‧Bungee Area

210‧‧‧Isolation structure

210a‧‧‧ gap

224‧‧‧ bit line contact window

226‧‧‧Source line contact window

L‧‧‧ Go straight

UC‧‧‧ single cell

WL‧‧‧ character line

SL‧‧‧ source line

Figure 1 is a top plan view of a conventional non-volatile memory array.

2 is a top plan view of a non-volatile memory having a discontinuous isolation structure and SONOS memory cells in accordance with an embodiment of the present invention.

3-7 are perspective cross-sectional views of a non-volatile memory having a discontinuous isolation structure and SONOS memory cells in different process steps according to an embodiment of the present invention.

Figure 8 is a first exemplary diagram showing the arrangement relationship between the isolation structure and the source line contact window of the present invention.

Figure 9 is a second exemplary diagram showing the arrangement relationship between the isolation structure and the source line contact window of the present invention.

Figure 10 is a third exemplary diagram showing the arrangement relationship between the isolation structure and the source line contact window of the present invention.

202‧‧‧ gate structure

202d‧‧‧Control gate

204‧‧‧ source area

206‧‧‧Bungee Area

210‧‧‧Isolation structure

224‧‧‧ bit line contact window

Claims (11)

A non-volatile memory having a discontinuous isolation structure and a SONOS memory cell, comprising: a semiconductor substrate having an array region, the array region comprising a plurality of isolation structures, the isolation structures being parallel to each other and each The isolation structure has a plurality of voids that cut the isolation structure, the voids forming a plurality of channels exposing the semiconductor substrate in a direction perpendicular to the isolation structure; the plurality of source lines being perpendicular to the arrangement direction of the isolation structures The source lines are located in the channels of the semiconductor substrate; a plurality of SONOS memory cells are located on the semiconductor substrate between adjacent two isolation structures; and a plurality of gate regions are located adjacent to each other In the semiconductor substrate between the isolation structures, wherein the drain region of each SONOS memory cell and the connected source line are located in the semiconductor substrate on different sides of the word line parallel to the source lines In the semiconductor substrate, every two intermittent isolation structures have a complete isolation structure that is not cut, and adjacent to the two Drain off the region between the isolation structure and the intersection of the source line source line having a source line contact window. The non-volatile memory of claim 1, wherein the isolation structure is a shallow trench isolation structure. The non-volatile memory of claim 1, wherein in the semiconductor substrate, the source line passes through two intermittent isolation structures. A source line contact window is connected. The non-volatile memory of claim 1, wherein in the semiconductor substrate, the source line is connected to a source line contact window for each of the 64 intermittent isolation structures. The non-volatile memory of claim 4, wherein the isolation structure and the region between the adjacent two isolation structures in the semiconductor substrate have 0.16 μm in a direction parallel to the word line. The width. The non-volatile memory of claim 5, wherein the source lines have a width in a direction of a vertical word line, and each source line and character on the semiconductor substrate The distance between the lines is 0.1 μm. The non-volatile memory of claim 1, wherein the source line contact window parallel to the isolation structures is a discontinuous isolation structure, the straight line and the adjacent line. The isolation structure forms an isolated structural region of a larger block. The non-volatile memory according to claim 1, wherein the material of the source lines is one of cobalt telluride, nickel telluride and titanium telluride. A method for fabricating a non-volatile memory having a discontinuous isolation structure and a SONOS memory cell, comprising the steps of: forming a plurality of intermittent isolation structures in a semiconductor substrate, wherein each isolation structure has a cutoff a plurality of voids of the isolation structure, the voids forming a plurality of channels exposing the semiconductor substrate in a direction perpendicular to the isolation structure; performing a source ion implantation process for the semiconductor substrates Forming a plurality of source lines in the track; forming an ONO structure on the semiconductor substrate; depositing a control gate and patterning the control gate to form a plurality of word lines; and forming a source line contact window, wherein the step of forming the isolation structures In the middle, every two discontinuous isolation structures are formed with a complete isolation structure that is not cut. The manufacturing method of claim 9, wherein in the step of forming the source line contact window, each source line is connected to a source line contact window for each of the two intermittent isolation structures. The manufacturing method of claim 9, wherein in the step of forming the source line contact window, each source line is connected to a source line contact window for each of the 64 intermittent isolation structures.