CN103579247B - A kind of Nonvolatile memory and operational approach, manufacture method - Google Patents

A kind of Nonvolatile memory and operational approach, manufacture method Download PDF

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Publication number
CN103579247B
CN103579247B CN201210269312.3A CN201210269312A CN103579247B CN 103579247 B CN103579247 B CN 103579247B CN 201210269312 A CN201210269312 A CN 201210269312A CN 103579247 B CN103579247 B CN 103579247B
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China
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described
isolation structure
semiconductor substrate
nonvolatile memory
source
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CN201210269312.3A
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Chinese (zh)
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CN103579247A (en
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赤荻隆男
吴怡德
陈宜秀
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宜扬科技股份有限公司
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Abstract

The invention discloses a kind of there is discontinuous isolation structure and the Nonvolatile memory of SONOS memory cell and operational approach, manufacture method, it is on the semiconductor substrate with an array region, each isolation structure is made to have multiple space and form the isolation structure of discontinuous, so that source electrode line can be implanted in the semiconductor substrate in described space.Thereby, not being isolated structure due to source electrode line and interrupt, the potential barrier plug quantity of disconnected unit and line can be greatly decreased, and then saves the space that potential barrier plug in Nonvolatile memory can take.

Description

A kind of Nonvolatile memory and operational approach, manufacture method

Technical field

The present invention is about a kind of Nonvolatile memory, more particularly has discontinuous isolation structure and the Nonvolatile memory of SONOS memory cell and the operational approach of described Nonvolatile memory, manufacture method about a kind of.

Background technology

Along with the development of semiconductor integrated circuit manufacturing technology, memory cell quantity contained in Nonvolatile memory is continuously increased, and the size of assembly also constantly reduces because of the raising of integration.

But, no matter how little the size of assembly be reduced to, and remains a need for making suitable insulation or isolation between each memory cell in Nonvolatile memory, stability during to guarantee that memory cell works and reach to play good storage characteristics.

Fig. 1 is existing Nonvolatile memory array top view.Fig. 1 shows part Nonvolatile memory array, has the multiple grid structures 102 as SONOS memory cell in described memory array, and described grid structure 102 is connected into transversely arranged character line by controlling lock 102d.The drain region 106 that be parallel to character line adjacent with a grid structure 102 and source region 104.As shown in Figure 1, on source area 104 between adjacent two character lines, there is source line contact hole 122, potential barrier plug can be filled in source line contact window 122 and link together through source line (not shown) in top, and then making to be isolated the source area 104 that structure 110 separates and can be electrically connected and be connected into the source electrode line of a rule.Then there is on drain region 106 bit line contacting window 124, potential barrier plug can be filled in bit line contacting window 124 and link together through a bit line (not shown) in top, so make to be isolated drain region 106 that structure 110 separates can be in the bit line being connected above into a rule.

But, due to described contact hole 122,124 and the setting of potential barrier plug, technologic difficulty can be caused for the target of micro size of components and reduce the yield of product.

Summary of the invention

One of present invention purpose is the arrangement space in simplifying Nonvolatile memory, and then contributes to the micro of internal memory.

For reaching above-mentioned purpose and other purposes, the present invention proposes a kind of Nonvolatile memory with discontinuous isolation structure and SONOS memory cell, described Nonvolatile memory comprises: semiconductor substrate, described have an array region, this array region comprises a plurality of isolation structure, parallel to each other and each isolation structure of isolation structure has the multiple spaces cutting off this isolation structure, and described space is upwardly formed the plurality of passages exposing this semiconductor substrate in the side being perpendicular to isolation structure;A plurality of source electrode line, is perpendicular to the orientation of described isolation structure, and described source electrode line is positioned in the described passage of this semiconductor substrate;Multiple SONOS memory cells, are positioned on the described semiconductor substrate between adjacent two isolation structures;And multiple drain region, it is positioned in the described semiconductor substrate between adjacent two isolation structures, wherein, in the described semiconductor substrate of the not homonymy that the drain region of each SONOS memory cell and the source electrode line connected are located parallel to the character line of described source electrode line.

In an embodiment, this isolation structure is a fleet plough groove isolation structure.

In an embodiment, in this semiconductor substrate, this source electrode line often connects through the isolation structure of 2 discontinuous source line contact hole.

In an embodiment, in this semiconductor substrate, this source electrode line often connects through the isolation structure of 64 discontinuous source line contact hole.Additionally, the region in this semiconductor substrate between described isolation structure and adjacent two isolation structures, the direction be parallel to character line can have the width of 0.16 μm.Further, on the width that described source electrode line has on the direction of vertical characters line, and this semiconductor substrate, every distance between source line and character line, is 0.1 μm.

In an embodiment, described source electrode line material is one of them of cobalt silicide, nickle silicide and titanium silicide three.

In an embodiment, in this semiconductor substrate, every the isolation structure of two discontinuous, there is a complete isolation structure being not switched off, and adjacent to the drain region between described two cut-off isolation structures and source electrode line confluce, there is source line contact hole.Additionally, the craspedodrome being parallel to described isolation structure with described source line contact window also can be all the isolation structure of discontinuous, this craspedodrome forms the isolation structure region of bigger block with adjacent isolation structure.

The present invention proposes the operational approach of a kind of aforesaid Nonvolatile memory simultaneously, and it comprises: a programming step, to the source area of SONOS memory cell to be programmed and the one of drain region and grid all applies positive voltage;One erases step, the source area of the SONOS memory cell to be erased and the one of drain region is applied positive voltage, and the grid of the SONOS memory cell to be erased is applied negative voltage;And a read step, to the drain region of SONOS memory cell to be read and the one of source area and grid all to be applied positive voltage.

For reaching above-mentioned purpose and other purposes, the present invention proposes the manufacture method of a kind of Nonvolatile memory with discontinuous isolation structure and SONOS memory cell simultaneously, comprise the steps of the isolation structure forming a plurality of discontinuous in semiconductor substrate, wherein, each isolation structure has the multiple spaces cutting off described bar isolation structure, and described space is upwardly formed the plurality of passages exposing described semiconductor substrate in the side being perpendicular to isolation structure;Carry out source ion implanting processes, to form a plurality of source electrode line in the described passage of described semiconductor substrate;ONO structure is formed on described semiconductor substrate;Depositional control lock and pattern described control lock to form a plurality of character line;And form source line contact window.

Thereby, the present invention is by particular arrangement during formation isolation structure, it is formed without described isolation structure so that the Nonvolatile memory of the present invention is not required to as known techniques to need substantial amounts of source line contact window will be isolated the source area that structure separates and be electrically connected with into the source electrode line of a rule at the passage that can be passed through by source electrode line on semiconductor substrate in advance.

On the other hand, though the isolation structure of whole piece can be left to subsequent technique and excavate, but, be pre-formed that the isolation structure of discontinuous can exempt that the isolation structure needing to be pointed on source electrode line region on subsequent technique carries out excavates step.If aforesaid isolation structure excavates step when not excavating clean, the formation of implantation area can be hindered because not excavating clean isolation structure, so the resistance making source area is strengthened, and then cause whole active region to be lost efficacy.

Therefore, the discontinuous isolation structure of the present invention not only can be simplified metallization processes memory cell more can be avoided not excavate risk that is clean and that lost efficacy because of isolation structure.

Accompanying drawing explanation

Fig. 1 is the top view of existing Nonvolatile memory array.

Fig. 2 is the top view of the Nonvolatile memory in one embodiment of the invention with discontinuous isolation structure and SONOS memory cell.

Fig. 3-Fig. 7 is the sectional axonometric drawing that one embodiment of the invention has the Nonvolatile memory of discontinuous isolation structure and SONOS memory cell under different process step.

Fig. 8 is the first exemplary plot of the configuration relation between the isolation structure of the present invention and source line contact window.

Fig. 9 is the second exemplary plot of the configuration relation between the isolation structure of the present invention and source line contact window.

Figure 10 is the 3rd exemplary plot of the configuration relation between the isolation structure of the present invention and source line contact window.

Drawing reference numeral:

102 grid structures

102d controls lock

104 source areas

106 drain regions

110 isolation structures

122 source line contact windows

124 bit line contacting windows

200 semiconductor substrates

202 grid structures

202a tunnel oxide

202b silicon nitride layer

202c silicon oxide layer

202d control gate

204 source areas

206 drain regions

210 isolation structures

210a space

224 bit line contacting windows

226 source line contact windows

L keeps straight on

The single cell element of UC

WL character line

SL source electrode line

Detailed description of the invention

For being fully understood by the purpose of the present invention, feature and effect, hereby by following specific embodiment, and coordinate institute's accompanying drawings, the present invention be described in detail, be described as follows:

Be interrupted of isolation structure that the present invention will be formed originally on semiconductor substrate, the space being interrupted described isolation structure can be upwardly formed the source area of a whole piece, to remove the shortcoming that corresponding each grid structure is accomplished by source line contact hole from the side being perpendicular to isolation structure.

First, refer to Fig. 2, one embodiment of the invention has the Nonvolatile memory top view of discontinuous isolation structure and SONOS memory cell.Fig. 2 shows the Nonvolatile memory array of part, has the multiple grid structures 202 as SONOS memory cell in this memory array, and described grid structure 202 is connected into transversely arranged character line by control gate 202d.The adjacent drain region 206 being parallel to character line of one grid structure 202 and source region 204.The isolation structure 210 of the present invention is discontinuous.As shown in Figure 2, without the existence of isolation structure 210 between the source area 104 being spaced in prior art, that is, implant the source area of a whole piece will can be gone out when source area implant, eliminate the making step of the potential barrier plug of source line contact window and correspondence thereof, and then the arrangement space in simplifying Nonvolatile memory.

Under structure in embodiments of the present invention, can be in the SONOS memory cell every a predetermined quantity, just need to arrange one for the source region contact window that exposed electrical connects and corresponding potential barrier plug thereof, significantly simplified the arrangement space in assembly, and then contributed to the micro of internal memory.For example, at least can be spaced two SONOS memory cells and one potential barrier plug is just set.One potential barrier plug just need to be set as the SONOS memory cell being spaced many small number and can be depending on the driving force of whole assembly, that is, can design according to being actually needed.

As for the most still having bit line contacting window 224 on drain region 206, potential barrier plug can be filled in bit line contacting window 224 and link together through a bit line (not shown) in top, so make described be isolated drain region 206 that structure 210 separates can be in the bit line being connected above into a rule.

Then, referring to Fig. 3 to Fig. 7, one embodiment of the invention has the sectional axonometric drawing of the Nonvolatile memory of discontinuous isolation structure and SONOS memory cell under different process step.Described sectional axonometric drawing is only a part for Nonvolatile memory sectional axonometric drawing, and each assembly ratio in figure is only used as signal with reference to using.

Referring initially to Fig. 3, in semiconductor substrate 200, first form the isolation structure 210 of a plurality of discontinuous with shielding or other equivalent way.Each isolation structure 210 has the multiple space 210a cutting off this isolation structure 210.Described space 210a can be upwardly formed a plurality of channel exposing this semiconductor substrate 200 in the side being perpendicular to isolation structure 210.Then source ion implanting processes is carried out, described a plurality of channel is i.e. used for the implant for source area, to allow implant ion cloth implant in the semiconductor substrate 200 at passage, forming source area 204, described source area 204 is in the semiconductor substrate 200 of grid structure 202 (referring to Fig. 7) side after the carrying out of subsequent technique.The material of described semiconductor substrate 200 can be silicon (Si), SiGe (SiGe), silicon-on-insulator (SiliconOnInsulator, SOI), silicon-on-insulator germanium (SiliconGermaniumOnInsulator, SGOI), insulating barrier overlying germanium (GermaniumOnInsulator, GOI).

Accordingly, source area and other wellblocks cloth in the lump are implanted in this semiconductor substrate 200 by the present invention in the first special arrangement i.e. utilizing discontinuous isolation structure of technique.Wherein, the implantation of other wellblocks is the customary means belonging to those skilled in the art, repeats no more in this.

Then refer to Fig. 4, described semiconductor substrate 200 utilize such as thermal oxidation process to make tunnel oxide 202a(tunneloxidelayer), described tunnel oxide 202a for example, silicon oxide layer.Recycle such as Low Pressure Chemical Vapor Deposition (LowPressureChemicalVaporDeposition, LPCVD) and carry out deposited silicon nitride layer 202b.Follow-up, be to utilize such as thermal oxidation process to carry out silicon oxide layer deposited 202c (being i.e. coated with oxide layer), form a kind of ONO(Oxide-Nitride-Oxide) structure (referring to Fig. 5).

Then Fig. 6 is referred to, form a control lock 202d (such as: deposit polycrystalline silicon poly) again, described control gate 202d is deposited on ONO structure, multiple grid structures 202 (referring to Fig. 7) of storehouse are formed again by the Patternized technique of the shielding of e.g. photoresistance with etching, wherein, not having the stack architecture at isolation structure 210 and become grid structure 202 (such as the marked position of Fig. 7), horizontal grid structure 202 connects into the character line WL of a rule.Additionally, as it can be seen, described control lock 202d orientation on this semiconductor substrate 200 is perpendicular to described isolation structure 210.

Then Fig. 8 is referred to, the exemplary plot 1 of the configuration relation between the isolation structure of the present invention and source line contact window.In graphic, single cell element " UnitCell " be graphic in UC region.In this semiconductor substrate, for the horizontal direction of Fig. 8, source electrode line SL often connects through the isolation structure 210 of 2 discontinuous source line contact hole 226.Often i.e. connect through the isolation structure 210 of 64 discontinuous in a preferred embodiment this source electrode line SL and have source line contact hole 226, that is, the pin (Vsspickup) with a reference potential it is coupled to every 64 bit lines.Further, the region in this semiconductor substrate between described isolation structure 210 and adjacent two isolation structures 210, the direction being parallel to character line WL has the width (i.e. " X ") of 0.16 μm;The width that described source electrode line SL has on the direction of vertical characters line WL, and the every source line SL on this semiconductor substrate and the distance between character line WL (i.e. " Y "), it is all 0.1 μm.

Then Fig. 9 is referred to, the second exemplary plot of the configuration relation between the isolation structure of the present invention and source line contact window.In this semiconductor substrate, every the isolation structure 210 of two discontinuous, there is a complete isolation structure 210 being not switched off, and with source electrode line SL confluce, there is source line contact hole 226 adjacent to the drain region 206 between these two cut-off isolation structures 210.

Then Figure 10 is referred to, the 3rd exemplary plot of the configuration relation between the isolation structure of the present invention and source line contact window.Wherein, there is the craspedodrome being parallel to described isolation structure 210 of this source line contact window 226 " L " it is all the isolation structure 210 of discontinuous, this craspedodrome forms the isolation structure region of bigger block with adjacent isolation structure.

On the other hand, operational approach for aforesaid Nonvolatile memory comprises: a programming step, to the source area of SONOS memory cell to be programmed and the one of drain region and to grid, (that is: source area and grid or drain region and grid) both this is all applied positive voltage;One erases step, the source area of the SONOS memory cell to be erased and the one of drain region is applied positive voltage, and the grid of the SONOS memory cell to be erased is applied negative voltage;And a read step, to the drain region of SONOS memory cell to be read and the one of source area and to grid, (that is: drain region and grid or source area and grid) both this is all applied positive voltage, the voltage wherein applied in this read step is less than the voltage applied in this programming step, therefore, the read step of low applied voltage is only read out.

In sum, disclosed structure can significantly simplify the arrangement space in Nonvolatile memory, and then contribute to the micro of internal memory, for example, grid structure under two adjacent character lines can be designed closer to, and if also need to as prior art consider source line contact window space.

The present invention discloses with preferred embodiment the most, is so familiar with the technology person and it should be understood that described embodiment is only used for describing the present invention, and is not construed as limiting the scope of the present invention.It should be noted that such as equivalent with this embodiment change and displacement, all should be set to be covered by scope of the invention.Therefore, protection scope of the present invention is when as defined in claim.

Claims (8)

1. a Nonvolatile memory with discontinuous isolation structure and SONOS memory cell, it is characterised in that described Nonvolatile memory comprises:
Semiconductor substrate, there is an array region, described array region comprises a plurality of isolation structure, parallel to each other and each isolation structure of described a plurality of isolation structure has the multiple spaces cutting off described bar isolation structure, and described space is upwardly formed the plurality of passages exposing described semiconductor substrate in the side being perpendicular to isolation structure;
A plurality of source electrode line, is perpendicular to the orientation of described isolation structure, and described source electrode line is positioned in the described passage of described semiconductor substrate;
Multiple SONOS memory cells, are positioned on the described semiconductor substrate between adjacent two isolation structures;And
Multiple drain regions, are positioned in the described semiconductor substrate between adjacent two isolation structures, wherein, in the described semiconductor substrate of the not homonymy that the drain region of each SONOS memory cell and the source electrode line connected are located parallel to the character line of described source electrode line,
Wherein, in described semiconductor substrate, every the isolation structure of two discontinuous, there is a complete isolation structure being not switched off, adjacent to and the craspedodrome that is parallel between described two cut-off isolation structures with source electrode line confluce, there is source line contact hole.
2. Nonvolatile memory as claimed in claim 1, it is characterised in that described isolation structure is a fleet plough groove isolation structure.
3. Nonvolatile memory as claimed in claim 1, it is characterised in that the region in described semiconductor substrate between described isolation structure and adjacent two isolation structures, has the width of 0.16 μm on the direction be parallel to character line.
4. Nonvolatile memory as claimed in claim 3, it is characterised in that the width that described source electrode line has on the direction of vertical characters line, and the every source line on described semiconductor substrate and the distance between character line, be 0.1 μm.
5. Nonvolatile memory as claimed in claim 1, it is characterized in that, the craspedodrome being parallel to described isolation structure with described source line contact window is all the isolation structure of discontinuous, and described craspedodrome forms the isolation structure region of bigger block with adjacent isolation structure.
6. the Nonvolatile memory as described in claim 1, it is characterised in that the material of described source electrode line is one of them of cobalt silicide, nickle silicide and titanium silicide three.
7. the operational approach using Nonvolatile memory as claimed in claim 1, it is characterised in that described operational approach comprises:
One programming step, to the source area of SONOS memory cell to be programmed and the one of drain region and grid all applies positive voltage;
One erases step, the source area of the SONOS memory cell to be erased and the one of drain region is applied positive voltage, and the grid of the SONOS memory cell to be erased is applied negative voltage;And
One read step, to the drain region of SONOS memory cell to be read and the one of source area and grid all applies positive voltage.
8. the manufacture method of a Nonvolatile memory with discontinuous isolation structure and SONOS memory cell, it is characterised in that described manufacture method comprises the steps of
Forming the isolation structure of a plurality of discontinuous in semiconductor substrate, wherein, each isolation structure has the multiple spaces cutting off described bar isolation structure, and described space is upwardly formed the plurality of passages exposing described semiconductor substrate in the side being perpendicular to isolation structure;
Carry out source ion implanting processes, to form a plurality of source electrode line in the described passage of described semiconductor substrate;
ONO structure is formed on described semiconductor substrate;
Depositional control lock and pattern described control lock to form a plurality of character line;And
Form source line contact window,
Wherein, in the step forming described isolation structure, in the isolation structure every two discontinuous, there is a complete isolation structure being not switched off.
CN201210269312.3A 2012-07-31 2012-07-31 A kind of Nonvolatile memory and operational approach, manufacture method CN103579247B (en)

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KR100432888B1 (en) * 2002-04-12 2004-05-22 삼성전자주식회사 Non-volitile memory device and method thereof
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TW200943494A (en) * 2008-04-11 2009-10-16 Eon Silicon Solution Inc Non-volatile memory device and manufacturing method thereof
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Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5976927A (en) * 1998-04-10 1999-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Two mask method for reducing field oxide encroachment in memory arrays
US6436751B1 (en) * 2001-02-13 2002-08-20 United Microelectronics Corp. Fabrication method and structure of a flash memory
CN1545707A (en) * 2001-08-25 2004-11-10 崔雄林 Non-volatile semiconductor memory and method of operating the same
KR20080030243A (en) * 2006-09-29 2008-04-04 주식회사 하이닉스반도체 Flash memory device
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