TWI470464B - Circuit design simulation system and curcuit design method for pcb - Google Patents

Circuit design simulation system and curcuit design method for pcb Download PDF

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TWI470464B
TWI470464B TW101133247A TW101133247A TWI470464B TW I470464 B TWI470464 B TW I470464B TW 101133247 A TW101133247 A TW 101133247A TW 101133247 A TW101133247 A TW 101133247A TW I470464 B TWI470464 B TW I470464B
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printed circuit
circuit board
density
density value
information
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TW101133247A
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TW201411384A (en
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wei fan Yu
Aries De Guzman Lumague
Ruey Rong Chang
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Wistron Corp
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Description

印刷電路板之電路設計模擬系統及其電路設計方法Circuit design simulation system of printed circuit board and circuit design method thereof

本發明係有關於一種電路設計方法,且特別有關於一種印刷電路板的電路設計方法。The present invention relates to a circuit design method, and more particularly to a circuit design method for a printed circuit board.

在電子產品的開發成本中,印刷電路板(Printed Circuit Board,PCB)的價格幾乎佔了整體3分之1至2分之1的比例。因此,印刷電路板的價格對產品整體的價格具有決定性的影響。印刷電路板的價格取決於印刷電路板的佈局層數以及印刷電路板的製程。傳統上,必須先請機構工程師與電子工程師準備相關資料給佈局(layout)工程師,再由佈局工程師透過佈局工具/軟體來實際擺放零件與佈線,因此需要花費2~3天的時間才能得知佈局層數等結果。Among the development costs of electronic products, the price of printed circuit boards (PCBs) accounts for almost one-third to one-half of the total. Therefore, the price of the printed circuit board has a decisive influence on the overall price of the product. The price of a printed circuit board depends on the number of layout layers of the printed circuit board and the process of the printed circuit board. Traditionally, institutional engineers and electronic engineers must first prepare relevant materials for the layout engineer, and then the layout engineer actually places the parts and wiring through the layout tool/software, so it takes 2 to 3 days to know. Results such as the number of layout layers.

因此,需要一種自動化模擬程式能即時地進行印刷電路板層數與製程之模擬分析。Therefore, there is a need for an automated simulation program that enables instant simulation analysis of printed circuit board levels and processes.

本發明提供一種電路設計方法,適用於一印刷電路板。經由一使用者介面,得到欲設置在上述印刷電路板之一積體電路的複數規格參數。根據上述規格參數,得到上述積體電路於上述印刷電路板之一扇出腳位。根據上述扇出腳位以及上述規格參數,決定上述印刷電路板的一製程類型。根據上述製程類型,得到設置上述積體電路於上述印刷電路板所需的一印刷電路板層數以及一密度值。The present invention provides a circuit design method suitable for use in a printed circuit board. Through a user interface, a plurality of specifications of the integrated circuit to be disposed on one of the printed circuit boards are obtained. According to the above specification parameters, the integrated circuit is obtained from a fan-out position of the printed circuit board. A process type of the printed circuit board is determined according to the fan-out position and the above specification parameters. According to the above process type, a number of printed circuit board layers and a density value required for setting the integrated circuit on the printed circuit board are obtained.

再者,本發明提供一種電路設計模擬系統,適用於一印刷電路板。上述電路設計模擬系統包括:一顯示器,用 以顯示一使用者介面;以及一處理器,耦接於上述顯示器。上述處理器經由上述使用者介面而得到欲設置在上述印刷電路板之一積體電路的複數規格參數。上述處理器根據上述規格參數而得到上述積體電路於上述印刷電路板之一扇出腳位,以決定上述印刷電路板的一製程類型。上述處理器根據上述製程類型而得到設置上述積體電路於上述印刷電路板所需的一印刷電路板層數以及一密度值。Furthermore, the present invention provides a circuit design simulation system suitable for use in a printed circuit board. The above circuit design simulation system includes: a display, used To display a user interface; and a processor coupled to the display. The processor obtains a plurality of specification parameters to be provided on one of the integrated circuits of the printed circuit board via the user interface. The processor obtains the fan-out circuit of the integrated circuit on the printed circuit board according to the specification parameter to determine a process type of the printed circuit board. The processor obtains a number of printed circuit board layers and a density value required to set the integrated circuit on the printed circuit board according to the process type.

為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:實施例:第1圖係顯示根據本發明一實施例所述之適用於一印刷電路板的電路設計模擬系統100。電路設計模擬系統100包括處理器10、顯示器20以及儲存裝置30。顯示器20係用以顯示使用者介面40。處理器10耦接於顯示器20,因此使用者可透過顯示器20上的使用者介面40輸入欲模擬之積體電路的相關資訊,例如規格參數、積體電路之產品類型等。在接收到積體電路的相關資訊之後,處理器10會根據儲存在儲存裝置30的相關資料庫來執行自動化模擬程式,以便得到欲設置在印刷電路板之該積體電路所需使用到的印刷電路板層數、密度值以及製造成本等訊息。The above and other objects, features and advantages of the present invention will become more <RTIgt; A circuit design simulation system 100 suitable for use in a printed circuit board according to an embodiment of the invention. The circuit design simulation system 100 includes a processor 10, a display 20, and a storage device 30. Display 20 is used to display user interface 40. The processor 10 is coupled to the display 20, so that the user can input information about the integrated circuit to be simulated, such as the specification parameters, the product type of the integrated circuit, and the like through the user interface 40 on the display 20. After receiving the relevant information of the integrated circuit, the processor 10 executes an automated simulation program according to the relevant database stored in the storage device 30 to obtain the printing required for the integrated circuit to be set on the printed circuit board. Messages such as board count, density values, and manufacturing costs.

第2圖係顯示根據本發明一實施例所述之適用於一印刷電路板的電路設計方法。同時參考第1圖以及第2圖,首先,在步驟S202,處理器10可透過使用者介面40得到 欲設置在印刷電路板之積體電路的產品類型,例如該積體電路為中央處理器、晶片組或是圖形處理器等等。在此實施例中,積體電路的產品類型會影響印刷電路板之層數以及密度值。此外,該積體電路為球閘陣列封裝(ball grid array,BGA)之晶片。接著,處理器10會判斷使用者是否在設計佈局軟體(例如Allegro)上執行此實施例之印刷電路板的電路設計方法(步驟S204)。若否,處理器10會判定使用者是在全球資訊網(Web)的介面上執行此實施例之印刷電路板的電路設計方法(步驟S206)。接著,處理器10會啟動BGA模擬器(步驟S208),以便執行扇出(fanout)分析而得到該積體電路的扇出腳位(footprint)(步驟S210)。反之,若處理器10判定使用者是在設計佈局軟體(例如Allegro)上執行此實施例之印刷電路板的電路設計方法,則處理器10會直接執行扇出分析而得到該積體電路的扇出腳位(步驟S210)。接著,在步驟S212,處理器10會根據該積體電路的扇出腳位來進行製程分析,以決定印刷電路板的製程類型,例如高密度內連線(High density interconnection,HDI)製程或非HDI製程。接著,在步驟S214,處理器10會根據所決定之印刷電路板的製程類型進行密度分析,以便得到欲將該積體電路設置在印刷電路板上所需的電路板層數以及密度值,其中密度值係指示印刷電路板之銅箔使用空間比值。接者,在步驟S216,處理器10會對密度值進行判別,以進一步判斷該積體電路實際上在印刷電路板上的佈局是否可行。接著,在步驟S218,可根據密度值之判別結果,使用者可透 過使用者介面40來進一步對積體電路的相關資訊(例如規格參數、積體電路之產品類型)進行修正,並重新執行步驟S210。若不需要對參數進行修正,則處理器10會將詳細結果顯示於使用者介面40上,並將對應於該積體電路之扇出腳位、製程類型、印刷電路板層數以及密度值儲存在儲存裝置30中(步驟S220)。Figure 2 is a diagram showing a circuit design method suitable for a printed circuit board according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 2 simultaneously, first, in step S202, the processor 10 can be obtained through the user interface 40. The product type of the integrated circuit to be disposed on the printed circuit board, for example, the integrated circuit is a central processing unit, a chipset, or a graphics processor. In this embodiment, the product type of the integrated circuit affects the number of layers of the printed circuit board as well as the density value. In addition, the integrated circuit is a ball grid array (BGA) wafer. Next, the processor 10 determines whether the user performs the circuit design method of the printed circuit board of this embodiment on the design layout software (for example, Allegro) (step S204). If not, the processor 10 determines that the user is performing the circuit design method of the printed circuit board of this embodiment on the interface of the World Wide Web (Web) (step S206). Next, the processor 10 starts the BGA simulator (step S208) to perform a fanout analysis to obtain a fan-out footprint of the integrated circuit (step S210). On the other hand, if the processor 10 determines that the user is performing the circuit design method of the printed circuit board of the embodiment on the design layout software (for example, Allegro), the processor 10 directly performs fan-out analysis to obtain the fan of the integrated circuit. The foot position (step S210). Next, in step S212, the processor 10 performs process analysis according to the fan-out pin of the integrated circuit to determine the process type of the printed circuit board, such as a high-density interconnect (HDI) process or a non- HDI process. Next, in step S214, the processor 10 performs density analysis according to the determined process type of the printed circuit board to obtain the number of circuit board layers and density values required to set the integrated circuit on the printed circuit board, wherein The density value indicates the space ratio of the copper foil used for the printed circuit board. Then, in step S216, the processor 10 discriminates the density value to further determine whether the layout of the integrated circuit actually on the printed circuit board is feasible. Next, in step S218, according to the discrimination result of the density value, the user can The user interface 40 is further used to further correct information about the integrated circuit (for example, the specification parameter, the product type of the integrated circuit), and the step S210 is re-executed. If the parameter is not required to be corrected, the processor 10 displays the detailed result on the user interface 40, and stores the fan-out pin, the process type, the number of printed circuit board layers, and the density value corresponding to the integrated circuit. In the storage device 30 (step S220).

第3圖係顯示根據本發明一實施例所述之執行扇出分析(例如第2圖之步驟S210)的流程圖。同時參考第1圖以及第3圖,首先,在步驟S302,處理器10會得到該積體電路的資料,例如產品編號。接著,處理器10會判斷該積體電路的資料是否儲存在儲存單元30內的密度模擬結果資料庫內(步驟S304)。若是,則處理器10會從密度模擬結果資料庫內得到該積體電路的密度模擬結果(步驟S306),例如欲設置在印刷電路板之該積體電路所需使用到的印刷電路板層數、密度值以及製造成本等,並將密度模擬結果顯示在使用者介面40。若該積體電路的資料並未儲存在密度模擬結果資料庫內,則處理器10會判斷該積體電路的資料是否儲存在儲存單元30內的佈局零件資料庫內(步驟S308)。若是,則處理器10會從佈局零件資料庫內得到該積體電路的扇出腳位(步驟S310),並進行第2圖之步驟212。若該積體電路的資料並未儲存在佈局零件資料庫內,則使用者可透過使用者介面40來對該積體電路的規格參數進行設定(步驟S312)。接著,處理器10便可根據所設定的規格參數建立扇出腳位(步驟S314)。Figure 3 is a flow chart showing the execution of a fan-out analysis (e.g., step S210 of Figure 2) in accordance with an embodiment of the present invention. Referring to FIG. 1 and FIG. 3 simultaneously, first, in step S302, the processor 10 obtains data of the integrated circuit, such as a product number. Next, the processor 10 determines whether the data of the integrated circuit is stored in the density simulation result database in the storage unit 30 (step S304). If so, the processor 10 obtains the density simulation result of the integrated circuit from the density simulation result database (step S306), for example, the number of printed circuit board layers to be used in the integrated circuit of the printed circuit board. The density value, the manufacturing cost, and the like, and the density simulation result is displayed on the user interface 40. If the data of the integrated circuit is not stored in the density simulation result database, the processor 10 determines whether the data of the integrated circuit is stored in the layout part database in the storage unit 30 (step S308). If so, the processor 10 obtains the fan-out pin of the integrated circuit from the layout component database (step S310), and proceeds to step 212 of FIG. If the data of the integrated circuit is not stored in the layout component database, the user can set the specification parameters of the integrated circuit through the user interface 40 (step S312). Next, the processor 10 can establish a fan-out pin according to the set specification parameters (step S314).

第4圖係顯示根據本發明一實施例所述之使用者介面 400,用以設定積體電路的規格參數(BGA Parameters)。在使用者介面400中,使用者可透過欄位Name來輸入該積體電路之產品編號。因此,在第3圖之步驟S304以及步驟S308中,處理器10便可判斷產品編號BGA645是否儲存在儲存單元30內的密度模擬結果資料庫或是佈局零件資料庫中。若產品編號BGA645已儲存在密度模擬結果資料庫或是佈局零件資料庫中,則表示該積體電路先前已分析過,則處理器10會將該積體電路的相關參數以及分析結果顯示在使用者介面40上。若產品編號BGA645並未儲存在密度模擬結果資料庫或是佈局零件資料庫中,則使用者可透過使用者介面400進一步對該積體電路的規格參數進行設定。舉例來說,欄位Height係用來設定該積體電路的高度。欄位Pad係用來設定該積體電路的接腳尺寸。欄位pad to via係用來設定該積體電路的接腳至穿孔的間距。欄位Need 9-Corner Padstack係用來設定該積體電路之四個角落的接腳是否需要增大,以便增加零件的焊接性。此外,欄位PinCount係用來設定該積體電路的接腳總數量。欄位Pitch係用來設定該積體電路的接腳至接腳的間距。欄位Body係用來設定該積體電路的大小。欄位Fanout Via係用來設定扇出之穿孔規格。因此,一旦完成該積體電路的規格參數設定之後,處理器10便可根據規格參數的資訊建立該積體電路的扇出腳位。接著,處理器10便可依據欄位Pitch與欄位Fan out via的設定來對印刷電路板製程進行分析(例如HDI or None HDI),如第2圖的步驟S212所顯示。在一實施例中,若依基本的設計規範條件所分析出的 結果是HDI製程,有可能的原因是因為欄位Pitch的值差了一點點,導致無法放置穿孔所致。此時,使用者可以藉由調整欄位Pad的設定,使處理器10再重新分析一次,則有可能就不需要HDI製程。因此,使用者可透過使用者介面400來調整參數的設定值,以便得到更多分析的組合,以確保最低的印刷電路板的成本。Figure 4 is a diagram showing a user interface according to an embodiment of the invention. 400, used to set the BGA Parameters of the integrated circuit. In the user interface 400, the user can input the product number of the integrated circuit through the field name. Therefore, in step S304 and step S308 of FIG. 3, the processor 10 can determine whether the product number BGA 645, is stored in the density simulation result database or the layout part database in the storage unit 30. If the product number BGA645 has been stored in the density simulation result database or the layout part database, it indicates that the integrated circuit has been analyzed before, and the processor 10 displays the relevant parameters and analysis results of the integrated circuit in use. Interface 40. If the product number BGA645 is not stored in the density simulation result database or the layout part database, the user can further set the specification parameters of the integrated circuit through the user interface 400. For example, the field Height is used to set the height of the integrated circuit. The field Pad is used to set the pin size of the integrated circuit. The pad to via field is used to set the pitch of the integrated circuit to the perforation. The field Need 9-Corner Padstack is used to set whether the pins of the four corners of the integrated circuit need to be increased in order to increase the weldability of the parts. In addition, the field PinCount is used to set the total number of pins of the integrated circuit. The field Pitch is used to set the pitch of the integrated circuit to the pin. The field Body is used to set the size of the integrated circuit. The field Fanout Via is used to set the perforation specification for fanout. Therefore, once the specification parameter setting of the integrated circuit is completed, the processor 10 can establish the fan-out pin of the integrated circuit according to the information of the specification parameter. Then, the processor 10 can analyze the printed circuit board process (for example, HDI or None HDI) according to the setting of the field Pitch and the field Fan out via, as shown in step S212 of FIG. In an embodiment, if analyzed according to basic design specification conditions The result is the HDI process, and the possible reason is that the value of the Pitch in the field is a little worse, resulting in the inability to place the perforation. At this time, the user can re-analyze the processor 10 by adjusting the setting of the field Pad, and then the HDI process may not be needed. Therefore, the user can adjust the set value of the parameter through the user interface 400 to obtain a combination of more analysis to ensure the lowest cost of the printed circuit board.

第5圖係顯示根據本發明一實施例所述之執行密度分析(例如第2圖之步驟S214)的流程圖。同時參考第1圖以及第5圖,首先,使用者可透過使用者介面40來對先前第2圖之步驟S212所確定之製程類型的印刷電路板參數進行設定(步驟S502)。接著,處理器10會根據所設定之印刷電路板參數來進行電路板層數的分析(步驟S504)。接著,處理器10會根據模擬的電路板層數來進行密度分析(步驟S506),其中密度分析所得到之結果即為密度值(即電路板上銅箔使用空間比值)。Figure 5 is a flow chart showing the execution of a density analysis (e.g., step S214 of Figure 2) in accordance with an embodiment of the present invention. Referring to FIG. 1 and FIG. 5 simultaneously, first, the user can set the process type printed circuit board parameters determined by step S212 of the previous FIG. 2 through the user interface 40 (step S502). Next, the processor 10 analyzes the number of board layers based on the set printed circuit board parameters (step S504). Next, the processor 10 performs density analysis according to the number of simulated circuit board layers (step S506), wherein the result obtained by the density analysis is the density value (ie, the copper foil use space ratio on the circuit board).

第6圖係顯示根據本發明一實施例所述之使用者介面600,用以設定印刷電路板的印刷電路板參數(Density Parameters)。在此實施例中,使用者介面600係顯示非HDI製程的印刷電路板參數。在使用者介面600中,處理器10會將模擬得到的電路板層數顯示在相關欄位中。舉例來說,欄位Total Layer Count係顯示所需之印刷電路板的總層數。欄位Routing Layer Count係顯示印刷電路板中佈線層的數量,而欄位Plane Layer Count係顯示印刷電路板中平面層的數量。此外,欄位Trace Width係顯示印刷電路板上走線之寬度。在此實施例中,使用者可透過使用者介 面600來調整欄位Routing Layer Count、欄位Plane Layer Count以及欄位Trace Width。於是,處理器10可根據調整後的印刷電路板參數來重新進行密度分析。Figure 6 shows a user interface 600 for setting printed circuit board parameters of a printed circuit board in accordance with an embodiment of the present invention. In this embodiment, the user interface 600 displays printed circuit board parameters for non-HDI processes. In the user interface 600, the processor 10 displays the simulated number of board levels in the relevant fields. For example, the field Total Layer Count displays the total number of layers of the desired printed circuit board. The Routing Layer Count displays the number of routing layers in the printed circuit board, while the Plane Layer Count displays the number of planar layers in the printed circuit board. In addition, the field Trace Width displays the width of the traces on the printed circuit board. In this embodiment, the user can access the user interface. Face 600 adjusts the field Routing Layer Count, the field Plane Layer Count, and the field Trace Width. Processor 10 can then re-densitize the density based on the adjusted printed circuit board parameters.

第7圖係顯示根據本發明另一實施例所述之使用者介面700,用以設定印刷電路板的印刷電路板參數(Density Parameters)。在此實施例中,使用者介面700係顯示HDI製程的印刷電路板參數。相較於第6圖的使用者介面600,使用者介面700更包括欄位Laser Count以及欄位HDI Type。欄位Laser Count係用來設定進行雷射之次數,而欄位HDI Type係用來設定HDI製程的型態。因此,除了可調整欄位Routing Layer Count、欄位Plane Layer Count以及欄位Trace Width的參數值之外,使用者更可選擇不同型態的HDI製程方式來進行進一步的分析。於是,處理器10可根據調整後的印刷電路板參數來重新進行密度分析。Figure 7 is a diagram showing a user interface 700 for setting printed circuit board parameters of a printed circuit board in accordance with another embodiment of the present invention. In this embodiment, the user interface 700 displays printed circuit board parameters for the HDI process. Compared with the user interface 600 of FIG. 6, the user interface 700 further includes a field Laser Count and a field HDI Type. The field Laser Count is used to set the number of times the laser is performed, and the field HDI Type is used to set the type of the HDI process. Therefore, in addition to adjusting the parameter values of the field Routing Layer Count, the field Plane Layer Count and the field Trace Width, the user can select different types of HDI process for further analysis. Processor 10 can then re-densitize the density based on the adjusted printed circuit board parameters.

處理器10所得到的密度值以及印刷電路板層數只是參考,此分析之結果並不代表實際的佈局是可實施的。因此,為了確保分析之結果可應用在實際的電路佈局上,處理器10會根據過去實際做過的佈局資料庫來進行密度判別,以歸類出可行性判斷的標準方式。為了擷取實際做過之佈局資料庫的密度值,處理器10可在佈局資料庫中自動擷取BGA零件的密度值。此外,使用者亦可設定BGA零件之佈局的難易度權重值。於是,處理器10可根據實際做過之佈局資料庫的密度值以及難易度權重值進行資料的分析與歸類,並將結果儲存在儲存單元30的佈局密度萃取資料庫中,以便進行密度判別。The density values obtained by the processor 10 and the number of printed circuit board layers are only references, and the results of this analysis do not represent that the actual layout is implementable. Therefore, in order to ensure that the results of the analysis can be applied to the actual circuit layout, the processor 10 performs density discrimination based on the layout database actually done in the past to classify the standard way of feasibility judgment. In order to retrieve the density value of the layout database actually done, the processor 10 can automatically retrieve the density value of the BGA part in the layout database. In addition, the user can also set the difficulty weight value of the layout of the BGA part. Therefore, the processor 10 can analyze and classify the data according to the density value and the difficulty weight value of the layout database actually performed, and store the result in the layout density extraction database of the storage unit 30 for density discrimination. .

第8圖係顯示根據本發明一實施例所述之執行密度判別(例如第2圖之步驟S216)的流程圖。首先,處理器10會判斷密度值是否大於第一參考值(步驟S802)。若是,則處理器10會判定該密度值為無效(步驟S804),即該密度值在實際上的佈局是非常困難或是無法達成。若密度值小於或等於第一參考值,則處理器10會進一步判斷密度值是否小於或等於第二參考值(步驟S806),其中第二參考值小於第一參考值。若是,則處理器10會判定該密度值為有效,即該密度值在實際上的佈局是可行的(步驟S810)。反之,若密度值大於第二參考值,則處理器10會判定該密度值在實際上的佈局是具挑戰性的(步驟S808)。於是,使用者可透過使用者介面40來調整部分參數(第2圖之步驟S218),以便能得到小於或等於第二參考值之密度值。在此實施例中,第一參考值與第二參考值係從儲存單元30之佈局密度萃取資料庫所得到。Figure 8 is a flow chart showing the execution density discrimination (e.g., step S216 of Figure 2) in accordance with an embodiment of the present invention. First, the processor 10 determines whether the density value is greater than the first reference value (step S802). If so, the processor 10 determines that the density value is invalid (step S804), that is, the density value is very difficult or impossible to achieve in the actual layout. If the density value is less than or equal to the first reference value, the processor 10 further determines whether the density value is less than or equal to the second reference value (step S806), wherein the second reference value is smaller than the first reference value. If so, the processor 10 determines that the density value is valid, i.e., the density value is feasible in the actual layout (step S810). Conversely, if the density value is greater than the second reference value, the processor 10 determines that the density value is challenging in the actual layout (step S808). Thus, the user can adjust some of the parameters through the user interface 40 (step S218 of FIG. 2) so that a density value less than or equal to the second reference value can be obtained. In this embodiment, the first reference value and the second reference value are obtained from the layout density extraction database of the storage unit 30.

參考回第2圖,當處理器10判定該密度值為有效(步驟S216)且使用者不需對參數進行修正(步驟S218)時,處理器10會根據儲存單元30內的各製造商之價格資訊而分別得到對應於每一製造商之製造成本。接著,處理器10會將詳細結果顯示在使用者介面40上(步驟S220)。第9圖係顯示根據本發明一實施例所述之使用者介面900,用以顯示執行第2圖之電路設計方法的密度資料(Density Data)。在使用者介面900中,全部面積(Total Area)係表示印刷電路板中佈線層的數量再乘上該積體電路的面積。頂層面積(Top Area)係表示該積體電路的本體面積。 穿孔面積(Via Area)係表示佈線層上穿孔的總面積。走線面積(Trace Area)係表示全部走線的總面積。密度值(Density)係表示頂層面積、穿孔面積與走線面積的總和與全部面積的比例。成本比例(Cost Ratio)係根據密度值所得到的最低製造成本。Referring back to FIG. 2, when the processor 10 determines that the density value is valid (step S216) and the user does not need to correct the parameters (step S218), the processor 10 according to the price of each manufacturer in the storage unit 30. The information is obtained separately for each manufacturer's manufacturing cost. Next, the processor 10 displays the detailed result on the user interface 40 (step S220). FIG. 9 is a diagram showing a user interface 900 for displaying a density data (Density Data) for performing the circuit design method of FIG. 2 according to an embodiment of the invention. In the user interface 900, the total area (Total Area) indicates the number of wiring layers in the printed circuit board and multiplied by the area of the integrated circuit. The top area indicates the body area of the integrated circuit. The Via Area indicates the total area of the perforations on the wiring layer. The Trace Area is the total area of all traces. Density is the ratio of the total area of the top layer, the area of the perforation and the area of the trace to the total area. The Cost Ratio is the lowest manufacturing cost based on the density value.

根據本發明實施例之電路設計方法,不需要機構工程師與電子工程師提供機構圖與線路圖來進行佈局設計,而可隨時進行自動模擬分析與判斷。因此,避免了費時又費力的人工作業模式,同時也能提供即時且可信賴的價格因子,於是可提升產品即時報價的應變能力。通常,影響印刷電路板佈局層數與製程的主要因子即為所選用之BGA零件,一旦決定了BGA零件的電路板層數與製程,則整個印刷電路板的價格也就確定了。因此,透過處理器10來執行自動化模擬分析程式,就可以即時模擬分析所使用之各型態的BGA零件,而得到即時的印刷電路板價格。此外,自動化模擬分析程式可架構在既有的佈局工具內執行,也可以架構在WEB上,因此使用上較有彈性。According to the circuit design method of the embodiment of the invention, the mechanism engineer and the electronic engineer are not required to provide the mechanism diagram and the circuit diagram for layout design, and the automatic simulation analysis and judgment can be performed at any time. As a result, the time-consuming and labor-intensive manual mode of operation is avoided, and an immediate and reliable price factor is provided, thereby improving the resilience of the product's real-time quote. Generally, the main factor affecting the number of printed circuit board layout layers and processes is the BGA parts selected. Once the number of layers and processes of the BGA parts are determined, the price of the entire printed circuit board is determined. Therefore, by executing the automated simulation analysis program through the processor 10, it is possible to instantly simulate and analyze various types of BGA parts used, and obtain an instant printed circuit board price. In addition, the automated simulation analysis program can be implemented in the existing layout tool or on the WEB, so it is more flexible in use.

雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中包括通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is intended that the invention may be modified and modified without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10‧‧‧處理器10‧‧‧ processor

20‧‧‧顯示器20‧‧‧ display

30‧‧‧儲存裝置30‧‧‧Storage device

40、400、600、700、900‧‧‧使用者介面40, 400, 600, 700, 900‧‧‧ user interface

100‧‧‧電路設計模擬系統100‧‧‧Circuit Design Simulation System

S202-S220、S302-S314、S502-S506、S802-S810‧‧‧步驟S202-S220, S302-S314, S502-S506, S802-S810‧‧‧ steps

第1圖係顯示根據本發明一實施例所述之適用於一印刷電路板的電路設計模擬系統; 第2圖係顯示根據本發明一實施例所述之適用於一印刷電路板的電路設計方法;第3圖係顯示根據本發明一實施例所述之執行扇出分析的流程圖;第4圖係顯示根據本發明一實施例所述之使用者介面,用以設定積體電路的規格參數;第5圖係顯示根據本發明一實施例所述之執行密度分析的流程圖;第6圖係顯示根據本發明一實施例所述之使用者介面,用以設定印刷電路板的印刷電路板參數;第7圖係顯示根據本發明另一實施例所述之使用者介面,用以設定印刷電路板的印刷電路板參數;第8圖係顯示根據本發明一實施例所述之執行密度判別的流程圖;以及第9圖係顯示根據本發明一實施例所述之使用者介面,用以顯示執行第2圖之電路設計方法的密度資料。1 is a circuit design simulation system suitable for a printed circuit board according to an embodiment of the invention; 2 is a circuit design method suitable for a printed circuit board according to an embodiment of the invention; FIG. 3 is a flow chart showing a fan-out analysis according to an embodiment of the invention; FIG. The user interface according to an embodiment of the invention is used to set the specification parameters of the integrated circuit; and FIG. 5 is a flow chart showing the execution density analysis according to an embodiment of the invention; A user interface according to an embodiment of the invention is used to set printed circuit board parameters of a printed circuit board; and FIG. 7 is a diagram showing a user interface for setting a printed circuit according to another embodiment of the invention. Printed circuit board parameters of the board; FIG. 8 is a flow chart showing the execution density discrimination according to an embodiment of the present invention; and FIG. 9 is a view showing a user interface according to an embodiment of the present invention for displaying Perform the density data for the circuit design method in Figure 2.

10‧‧‧處理器10‧‧‧ processor

20‧‧‧顯示器20‧‧‧ display

30‧‧‧儲存裝置30‧‧‧Storage device

40‧‧‧使用者介面40‧‧‧User interface

100‧‧‧電路設計模擬系統100‧‧‧Circuit Design Simulation System

Claims (16)

一種電路設計方法,適用於一印刷電路板,包括:經由一使用者介面,得到欲設置在上述印刷電路板之一積體電路的複數規格參數;根據上述規格參數,得到上述積體電路於上述印刷電路板之一扇出腳位;根據上述扇出腳位以及上述規格參數,決定上述印刷電路板的一製程類型;根據上述製程類型,得到設置上述積體電路於上述印刷電路板所需的一印刷電路板層數以及一密度值;判斷上述密度值是否有效;當上述密度值為有效時,得到一密度結果;儲存上述密度結果、上述密度值以及上述規格參數至一密度模擬結果資料庫;以及顯示上述印刷電路板層數、上述密度值以及上述密度結果於上述使用者介面。 A circuit design method, applicable to a printed circuit board, comprising: obtaining a plurality of specification parameters of an integrated circuit to be disposed on one of the printed circuit boards via a user interface; and obtaining the integrated circuit according to the above specification parameters a fan-out board of the printed circuit board; determining a process type of the printed circuit board according to the fan-out pin position and the specification parameter; and obtaining, according to the process type, the required setting of the integrated circuit on the printed circuit board a printed circuit board layer number and a density value; determining whether the density value is valid; when the density value is valid, obtaining a density result; storing the density result, the density value, and the specification parameter to a density simulation result database And displaying the number of printed circuit board layers, the density value, and the density results described above in the user interface. 如申請專利範圍第1項所述之電路設計方法,其中上述得到上述扇出腳位之步驟,更包括:根據上述規格參數中接腳數量之資訊、晶片尺寸之資訊、接腳尺寸之資訊以及接腳至穿孔的間距之資訊,建立上述扇出腳位。 The circuit design method of claim 1, wherein the step of obtaining the fan-out position includes: information on the number of pins in the specification parameter, information on the size of the chip, information on the size of the pin, and The pin-to-pitch spacing information is used to establish the above-mentioned fan-out position. 如申請專利範圍第2項所述之電路設計方法,其中上述建立上述扇出腳位之步驟,更包括:判斷上述規格參數是否儲存在於上述密度模擬結果資料庫中; 當上述規格參數未儲存在於上述密度模擬結果資料庫時,判斷上述規格參數是否存在於一佈局零件資料庫中;當上述規格參數未儲存在於上述佈局零件資料庫時,經由上述使用者介面來設定上述規格參數;以及根據已設定之上述規格參數,建立上述扇出腳位。 The circuit design method of claim 2, wherein the step of establishing the fan-out position further comprises: determining whether the specification parameter is stored in the density simulation result database; When the specification parameter is not stored in the density simulation result database, it is determined whether the specification parameter exists in a layout part database; when the specification parameter is not stored in the layout part database, the user interface is used to set The above specification parameters; and the above fan-out pins are established according to the above-mentioned specification parameters that have been set. 如申請專利範圍第3項所述之電路設計方法,其中上述建立上述扇出腳位之步驟,更包括:當上述規格參數已儲存在於上述密度模擬結果資料庫時,從上述密度模擬結果資料庫得到上述密度值;以及當上述規格參數已儲存在於上述佈局零件資料庫時,從上述佈局零件資料庫得到上述扇出腳位。 The circuit design method of claim 3, wherein the step of establishing the fan-out position further comprises: when the specification parameter is stored in the density simulation result database, from the density simulation result database Obtaining the above density value; and obtaining the fan-out pin from the layout part database when the specification parameter is stored in the layout part database. 如申請專利範圍第2項所述之電路設計方法,其中上述決定上述製程類型之步驟,更包括:根據上述扇出腳位以及上述規格參數中接腳至接腳的間距之資訊以及扇出穿孔之資訊,判斷上述印刷電路板的上述製程類型是否為一高密度內連線製程。 The circuit design method of claim 2, wherein the step of determining the type of the process further comprises: according to the fan-out pin and the pin-to-pin pitch information and the fan-out hole in the specification parameter. The information determines whether the process type of the printed circuit board is a high-density interconnect process. 如申請專利範圍第2項所述之電路設計方法,其中上述得到上述印刷電路板層數以及上述密度值之步驟,更包括:經由上述使用者介面,得到對應於上述製程類型之一印刷電路板參數;根據上述印刷電路板參數,得到上述印刷電路板層數;以及根據上述印刷電路板層數,得到上述密度值;其中上述密度值係指示上述印刷電路板之銅箔使用空 間比值。 The circuit design method according to claim 2, wherein the step of obtaining the number of layers of the printed circuit board and the density value, further comprising: obtaining, by using the user interface, a printed circuit board corresponding to one of the process types a parameter; obtaining the number of layers of the printed circuit board according to the printed circuit board parameters; and obtaining the density value according to the number of the printed circuit board layers; wherein the density value indicates that the copper foil of the printed circuit board is empty Ratio between. 如申請專利範圍第6項所述之電路設計方法,其中上述印刷電路板參數包括佈線層數量之資訊、平面層數量之資訊以及走線寬度之資訊。 The circuit design method of claim 6, wherein the printed circuit board parameters include information on the number of wiring layers, information on the number of planar layers, and information on the width of the traces. 如申請專利範圍第6項所述之電路設計方法,其中上述判斷上述密度值是否有效之步驟,更包括:當上述密度值大於一第一參考值時,判斷上述密度值為無效;當上述密度值小於一第二參考值時,判斷上述密度值為有效;以及當上述密度值介於上述第一參考值與上述第二參考值之間時,調整上述印刷電路板參數或是上述規格參數,以便得到一新密度值;其中上述第一參考值大於上述第二參考值。 The circuit design method of claim 6, wherein the step of determining whether the density value is valid further comprises: determining that the density value is invalid when the density value is greater than a first reference value; When the value is less than a second reference value, determining that the density value is valid; and adjusting the printed circuit board parameter or the specification parameter when the density value is between the first reference value and the second reference value, In order to obtain a new density value; wherein the first reference value is greater than the second reference value. 如申請專利範圍第8項所述之電路設計方法,其中上述得到上述密度結果之步驟,更包括:根據上述印刷電路板層數、上述密度值以及複數個製造商之價格資訊,分別得到對應於每一上述製造商之製造成本;其中上述密度結果係指示上述製造成本中之一最低製造成本。 The circuit design method of claim 8, wherein the step of obtaining the density result comprises: corresponding to the number of layers of the printed circuit board, the density value, and the price information of the plurality of manufacturers, respectively The manufacturing cost of each of the above manufacturers; wherein the above density result indicates one of the above manufacturing costs, the lowest manufacturing cost. 一種電路設計模擬系統,適用於一印刷電路板,包括:一顯示器,用以顯示一使用者介面;以及一處理器,耦接於上述顯示器,用以經由上述使用者 介面而得到欲設置在上述印刷電路板之一積體電路的複數規格參數、根據上述規格參數而得到上述積體電路於上述印刷電路板之一扇出腳位,以決定上述印刷電路板的一製程類型,以及根據上述製程類型而得到設置上述積體電路於上述印刷電路板所需的一印刷電路板層數以及一密度值;其中當上述密度值為有效時,上述處理器根據上述密度值而得到一密度結果,並顯示上述印刷電路板層數、上述密度值以及上述密度結果於上述使用者介面。 A circuit design simulation system, which is applicable to a printed circuit board, comprising: a display for displaying a user interface; and a processor coupled to the display for using the user And obtaining a plurality of specifications of the integrated circuit to be provided on one of the printed circuit boards, and obtaining the integrated circuit on one of the printed circuit boards according to the specification parameter to determine one of the printed circuit boards. a process type, and a number of printed circuit board layers and a density value required for setting the integrated circuit on the printed circuit board according to the process type; wherein when the density value is valid, the processor is based on the density value A density result is obtained and the number of printed circuit board layers, the density values, and the density results are displayed on the user interface. 如申請專利範圍第10項所述之電路設計模擬系統,其中上述規格參數包括接腳數量之資訊、晶片尺寸之資訊、接腳尺寸之資訊、接腳至穿孔的間距之資訊、接腳至接腳的間距之資訊以及扇出穿孔之資訊。 For example, the circuit design simulation system described in claim 10, wherein the specification parameters include information on the number of pins, information on the size of the chip, information on the size of the pins, information on the pitch of the pins to the perforations, and pin-to-connection Information on the spacing of the feet and information on the fan-outs. 如申請專利範圍第11項所述之電路設計模擬系統,其中上述處理器係根據上述接腳至接腳的間距之資訊以及上述扇出穿孔之資訊,判斷上述印刷電路板的上述製程類型是否為一高密度內連線製程。 The circuit design simulation system of claim 11, wherein the processor determines whether the process type of the printed circuit board is based on the information of the distance between the pin and the pin and the information of the fan-out hole A high-density interconnect process. 如申請專利範圍第12項所述之電路設計模擬系統,其中上述處理器更經由上述使用者介面,而得到對應於上述製程類型之一印刷電路板參數,以及上述處理器係根據上述印刷電路板參數而得到上述印刷電路板層數以及上述密度值,其中上述密度值係指示上述印刷電路板之銅箔使用空間比值。 The circuit design simulation system of claim 12, wherein the processor further obtains a printed circuit board parameter corresponding to one of the process types via the user interface, and the processor is based on the printed circuit board. The number of layers of the printed circuit board and the density value are obtained by parameters, wherein the density value indicates a space ratio of copper foil used in the printed circuit board. 如申請專利範圍第13項所述之電路設計模擬系統,其中上述上印刷電路板參數包括佈線層數量之資訊、 平面層數量之資訊以及走線寬度之資訊。 The circuit design simulation system of claim 13, wherein the upper printed circuit board parameter includes information on the number of wiring layers, Information on the number of plane layers and information on the width of the traces. 如申請專利範圍第13項所述之電路設計模擬系統,其中當上述密度值大於一第一參考值時,上述處理器判斷上述密度值為無效、當上述密度值小於一第二參考值時,上述處理器判斷上述密度值為有效,以及當上述密度值介於上述第一參考值與上述第二參考值之間時,上述處理器經由上述使用者介面得到已調整之上述印刷電路板參數或是已調整之上述規格參數,以便得到一新密度值,其中上述第一參考值大於上述第二參考值。 The circuit design simulation system of claim 13, wherein when the density value is greater than a first reference value, the processor determines that the density value is invalid, and when the density value is less than a second reference value, The processor determines that the density value is valid, and when the density value is between the first reference value and the second reference value, the processor obtains the adjusted printed circuit board parameter via the user interface or It is the above-mentioned specification parameter that has been adjusted to obtain a new density value, wherein the first reference value is greater than the second reference value. 如申請專利範圍第15項所述之電路設計模擬系統,其中上述處理器根據上述印刷電路板層數、上述密度值以及複數個製造商之價格資訊,而分別得到對應於每一上述製造商之製造成本,以及上述密度結果係指示上述製造成本中之一最低製造成本。 The circuit design simulation system of claim 15, wherein the processor is respectively corresponding to each of the above manufacturers according to the number of the printed circuit board layers, the density value, and the price information of the plurality of manufacturers. The manufacturing cost, as well as the above density results, indicates one of the above manufacturing costs, the lowest manufacturing cost.
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