TWI469267B - Method for fabricating a sonos memory - Google Patents

Description

Method for making bismuth-oxide-nitride-oxide-germanium memory

The invention relates to a method for fabricating a SONOS memory, in particular to a method for maintaining the proportion of an ONO stack structure in a SONOS memory.

The non-volatile memory device is widely used because it has a characteristic that the stored data is not lost due to power supply interruption. Non-volatile memory devices widely used today include read-only-memory (ROM), programmable-read-only memory (PROM), erasable and programmable Erasable-programmable-read-only memory (EPROM) and electronically erasable-programmable-read-only memory (EEPROM). Among them, electronic erasable programmable read-only memory is different from other non-volatile memory in that they can use electronic to program and erase.

At present, the direction of product development in EEPROM devices is focused on increasing the speed of stylization, reducing the voltage during programming and reading, prolonging the time for data storage, reducing the erasing time of memory cells, and reducing the size of memory components. . In addition, some flash memory arrays today use a dual poly-Si gate formed by a stack of two-layer polysilicon, and in this gate structure, polysilicon is usually oxide- A dielectric material composed of an oxide-nitride-oxide (ONO) is used as a spacer, and when the device is operated, electrons are injected from the substrate into the underlying polysilicon to achieve the function of storing data. However, the memory array formed by the double-layer polysilicon gate is more difficult to increase the memory capacity because it can store only a single bit of data. Therefore, another derivative flash memory uses 矽-oxide-nitride-oxide-矽 (SONOS) as a data storage unit, and can be used as a transistor to store two bits at the same time. The function is to reduce the size of the component and increase the capacity of the memory. The operation of the SONOS device is exemplified as follows.

When the SONOS memory is programmed, the charge is transferred from a substrate to the tantalum nitride layer in the ONO structure. For example, the user first applies a voltage to the gate and the drain and establishes a vertical electric field and a lateral electric field, and then increases the speed of the electron along the channel by these electric fields. . As the electron moves along the channel, a portion of the electrons will gain sufficient energy to trap trapped in the tantalum nitride layer of the ONO structure across the potential barrier of the bottom ceria layer. Since the electric field near the bungee zone is the strongest, electrons are usually trapped in areas close to the bungee. Conversely, when the operator reverses the potential applied to the source and drain regions, the electrons travel in the opposite direction along the channel and are implanted into the tantalum nitride layer near the source region. Since a portion of the tantalum nitride layer is not electrically conductive, these charges introduced into the tantalum nitride layer tend to remain localized. Thus, depending on the applied voltage, the charge can be stored in different regions of the single tantalum nitride layer.

According to the conventional process of fabricating SONOS memory and MOS transistor, a patterned ONO stack structure is usually formed on the surface of the semiconductor substrate before the memory region, and then the gate oxide layer is directly covered on the uppermost layer of the ONO stack structure. On the surface of the yttrium oxide layer and on the semiconductor substrate of the transistor region. However, the stacking of the gate oxide layer and the oxide layer in the stacked structure tends to change the ratio between the layers in the entire ONO stack structure, thereby affecting the operation of the entire SONOS memory. Therefore, how to improve the current SONOS memory process to maintain the thickness ratio of the ONO structure in the memory cell is an important issue today.

Therefore, the present invention discloses a method for fabricating SONOS memory to solve the bottleneck encountered in the above conventional processes.

The present invention is directed to a method of making a strontium-oxide-nitride-oxide-germanium (SONOS) memory. First, a semiconductor substrate is provided, and then a first tantalum oxide layer, a tantalum nitride layer, and a second tantalum oxide layer are formed on the surface of the semiconductor substrate. A hard mask is then formed on the surface of the second tantalum oxide layer, and the hard mask, the first tantalum oxide layer, the tantalum nitride layer and the second tantalum oxide layer are patterned to form a patterned hard mask and a stacked structure. A gate oxide layer is then formed on the patterned hard mask surface, the gate oxide layer and the patterned hard mask are removed, and a patterned polysilicon layer is formed on the surface of the stacked structure. Finally, a source/drain region is formed in the semiconductor substrate on both sides of the polysilicon layer.

Another embodiment of the present invention discloses a method of fabricating a SONOS memory, comprising the steps of: providing a semiconductor substrate having a memory region and a transistor region; forming a first ruthenium oxide layer, a tantalum nitride layer and a second hafnium oxide layer on the surface of the semiconductor substrate of the memory region and the transistor region; forming a hard mask on the surface of the second hafnium oxide layer; patterning the hard mask, the first hafnium oxide layer, and the nitrogen layer The ruthenium layer and the second ruthenium oxide layer form a patterned hard mask and a stacked structure in the memory region; a gate oxide layer is formed on the surface of the patterned hard mask and the transistor region; and the gate of the memory region is removed a pole oxide layer; a patterned hard mask for removing the memory region; forming a patterned polysilicon layer on the stacked structure surface and the transistor region of the memory region; and forming a source/drain region in the memory The semiconductor substrate on both sides of the polysilicon layer of the region and the transistor region.

Please refer to FIG. 1 to FIG. 9 . FIG. 1 to FIG. 9 are schematic diagrams showing a SONOS memory according to a preferred embodiment of the present invention. As shown in FIG. 1, a semiconductor substrate 12 is first provided, such as a substrate composed of gallium arsenide, a silicon on insulator (SOI) layer, an epitaxial layer, a germanium layer, or other semiconductor substrate material. A memory region 14 and a transistor region 16 are defined on the semiconductor substrate 12, and then a first hafnium oxide layer 18, a tantalum nitride layer 20, a second hafnium oxide layer 22, and a hard mask 26 are sequentially formed. The entire surface of the semiconductor substrate 12. In the present embodiment, the hard mask 26 is preferably made of tantalum nitride and has a thickness of between about 100 angstroms and 200 angstroms, and preferably 150 angstroms.

As shown in FIG. 2, a patterned photoresist layer 28 is first formed on the hard mask 26 of the memory region 14, and then a dry etching process is performed using the patterned photoresist layer 28 as a mask to remove the memory region. a 14-part hard mask 26, a portion of the second hafnium oxide layer 22 and a portion of the tantalum nitride layer 20, and the hard mask 26, the second hafnium oxide layer 22 and the tantalum nitride layer 20 of the transistor region 16 are stopped at The surface of the first ruthenium oxide layer 18.

As shown in FIG. 3, a wet etching process is then performed using the patterned photoresist layer 28 as a mask to remove a portion of the first hafnium oxide layer 18 of the memory region 14 and the first hafnium oxide of the transistor region 16. Layer 18 forms an ONO stack structure 24 for memory region 14.

Next, as shown in FIG. 4, a cleaning process is performed using a sulfuric acid-hydrogen peroxide mixture (SPM) to remove the patterned photoresist layer 28. It should be noted that although part of the hard mask 26 is lost during the cleaning process, most of the hard mask 26 covers the surface of the second ruthenium oxide layer 22, so that only the memory remains on the entire surface of the semiconductor substrate 12. The region 14 has a stacked structure 24 of ONOs, and the top of this ONO stack structure 24 is still covered with a hard mask 26. In the present embodiment, the remaining hard mask 26 via the SPM cleaning step has a thickness of between about 60 angstroms and 80 angstroms.

Then, as shown in FIG. 5, an in-situ steam generation (ISSG) process is performed on the entire surface of the semiconductor substrate 12 to form a gate on the surface of the semiconductor substrate 12 and the hard mask 26 of the memory region 14. The oxide layer 30 simultaneously forms a gate oxide layer 32 on the surface of the semiconductor substrate 12 of the transistor region 16. In the present embodiment, the thickness of the gate oxide layer 30/32 is preferably about 30 angstroms.

In addition, it should be noted that since the on-site vapor growth process is an invasive oxide growth step, when the gate oxide layer 30 is formed on the surface of the hard mask 26, part of the hard mask 26 is simultaneously consumed and the hard cover is reduced. The thickness of the cover 26. In accordance with a preferred embodiment of the present invention, the remaining thickness of the hard mask 26 after the in-situ vapor growth process is between about 40 angstroms and 50 angstroms. However, even if a portion of the hard mask 26 is consumed during the formation of the gate oxide layer 30, the present invention maintains the first hafnium oxide layer 18 and nitride in the entire stacked structure 24 by the protection of the hard mask 26. The thickness ratio of the tantalum layer 20 to the second hafnium oxide layer 22.

A portion of the transistor region 16 is then covered with a patterned photoresist layer (not shown) and exposes the surface of the gate oxide layer 30 of the memory region 14. Then, as shown in FIG. 6, a portion of the gate oxide layer of the portion of the transistor region 16 and the gate oxide layer 30 of the memory region 14 are removed by a wet etching process. Next, as shown in FIG. 7, the hard mask 26 and the patterned photoresist layer disposed in the memory region 14 are removed by using a mixture of monosulfuric acid and hydrogen peroxide, thereby exposing the second oxidation of the uppermost layer in the stacked structure 24.矽 layer 22.

According to an embodiment of the invention, the transistor region 16 further includes an input/output (I/O) region and a core region, and the patterned photoresist layer is preferably formed in the I/O region. On the substrate 12. Therefore, when the gate oxide layer 30 of the memory region 14 is removed by the above wet etching process, it is preferable to simultaneously remove the gate oxide layer of the core region. Another on-site vapor growth process is then performed to form a thinner gate oxide layer in the core region. In other words, the surface of the semiconductor substrate 12 of the I/O region and the core region respectively forms gate oxide layers of two different thicknesses.

As shown in FIG. 8, a polysilicon layer (not shown) is first overlying the semiconductor substrate 12 of the memory region 14 and the transistor region 16, wherein the polysilicon layer disposed in the memory region 14 preferably covers the semiconductor substrate 12 and The surface of the structure 24 is stacked, and the polysilicon layer provided in the transistor region 16 preferably covers the surface of the gate oxide layer 32. Then, a pattern transfer process is performed. For example, a patterned photoresist layer (not shown) is used as a mask to perform an etching process to remove a portion of the polysilicon layer to form a stacked gate on the surface of the semiconductor substrate 12 of the memory region 14. 34 and a gate electrode 36 is formed in the transistor region 16. The stack gate 34 includes a control gate electrode composed of the patterned polysilicon layer 33 and an ONO stack structure composed of the second hafnium oxide layer 22, the tantalum nitride layer 20 and the first hafnium oxide layer 18. As previously described, the tantalum nitride layer 20 acts as a charge storage layer when programmed and erased.

Then, as shown in FIG. 9, an ion implantation process is performed, using the stacked gate 34 and the gate electrode 36 as a mask to form each of the semiconductor substrate 12 on both sides of the stacked gate 34 and the gate electrode 36. A source/drain region 38/40.

An inter-layer dielectric (ILD) 42 is then formed on the semiconductor substrate 12 of the memory region 14 and the transistor region 16 and covers the stack gate 34 and the gate electrode 36, and then another pattern transfer process is performed. For example, an etching process is performed using a patterned photoresist layer (not shown) as a mask to form a plurality of contact holes 44 in the interlayer dielectric layer 42. A metal layer made of tungsten (W) or the like is then overlying the interlayer dielectric layer 42 and fills the contact holes 44 to form a plurality of contact plugs 46 in the contact holes 44. Thus, a SONOS memory cell of a preferred embodiment of the present invention is completed, which preferably comprises a SONOS transistor and a MOS transistor. It should be noted that although the above process is exemplified by integrating the SONOS transistor and the MOS transistor, the present invention is not limited thereto, and the invention can only implement the process of the memory region 14 according to the process requirements and only produce the SONOS transistor. Designs are also within the scope of the invention.

In addition, according to an embodiment of the invention, the SONOS transistor disclosed in the above process can be applied to a non-volatile memory, such as a non-volatile product having the advantages of both a volatile memory component and a non-volatile memory component. Non-volatile static random access memory (NVSRAM) component. The NVSRAM device preferably includes a memory cell array, a plurality of bit lines, and a plurality of word lines. The memory cell array includes a plurality of rows of NVSRAM cells in a vertical direction and a plurality of columns of NVSRAM cells in a horizontal direction. The bit lines are arranged parallel to the direction of the plurality of rows of NVSRAM cells in the memory cell array, and the plurality of word lines are arranged parallel to the direction of the plurality of columns of NVSRAM cells in the memory cell array. In the memory cell array, each NVSRAM cell has the same structure, each column of NVSRAM cells shares a corresponding set of bit lines BT and BC, and each row of NVSRAM shares a corresponding word line WL.

Please refer to FIG. 10. FIG. 10 is a schematic diagram showing an equivalent circuit of applying the SONOS transistor completed in the above process to an NVSRAM device according to the present invention. As shown in the figure, an NVSRAM cell 52 in the memory cell array includes a volatile circuit 54 and two sets of three transistor SONOS cells 56. The 3T-SONOS units 56 each include a SONOS transistor 58 and two MOS transistors disclosed in the above embodiments. The volatility circuit 54 is a six-cell (6T) architecture, and each transistor is of a MOS transistor type.

In the case of continuous power supply, the NVSRAM unit 52 can store its memory data through the volatile circuit 54, and in the case of power failure, the NVSRAM unit 52 can store the signal or data back to the 3T-SONOS unit 56, etc. When the power is supplied, the data is read out, and the volatile function is converted into a non-volatile function to achieve the memory effect.

In summary, the present invention preferably forms a thick hard mask on the surface of the ONO stacked structure after forming the ONO stack structure in the memory region, and then uses the patterned photoresist layer to pattern the ONO stack structure. Due to the thick thickness of the hard mask, a portion of the hard mask remains on the patterned ONO stack when the patterned photoresist layer is removed. Next, when performing the vapor growth process of the gate oxide layer, the gate oxide layer may be directly disposed on the surface of the remaining hard mask, and then the gate oxide layer patterning step of the transistor region is sequentially removed to remove the memory region. The gate oxide layer and the hard mask. Since the ONO stack structure of the memory region is covered by the hard mask during the entire manufacturing process, the present invention can maintain the thickness ratio of each layer in the ONO stack structure without adding an additional process, and can also be used in electricity. After the crystal region forms the desired patterned gate oxide layer, the ONO stack structure of the memory region is appropriately exposed to deposit the subsequent polysilicon layer, thereby producing a stable SONOS memory cell.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

12. . . Semiconductor substrate

14. . . Memory area

16. . . Transistor region

18. . . First ruthenium oxide layer

20. . . Tantalum nitride layer

twenty two. . . Second ruthenium oxide layer

twenty four. . . Stack structure

26. . . Hard mask

28. . . Patterned photoresist layer

30. . . Gate oxide layer

32. . . Gate oxide layer

33. . . Polycrystalline layer

34. . . Stack gate

36. . . Gate electrode

38. . . Source/drain region

40. . . Source/drain region

42. . . Interlayer dielectric layer

44. . . Contact hole

46. . . Contact plug

52. . . NVSRAM unit

54. . . Volatile circuit

56. . . 3T-SONOS unit

58. . . SONOS transistor

1 to 9 are schematic views showing a SONOS memory according to a preferred embodiment of the present invention.

Figure 10 is a schematic diagram of an equivalent circuit for applying a SONOS transistor to an NVSRAM device of the present invention.

12. . . Semiconductor substrate

14. . . Memory area

16. . . Transistor region

18. . . First ruthenium oxide layer

20. . . Tantalum nitride layer

twenty two. . . Second ruthenium oxide layer

32. . . Gate oxide layer

33. . . Polycrystalline layer

36. . . Gate electrode

38. . . Source/drain region

40. . . Source/drain region

42. . . Interlayer dielectric layer

44. . . Contact hole

46. . . Contact plug

Claims (19)

A method of fabricating a germanium-oxide-nitride-oxide-germanium (SONOS) memory, comprising the steps of: providing a semiconductor substrate; forming a first tantalum oxide layer, a tantalum nitride layer, and a second oxide Laminating a layer on the surface of the semiconductor substrate; forming a hard mask on the surface of the second ruthenium oxide layer; patterning the hard mask, the first ruthenium oxide layer, the tantalum nitride layer and the second ruthenium oxide layer to form a patterned hard mask and a stacked structure; forming a gate oxide layer on the surface of the patterned hard mask; removing the patterned oxide mask after completely removing the gate oxide layer; forming a patterned polysilicon layer And a source/drain region is formed in the semiconductor substrate on both sides of the polysilicon layer. The method of claim 1, wherein the step of patterning the hard mask, the first hafnium oxide layer, the tantalum nitride layer, and the second hafnium oxide layer further comprises: forming a patterned photoresist Laminating the hard mask surface; using the patterned photoresist layer to remove a portion of the hard mask, a portion of the second hafnium oxide layer and a portion of the tantalum nitride layer; removing a portion of the first hafnium oxide layer; The patterned photoresist layer is removed. The method of claim 2, further comprising removing a portion of the hard mask, a portion of the second hafnium oxide layer and a portion of the tantalum nitride layer by a dry etching process. The method of claim 2, further comprising removing a portion of the first ruthenium oxide layer by a wet etching process. The method of claim 2, further comprising removing the patterned photoresist layer using a sulfuric acid-hydrogen peroxide mixture (SPM). The method of claim 1, wherein the hard mask comprises tantalum nitride. The method of claim 1, further comprising forming the gate oxide layer using an in-situ steam generation (ISSG) process. The method of claim 1, further comprising removing the gate oxide layer by a wet etching process. The method of claim 1, further comprising removing the hard mask with a mixture of monosulfuric acid and hydrogen peroxide. A method of fabricating a SONOS memory, comprising the steps of: providing a semiconductor substrate having a memory region and a transistor region; forming a first hafnium oxide layer, a tantalum nitride layer, and a second a ruthenium oxide layer on the surface of the semiconductor substrate and the surface of the semiconductor substrate; forming a hard mask on the surface of the second ruthenium oxide layer; patterning the hard mask, the first ruthenium oxide layer, and nitriding The ruthenium layer and the second ruthenium oxide layer form a patterned hard mask and a stacked structure in the memory region; forming a gate oxide layer on the semiconductor substrate of the transistor region; completely removing the memory region After the gate oxide layer, the patterned hard mask of the memory region is removed; a patterned polysilicon layer is formed on the surface of the stacked structure of the memory region and the transistor region; and each source is formed. The / drain region is in the memory region and the semiconductor substrate on both sides of the polysilicon layer of the transistor region. The method of claim 10, wherein the step of patterning the hard mask, the first tantalum oxide layer, the tantalum nitride layer, and the second tantalum oxide layer further comprises: Forming a patterned photoresist layer on the hard mask surface of the memory region; removing the portion of the memory region by the patterned photoresist layer, the portion of the second ruthenium oxide layer and a portion of the nitridation layer a layer of germanium, and the hard mask, the second layer of tantalum oxide and the layer of tantalum nitride removed from the transistor region; removing a portion of the first germanium oxide layer and the first region of the transistor region a ruthenium oxide layer; and removing the patterned photoresist layer. The method of claim 11, further comprising removing a portion of the hard mask, a portion of the second hafnium oxide layer, and a portion of the tantalum nitride layer by a dry etching process. The method of claim 11, further comprising removing a portion of the first hafnium oxide layer by a wet etching process. The method of claim 11, further comprising removing the patterned photoresist layer using a sulfuric acid-hydrogen peroxide mixture (SPM). The method of claim 10, wherein the hard mask comprises tantalum nitride. For example, the method described in claim 10 of the patent application, including the use of a present A field vapor growth process is used to form the gate oxide layer. The method of claim 10, further comprising removing the gate oxide layer by a wet etching process. The method of claim 10, further comprising removing the hard mask with a mixture of monosulfuric acid and hydrogen peroxide. The method of claim 10, wherein the removing the patterned hard mask of the memory region further comprises: forming the gate oxide layer on the patterned hard mask surface and the semiconductor region of the transistor region On the substrate; and removing the gate oxide layer of the memory region.