TWI606578B - Non-volatile memory array and method of fabricating the same - Google Patents

Description

Non-volatile memory array and method of manufacturing same

This invention relates to a memory related technique, and more particularly to a non-volatile memory array and method of fabricating the same.

A memory is a semiconductor component used to store data or data. As the functions of computer microprocessors become stronger and stronger, the programs and operations performed by software become larger and larger, and the demand for memory becomes higher and higher. Among various memory components, non-volatile memory has the advantage that the stored data does not disappear after power-off, so many electrical products must have such memory to maintain the normal operation of the electrical product when it is turned on.

In general, a non-volatile memory cell has a floating gate and a control gate made of doped polysilicon. When the memory is programmed, the electrons injected into the floating gate are evenly distributed throughout the polysilicon floating gate. In addition, there are also non-volatile memories that use a charge trapping layer instead of a polysilicon floating gate. When the device is programmed, electrons are only stored in the charge trapping layer near the top of the source or drain.

When operating on a memory cell, the power supply energy provided by the bit line will affect the memory cells that are connected to the same bit line but are not selected, and are called bit line interference. The above bit line interference will directly affect the storage capacity of the data of the memory unit, resulting in data loss.

The present invention provides a non-volatile memory array that avoids the effects of bit line interference on non-volatile memory.

The present invention further provides a method of fabricating a non-volatile memory array capable of fabricating a non-volatile memory array without bit line interference.

The non-volatile memory array of the present invention includes a substrate, a bit line, an isolation structure, a patterned stacked structure, an oxide layer, and a word line. The bit line is located in the substrate, wherein the adjacent two bit lines are composed of the first area and the second area. The isolation structure is on the bit line. The patterned stacked structure is on a substrate of the first region, wherein the patterned stacked structure includes at least a charge trapping layer and a tunneling dielectric layer. The oxide layer is then located on the substrate of the second region and the patterned stack. The word line is located on the oxide layer and spans the isolation structure on the bit line.

According to an embodiment of the invention, the isolation structure comprises a shallow trench isolation structure or a field oxide layer structure.

According to an embodiment of the invention, the material of the isolation structure comprises an oxide.

According to an embodiment of the invention, the material of the tunneling dielectric layer comprises an oxide.

According to an embodiment of the invention, the material of the charge trap layer comprises a nitride.

According to an embodiment of the invention, the material of the word line comprises polysilicon.

A method of fabricating a non-volatile memory array of the present invention includes forming a patterned stacked structure on a substrate to expose a portion of the substrate, wherein the patterned stacked structure comprises a charge trapping layer and a tunneling dielectric layer. The patterned stacked structure is used as a mask to form a plurality of bit lines in the exposed substrate, wherein the adjacent two bit lines are composed of the first area and the second area. The patterned stack structure in the second zone is removed to expose the substrate of the second zone. An oxide layer is formed on the substrate and the patterned stacked structure, and a plurality of word lines extending across the bit line are formed on the oxide layer.

According to another embodiment of the present invention, the method steps of forming the above-described patterned stacked structure are as follows. A tunneling dielectric layer is formed on the substrate. A charge trapping layer is formed on the tunneling dielectric layer. The charge trapping layer and the tunneling dielectric layer are patterned.

According to another embodiment of the present invention, the method of forming the above oxide layer includes a thermal oxidation method.

According to another embodiment of the present invention, the formation of the oxide layer includes forming an isolation structure on each of the bit lines.

According to another embodiment of the present invention, before the patterned stacked structure located in the second region is removed, an isolation structure may be formed on each of the bit lines.

Based on the above, the present invention retains a charge storage structure in the first region by forming only an oxide layer in the second region between adjacent two bit lines. Therefore, with the miniaturization of the memory, the bit lines in the non-volatile memory do not affect the unselected memory cells and cause bit line interference when the operation is performed.

The above described features and advantages of the invention will be apparent from the following description.

1A to 1E are schematic cross-sectional views showing a manufacturing process of a nonvolatile memory array in accordance with a first embodiment of the present invention.

Referring to FIG. 1A, a patterned stacked structure 106 is formed on the substrate 100 to expose a portion of the substrate 100. The patterned stacked structure 106 includes at least a tunneling dielectric layer 102 and a charge trapping layer 104. In the present embodiment, the patterned stacked structure 106 is formed by the tunneling dielectric layer 102 and the charge trapping layer 104, and the tunneling dielectric layer 102 is located between the charge trapping layer 104 and the substrate 100. The patterned stacked structure 106 is formed by sequentially forming a tunneling dielectric layer 102 and a charge trapping layer 104 on the substrate 100, and then patterning the charge trapping layer 104 and the tunneling dielectric layer 102 to form a patterned stacked structure 106. . As for the substrate 100, it may be a semiconductor substrate having a conductivity type, such as an N-type or P-type substrate. The material that tunnels through the dielectric layer 102 is, for example, an oxide. The material of the charge trap layer 104 is, for example, a nitride.

Next, referring to FIG. 1A, the patterned stacked structure 106 is used as a mask, and a plurality of bit lines 108 are formed in the exposed substrate 100, wherein the adjacent two bit lines 108 are separated by a first area R1 and a first The second district is composed of R2. The formation of the bit line 108 is, for example, by implanting an N-type or P-type dopant into the substrate 100 by ion implantation, wherein the bit line 108 has an opposite electrical property to the substrate 100. For example, when the substrate 100 is a P-type substrate, the bit line 108 implants the N-type dopant into the substrate 100 by ion implantation; and vice versa.

Then, referring to FIG. 1B, an isolation structure 110 is formed on each of the bit lines 108. The material of the isolation structure 110 is, for example, an oxide. In the present embodiment, the isolation structure 110 is, for example, a field oxide layer structure formed by local oxidation (LOCOS), but the invention is not limited thereto; for example, the isolation structure 110 may also be a shallow trench isolation structure ( STI). Further, the method of forming the isolation structure 110 is, for example, a thermal oxidation method, a chemical vapor deposition method, or a combination thereof, but this is merely an example and not a limitation of the present invention.

Next, referring to FIG. 1C, a patterned photoresist layer 112 is formed on the patterned stacked structure 106 and the isolation structure 110, wherein the patterned photoresist layer 112 exposes the patterned stacked structure on the substrate 100 in the second region R2. 106. The patterned photoresist layer 112 is formed by, for example, spin coating on the entire substrate 100 and then formed by a lithography process, but this is merely an example and not a limitation of the present invention.

Thereafter, referring to FIG. 1D, the patterned photoresist layer 112 of FIG. 1C is an etching mask, and the patterned stacked structure 106 located in the second region R2 is removed to expose the substrate 100 of the second region R2. Next, after the patterned photoresist layer 112 is removed, an oxide layer 114 is formed on the substrate 100, wherein the oxide layer 114 covers the substrate 100 of the second region R2, the charge trap layer 104a, and the isolation structure 110. The charge storage structure 116 composed of the tunneling dielectric layer 102a, the charge trapping layer 104a and the oxide layer 114 on the first region R1 substrate 100 is not formed on the substrate 100 of the second region R2, but in the adjacent two The bit lines 108 exhibit an asymmetrical structure between them. Therefore, bit line interference is not caused when the operation is performed. For example, when a programming voltage is applied to one of the bit lines 108, the first region R1 on one side of the single strip line 108 has a charge storage structure 116, and the second region R2 on the other side has no charge. Since the structure 116 is stored, the unselected second region R2 is not affected, so that bit line interference can be avoided, thereby improving the reliability of the memory device. Further, the method of forming the above oxide layer 114 is, for example, a thermal oxidation method, a chemical vapor deposition method, or a combination thereof. The material of the oxide layer 114 is, for example, cerium oxide.

Finally, referring to FIG. 1E, a word line 118 spanning the bit line 108 is formed over the oxide layer 114. The material of the word line 118 is, for example, polysilicon. In the present embodiment, the formation method of the word line 118 is first formed by a chemical vapor deposition method, a physical vapor deposition method, or the like, and the conductive layer is patterned by photolithography to obtain a word line. The non-volatile memory array fabricated in accordance with the first embodiment of the present invention has been shown in FIG. 1E, and since FIG. 1E is a cross-sectional view, it should be understood by those of ordinary skill in the art that there is more than one word line 118. And the extending direction of each word line 118 is different from the extending direction of the bit line 108.

2A through 2D are schematic cross-sectional views showing a manufacturing process of a non-volatile memory array in accordance with a second embodiment of the present invention.

Referring to FIG. 2A, a patterned stacked structure 206 including a tunneling dielectric layer 202 and a charge trapping layer 204 is formed on the substrate 200, and a portion of the substrate is exposed. In the present embodiment, the patterned stacked structure 206 is composed of the tunneling dielectric layer 202 and the charge trapping layer 204 , and the tunneling dielectric layer 202 is located between the charge trapping layer 204 and the substrate 200 . Next, with the patterned stacked structure 206 as a mask, a plurality of bit lines 208 are formed in the exposed substrate 200, wherein the adjacent two bit lines 208 are composed of a first region R1 and a second region R2. The patterned stacked structure 206 and the bit line 208 of the present embodiment are the same as the patterned stacked structure 106 and the bit line 108 of the first embodiment of the present invention, and thus the detailed description thereof will not be repeated here.

Next, referring to FIG. 2A , a patterned photoresist layer 210 is formed on the patterned stacked structure 206 and the substrate 200 , wherein the patterned photoresist layer 210 exposes the patterned stacked structure 206 located in the second region R2 . The patterned photoresist layer 210 is formed by, for example, spin coating a photoresist layer on the patterned stacked structure 206 and the substrate 200 and performing a lithography process thereon.

Then, referring to FIG. 2B, the patterned stacked structure (206) located in the second region R2 not covered by the patterned photoresist layer 210 is removed to expose the substrate 200 of the second region R2 and tunnel the dielectric layer 202a and the charge trapping layer 204a are only located in the first region R1, and the patterned photoresist layer 210 of FIG. 2A is removed.

Next, referring to FIG. 2C, an oxide layer 212a is formed on the substrate 200 of the second region R2, and an isolation structure 212b on the bit line 208 is simultaneously formed, wherein the oxide layer 212a also covers the patterned stacked structure 206a of the first region R1. . In the present embodiment, since the formation method of the oxide layer 212a is a thermal oxidation method, the oxide growth rate on the bit line 208 having a high doping concentration is high, so that a thick thickness can be obtained and can be regarded as the isolation structure 212b. Oxide layer. Therefore, the step of additionally forming an isolation structure on the bit line 208 can be omitted, so that the manufacturing cost and time can be reduced. At this time, the charge storage structure 214 composed of the tunneling dielectric layer 202a, the charge trapping layer 204a and the oxide layer 212a is formed only in the first region R1 and not in the second region R2, but in the adjacent two An asymmetrical structure is present between the bit lines 208. Therefore, the bit line 208 does not cause bit line interference when the operation is performed, thereby improving the reliability of the memory array.

Thereafter, referring to FIG. 2D, a word line 216 spanning the bit line 208 is formed over the oxide layer 212a and the isolation structure 212b. Since the word line 216 of the present embodiment and its process are as described in the first embodiment, the description thereof will not be repeated.

3 is an equivalent circuit diagram of the non-volatile memory cells of the first and second embodiments, wherein WL represents a word line and BL represents a bit line. Therefore, when the memory cell is operating, the same bit line BL only turns on (reads) the charge storage structure of one side (such as the first region) does not affect the memory of the other side (such as the second region). The unit, so it does not cause bit line interference, which can improve the reliability of the memory array.

In summary, according to the non-volatile memory array of the present invention, since the charge storage structure is formed only in the first region between the bit lines, it is not formed in the second region between the bit lines; that is, An asymmetric charge storage structure is present between adjacent two bit lines. Therefore, the memory does not interfere with each other during operation, causing bit line interference, thereby improving the reliability of the memory device.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100, 200‧‧‧ base

102, 102a, 202, 202a‧‧‧ tunneling dielectric layer

104, 104a, 204, 204a‧‧‧ charge trapping layer

106, 206‧‧‧ patterned stacking structure

108, 208‧‧‧ bit line

110, 212b‧‧‧Isolation structure

112, 210‧‧‧ patterned photoresist layer

114, 212a‧‧‧ oxide layer

116, 214‧‧‧ charge storage structure

118, 216‧‧‧ character line

R1‧‧‧ first district

R2‧‧‧Second District

1A to 1E are schematic cross-sectional views showing a manufacturing process of a nonvolatile memory array in accordance with a first embodiment of the present invention. 2A through 2D are schematic cross-sectional views showing a manufacturing process of a non-volatile memory array in accordance with a second embodiment of the present invention. Fig. 3 is an equivalent circuit diagram of the non-volatile memory of the first and second embodiments.

100‧‧‧Base

102a‧‧‧Tunnel dielectric layer

104a‧‧‧Charge trapping layer

108‧‧‧ bit line

110‧‧‧Isolation structure

114‧‧‧Oxide layer

116‧‧‧Charge storage structure

118‧‧‧ character line

R1‧‧‧ first district

R2‧‧‧Second District

Claims (11)

A non-volatile memory array comprising: a substrate; a plurality of bit lines located in the substrate, wherein two adjacent ones of the bit lines are composed of a first region and a second region; a structure on the plurality of bit lines; a patterned stacked structure on the substrate of the first region, wherein the patterned stacked structure comprises at least a charge trapping layer and a tunneling dielectric layer; an oxide layer, Located on the substrate of the second region and the patterned stack structure; and a plurality of word lines on the oxide layer and across the plurality of isolation structures on the plurality of bit lines, An asymmetric structure is present between two adjacent bit lines. The non-volatile memory array of claim 1, wherein the plurality of isolation structures comprise a shallow trench isolation structure or a field oxide layer structure. The non-volatile memory array of claim 1, wherein the material of the plurality of isolation structures comprises an oxide. The non-volatile memory array of claim 1, wherein the material of the tunneling dielectric layer comprises an oxide. The non-volatile memory array of claim 1, wherein the material of the charge trapping layer comprises a nitride. The non-volatile memory array of claim 1, wherein the material of the plurality of word lines comprises polysilicon. A method of fabricating a non-volatile memory array, comprising: forming a patterned stacked structure on a substrate to expose a portion of the substrate, wherein the patterned stacked structure comprises a charge trapping layer and a tunneling dielectric layer; The stacked structure is a mask, and a plurality of bit lines are formed in the exposed substrate, wherein two adjacent ones of the bit lines are composed of a first area and a second area; The patterned stacked structure of the second region to expose the substrate of the second region; forming an oxide layer on the substrate and the patterned stacked structure; and forming across the oxide layer A plurality of word lines of the plurality of bit lines, wherein the adjacent two of the bit lines exhibit an asymmetrical structure. The method of fabricating a non-volatile memory array according to claim 7, wherein the method of forming the patterned stacked structure comprises: forming a tunneling dielectric layer on the substrate; Forming a charge trapping layer on the electrical layer; and patterning the charge trapping layer and the tunneling dielectric layer. The method of manufacturing a non-volatile memory array according to claim 7, wherein the method of forming the oxide layer comprises a thermal oxidation method. The method of manufacturing a non-volatile memory array according to claim 7, wherein the forming of the oxide layer includes forming an isolation structure on each of the plurality of bit lines. The method of manufacturing a non-volatile memory array according to claim 7, wherein the plurality of bit lines are further included before the patterning stack structure located in the second region is removed. An isolation structure is formed on each of the strips.