CN112310114A - Non-volatile memory device including ferroelectric layer having negative capacitance - Google Patents

Non-volatile memory device including ferroelectric layer having negative capacitance Download PDF

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CN112310114A
CN112310114A CN202010271847.9A CN202010271847A CN112310114A CN 112310114 A CN112310114 A CN 112310114A CN 202010271847 A CN202010271847 A CN 202010271847A CN 112310114 A CN112310114 A CN 112310114A
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layer
memory device
volatile memory
gate dielectric
ferroelectric
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李在吉
刘香根
李世昊
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SK Hynix Inc
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

A non-volatile memory device includes a ferroelectric layer having a negative capacitance. A nonvolatile memory device according to an aspect of the present disclosure includes: a substrate having a channel layer; a gate dielectric layer structure disposed on the channel layer; a ferroelectric layer disposed on the gate dielectric layer structure; and a gate electrode layer provided on the ferroelectric layer. The gate dielectric layer structure has a positive capacitance. The ferroelectric layer has a negative capacitance. The gate dielectric structure includes a charge tunneling layer, a charge trapping layer, and a charge barrier layer disposed on the channel layer.

Description

Non-volatile memory device including ferroelectric layer having negative capacitance
Technical Field
The present disclosure relates generally to a nonvolatile memory device, and more particularly, to a nonvolatile memory device including a ferroelectric layer having a negative capacitance and a method of manufacturing the same.
Background
As the integration density of semiconductor devices increases, proper dissipation of generated heat becomes more important. Researchers have been working on finding ingenious ways to reduce heat generation by lowering the operating voltage and power consumption of semiconductors. Furthermore, even for memory devices, the size of memory cells and peripheral circuits is continually being reduced to accommodate overall design rules. Therefore, it is necessary to reduce the operating voltage applied to the memory device during operation of the memory device so that various circuits of the memory device can withstand the applied operating voltage and properly dissipate the generated heat.
Meanwhile, examples of memory devices widely used in recent years include a transistor-type (transistor-type) nonvolatile memory device employing a three-layer stacked structure of a charge tunneling layer, a charge trapping layer, and a charge barrier layer as a gate dielectric layer structure. The nonvolatile memory device may perform an operation of introducing charges from the substrate into the charge trapping layer (a programming operation) or an operation of erasing charges of the charge trapping layer (an erasing operation). The charge trapping layer performs a memory function by non-volatile storage of the introduced charge. The nonvolatile memory device can be implemented as a three-dimensional "NAND" type structure in which a plurality of cell transistors are connected to each other and have a string shape.
Disclosure of Invention
Embodiments of the present disclosure provide a nonvolatile memory device capable of reducing an operating voltage externally applied to a gate electrode layer.
A nonvolatile memory device according to an aspect of the present disclosure includes: a substrate having a channel layer; a gate dielectric layer structure disposed on the channel layer; a ferroelectric layer disposed on the gate dielectric layer structure; and a gate electrode layer provided on the ferroelectric layer. The gate dielectric layer structure has a positive capacitance. The ferroelectric layer has a negative capacitance. The gate dielectric structure includes a charge tunneling layer, a charge trapping layer, and a charge barrier layer disposed on the channel layer.
A nonvolatile memory device according to another aspect of the present disclosure includes: a substrate; an electrode laminated structure provided on a substrate; a trench penetrating the electrode stack structure and exposing sidewall surfaces of the gate electrode layer and the interlayer insulating layer; a ferroelectric layer provided so as to cover the interlayer insulating layer and the gate electrode layer along an inner wall surface of the trench; a gate dielectric layer structure disposed on the ferroelectric layer; and a channel layer disposed on the gate dielectric layer structure. The gate dielectric layer structure has a positive capacitance. The ferroelectric layer has a negative capacitance. The electrode stack structure includes at least one gate electrode layer and at least one interlayer insulating layer alternately stacked in a direction perpendicular to the substrate. The gate dielectric structure includes a charge tunneling layer, a charge trapping layer, and a charge barrier layer disposed on the channel layer.
Drawings
Fig. 1 is a cross-sectional view schematically illustrating a nonvolatile memory device according to an embodiment of the present disclosure.
Fig. 2 is a graph showing polarization versus voltage for a gate dielectric layer structure having a positive capacitance.
Fig. 3 is a graph showing polarization versus voltage for a gate dielectric layer structure having a negative capacitance.
Fig. 4 is a circuit diagram in which a gate dielectric layer structure and a ferroelectric layer are connected in series as a capacitor in a nonvolatile memory device according to an embodiment of the present disclosure.
Fig. 5 is a circuit diagram schematically illustrating a nonvolatile memory device according to an embodiment of the present disclosure.
Fig. 6A is a cross-sectional view schematically illustrating a nonvolatile memory device according to one embodiment of the present disclosure, fig. 6B is an enlarged view of a region "a" shown in fig. 6A, and fig. 6C is an enlarged view of a region "B" shown in fig. 6A.
Detailed Description
Various embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the size of layers and regions may be exaggerated for clarity of illustration. In general, the figures are described from the viewpoint of an observer. If an element is referred to as being "on" or "under" another element, it can be directly on or under the other element or an additional element may be interposed between the element and the other element. In the drawings, like numerals refer to substantially identical elements throughout the several views.
Furthermore, expressions which are singular of words should be understood to include plural forms of words unless explicitly used otherwise. It will be understood that the terms "comprises" or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, or groups thereof.
Fig. 1 is a cross-sectional view schematically showing a nonvolatile memory device 1 according to an embodiment of the present disclosure. Fig. 2 is a graph showing polarization versus voltage for a gate dielectric layer structure having a positive capacitance. Fig. 3 is a graph showing polarization versus voltage for a gate dielectric layer structure having a negative capacitance. Fig. 4 is a circuit diagram in which a gate dielectric layer structure and a ferroelectric layer are connected in series as a capacitor in the nonvolatile memory device 1 according to one embodiment of the present disclosure.
Referring to fig. 1, a nonvolatile memory device 1 may include a substrate 101, a gate dielectric layer structure 110, a ferroelectric layer 120, and a gate electrode layer 130. The gate dielectric structure 110 may include a charge tunneling layer 112, a charge trapping layer 114, and a charge barrier layer 116. In addition, the substrate 101 may include a channel layer 102 under the gate dielectric layer structure 110, and a source region 105 and a drain region 106 in regions of the substrate 101 at opposite ends of the channel layer 102. In the embodiment shown in fig. 1, the channel layer 102 may be located directly below the charge tunneling layer of the gate dielectric layer structure 110. Furthermore, the charge trapping layer 114 may be located directly on the charge tunneling layer 112, and the charge barrier layer 116 may be located directly on the charge trapping layer 114. In addition, the ferroelectric layer may be directly on the charge barrier layer 116, and the gate electrode 130 may be directly on the ferroelectric layer 120. In one embodiment, the non-volatile memory device 1 may be a flash memory device in the form of a field effect transistor.
The substrate 101 may, for example, comprise any suitable semiconductor material. The substrate 101 may be, for example, a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate. In one embodiment, the substrate 101 may be doped with a dopant to enhance its conductivity. For example, the dopant may be an n-type dopant or a p-type dopant.
In one embodiment, the substrate 101 may include a well region doped with n-type dopants or p-type dopants in the substrate 101. Source region 105 and drain region 106 may be regions of substrate 101 that are doped with a dopant of the opposite type to that used in the well region. For example, if the substrate 101 is doped with n-type dopants, the source and drain regions 105 and 106 may be regions doped with p-type dopants, and if the substrate 101 is doped with p-type dopants, the source and drain regions 105 and 106 may be regions doped with n-type dopants. In other words, the source region 105 and the drain region 106 may be regions doped with a dopant of a type opposite to that of the substrate 101. Channel layer 102 may be a region in which carriers having charges conduct when a voltage is applied between source region 105 and drain region 106. For example, the channel region 102 may refer to a region of the substrate 101 having high electron or hole mobility between the source region 105 and the drain region 106.
A gate dielectric layer structure 110 may be disposed on the channel layer 102. More specifically, gate dielectric layer structure 110 may be disposed directly on channel layer 102. In addition, the gate dielectric layer structure 110 may include a charge tunneling layer 112, a charge trapping layer 114, and a charge barrier layer 116 disposed on top of each other in that order over the channel layer 102. In one embodiment, the gate dielectric layer structure 110 may have a positive capacitance. Positive capacitance refers to the following: when a voltage V is applied to both ends of the dielectric layer, the polarization P generated inside the dielectric layer has a positive slope with respect to the applied voltage V, as shown in fig. 2. Further, the paramagnetic layer (paralecric layer) means a material layer having the following characteristics: wherein, when the applied voltage V is removed from the dielectric layer among the dielectric layers having the positive capacitance (i.e., the applied voltage is 0V), the polarization P in the dielectric layer disappears. Fig. 2 is an example of the paraelectric polarization characteristic.
In one embodiment, the charge tunneling layer 112, the charge trapping layer 114, and the charge barrier layer 116 may all be a paramagnetic layer. For example, the charge tunneling layer 112 may include silicon oxide. The charge trapping layer 114 may comprise silicon nitride. The charge barrier layer 116 may include silicon oxide.
When a predetermined programming voltage is applied between the substrate 101 and the gate dielectric layer structure 110, electrons of the channel layer 102 may tunnel through the charge tunneling layer 112 and move to the charge trapping layer 114, and may then be trapped in the charge trapping layer 114. In this case, the charge barrier layer 116 may function as an energy barrier layer that suppresses electrons trapped in the charge-trapping layer 114 from moving to the ferroelectric layer 120 and the gate electrode layer 130. When a predetermined erase voltage is applied between the substrate 101 and the gate dielectric layer structure 110, holes from the channel layer 102 may tunnel through the charge tunneling layer 112 and move to the charge trapping layer 114. Electrons can be erased by recombination of the moving holes with electrons trapped in the charge trapping layer 114. Alternatively, electrons trapped in the charge trapping layer 114 may be erased from the charge trapping layer 114 via tunneling through the charge tunneling layer 112 and moving to the channel layer 102 using an erase voltage.
Meanwhile, the ferroelectric layer 120 may be disposed on the gate dielectric layer structure 110. The ferroelectric layer 120 may be disposed directly on the gate dielectric layer structure 110. In one embodiment, ferroelectric layer 120 may comprise hafnium oxide, zirconium oxide, hafnium zirconium oxide (hafnium zirconia oxide), or a combination of two or more thereof. In one embodiment, ferroelectric layer 120 may be disposed to form an interface with charge barrier layer 116. Ferroelectric layer 120 may directly interface with charge barrier layer 116. The ferroelectric layer 120 may have a negative capacitance. Negative capacitance refers to the following situation: wherein, when a voltage V is applied to both ends of the ferroelectric layer, the magnitude of the polarization P generated inside the ferroelectric layer has a curve portion 22 that changes to have a negative slope with respect to the applied voltage V, as shown in fig. 3. That is, the ferroelectric layer may be said to have a negative capacitance in the range of the curve portion 22. As will be described later, when a voltage corresponding to a coercive voltage (coercive voltage) Vc or-Vc of the ferroelectric layer is applied to the ferroelectric layer, the ferroelectric layer may have a negative capacitance.
Referring to fig. 3, typically the polarization P of the ferroelectric layer with respect to the applied voltage V may follow a hysteresis curve 21. The hysteresis curve 21 may be a closed loop having a pair of first and second coercive voltages Vc and-Vc and a pair of first and second remanent polarizations Pr and-Pr. The first and second remanent polarizations Pr and Pr may be obtained by applying voltages equal to or greater than the first and second saturation voltages Vs and Vs, respectively, to the ferroelectric layer and removing the voltages. The first coercive voltage Vc and the second coercive voltage-Vc may each refer to a voltage of minimum magnitude necessary to switch at least a portion of the remanent polarization stored in the ferroelectric layer in opposite directions.
Meanwhile, it has been reported that negative capacitance occurs when the ferroelectric layer is in an unstable state in terms of energy. Currently, the negative capacitance is described using a concept called phenomenological Landau free energy (phenomenological Landau free energy). Referring again to fig. 3, for example, when the ferroelectric layer has the second remanent polarization-Pr, voltages sequentially increasing in a positive direction from 0V may be applied to the ferroelectric layer. When the ferroelectric layer is in an unstable state, the polarization P of the ferroelectric layer may not change from a negative value to a positive value along the hysteresis curve 21 but may change from a negative value to a positive value along the new curve portion 22 if the voltage reaches the first coercive voltage Vc. I.e. in case a negative voltage is induced in the ferroelectric layer, the polarization P may vary along a curve portion 22 having a negative slope.
Similarly, for example, when the ferroelectric layer has the first residual polarization Pr, voltages sequentially increasing from 0V in the negative direction may be applied to the ferroelectric layer. When the ferroelectric layer is in an unstable state, the polarization P of the ferroelectric layer may not change from a positive value to a negative value along the hysteresis curve 21 but may change from a positive value to a negative value along the new curve portion 22 if the voltage reaches the second coercive voltage-Vc.
In addition, the energy unstable state of the ferroelectric layer can be stabilized by electrically connecting the ferroelectric layer to the paramagnetic layer in series. In one embodiment, the negative capacitance characteristic of the ferroelectric layer can be stably achieved by directly contacting the ferroelectric layer with the paraelectric layer. Fig. 4 shows a circuit diagram in which a gate dielectric layer structure 110 having a positive capacitance and a ferroelectric layer 120 having a negative capacitance are connected in series as a capacitor.
Referring again to fig. 1, a gate electrode layer 130 may be disposed on the ferroelectric layer 120. The gate electrode layer 130 may be disposed directly on the ferroelectric layer 120. The gate electrode layer 130 may include a conductive material. The conductive material may include, for example, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.
Hereinafter, a circuit in which each of the gate dielectric layer structure 110 and the ferroelectric layer 120 functions as a capacitor when a predetermined voltage is applied between the gate electrode layer 130 and the substrate 101 will be described in detail with reference to fig. 4. For convenience of description, the substrate 101 is grounded, and the capacitance of the substrate 101 itself is excluded from discussion. In fig. 4, the capacitance of the gate dielectric layer structure 110 is denoted as C110, and the capacitance of the ferroelectric layer 120 is denoted as C120.
In the case where the gate dielectric layer structure 110 and the ferroelectric layer 120 are electrically connected in series, the total capacitance C of the series circuit can be calculated by the following equation 1tot。
1/Ctot＝1/C110+1/C120…… (1)
In this case, the gate dielectric layer structure 110 includes the charge tunneling layer 112, the charge trapping layer 114, and the charge barrier layer 116 as a cis layer connected in series, and thus the capacitance C of the gate dielectric layer structure 110 can be calculated by the following equation 2110。
1/C110＝1/C112+1/C114+1/C116…… (2)
In equation 2, C112Is the capacitance, C, of the charge tunneling layer 112114Is the capacitance of the charge trapping layer 114, and C116Is the capacitance of the charge barrier layer 116.
At the same time, referring again to FIG. 4, apply to the wholeGate voltage V of the circuitgCan be divided into a first internal voltage V applied to the gate dielectric layer structure 110inAnd a second internal voltage V applied to the ferroelectric layer 120g-Vin. In this case, the first internal voltage V may be calculated by the following equation 3inAnd gate voltage VgThe ratio of (a) to (b).
Vin/Vg＝C120/(C110+C120)…… (3)
As described above, when the ferroelectric layer 120 has a negative capacitance (i.e., C)120<0) And the absolute value of the capacitance of the ferroelectric layer 120 is greater than the absolute value of the capacitance of the gate dielectric layer structure 110 (i.e., | C)120|>|C110L) when Vin/VgAnd may be greater than 1. In other words, the internal voltage applied to the gate dielectric layer structure 110 may be greater than the gate voltage applied to the gate electrode layer 130. This phenomenon is also referred to as amplification of the internal voltage hereinafter.
Referring again to fig. 3, when the gate voltage sequentially increases from 0V to reach the first coercive voltage Vc or the second coercive voltage-Vc of the ferroelectric layer 120, respectively, internal voltage amplification may occur. That is, when a gate voltage corresponding to a polarization switching voltage (polarization switching voltage) of the ferroelectric layer 120 is applied, a voltage having a polarity opposite to that of the gate voltage may be induced in the ferroelectric layer 120 along the curve portion 22 to generate a negative capacitance. As a result, an internal voltage greater than the gate voltage may be applied to the gate dielectric layer structure 110. In this case, the internal voltage may be used as a substantial operation voltage for introducing charges into the charge trapping layer 114 in the gate dielectric layer structure 110 (program operation) or for erasing charges of the charge trapping layer 114 (erase operation). Therefore, by using a phenomenon that the internal voltage is amplified with respect to the gate voltage, the gate voltage can be designed to be reduced by an amount of increase in the internal voltage. Therefore, by reducing the gate voltage applied to the gate electrode layer of the nonvolatile memory device, power consumption in the memory cell of the nonvolatile memory device can be effectively reduced.
Fig. 5 is a circuit diagram schematically illustrating the nonvolatile memory device 2 according to the embodiment of the present disclosure. Referring to fig. 5, the nonvolatile memory device 2 may include a string 2a having a plurality of cell arrays in which channels are connected in series with each other. One end of the string 2a may be connected to a source line SL, and the other end of the string 2a may be connected to a bit line BL. The string 2a may have first to sixth memory cell transistors MC1, MC2, MC3, MC4, MC5, and MC6 connected in series with each other. Further, the string 2a may include a lower selection transistor LST disposed between the first memory cell transistor MC1 and the source line SL, and an upper selection transistor UST disposed between the sixth memory cell transistor MC6 and the bit line BL.
Although fig. 5 shows that the string 2a includes six memory cell transistors for convenience of description, the present disclosure is not necessarily limited thereto, and the number of memory cell transistors constituting the string 2a is not limited. Further, fig. 5 shows that the string 2a includes one lower selection transistor LST and one upper selection transistor UST, but the present disclosure is not necessarily limited thereto. As the lower selection transistor LST, a plurality of lower selection transistors whose channels are connected to each other in series may be arranged. Also, as the upper selection transistor UST, a plurality of upper selection transistors whose channels are connected to each other in series may be arranged. The non-volatile memory device 2 may be, for example, a NAND-type flash memory device.
The first to sixth memory cell transistors MC1, MC2, MC3, MC4, MC5, and MC6 may have corresponding first to sixth channel layers ch1, ch2, ch3, ch4, ch5, and ch6, respectively, between the source line SL and the bit line BL. The first to sixth memory cell transistors MC1, MC2, MC3, MC4, MC5, and MC6 may have charge trap layers adjacent to the first to sixth channel layers ch1, ch2, ch3, ch4, ch5, and ch6, respectively. The gate electrode layers of the first to sixth memory cell transistors MC1, MC2, MC3, MC4, MC5, and MC6 may be connected to different first to sixth channel layers ch1, ch2, ch3, ch4, ch5, and ch6, respectively. The upper selection transistor UST and the lower selection transistor LST may be turned on or off, respectively, to apply a voltage between the bit line BL and the source line SL to the first to sixth channel layers ch1, ch2, ch3, ch4, ch5, and ch6, respectively, or to remove a voltage from the first to sixth channel layers ch1, ch2, ch3, ch4, ch5, and ch6, respectively. Gate electrode layers of the upper and lower selection transistors UST and LST may be connected to the upper and lower selection lines USL and LSL, respectively.
In one embodiment, the upper and lower select transistors UST and LST may be turned on, and a predetermined gate voltage may be applied to the corresponding memory cell transistors MC1, MC2, MC3, MC4, MC5, and MC6 through the first to sixth word lines WL1, WL2, WL3, WL4, WL5, and WL 6. In the memory cell transistor to which the gate voltage is applied, a program operation or an erase operation may occur between the charge trapping layer and the channel layer. The program operation or the erase operation may be performed as an operation of: wherein electrons or holes in the channel layer are tunneled to the charge trapping layer such that electrons are introduced into the charge trapping layer or electrons stored in the charge trapping layer are removed. The change of electrons after the program operation or the erase operation may be stored in the charge trapping layer as an electrical signal in a nonvolatile manner. Accordingly, the first to sixth memory cell transistors MC1, MC2, MC3, MC4, MC5 and MC6 may perform a nonvolatile memory operation.
Fig. 6A is a sectional view schematically showing the nonvolatile memory device 3 according to the embodiment of the present disclosure, fig. 6B is an enlarged view of the region "a" shown in fig. 6A, and fig. 6C is an enlarged view of the region "B" shown in fig. 6A. The nonvolatile memory device 3 of fig. 6A to 6C is an example of the nonvolatile memory device 2 having the circuit configuration of fig. 5.
Referring to fig. 6A to 6C, the nonvolatile memory device 3 may include a substrate 201 and an electrode stack structure 3a disposed on the substrate 201. The electrode stack structure 3a may have the first to eighth gate electrode layers 310a, 310b, 310c, 310d, 310e, 310f, 310g, and 310h and the first to eighth interlayer insulating layers 210a, 210b, 210c, 210d, 210e, 210f, 210g, and 210h alternately disposed. In one embodiment, the eighth interlayer insulating layer 210h may be thicker than the first to seventh interlayer insulating layers 210a, 210b, 210c, 210d, 210e, 210f and 210 g. In one embodiment, the first to seventh interlayer insulating layers 210a, 210b, 210c, 210d, 210e, 210f and 210g may have the same thickness or substantially the same thickness. Likewise, first through eighth gate electrode layers 310a, 310b, 310c, 310d, 310e, 310f, 310g, and 310h may have the same thickness or substantially the same thickness.
Furthermore, the non-volatile memory device 3 may comprise a trench 10 having a first portion 10a and a second portion 10 b. The first portion 10a of the trench 10 may be formed to penetrate the electrode stack structure 3a on the substrate 201. The second portion 10b of the trench 10 may have a shape discontinuously extending below the first portion 10a, and is formed in the substrate 201. The first portion 10a of the trench 10 may expose sidewall surfaces of the first to eighth gate electrode layers 310a, 310b, 310c, 310d, 310e, 310f, 310g, and 310h and sidewall surfaces of the first to eighth interlayer insulating layers 210a, 210b, 210c, 210d, 210e, 210f, 210g, and 210 h.
A source contact layer 203 and a source insulating layer 205 may be disposed between the substrate 201 and the electrode stack structure 3 a. The source contact layer 203 may separate the first and second portions 10a and 10b of the trench 10 from each other in a direction perpendicular to the substrate 201 (i.e., a z-direction). The side of the trench 10 may be partially entered by the source contact layer 203 in a direction parallel to the substrate 201. The trench 10 may be partially disconnected in the z-direction by the source contact layer 203.
The source contact layer 203 may include a conductive material. The source contact layer 203 may, for example, comprise a semiconductor material doped to be n-type or p-type. In particular, the source contact layer 203 may include n-type doped silicon. The source insulating layer 205 may electrically insulate the source contact layer 203 from the first gate electrode layer 310 a. The source insulating layer 205 may include, for example, an insulating oxide, an insulating nitride, an insulating oxynitride, or the like.
The non-volatile memory device 3 may include a ferroelectric layer 410 disposed along an inner surface of the trench 10. The ferroelectric layer 410 may extend in a direction perpendicular to the substrate 201 (i.e., z direction). Specifically, the ferroelectric layer 410 may be disposed to cover the first to eighth gate electrode layers 310a, 310b, 310c, 310d, 310e, 310f, 310g, and 310h and the first to eighth interlayer insulating layers 210a, 210b, 210c, 210d, 210e, 210f, 210g, and 210h along the inner surface of the first portion 10a of the trench 10. The source contact layer 203 may partially protrude inside the trench in the x-direction to interrupt the continuity of the ferroelectric layer 410 and the gate dielectric layer structure 420, and directly contact the channel layer 430. Further, the ferroelectric layer 410 may be disposed to cover the substrate 201 along the inner surface of the second portion 10b of the trench 10. In one embodiment, ferroelectric layer 410 may have a negative capacitance. The ferroelectric layer 410 may be substantially the same as the ferroelectric layer 120 of the nonvolatile memory device 1 described above with reference to fig. 1 to 4.
Furthermore, the non-volatile memory device 3 may comprise a gate dielectric layer structure 420 arranged on the ferroelectric layer 410 along the inner surface of the trench 10. A gate dielectric layer structure 420 may be disposed directly on the ferroelectric layer 410 along the inner surface of the trench 10. The gate dielectric layer structure 420 may extend in a direction perpendicular to the substrate 201 (i.e., a z-direction) to cover the first to eighth gate electrode layers 310a, 310b, 310c, 310d, 310e, 310f, 310g, and 310h and the first to eighth interlayer insulating layers 210a, 210b, 210c, 210d, 210e, 210f, 210g, and 210 h. The gate dielectric layer structure 420 may include a charge barrier layer 422, a charge trapping layer 424, and a charge tunneling layer 426 sequentially disposed on the ferroelectric layer 410.
Charge barrier layer 422 may be disposed to interface with ferroelectric layer 410. Charge barrier layer 422 may be disposed to directly interface with ferroelectric layer 410. In one embodiment, the gate dielectric layer structure 420 may have a positive capacitance. The charge barrier layer 422, the charge trapping layer 424, and the charge tunneling layer 426 may all be a paramagnetic layer. The charge barrier layer 422, the charge trapping layer 424, and the charge tunneling layer 426 may be the same or substantially the same as the charge barrier layer 116, the charge trapping layer 114, and the charge tunneling layer 112 described above with reference to fig. 1-4.
In addition, the nonvolatile memory device 3 may include a channel layer 430 disposed on the gate dielectric layer structure 420 and the source contact layer 203. The channel layer 430 may be disposed directly on the gate dielectric layer structure 420 and the source contact layer 203. More specifically, referring to fig. 6A and 6C, in the case where a portion of the channel layer 430 is disposed to contact a side surface of the source contact layer 203, the channel layer 430 may be electrically connected to the source contact layer 203. As an example, the channel layer 430 may include a semiconductor material. The semiconductor material may include silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or combinations of two or more thereof. In one embodiment, the semiconductor material may be doped with n-type or p-type dopants. As another example, the channel layer 430 may include a conductive metal oxide. The conductive metal oxide may include indium gallium zinc oxide, indium tin oxide, or the like. Meanwhile, a filling insulation layer 450 may be disposed on the channel layer 430. In one embodiment, a filling insulating layer 450 may be provided to fill the trench 10.
The channel contact layer 460 may be disposed on the filling insulation layer 450 to cover the trench while directly contacting the channel layer 430 with its side surface. The channel contact layer 460 may be electrically connected to a bit line (not shown) such that one end of the channel layer 430 may be electrically connected to the bit line. As described above, the other end of the channel layer 430 may be connected to the source contact layer 203. The channel layer 430 may be further electrically connected to a source line (not shown) via its connection with the source contact layer 203.
Meanwhile, portions of the ferroelectric layer 410, the gate dielectric layer structure 420, and the channel layer 430 covered by the first to eighth gate electrode layers 310a, 310b, 310c, 310d, 310e, 310f, 310g, and 310h in a lateral direction (e.g., x-direction or y-direction) may respectively constitute the lower selection transistor LST, the first to sixth memory cell transistors MC1, MC2, MC3, MC4, MC5, and MC6, and the upper selection transistor UST of the nonvolatile memory device 2 disclosed in fig. 5.
Referring again to fig. 6A to 6C, the ferroelectric layer 410 may be disposed to contact the gate dielectric layer structure 420 having a positive capacitance. At this time, the absolute value of the capacitance of the ferroelectric layer 410 may be greater than the absolute value of the capacitance of the gate dielectric layer structure 420. When a gate voltage having magnitudes of coercive voltages Vc and-Vc of the ferroelectric layer 410 is applied to at least one of the first to eighth gate electrode layers 310a, 310b, 310c, 310d, 310e, 310f, 310g, and 310h, the ferroelectric layer 410 may allow an internal voltage greater than the gate voltage to be applied to the gate dielectric layer structure 420. In this case, the gate voltage having the magnitudes of coercive voltages Vc and-Vc may correspond to the polarization switching voltage of ferroelectric layer 410.
An internal voltage applied to the gate dielectric layer structure 420 may generate charge movement between the gate dielectric layer structure 420 and the channel layer 430. In one embodiment, a program operation or an erase operation may be generated for the gate dielectric layer structure 420 when the internal voltage is greater than a predetermined threshold voltage. In this case, the internal voltage generating the program operation or the erase operation may be referred to as a program voltage or an erase voltage.
In particular, the charge tunneling layer 426 may be used to tunnel electrons or holes from the channel layer 430 to the charge trapping layer 424 when a program voltage or an erase voltage is applied to the gate dielectric layer structure 420. The charge tunneling layer 426 may be used to suppress leakage current between the channel layer 430 and the charge trapping layer 424 when the internal voltage is less than the threshold voltage.
During a programming operation, the charge trapping layer 424 may trap electrons introduced from the channel layer 430 at trap sites (trap sites) of the charge trapping layer 424, thereby storing the electrons in a nonvolatile manner. Further, during the erase operation, the charge trapping layer 424 may recombine holes introduced from the channel layer 430 with electrons stored in the charge trapping layer 424 to erase the stored electrons.
The charge barrier layer 422 may function as a barrier layer preventing electrons or holes introduced from the channel layer 430 into the charge trapping layer 424 from moving to the ferroelectric layer 410 and the gate electrode layers 310a, 310b, 310c, 310d, 310e, 310f, 310g, and 310 h.
As described above, according to an embodiment of the present disclosure, a nonvolatile memory device includes a gate dielectric layer structure having a positive capacitance and a ferroelectric layer having a negative capacitance electrically connected in series with each other. When a gate voltage corresponding to a polarization switching voltage of the ferroelectric layer is applied to the gate electrode layer covering the gate dielectric layer structure and the ferroelectric layer, an internal voltage greater than the gate voltage may be applied to the gate dielectric layer structure. The internal voltage may be used as a substantial operating voltage for introducing charges into the charge trapping layer in the gate dielectric layer structure or erasing charges in the charge trapping layer.
In this way, according to the embodiments of the present disclosure, by using a phenomenon that the internal voltage is amplified compared to the gate voltage, the gate voltage may be designed to be decreased by an increase amount of the internal voltage. Therefore, by reducing the gate voltage applied to the gate electrode layer of the nonvolatile memory device, power consumption in the memory cell of the nonvolatile memory device can be effectively reduced.
Embodiments of the inventive concept have been disclosed above for purposes of illustration. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the inventive concept disclosed in the accompanying claims.
Cross Reference to Related Applications
The present application claims priority from korean patent application No.10-2019-0093548, filed on 31.7.2019, the entire contents of which are incorporated herein by reference.

Claims (20)

1. A non-volatile memory device, the non-volatile memory device comprising:
a substrate having a channel layer;
a gate dielectric layer structure disposed on the channel layer;
a ferroelectric layer disposed on the gate dielectric layer structure; and
a gate electrode layer disposed on the ferroelectric layer,
wherein the gate dielectric layer structure has a positive capacitance,
wherein the ferroelectric layer has a negative capacitance,
wherein the gate dielectric layer structure includes a charge tunneling layer, a charge trapping layer, and a charge barrier layer disposed on the channel layer.
2. The non-volatile memory device of claim 1,
wherein each of the charge tunneling layer, the charge trapping layer, and the charge barrier layer is a paramagnetic layer.
3. The non-volatile memory device of claim 2,
wherein the charge tunneling layer comprises silicon oxide,
wherein the charge trapping layer comprises silicon nitride, and
wherein the charge barrier layer comprises silicon oxide.
4. The non-volatile memory device of claim 1,
wherein the ferroelectric layer comprises at least one selected from the group consisting of hafnium oxide, zirconium oxide, and zirconium hafnium oxide.
5. The non-volatile memory device of claim 1,
wherein the ferroelectric layer is disposed to form an interface with the charge barrier layer.
6. The non-volatile memory device of claim 1,
wherein the gate dielectric layer structure and the ferroelectric layer are electrically connected in series with each other between the gate electrode layer and the channel layer.
7. The non-volatile memory device of claim 6,
wherein an absolute value of a capacitance of the ferroelectric layer is greater than an absolute value of a capacitance of the gate dielectric layer structure.
8. The non-volatile memory device of claim 6,
wherein, when a gate voltage corresponding to a polarization switching voltage of the ferroelectric layer is applied to the gate electrode layer, an internal voltage greater than the gate voltage is applied to the gate dielectric layer structure.
9. The non-volatile memory device of claim 1,
wherein the substrate includes at least one selected from the group consisting of silicon Si, germanium Ge, silicon germanium SiGe, gallium arsenide GaAs, and indium phosphide InP.
10. The non-volatile memory device of claim 1, further comprising:
a source region and a drain region disposed in substrate regions at different ends of the channel layer.
11. A non-volatile memory device, the non-volatile memory device comprising:
a substrate;
an electrode stack structure disposed on the substrate, wherein the electrode stack structure includes at least one gate electrode layer and at least one interlayer insulating layer alternately stacked on the substrate;
a trench penetrating the electrode stack structure and exposing sidewall surfaces of the gate electrode layer and the interlayer insulating layer;
a ferroelectric layer provided so as to cover the interlayer insulating layer and the gate electrode layer along an inner surface of the trench, the ferroelectric layer having a negative capacitance;
a gate dielectric layer structure disposed on the ferroelectric layer, the gate dielectric layer structure having a positive capacitance; and
a channel layer disposed on the gate dielectric layer structure,
wherein the gate dielectric layer structure includes a charge tunneling layer, a charge trapping layer, and a charge barrier layer disposed on the channel layer.
12. The non-volatile memory device of claim 11,
wherein each of the ferroelectric layer and the gate dielectric layer structure extends in a direction perpendicular to the substrate and is disposed to cover the gate electrode layer.
13. The non-volatile memory device of claim 11,
wherein each of the charge tunneling layer, the charge trapping layer, and the charge barrier layer is a paramagnetic layer.
14. The non-volatile memory device of claim 11,
wherein the charge tunneling layer comprises silicon oxide,
wherein the charge trapping layer comprises silicon nitride, and
wherein the charge barrier layer comprises silicon oxide.
15. The non-volatile memory device of claim 11,
wherein the ferroelectric layer comprises at least one selected from the group consisting of hafnium oxide, zirconium oxide, and zirconium hafnium oxide.
16. The non-volatile memory device of claim 11,
wherein the ferroelectric layer is disposed to form an interface with the charge barrier layer.
17. The non-volatile memory device of claim 11,
wherein the gate dielectric layer structure and the ferroelectric layer are electrically connected in series with each other between the gate electrode layer and the channel layer.
18. The non-volatile memory device of claim 17,
wherein an absolute value of a capacitance of the ferroelectric layer is greater than an absolute value of a capacitance of the gate dielectric layer structure.
19. The non-volatile memory device of claim 17,
wherein, when a gate voltage corresponding to a polarization switching voltage of the ferroelectric layer is applied to the gate electrode layer, an internal voltage greater than the gate voltage is applied to the gate dielectric layer structure.
20. The non-volatile memory device of claim 11,
wherein the channel layer includes at least one selected from the group consisting of silicon Si, germanium Ge, silicon germanium SiGe, gallium arsenide GaAs, indium gallium arsenide, indium gallium zinc oxide, and indium tin oxide.
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