TWI467767B - 石墨烯電晶體 - Google Patents

石墨烯電晶體 Download PDF

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TWI467767B
TWI467767B TW101146094A TW101146094A TWI467767B TW I467767 B TWI467767 B TW I467767B TW 101146094 A TW101146094 A TW 101146094A TW 101146094 A TW101146094 A TW 101146094A TW I467767 B TWI467767 B TW I467767B
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graphene
layer
transistor
doped
drain
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TW201423992A (zh
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Chun Wei Chen
Po Hsun Ho
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Univ Nat Taiwan
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606Graphene
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Description

石墨烯電晶體
本發明係關於一種電晶體,特別是有關一種石墨烯電晶體(graphene transistor)。
石墨烯具有高載子遷移率,因此適合作為主動元件,例如石墨烯電晶體。
石墨烯電晶體可以製成N型石墨烯電晶體或P型石墨烯電晶體,製造N型石墨烯電晶體或P型石墨烯電晶體的方法是對石墨烯電晶體實施N型摻雜(N-type doping)或P型摻雜(P-type doping)的步驟,然而實施N型摻雜或P型摻雜所製造出的石墨烯電晶體之穩定性不佳,使得石墨烯電晶體的應用受到限制。
此外,現有摻雜方法所製成的石墨烯電晶體容易受到週遭環境的影響而使其特性變差,舉例來說,N型石墨烯電晶體容易受到週遭環境空氣及/或水氣的影響而降低其摻雜程度及載子遷移率,導致元件特性變差。
因此需要對上述石墨烯電晶體其穩定性不佳與石墨烯電晶體曝露在空氣中易受週遭環境影響的問題提出解決方法。
本發明之一目的在於提供一種石墨烯電晶體,其具有較佳之穩定性且不易受週遭環境的影響。
為達到上述目的,根據本發明之一特點係提供一種石 墨烯電晶體,包括:一源極、一汲極、一石墨烯層、一絕緣層、一閘極以及至少一摻雜層。該石墨烯層設置於該源極與該汲極之間。該閘極與該石墨烯層、該源極及該汲極之間透過該絕緣層分隔。該至少一摻雜層設置在該石墨烯層之上方及下方之至少一者,用於提供摻雜載子給該石墨烯層。該摻雜層包括非化學計量比化合物。
為達到上述目的,根據本發明之另一特點係提供一種石墨烯電晶體,包括:一源極、一汲極、一石墨烯層、一絕緣層、一閘極以及一摻雜層。該石墨烯層設置於該源極與該汲極之間。該閘極與該石墨烯層、該源極及該汲極之間透過該絕緣層分隔。該摻雜層設置在該石墨烯層之上方,用於密封該石墨烯層。該摻雜層包括非化學計量比化合物。
本發明之石墨烯電晶體中,摻雜層包括非化學計量比化合物可以對石墨烯層進行高程度摻雜。再者,在石墨烯層上設置密封之摻雜層可以防止石墨烯層受到週遭環境空氣及/或水氣的影響,防止摻雜程度降低。
以下結合附圖對本發明的技術方案進行詳細說明。
請參閱第1圖,其係繪示根據本發明第一實施例之石墨烯電晶體。
本發明之石墨烯電晶體包括一源極100、一汲極102、一石墨烯層104、一絕緣層106、一閘極108以及一摻雜層110。
於本實施例中,閘極108為具有高度N型摻雜的矽基板。於另一實施例中,閘極108可以為具有高度P型摻雜的基板。
絕緣層106形成在閘極108上。絕緣層106之材料可以為二氧化矽或其他適合之材料。閘極108與石墨烯層104、源極100與汲極102之間透過絕緣層106分隔。
與習知之石墨烯電晶體相比,本發明之石墨烯電晶體之特徵在於所使用之摻雜層110包括非化學計量比化合物,摻雜層110可以設置在石墨烯層104之上方及下方之至少一者。於本實施例中,摻雜層110係設置在石墨烯層104之下方。
石墨烯層104形成在摻雜層110上,源極100與汲極102係分開設置在石墨烯層104之兩側,亦即石墨烯層104設置在源極100與汲極102之間且與源極100與汲極102電性耦接。石墨烯層104之功能作為該石墨烯電晶體的通道層。於本實施例中,包括非化學計量比化合物之摻雜層110可以提供N型摻雜載子(N-type dopant)給石墨烯層104,以使石墨烯層104為N型摻雜。較佳而言,非化學計量比化合物(nonstoichiometric compound,又稱為非當量比化合物)包括氧化鈦(TiOx)。本發明之摻雜層110使用氧化鈦之摻雜程度高於習知使用有機分子之摻雜程度。
請參閱第2圖,其係繪示根據本發明第二實施例之石墨烯電晶體。
於第一實施例中,用於提供摻雜載子之摻雜層110係設 置在石墨烯層104之下方。於本實施例中,摻雜層112係設置在石墨烯層104之上方,包括非化學計量比化合物之摻雜層112除了可以直接對石墨烯層104進行摻雜外,還能覆蓋石墨烯層104。於另一實施例中,摻雜層112可以完整覆蓋石墨烯層104,達到密封石墨烯層104的功能,防止石墨烯層104與空氣接觸,避免受到環境中氣體及/或水氣的影響而使石墨烯電晶體變質,也就是說,使石墨烯電晶體在空氣中具有更好的穩定度,不會因為石墨烯層104的表面接觸到空氣及/或水氣而造成摻雜程度下降。
源極100、汲極102、石墨烯層104、絕緣層106及閘極108與第一實施例相同,此不多加贅述。
請參閱第3圖以及第4圖,第3圖係繪示根據本發明第三實施例之石墨烯電晶體,第4圖係繪示第3圖中摻雜層110、112將石墨烯層104夾在中間之示意圖。
與前兩實施例之不同在於第三實施例之石墨烯電晶體係在石墨烯層104之上方與下方分別包括摻雜層112、110,石墨烯層104下方之摻雜層110能提供摻雜載子給石墨烯層104,石墨烯層104上方之摻雜層112亦能提供摻雜載子給石墨烯層104並能覆蓋石墨烯層104,使石墨烯電晶體在空氣中具有更好的穩定度。於本實施例中,摻雜層112和110可以完整覆蓋石墨烯層104,達到密封石墨烯層104的功能,使石墨烯電晶體在空氣中具有更好的穩定度,不會因為石墨烯層104的表面接觸到空氣及/或水氣而造成摻雜程度下降。
此外,本實施例之石墨烯電晶體包括兩層摻雜層110、112,因此能達到較高摻雜程度,由於摻雜層110、112本身具有疏水性,故比第2圖具有更好的水氣阻隔效果。
源極100、汲極102、石墨烯層104、絕緣層106及閘極108與第一及第二實施例相同,此不多加贅述。
上述第一實施例至第三實施例之石墨烯電晶體為底部閘極型電晶體,亦即閘極108位於源極100與汲極102之下方。
較佳而言,上述摻雜層110、112之厚度為10至50奈米。
請參閱第5圖,其係繪示根據本發明第四實施例之石墨烯電晶體。
本實施例之石墨烯電晶體包括一源極100、一汲極102、一石墨烯層104、一絕緣層106、一閘極108以及兩摻雜層110、112。與上述實施例之不同在於第四實施例之石墨烯電晶體為頂部閘極型電晶體,亦即閘極108位於源極100與汲極102之上方。
石墨烯層104設置於源極100與汲極102之間以作為該石墨烯電晶體的通道層。石墨烯層104電性耦接源極100與汲極102。
摻雜層112、110分別設置在石墨烯層104之上方及下方。於本實施例中,包括非化學計量比化合物之摻雜層110、112提供N型摻雜載子(N-type dopant)給石墨烯層104,以使石墨烯層104為N型摻雜。摻雜層104之材料包 括非化學計量比化合物,較佳而言,非化學計量比化合物包括氧化鈦。石墨烯層104上方之摻雜層112除了能提供N型摻雜載子給石墨烯層104外,還能覆蓋並密封石墨烯層104,使石墨烯電晶體在空氣中具有更好的穩定度。由於本實施例之石墨烯電晶體包括兩層摻雜層110、112,因此能達到較高摻雜程度。
要說明的是,本實施例之石墨烯電晶體之摻雜層112可以完整覆蓋石墨烯層104,達到密封石墨烯層104的功能或僅覆蓋石墨烯層104的一部分。
如同第一實施例與第二實施例,本實施例之石墨烯電晶體可以僅包括摻雜層110、112之其中一者。
閘極108與石墨烯層104、源極100及汲極102之間透過絕緣層106分隔。絕緣層106之材料可以為二氧化矽或其他適合之材料。
綜上可知,本發明之摻雜層110、112包括非化學計量比化合物可以提供N型摻雜載子。此外,摻雜層110、112使用氧化鈦之摻雜程度高於習知使用有機分子之摻雜程度。
上述第一實施例至第四實施例中,摻雜層110、112可以藉由溶液製程(solution process)形成,不需經過高溫製成且沒有毒性。舉例來說,以旋轉塗佈(spin-coating)的方式噴灑氧化鈦溶液來形成摻雜層110、112。要說明的是,其他適合形成摻雜層110、112的方式為本領域所屬技術人員所熟知,此不多加贅述。
下列第6A圖、第6B圖及第7圖將說明本發明之摻雜層使用氧化鈦對石墨烯層具有摻雜載子的作用。
請參閱第6A圖,其係繪示不同濃度之氧化鈦作為摻雜層時,藉由X射線光電子光譜法(X-ray photoelectron spectroscopy;XPS)所測得Cls峰值之光譜。對應至純sp2 混成狀態(pure sp2 -hybridized state)之原始(pristine)石墨烯(即未包括摻雜層)之Cls峰值之結合能集中在284.5±0.05電子伏特(electron volt;eV),隨著作為摻雜層之氧化鈦的濃度越高,Cls峰值朝向較高的結合能逐漸偏移,氧化鈦濃度為20毫克/毫升(mg/mL)時,Cls峰值大約偏移0.75電子伏特。濃度再增加時不會再造成Cls峰值的偏移,而會加寬其帶寬(bandwidth)。束縛能的偏移係因為在氧化鈦(亦即摻雜層)與石墨烯層之間的介面產生電子傳遞(electron transfer),使費米能階(Fermi level)朝向或高於石墨烯層的迪拉克點(Dirac point),亦即摻雜層提供N型摻雜載子,使石墨烯層變成N型摻雜。
請參閱第6B圖,其係繪示不同濃度之氧化鈦作為摻雜層時,拉曼光譜(Raman spectroscopy)之測量結果。測量時使用之激發光譜為633奈米(nanometer,nm)。由於石墨烯層變成N型摻雜,費米能階偏移對聲子頻率(phonon frequency)的作用使得石墨烯電晶體之2D band從2644cm-1 (原始)至2634cm-1 (氧化鈦濃度為10毫克/毫升)與2632cm-1 (氧化鈦濃度為20毫克/毫升)。
請參閱第7圖,其係繪示不同濃度之氧化鈦作為摻雜 層時之閘極相依導電率(gate-dependent conductivity)σ。不同濃度之氧化鈦所製成的石墨烯電晶體係在真空條件為10-4 托耳(torr)下測量。氧化鈦濃度越高時,迪拉克點會朝向負向閘極電壓偏移,表示石墨烯層為N型摻雜。
下列第8圖、第9A圖及第9B圖將說明本發明之石墨烯電晶體具有在空氣中具有較佳之穩定度。
請參閱第8圖,其係繪示第3圖之石墨烯電晶體(包括兩層摻雜層)曝露在空氣中之閘極相依導電率曲線。石墨烯電晶體曝露在空氣中五天後,迪拉克電壓從-80伏特變成-78伏特,石墨烯電晶體曝露在空氣中十天後,迪拉克電壓變成-62伏特。與習知石墨烯電晶體相比,本發明之石墨烯電晶體以氧化鈦作為摻雜層較不易受到週遭環境的影響,亦即本發明之石墨烯電晶體在空氣中具有較佳之穩定度。
請參閱第9A圖與第9B圖,第9A圖係繪示本發明之石墨烯電晶體具有摻雜層(氧化鈦)設置在絕緣層(二氧化矽)上(如第1圖所示)時之接觸角(contact angle),第9B圖係繪示習知石墨電晶體之絕緣層(二氧化矽)之接觸角。本發明之氧化鈦/二氧化矽結構具有76°度之接觸角,表示具有疏水性(hydrophobic),習知二氧化矽具有7°度之接觸角,表示具有親水性(hydrophilic),因此本發明之氧化鈦/二氧化矽結構可以大幅降低水氣的影響。
本發明之石墨烯電晶體具有下列優點:(1)摻雜層使用非化學計量比化合物比起習知之石墨烯電晶體具有更好 的摻雜效果;(2)不會造成載子遷移率下降;(3)在石墨烯層上設置密封之摻雜層可以防止石墨烯層受到週遭環境空氣及/或水氣的影響,防止摻雜程度降低;(4)摻雜層利用簡單的溶液製程形成,不須經過高溫製成。
綜上所述,雖然本發明已用較佳實施例揭露如上,然其並非用以限定本發明,本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧源極
102‧‧‧汲極
104‧‧‧石墨烯層
106‧‧‧絕緣層
108‧‧‧閘極
110、112‧‧‧摻雜層
第1圖係繪示根據本發明第一實施例之石墨烯電晶體;第2圖係繪示根據本發明第二實施例之石墨烯電晶體;第3圖係繪示根據本發明第三實施例之石墨烯電晶體;第4圖係繪示第3圖中摻雜層將石墨烯層夾在中間之示意圖;第5圖係繪示根據本發明第四實施例之石墨烯電晶體;第6A圖係繪示不同濃度之氧化鈦作為摻雜層時,藉由X射線光電子光譜法所測得Cls峰值之光譜;第6B圖係繪示不同濃度之氧化鈦作為摻雜層時,拉曼光譜之測量結果;第7圖係繪示不同濃度之氧化鈦作為摻雜層時之閘極相依導電率;第8圖係繪示第3圖之石墨烯電晶體曝露在空氣中之閘極相依導電率曲線; 第9A圖係繪示本發明之石墨烯電晶體具有摻雜層設置在絕緣層上時之接觸角;以及第9B圖係繪示習知石墨電晶體之絕緣層之接觸角。
100‧‧‧源極
102‧‧‧汲極
104‧‧‧石墨烯層
106‧‧‧絕緣層
108‧‧‧閘極
110‧‧‧摻雜層

Claims (10)

  1. 一種石墨烯電晶體,包括:一源極;一汲極;一石墨烯層,設置於該源極與該汲極之間;一絕緣層;一閘極,與該石墨烯層、該源極及該汲極之間透過該絕緣層分隔;以及至少一摻雜層,設置在該石墨烯層之上方及下方之至少一者,用於提供摻雜載子給該石墨烯層,該摻雜層包括非化學計量比化合物。
  2. 如申請專利範圍第1項所述之石墨烯電晶體,其中該非化學計量比化合物包括氧化鈦。
  3. 如申請專利範圍第1項所述之石墨烯電晶體,其中該摻雜層係完整覆蓋該石墨烯層。
  4. 如申請專利範圍第1項所述之石墨烯電晶體,其中該摻雜層之厚度為10至50奈米。
  5. 如申請專利範圍第1項所述之石墨烯電晶體,包括兩層摻雜層分別設置在該石墨烯層之上方及下方,且設置在該石墨烯層之上方的摻雜層完整覆蓋該石墨烯層。
  6. 如申請專利範圍第1項所述之石墨烯電晶體,其係為一底部閘極型電晶體或一頂部閘極型電晶體。
  7. 一種石墨烯電晶體,包括:一源極; 一汲極;一石墨烯層,設置於該源極與該汲極之間;一絕緣層;一閘極,與該石墨烯層、該源極及該汲極之間透過該絕緣層分隔;以及一摻雜層,設置在該石墨烯層之上方,用於密封該石墨烯層,該摻雜層包括非化學計量比化合物。
  8. 如申請專利範圍第7項所述之石墨烯電晶體,其中該非化學計量比化合物包括氧化鈦。
  9. 如申請專利範圍第7項所述之石墨烯電晶體,其中該摻雜層之厚度為10至50奈米。
  10. 如申請專利範圍第7項所述之石墨烯電晶體,其係為一底部閘極型電晶體或一頂部閘極型電晶體。
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