TWI467746B - Semiconductor device, manufacturing method thereof, and electronic apparatus - Google Patents

Description

Semiconductor component, manufacturing method thereof and electronic device

The present invention relates to a semiconductor device such as a solid-state imaging device, a method of fabricating the same, and an electronic device including the solid-state imaging device, such as a camera.

As a solid-state imaging element, an amplifying type solid-state imaging element such as a MOS such as a CMOS (Complementary Metal Oxide Semiconductor) or an image sensor is known. Further, a charge transfer type solid-state imaging element such as a CCD (Charge Coupled Device) image sensor is known. These solid-state imaging elements are widely used in digital still cameras, digital video cameras, or the like. In recent years, MOS image sensors have been widely used in mobile devices (such as portable phones with a camera or PDA (personal digital assistant)) in terms of low power voltage and power consumption. Solid state imaging element.

In the MOS solid-state imaging element, a unit pixel includes a photodiode serving as one photoelectric conversion unit and a plurality of pixel transistors. The MOS solid-state imaging element includes a pixel array (pixel region) of a plurality of unit pixels configured in a two-dimensional array shape and a peripheral circuit region. The plurality of pixel transistors are formed as MOS transistors, and include three transistors that are a transmission transistor, a reset transistor, an amplifying transistor, or four transistors that additionally include a selection transistor.

Heretofore, as far as a MOS solid-state imaging element is concerned, various solid-state imaging elements have been proposed, including a semiconductor wafer in which one of a plurality of pixels is arranged, and a semiconductor wafer including one of logic circuits including signal processing. Electrically connected and thus configured as a single component. For example, Japanese Unexamined Patent Application Publication No. Publication No. No. 2006-49361 discloses a semiconductor module in which a micro-bump is used to include a backside illuminated image in one of the pixel cells. The tester wafer is connected to one another with a signal processing wafer including a plurality of micropads in which a signal processing circuit is formed.

International Publication No. WO 2006/129762 discloses a semiconductor image sensor module in which a stack includes a first semiconductor wafer of an image sensor, a second semiconductor wafer including an array of analog/digital converters, and A third semiconductor wafer comprising one of the memory device arrays. The first semiconductor wafer and the second semiconductor wafer are connected to each other via a bump, and the bump is a conductive connecting conductor. The second semiconductor wafer and the third semiconductor wafer are connected to each other by a through contact penetrating through the second semiconductor wafer.

Various techniques for combining different circuit wafers, such as image sensor wafers and logic circuits for performing signal processing, have been proposed as disclosed in Japanese Unexamined Patent Application Publication No. Publication No. No. No. No. No. No. No. No. No. No. No. In the related art, substantially completed functional wafers are connected to each other via the formed through-connection holes. Alternatively, the wafers are connected to one another via bumps.

The present application has proposed a solid-state imaging device in which a semiconductor wafer unit including a pixel array and a semiconductor wafer unit including a logic circuit are bonded to each other to enable the respective semiconductor wafers to perform sufficiently and thus achieve mass production and low cost. The solid state imaging device is formed by bonding a first semiconductor wafer unit including one of the half completed pixel arrays to a second semiconductor wafer unit including one of the half completed logic circuits; thinning the first semiconductor wafer unit; and then The pixel array is connected to the logic circuit. The pixel array and the logic circuit are connected by forming a connection conductor connected to one of the first semiconductor wafer unit wirings, penetrating the first semiconductor wafer unit, and connecting to one of the second semiconductor wafer units One of the wirings is connected to the connecting conductor and one of the connecting conductors that connects the two connecting conductors to each other. Thereafter, the finished product is divided into a number of wafers, and thus the solid state imaging element is configured as a backside illuminated solid state imaging element.

In the solid-state imaging device, the connection conductor and the through-connection conductor are formed to be buried between the through-holes of the first semiconductor wafer unit and the substrate through which an insulating film is interposed. The cross-sectional area of the connecting conductor and the cross-sectional area of the through-connecting conductor are relatively large. For this reason, when the parasitic capacitance between the germanium substrate and the connecting conductor and the through-connecting conductor is not neglected, the parasitic capacitance has been proven to deteriorate the driving speed of one of the circuits and thus the high performance of the solid-state imaging element. Deterioration.

In a solid-state imaging element having a configuration in which a bonded semiconductor wafer unit is connected to each other by a connection conductor and a through-connection conductor, a pair of conductors (connection conductors and through-connection conductors) are connected to correspond to each vertical signal Each wire of the wire (ie, laying wiring). At this time, a ground capacitance as a parasitic capacitance and an adjacent coupling capacitor appear. For example, the ground capacitance is a parasitic capacitance between a wiring and a semiconductor substrate having a ground potential. The adjacent coupling capacitors are parasitic capacitances between adjacent laying wires or a pair of adjacent conductors. The ground capacitance can be decomposed when power is increased or a snubber circuit current is supplied. However, adjacent coupling capacitors may not be decomposed due to interference with an adjacent line.

The problem of parasitic capacitance may even occur in a semiconductor device in which semiconductor wafer units each including a semiconductor integrated circuit are bonded to each other and the semiconductor wafer units are connected to each other by a connecting conductor and a through connecting conductor.

It is desirable to provide a semiconductor element such as a solid-state imaging element capable of reducing parasitic capacitance and achieving high performance, and a manufacturing method thereof. Furthermore, it is desirable to provide an electronic device including the solid-state imaging element, such as a camera.

According to an embodiment of the present invention, a semiconductor device including a stacked semiconductor wafer formed by bonding two or more semiconductor wafer units to each other, and at least one pixel array and A multilayer wiring layer is formed in a first semiconductor wafer unit and a logic circuit and a multilayer wiring layer are formed in a second semiconductor wafer unit. The first semiconductor wafer unit includes a semiconductor removal region in which one of the semiconductor segments of one of the first semiconductor wafer units is completely removed. A semiconductor element according to this embodiment of the present invention includes a plurality of connection wirings formed in the semiconductor removal region and connecting the first semiconductor wafer unit and the second semiconductor wafer unit to each other. Therefore, the semiconductor component is configured as a backside illuminated solid state imaging element.

In a semiconductor device in accordance with an embodiment of the present invention, the semiconductor removal region is formed such that a semiconductor segment of a portion of the first semiconductor wafer having a pixel array is completely removed. A connection wiring connecting the first semiconductor wafer unit and the second semiconductor wafer unit is formed in the semiconductor removal region. Therefore, the parasitic capacitance between the connection wiring and the semiconductor can be reduced.

In accordance with another embodiment of the present invention, a method of fabricating a semiconductor component is provided. The method includes bonding two or more semiconductor wafers including at least a first semiconductor wafer and a second semiconductor wafer. In the first semiconductor wafer, a pixel array and a multilayer wiring layer are formed in a region serving as a first semiconductor wafer unit. In the second semiconductor wafer, a logic circuit and a multilayer wiring layer are formed in a region serving as a second semiconductor wafer unit. The method further includes forming a semiconductor removal region by completely removing a semiconductor segment that is part of the region of the first semiconductor wafer unit in the first semiconductor wafer. The method further includes forming a plurality of connection wirings connecting the first semiconductor wafer unit and the second semiconductor wafer unit in the semiconductor removal region and dividing the semiconductor wafer formed into a final product into a plurality of wafers. Therefore, a back side illumination type solid state imaging element is manufactured.

In a method of fabricating a semiconductor device according to an embodiment of the present invention, two or more semiconductor wafers are bonded to each other, and a semiconductor segment serving as a portion of a region of the first semiconductor wafer unit having the pixel array is completely removed, A connection wiring connecting the first semiconductor wafer unit and the second semiconductor wafer unit to each other is formed in the semiconductor removal region. Therefore, a back side illumination type solid state imaging element capable of reducing parasitic capacitance between the connection wiring and the semiconductor can be manufactured.

According to still another embodiment of the present invention, an electronic device is provided, comprising: a solid-state imaging element; an optical system that directs incident light to one of the photoelectric conversion elements of the solid-state imaging element; and processes one of the outputs from the solid-state imaging element One of the signals is a signal processing circuit. The solid-state imaging device includes a stacked semiconductor wafer formed by bonding two or more semiconductor wafer units to each other, and wherein a pixel array and a multilayer wiring layer are formed at least in a first A logic circuit and a multilayer wiring layer are formed in the semiconductor wafer unit at least in a second semiconductor wafer unit. The first semiconductor wafer unit includes a semiconductor removal region in which one of the semiconductor segments of one of the first semiconductor wafer units is completely removed. The solid-state imaging element according to this embodiment of the present invention further includes a plurality of connection wirings formed in the semiconductor removal region and connecting the first semiconductor wafer unit and the second semiconductor wafer unit to each other. The solid state imaging element is configured as a backside illuminated solid state imaging element.

An electronic device according to an embodiment of the present invention includes a back side illumination type solid state imaging element having the configuration set forth above as a solid state imaging element. Therefore, the solid-state imaging element can reduce the parasitic capacitance between the semiconductor and the connection wiring connecting the first semiconductor wafer unit and the second semiconductor wafer unit.

According to still another embodiment of the present invention, a semiconductor device including a stacked semiconductor wafer formed by bonding two or more semiconductor wafer units to each other, and at least one of which is provided The first semiconductor integrated circuit and a multilayer wiring layer are formed in a first semiconductor wafer unit, and a second semiconductor integrated circuit and a multilayer wiring layer are formed in a second semiconductor wafer unit. The first semiconductor wafer unit includes a semiconductor removal region in which one of the semiconductor segments of one of the first semiconductor wafer units is completely removed. The semiconductor device according to this embodiment of the invention further includes a plurality of connection wirings formed in the semiconductor removal region and connecting the first semiconductor wafer unit and the second semiconductor wafer unit to each other.

In the semiconductor device according to this embodiment of the invention, a semiconductor removal region in which a semiconductor portion of a portion of the first semiconductor wafer unit is completely removed is formed and a semiconductor integrated circuit is formed in the semiconductor removal A connection wiring in which the first semiconductor wafer unit and the second semiconductor wafer unit in the region are connected to each other. Therefore, the parasitic capacitance between the connection wiring and the semiconductor can be reduced.

According to the semiconductor element of the embodiment of the invention, the parasitic capacitance between the semiconductor and the connection wiring connecting the first semiconductor wafer unit and the second semiconductor wafer unit to each other can be reduced. Therefore, a back side illumination type solid state imaging element formed of a bonded wafer having high performance can be realized.

According to this embodiment of the invention, the method of manufacturing the semiconductor element can reduce the parasitic capacitance between the semiconductor and the connection wiring connecting the first semiconductor wafer unit and the second semiconductor wafer unit to each other. Therefore, a back side illumination type solid state imaging element formed of a bonded wafer having high performance can be realized.

According to the electronic device of this embodiment of the present invention, parasitic capacitance can be reduced and a high-performance backside-illuminated solid-state imaging element formed of the bonded wafers can be provided. Thus, an electronic device such as a high quality camera can be provided.

According to the semiconductor element according to this embodiment of the invention, the parasitic capacitance between the semiconductor and the connection wiring connecting the first semiconductor wafer unit and the second semiconductor wafer unit to each other can be reduced. Therefore, a semiconductor integrated circuit element formed of a bonded wafer having high performance can be realized.

Hereinafter, a mode for carrying out the invention (hereinafter referred to as an embodiment) will be explained. The explanation will be made in the following order.

1. Example of the overall configuration of MOS solid-state imaging components

2. First Embodiment (Example of Configuration of Solid-State Imaging Element and Example of Manufacturing Method)

3. Second Embodiment (Example of Configuration of Solid-State Imaging Element and Example of Manufacturing Method)

4. Third Embodiment (Example of Configuration of Solid-State Imaging Element and Example of Manufacturing Method)

5. Fourth Embodiment (Example of Configuration of Solid-State Imaging Element)

6. Fifth Embodiment (Example of Configuration of Solid-State Imaging Element)

7. Sixth Embodiment (Example of Configuration of Solid-State Imaging Element)

8. Seventh Embodiment (Example of Configuration of Solid-State Imaging Element)

9. Eighth Embodiment (Example of Configuration of Semiconductor Element)

10. Ninth Embodiment (Example of Configuration of Semiconductor Element)

11. Tenth Embodiment (Example of Configuration of Semiconductor Element)

12. Eleventh Embodiment (Example of Configuration of Semiconductor Element)

1. Example of the overall configuration of MOS solid-state imaging components

1 is a diagram showing an overall configuration of a MOS solid-state imaging element applied to a semiconductor element in accordance with an embodiment of the present invention. The MOS solid-state imaging element is applied to a solid-state imaging element according to various embodiments. As shown in FIG. 1, an exemplary solid-state imaging device 1 includes a pixel array (so-called pixel region) 3 and a peripheral circuit segment in which pixels 2 of a plurality of photoelectric conversion units are included in two dimensions. The array form is regularly arranged on a semiconductor substrate 11 such as a germanium substrate. The pixel 2 includes a photoelectric conversion unit such as a photodiode and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors can include, for example, three transistors: a transmission transistor, a reset transistor, and an amplifying transistor. The plurality of pixel transistors can include four transistors by further providing a selection transistor. One of the unit pixel equivalent circuits has a conventional configuration and thus will not be described in detail. Pixel 2 can be configured as one unit pixel. Further, the pixel 2 has a pixel sharing structure. The pixel sharing structure is formed by a plurality of photodiodes, a plurality of transmission transistors, a common floating diffusion, and a common pixel transistor. That is, in the pixel sharing structure, the photodiode and the transmission transistor forming the plurality of unit pixels each share a different pixel transistor.

The peripheral circuit section includes a vertical drive circuit 4, a row signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8.

The control circuit 8 receives information about an input clock, an operation mode, or the like, and outputs information about internal information of the solid-state imaging element or the like. That is, the control circuit 8 generates a clock signal serving as a reference for the vertical drive circuit 4, the line signal processing circuit 5, the horizontal drive circuit 6, and the like, which are respectively based on a vertical synchronizing signal, a horizontal synchronizing signal, and a main clock. Or control signal. These signals are input to the vertical drive circuit 4, the line signal processing circuit 5, the horizontal drive circuit 6, and the like.

The vertical drive circuit 4 includes, for example, a shift register that selects pixel drive lines, supply pulses for driving pixels of the selected pixel drive lines, and drives the pixels in a column of cells. That is, the vertical driving circuit 4 sequentially selects and scans the pixels 2 of the pixel array 3 in units of one column in a vertical direction, and supplies the line signal processing circuit 5 via the vertical signal line 9 based on, for example, acting as a separate A pixel signal of a signal charge generated by the amount of light received in the photodiode of the photoelectric conversion unit of the pixel 2.

Since the pixels are arranged in each row, the row signal processing circuit 5 is disposed, for example, in 2 rows of each pixel, and performs a signal output from the pixel 2 corresponding to one of the lines of each pixel row. Signal processing, such as a noise removal process. That is, the line signal processing circuit 5 performs signal processing such as removing the CDS, signal amplification, and AD conversion of the fixed pattern noise unique in the pixel 2. A horizontal selection switch (not shown) is mounted in the output stage of the line signal processing circuit 5 to be connected between the output stage and the horizontal signal line 10.

The horizontal driving circuit 6 includes, for example, a shift register that sequentially selects the horizontal signal scanning circuit to sequentially select the horizontal signal processing circuit 5, and in the future, the pixel signals of the self-processing signal processing circuit 5 are respectively output to the horizontal signal. Line 10.

The output circuit 7 performs signal processing on the signals sequentially supplied from the self signal processing circuit 5 via the horizontal signal line 10 and outputs the processed signals. For example, output circuit 7 sometimes buffers such signals or sometimes performs various digital signal processing, such as black standard adjustments and line change corrections. An input/output terminal 12 transmits and receives signals to and from the outside.

2A through 2C are diagrams showing a basic overall configuration of a MOS solid-state imaging element according to an embodiment of the present invention. In the MOS solid-state imaging element 151 according to one of the related art, a pixel array 153, a control circuit 154, and a logic circuit 155 for performing signal processing are mounted in a semiconductor wafer 152 as shown in FIG. 2A. In general, pixel array 153 and control circuit 154 form an image sensor 156. On the other hand, in a MOS solid-state imaging device 20 according to an embodiment of the present invention, a pixel array 23 and a control circuit 24 are mounted in a first semiconductor wafer unit 22 and include a signal for performing signal processing. One of the processing circuits logic circuit 25 is mounted in a second semiconductor wafer unit 26, as shown in Figure 2B. The first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are electrically connected to each other to form a single semiconductor wafer of one of the MOS solid-state imaging elements 20. In a MOS solid-state imaging device 21 according to another embodiment of the present invention, a pixel array 23 is mounted in a first semiconductor wafer unit 22, and a control circuit 24 and a logic circuit 25 including a signal processing circuit Mounted in a second semiconductor wafer unit 26, as shown in Figure 2C. The first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are electrically connected to each other to form a single semiconductor wafer of one of the MOS solid-state imaging elements 21.

Although not illustrated, two or more semiconductor wafers may be bonded to each other, depending on the configuration of the MOS solid state imaging device. For example, in addition to the first semiconductor wafer unit and the second semiconductor wafer unit as set forth above, one semiconductor wafer unit including one memory device array and one semiconductor wafer unit including another circuit device may be added, and Three or more semiconductor wafer units may be bonded to each other to form a single wafer of one of the MOS solid-state imaging elements.

2. First embodiment Example of configuration of solid-state imaging components

Figure 3 is a diagram showing one of semiconductor elements (i.e., a MOS solid-state imaging element) according to a first embodiment of the present invention. The solid state imaging device 28 according to the first embodiment includes a stacked semiconductor wafer 27 including a pixel array 23 and a control circuit 24, a first semiconductor wafer unit 22 and a second semiconductor wafer including a logic circuit 25. Units 26 are joined to each other. The first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are bonded to each other such that the multilayer wiring layers 41 and 55 face each other. The semiconductor wafer units can be bonded to each other by an adhesive layer 57 with the protective films 42 and 56 interposed therebetween. The semiconductor wafer units can be bonded to each other by plasma welding.

In the present embodiment, one of the semiconductor segments of one of the first semiconductor wafer units 22 is completely removed to form a semiconductor removal region 52. In the semiconductor removal region 52, a connection wiring 67 is formed to connect the first semiconductor wafer unit 22 to the second semiconductor wafer unit 26. The semiconductor removal region 52 is an entire region including a portion in which each of the connection wirings 67 connected to one of the vertical signal lines corresponding to the pixel array 23 is formed. Semiconductor removal region 52 is formed outside of pixel array 23, as shown in Figure 15A. The semiconductor removal region 52 corresponds to a so-called electrode pad region. In FIG. 15A, the semiconductor removal region 52 is formed vertically outside the pixel array 23.

In the first semiconductor wafer unit 22, a photodiode (PD) serving as a photoelectric conversion unit, a pixel array 23 including a plurality of pixel transistors Tr1 and Tr2, and a MOS battery are formed in a thinned first semiconductor substrate 31. Control circuit 24 of crystals Tr3 and Tr4. This figure illustrates representative pixel transistors Tr1 and Tr2 and representative MOS transistors Tr3 and Tr4. In the present embodiment, on one surface 31a of the semiconductor substrate 31, a multilayer wiring layer 41 is formed in which three layers of metal M1 to M3 interposed with an interlayer insulating film 39 interposed therebetween are formed. Wiring 40 [40a, 40b, and 40c]. Hereinafter, when a method of manufacturing the pixel transistors Tr1 and Tr2 and the MOS transistors Tr3 and Tr4 is explained, the pixel transistors Tr1 and Tr2 and the MOS transistors Tr3 and Tr4 of the control circuit 24 will be described in detail.

In the second semiconductor wafer unit 26, a logic circuit 25 including MOS transistors Tr6 to Tr8 is formed on a second semiconductor substrate 45. In the present embodiment, on one surface 45a of the semiconductor substrate 45, a multilayer wiring layer 55 is formed in which three layers of metal M11 to M13 having an interlayer insulating film 49 interposed therebetween are formed. Wiring 53 [53a, 53b, and 53c]. The MOS transistors Tr6 and Tr8 will be described in detail below when a method of manufacturing the MOS transistors Tr6 and Tr8 is explained.

In the semiconductor removal region 52 of the first semiconductor wafer unit 22, the entire first semiconductor substrate 31 is removed by, for example, etching. One of the stacked insulating films 61 formed by, for example, a yttrium oxide (SiO ₂ ) film 58 and a tantalum nitride (SiN) film 59 is extended from the bottom surface and the side surface of the semiconductor removal region 52 to the semiconductor substrate. The surface is formed. The stacked insulating film 61 serves as a protective insulating film that protects the semiconductor substrate 31 exposed toward the side surface of the depressed portion of one of the semiconductor removal regions 52, and also functions as one of the antireflection films of the pixels.

In the semiconductor removal region 52, a connection hole 64 is formed to extend from the tantalum nitride film 59 to one of the plurality of wiring layers 41 electrically connected to the first semiconductor wafer unit 22 (in this example, by the third One of the first connection pads 65 of the laying wiring 40d) formed by the layer metal M3. Further, a through connection hole 62 is formed to penetrate the multilayer wiring layer 41 of the first semiconductor wafer unit 22 and extend to one of the plurality of wiring layers 55 electrically connected to the second semiconductor wafer unit 26 (in this example, The third layer metal M13 forms one of the second connection pads 63 of one of the wirings 53d).

The connection wiring 67 includes a buried connection hole 64 and 62 and is electrically connected to one of the first connection pads 65, and is electrically connected to one of the second connection pads 63, the through-connection conductor 69, and the upper portion of the electrical connection connection conductor 68. The end is connected to the conductor 71 at one of the upper ends of the through-connection conductors 69.

A light shielding film 72 covering one of the areas where light is to be shielded is formed on the rear surface 31b which is one of the light incident surfaces of the photodiode 34 serving as the first semiconductor wafer unit 22. Further, a planarization film 73 is formed so as to cover the light shielding film 72, a color filter 74 on the wafer is formed on the planarization film 73 to correspond to the respective pixels, and a wafer is formed on the wafer on the color filter 74. The microlens 75 is such that the back side illumination type solid state imaging element 28 is formed. The connection conductor 71 exposed outside the connection wiring 67 serves as an electrode pad which is connected to an external wiring with a bonding wire interposed therebetween.

Example of a method of manufacturing a solid-state imaging element

4 through 14 are diagrams showing a method of manufacturing the solid state imaging element 28 in accordance with the first embodiment.

As shown in FIG. 4, the image sensor is half-finished, that is, the pixel array 23 and the control are formed in the regions of the respective wafer units of the first semiconductor wafer (hereinafter, also referred to as a semiconductor substrate) 31. Circuit 24. That is, a photodiode (PD) serving as one of the photoelectric conversion units of each pixel is formed in a region in which each of the wafer units in which the semiconductor substrate (for example, a substrate) 31 is formed. A source/drain region 33 of each pixel transistor is formed in a semiconductor well region 32. The semiconductor well region 32 is formed by introducing a first conductivity type impurity (for example, a p-type impurity), and the source/drain region 33 is introduced by introducing a second conductivity type impurity (for example, an n-type impurity) ) formed. The photodiode (PD) and the source/drain regions 33 of each pixel transistor are formed by implanting ions from the front surface of the semiconductor substrate.

A photodiode (PD) is formed to include an n-type semiconductor region 34 and a p-type semiconductor region 35 on the side of the surface of the substrate. A gate electrode 36 (which forms a pixel) is formed on the surface of the substrate with a gate insulating film interposed therebetween, and a pixel transistor is formed by the gate electrode 36 and the pair of source/drain regions 33 Tr1 and Tr2. In FIG. 4, two pixel transistors Tr1 and Tr2 are illustrated as representative pixel transistors of a plurality of pixel transistors. The pixel transistor Tr1 adjacent to the photodiode (PD) corresponds to a transfer transistor, and its source/drain region corresponds to a floating diffusion (FD). The individual unit pixels 30 are isolated from one another by a device isolation region 38. For example, the device isolation region 38 is formed in an STI (shallow trench isolation) structure by embedding an insulating film (such as a SiO ₂ film) in a trench formed in the substrate.

On the other hand, on the side of the control circuit 24, a MOS transistor forming a control circuit is formed on the semiconductor substrate 31. In FIG. 4, MOS transistors Tr3 and Tr4 are illustrated as representative MOS transistors forming control circuit 23. The MOS transistors Tr3 and Tr4 are formed of an n-type source/drain region 33 and a gate electrode 36 with a gate insulating film interposed therebetween.

Next, a first interlayer insulating film 39 is formed on the surface of the semiconductor substrate 31, and then connection holes are formed in the interlayer insulating film 39 to form connection conductors 44 connected to the respective transistors. When forming the connection conductors 44 having different heights, a first insulating film 43a (such as a hafnium oxide film) and a second insulating film 43b (for example, one of an etch stop layer) are laminated on the entire surface including the upper surface of the transistor. Tantalum nitride film). The first interlayer insulating film 39 is formed on the second insulating film 43b. Connection holes having different depths are selectively formed in the first interlayer insulating film 39 up to the second insulating film 43b serving as an etch stop layer. Subsequently, the connection holes are formed so as to be continuous with the connection holes formed by selectively etching the first insulating film 43a and the second insulating film 43b with the same film thickness in the respective cells. Then, the connecting conductors 44 are buried in the respective connecting holes.

Next, the multilayer wiring layer 41 is formed by forming the wirings 40 [40a, 40b, and 40c]. In the present embodiment, the wiring 40 is made of three layers of metal M1 to M3 with the interlayer insulating film 39 interposed therebetween. It is formed to be connected to the respective connection conductors 44. The wiring 40 is formed of copper (Cu). In general, a barrier metal film that prevents Cu diffusion is covered with a respective copper wiring. Therefore, a top cover film of the copper wiring 40, a so-called protective film 42, is formed on the multilayer wiring layer 41. The first semiconductor substrate 31 including the pixel array 23 and the control circuit 24 as a semi-finished product is formed by a previously executed process.

On the other hand, as shown in FIG. 5, a semi-finished logic circuit 25 including a signal processing circuit that performs signal processing is formed in a region in which each of the wafer units of the second semiconductor substrate (semiconductor wafer) 45 is formed. That is, in the p-type semiconductor well region 46 on the surface of the semiconductor substrate (for example, a germanium substrate) 45, a plurality of MOS transistors forming a logic circuit are formed to be isolated by the device isolation region 50. Here, the MOS transistors Tr6, Tr7, and Tr8 are representative MOS transistors of a plurality of MOS transistors. The MOS transistors Tr6, Tr7, and Tr8 each include a pair of gate insulating films, a pair of source/drain regions 47, and a gate electrode 48 interposed therebetween. Logic circuit 25 can be configured in a CMOS transistor. The device isolation region 50 is formed in an STI structure by embedding an insulating film such as a SiO ₂ film in a trench formed in the substrate.

Next, a first interlayer insulating film 49 is formed on the surface of the semiconductor substrate 45, and then connection holes are formed in the interlayer insulating film 49 to form connection conductors 54 connected to the respective transistors. When forming the connection conductors 54 having different heights, a first insulating film 43a (such as a hafnium oxide film) and a second insulating film 43b (such as one of an etch stop layer) are laminated on the entire surface including the upper surface of the transistor. Tantalum nitride film) as explained above. The first interlayer insulating film 49 is formed on the second insulating film 43b. Connection holes having different depths are selectively formed in the first interlayer insulating film 39 up to the second insulating film 43b serving as an etch stop layer. Subsequently, the connection holes are formed so as to be continuous with the connection holes formed by selectively etching the first insulating film 43a and the second insulating film 43b with the same film thickness in the respective cells. Then, the connecting conductors 44 are buried in the respective connecting holes.

Next, the multilayer wiring layer 55 is formed by forming the wirings 53 [53a, 53b, and 53c]. In the present embodiment, the wiring 53 is made of three layers of metal M1 to M3 with the interlayer insulating film 49 interposed therebetween. It is formed to be connected to the respective connection conductors 54. The wiring 53 is formed of copper (Cu). As discussed above, a cap film of a copper wiring 53, a so-called protective film 56, is formed on the multilayer wiring layer 49. The second semiconductor substrate 45 including the logic circuit 25 is formed as a semi-finished product by a previously executed process.

Next, as shown in FIG. 6, the first semiconductor substrate 31 and the second semiconductor substrate 45 are bonded to each other such that the multilayer wiring layers 41 and 45 face each other. For example, the semiconductor substrates are bonded to each other by plasma welding or a bonding agent. In this example, the semiconductor substrates are bonded to each other by a bonding agent. When an adhesive is used, as shown in FIG. 7, an adhesive layer 58 is formed on one of the bonding surfaces of the first semiconductor substrate 31 and the second semiconductor substrate 45, and then the two semiconductor substrates are stacked and They are bonded to each other by means of an adhesive layer 58 interposed therebetween. That is, the first semiconductor substrate 31 and the second semiconductor substrate 45 are bonded to each other.

When the two semiconductor substrates are bonded to each other by plasma welding, although not illustrated, a plasma TEOS is formed on each of the bonding surfaces of the first semiconductor wafer 31 and the second semiconductor wafer 45. A film, a plasma SiN film, a SiON film (barrier film), a SiC film or the like. The bonding surface on which the film is formed is subjected to plasma treatment, stacked, and then subjected to an annealing treatment so that the two semiconductor substrates are bonded to each other. The bonding is preferably performed by a low temperature process at a temperature equal to or lower than one of 400 ° C, and one of the temperatures equal to or lower than 400 ° C has no effect on the wiring or the like.

Next, as shown in FIG. 8, the first semiconductor substrate 31 is thinned by grinding or polishing from the rear surface 31b of the first semiconductor substrate 31. This thinning is performed to face the photodiode (PD). After the thinning, a p-type semiconductor layer which prevents dark current is formed on the surface after the photodiode (PD). The thickness of the semiconductor substrate 31 is, for example, about 600 μm, but is thinned up to, for example, about 3 μm to about 5 μm. According to the related art, the thinning is performed by joining a separately prepared support substrate. However, in the present embodiment, the first semiconductor substrate 31 is thinned by using the second semiconductor substrate 45 including the logic circuit 25 as a supporting substrate. When the solid-state imaging element is configured as a back side illumination type solid-state imaging element, the rear surface 31b of the first semiconductor substrate 31 serves as a light incident surface.

Then, as shown in FIG. 9, in the bonding of the first semiconductor substrate 31 and the second semiconductor substrate 45 to each other, the entire first semiconductor wafer unit (that is, the partial semiconductor substrate 31) is used as a completed by completely removing. A semiconductor segment of one of the regions is formed to form a semiconductor removal region 52. The semiconductor removal region 52 is an entire region including a portion in which each of the connection wirings is connected to and adjacent to the layout wiring 40d corresponding to each vertical signal line of the pixel array, as shown in FIG. 15A. Show. In FIG. 15A, the semiconductor removal region 52 is formed vertically outside the pixel array 23.

Next, as shown in FIG. 10, a yttrium oxide (SiO ₂ ) film 58 and tantalum nitride are deposited from the inner surface of the semiconductor removal region 52 across the rear surface of the control circuit 24 (light incident surface) and the pixel array 23 ( One of the SiN) films 59 is laminated with an insulating film 61. The stacked insulating film 61 serves not only as a protective film of one of the semiconductor side surfaces of the semiconductor removal region 52 but also as an anti-reflection film of the pixel array 23.

Next, as shown in FIG. 11, in the semiconductor removal region 52, the through connection hole 62 of the connection pad 63 of one of the plurality of wiring layers 55 connected to the second semiconductor substrate 45 is connected to the via insulating film 61. The multilayer wiring layer 41 of the first semiconductor substrate 31 is penetrated. The through-connection hole 62 of this example reaches the second connection pad 63 electrically connected to the uppermost layer of the multilayer wiring layer (that is, the wiring 53d formed of the third-layer metal M13). The plurality of through-connection holes 62 are formed to correspond in number to the number of vertical signal lines of the pixel array 23. The wiring 53d formed of the third layer metal M13 connected to the second connection pad 63 serves as a wiring corresponding to one of the vertical signal lines. In this example, the second connection pad 63 is formed of the third layer metal M13 and is continuously formed in the laying wiring 53d corresponding to the vertical signal line.

Next, as shown in FIG. 12, a connection hole from the stacked insulating film 61 to the first connection pad 65 of the wiring 40 connected to the multilayer wiring layer 41 of the first semiconductor substrate 31 is formed in the semiconductor removal region 52. 64. In this example, the connection hole 64 is formed to reach the first connection pad 65 electrically connected to the wiring 40d formed of the third layer metal M3 of the multilayer wiring layer 41. A plurality of connection holes 64 are formed to correspond in number to the number of vertical signal lines of the pixel array 23. The wiring 40d formed of the third layer metal M3 connected to the first connection pad 65 serves as a wiring corresponding to one of the vertical signal lines. In this example, the first connection pads 65 are continuously formed in the laying wiring 40d formed of the third layer metal M3 and corresponding to the vertical signal.

Next, as shown in FIG. 13, a connection wiring 67 is formed to electrically connect the second connection pad 63 to the first connection pad 65. That is, a conductive film is formed on the entire rear surface of the first semiconductor substrate 31 to be buried in both the connection hole 62 and the connection hole 64, and then the connection wiring 67 is formed by etch back or patterning. The connection wiring 67 includes a connection conductor 68 and a through connection conductor 69. The connection conductor 68 is buried in the connection hole 64 and connected to the first connection pad 65. The through connection conductor 69 is buried in the through connection hole 62 and connected to the Two connection pads. The connection wiring 67 further includes a connection conductor 71 electrically connecting the connection conductor 68 to the through connection conductor 69 on the exposed bottom surface of the semiconductor removal region. The connecting conductor 68, the through connecting conductor 69, and the connecting conductor 71 are integrally formed of the same metal. The connection wiring 67 may be formed of a metal that can be patterned via a barrier metal (TiN or the like) such as tungsten (W), aluminum (Al), or gold (Au).

Next, as shown in FIG. 14, a light shielding film 72 is formed on a region in which light is required to be shielded. As illustrated in the diagram, the light shielding film 72 is formed on the control circuit 24, but the light shielding film 72 may be formed on the pixel transistor. The light shielding film 72 may be formed of a metal such as tungsten (W). A planarization film 73 is formed across the pixel array 23 to cover the light shielding film 72. A color filter 74 on a wafer (for example) of red (R), green (G), and blue (B) is formed on the planarization film 73 to correspond to respective pixels, and a color filter 74 is on the wafer. A wafer upper microlens 75 is formed thereon. In the first semiconductor substrate 31, the pixel array 23 and the control circuit 25 are formed as a finished product. The connection conductor 71 of the connection wiring 67 serves as an electrode pad exposed to the outside. In the second semiconductor substrate 45, the logic circuit 25 is formed as a finished product.

Next, the semiconductor substrates are divided into a plurality of wafers, and thus one of the targets of the back side illumination type solid-state imaging device 28 is obtained, as shown in FIG. The electrode pads formed by the connection conductors 71 of the connection wirings 67 of the solid-state imaging device 28 are connected to an external wiring by wire bonding.

According to the solid-state imaging element of the first embodiment and the method of manufacturing the same, the pixel array 23 and the control circuit 24 are formed in the first semiconductor wafer unit 22 and the logic circuit 25 that performs signal processing is formed in the second semiconductor wafer unit 26. In this manner, optimal processing techniques can be used for pixel array 23 and logic circuit 25 since pixel array functions and logic functions are implemented in different wafer units. Therefore, since the respective functions of the pixel array 23 and the logic circuit 25 can be sufficiently achieved, a solid-state imaging element having high performance can be provided.

In particular, in the present embodiment, a portion of the first semiconductor wafer unit 22, that is, a semiconductor segment in which the connection conductor and the region of the connection conductor are formed, is completely removed. Since the connection conductor 68 and the through connection conductor 69 are formed in the semiconductor removal region 52 in which the semiconductor segment has been removed, the parasitic capacitance between the semiconductor substrate 31 and the connection conductor 68 and the through connection conductor 69 can be reduced, whereby the parasitic capacitance between the semiconductor substrate 31 and the connection conductor 68 and the through connection conductor 69 can be reduced. A solid-state imaging element with higher performance is provided.

When the configuration shown in FIG. 2C is utilized, only the pixel array 23 that receives light can be formed in the first semiconductor wafer unit 22, and the control circuit 24 and the logic circuit 25 are separately formed and formed on the second semiconductor wafer unit. 26 in. Therefore, the optimum processing technique can be independently selected in the fabrication of the semiconductor wafer units 22 and 26 and the area of a product module can be reduced.

In the first embodiment, the first semiconductor substrate 31 including the pixel array 23 and the control circuit 24 and the second semiconductor substrate 45 including the logic circuit 25 are bonded to each other, and then the first semiconductor substrate is thinned. 31. That is, the second semiconductor substrate 45 is used as a support substrate of the first semiconductor substrate 31 when the first semiconductor substrate 31 is thinned. Therefore, components can be saved and manufacturing steps can be reduced.

In the present embodiment, since the first semiconductor substrate 31 is thinned and the through-connection holes 62 and the connection holes 64 are formed in the semiconductor removal region 52 in which the semiconductor segments are removed, the aspect ratio of the holes is reduced and The connection holes 62 and 64 can be formed with high precision. Therefore, it is possible to manufacture a high-performance solid-state imaging device with high precision.

3. Second embodiment Example of configuration of solid-state imaging components

Figure 16 is a diagram showing one of semiconductor elements (i.e., a MOS solid-state imaging device) according to a second embodiment of the present invention. The solid-state imaging device 78 according to the second embodiment has a configuration in which the stacked semiconductor wafer 27 is formed such that the first semiconductor wafer unit 22 including the pixel array 23 and the control circuit 24 and the second including the logic circuit 25 are formed The semiconductor wafer units 26 are bonded to each other. The first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are bonded to each other such that the multilayer wiring layers 41 and 55 face each other.

In the present embodiment, the semiconductor removal region 52 in which the semiconductor portion of a portion of the first semiconductor wafer unit 22 is completely removed is formed, and is formed from the inner surface of the semiconductor removal region 52 to the rear surface 31b of the semiconductor substrate 31. The insulating film 61 is stacked. A planarization insulating film 77 is formed in the semiconductor removal region 52 to be flush with the surface of the stacked insulating film 61 on the semiconductor substrate 31. The etching rate of the planarized insulating film 77 is different from the etching rate of the tantalum nitride film 59 on the surface of the stacked insulating film 61. For example, the planarized insulating film 77 is formed as an insulating film such as a hafnium oxide film.

The through-via flattening insulating film 77 forms a connection hole 64 and a through-connection hole 62 that reach the first connection pad 65 and the second connection pad 63. The connection wiring 67 connecting the first connection pad 65 and the second connection pad 63 is formed to pass through both of the connection holes 64 and 62. The connection wiring 67 includes a connection conductor 68 buried in the connection holes 64 and 62 and electrically connected to the first connection pad 65, a through connection conductor 69 electrically connected to the second connection pad 63, and an upper end of the electrical connection connection conductor 68. The connecting conductor 71 is connected to the upper end of the connecting conductor 69. The connection conductor 68, the through-connection conductor 69, and the connection conductor 71 are integrally formed of a metal. The connection conductor 71 is formed on the planarized insulating film 77.

The other configuration is the same as that explained in the first embodiment. The constituent elements of the constituent devices corresponding to FIG. 3 are given the same reference numerals, and the description thereof will not be repeated.

Example of a method of manufacturing a solid-state imaging element

17 through 24 are illustrations of one method of fabricating a solid state imaging element 78 in accordance with a second embodiment.

In Fig. 17, the configuration of the solid state imaging element 78 is the same as that set forth in the method of manufacturing the solid state imaging element 28 in accordance with the first embodiment set forth above with reference to Fig. 10. Since the steps up to FIG. 17 are the same as those from FIG. 4 to FIG. 10, the detailed description will not be repeated.

In the step of FIG. 17, the surface of the semiconductor removal region 52 is crossed from the rear surface of the control circuit 24 (light incident surface) and the pixel array 23 is deposited with a yttrium oxide (SiO ₂ ) film 58 of a tantalum nitride (SiN) film 59. The insulating film 61 is stacked.

Next, as shown in FIG. 18, an insulating film 77 such as a hafnium oxide film is stacked on the entire rear surface of the semiconductor substrate 31 to be buried in the semiconductor removal region 52.

Next, as shown in FIG. 19, the insulating film 77 is polished to a certain thickness by a chemical mechanical polishing (CMP) method.

Next, as shown in FIG. 20, the insulating film 77 is etched by a wet etching method using hydrofluoric acid until the tantalum nitride film 59, and the insulating film 77 is planarized to be flush with the tantalum nitride film 59. At this time, the tantalum nitride film 59 serves as an etch stop layer.

Next, as shown in FIG. 21, a second connection is formed in the semiconductor removal region 52 through the insulating film 77 and the multilayer wiring layer 41 and reaching the wiring 53d connected to the multilayer wiring layer 55 of the second semiconductor substrate 45. The connection hole 62 of the pad 63. In this example, as explained above, the connection hole 62 is formed to reach the second connection pad 63 electrically connected to the uppermost layer of the multilayer wiring layer 55 (that is, the wiring 53d formed of the third layer metal M13). The plurality of connection holes 62 are formed to correspond in number to the number of vertical signal lines of the pixel array 23. The wiring 53d formed of the third layer metal M13 connected to the second connection pad 63 serves as a wiring corresponding to one of the vertical signal lines. In this example, the second connection pads 63 are continuously formed in the laying wiring 53d formed of the third layer metal M13 and corresponding to the vertical signal lines.

Next, as shown in FIG. 22, a connection hole 64 from the insulating film 77 to the first connection pad 65 is formed in the semiconductor removal region 52. In this example, the connection hole 64 is formed to reach the first connection pad 65 electrically connected to the wiring 40d formed of the third layer metal M3 of the multilayer wiring layer 41. A plurality of connection holes 64 are formed to correspond in number to the number of vertical signal lines of the pixel array 23. The wiring 40d formed of the third layer metal M3 connected to the first connection pad 65 serves as a wiring corresponding to one of the vertical signal lines. In this example, the first connection pads 65 are continuously formed in the laying wiring 40d formed of the third layer metal M3 and corresponding to the vertical signal.

Next, as shown in FIG. 23, a connection wiring 67 is formed to electrically connect the second connection pad 63 to the first connection pad 65. That is, a conductive film is formed on the entire rear surface of the insulating film 77 and the first semiconductor substrate 31 to be buried in both the connection hole 62 and the connection hole 64, and then the connection wiring is formed by etch back or patterning. 67. The connection wiring 67 includes a connection conductor 68 and a through connection conductor 69. The connection conductor 68 is buried in the connection hole 64 and connected to the first connection pad 65. The through connection conductor 69 is buried in the through connection hole 62 and connected to the Two connection pads. The connection wiring 67 further includes a connection conductor 71 that electrically connects the connection conductor 68 to the through connection conductor 69 via the planarization insulating film 77. The connecting conductor 68, the through connecting conductor 69, and the connecting conductor 71 are integrally formed of the same metal to serve as a conductive film. The connection wiring 67 may be formed of a metal that can be patterned via a barrier metal (TiN or the like) such as tungsten (W), aluminum (Al), or gold (Au).

Next, as shown in FIG. 24, a light shielding film 72 is formed on a region in which light is required to be shielded. As illustrated in the diagram, the light shielding film 72 is formed on the control circuit 24, but the light shielding film 72 may be formed on the pixel transistor. The light shielding film 72 may be formed of a metal such as tungsten (W). A planarization film 73 is formed across the pixel array 23 to cover the light shielding film 72. A color filter 74 on a wafer (for example) of red (R), green (G), and blue (B) is formed on the planarization film 73 to correspond to respective pixels, and a color filter 74 is on the wafer. A wafer upper microlens 75 is formed thereon. In the first semiconductor substrate 31, the pixel array 23 and the control circuit 25 are formed as a finished product. The connection conductor 71 of the connection wiring 67 serves as an electrode pad exposed to the outside. In the second semiconductor substrate 45, the logic circuit 25 is formed as a finished product.

Next, the semiconductor substrates are divided into a plurality of wafers, and thus one of the targets of the back side illumination type solid-state imaging device 78 is obtained, as shown in FIG.

According to the solid-state imaging element 78 of the second embodiment and the method of manufacturing the same, a portion of the first semiconductor wafer unit 22 (that is, a semiconductor portion in which the connection conductor 68 and the through-connection conductor 69 are formed) is completely removed, and the insulation is to be insulated The film 77 is buried in the removed semiconductor removal region 52. Since the connection conductor 68 and the through-connection conductor 69 are buried in the connection hole 64 and the through-connection hole 62 formed in the insulating film 77, the connection conductors 68 and 69 are separated from the side surface of the semiconductor substrate 31 by the insulating film 77. Therefore, the parasitic capacitance between the semiconductor substrate 31 and the connection conductors 68 and 69 is reduced. Further, since the inner side of the semiconductor removal region 52 is buried in the insulating film 77, the surface of the semiconductor substrate 31 facing the side wall of the semiconductor removal region 52 can be mechanically and reliably protected in cooperation with the stacked insulating film 61. . Therefore, a solid-state imaging element having higher performance can be provided.

In the present embodiment, since the first semiconductor substrate 31 is thinned and the through-connection holes 62 and the connection holes 64 are formed, the aspect ratio of the holes is reduced and the connection holes 62 and 64 can be formed with high precision. Therefore, it is possible to manufacture a high-performance solid-state imaging device with high precision.

Although not otherwise illustrated, the same advantages as those of the first embodiment can be obtained.

4. Third Embodiment Example of configuration of solid-state imaging components

Figure 25 is a diagram showing one of semiconductor elements (i.e., a MOS solid-state imaging device) according to a third embodiment of the present invention. The solid-state imaging device 82 according to the third embodiment has a configuration in which the stacked semiconductor wafer 27 is formed such that the first semiconductor wafer unit 22 including the pixel array 23 and the control circuit 24 and the second including the logic circuit 25 are formed The semiconductor wafer units 26 are bonded to each other. The first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are bonded to each other such that the multilayer wiring layers 41 and 55 face each other.

In the present embodiment, the semiconductor removal region 52 in which the semiconductor portion of a portion of the first semiconductor wafer unit 22 is completely removed is formed and formed to extend from the inner surface of the semiconductor removal region 52 to the rear surface of the semiconductor substrate 31. The insulating film 61 is stacked. A planarization insulating film 77 which is flush with the surface of the stacked insulating film 61 on the semiconductor substrate 31 is formed in the semiconductor removal region 52, and is formed from the surface in a portion of the connection wiring 67 corresponding to the insulating film 77. One of the concave portions 81 having a certain depth. The etching rate of the planarized insulating film 77 is different from the etching rate of the tantalum nitride film 59 on the surface of the stacked insulating film 61. For example, the planarized insulating film 77 is formed as an insulating film such as a hafnium oxide film.

The connection hole 64 and the through connection hole 62 are formed to pass through the insulating film 77 under the recessed portion 81 to reach the first connection pad 65 and the second connection pad 63. The connection wiring 67 connecting the first connection pad 65 and the second connection pad 63 is formed to pass through both of the connection holes 64 and 62. The connection wiring 67 includes a connection conductor 68 buried in the connection holes 64 and 62 and electrically connected to the first connection pad 65, a through connection conductor 69 electrically connected to the second connection pad 63, and an upper end of the electrical connection connection conductor 68. The connecting conductor 71 is connected to the upper end of the connecting conductor 69. The connection conductor 68, the through-connection conductor 69, and the connection conductor 71 are integrally formed of a metal. The connection conductor 71 is buried in the recessed portion 81 of the insulating film 77 and the surface of the connection conductor 71 is formed to be flush with the surface of the planarization insulating film 77.

The other configuration is the same as that explained in the first embodiment. The constituent elements of the constituent devices corresponding to FIG. 3 are given the same reference numerals, and the description thereof will not be repeated.

Example of a method of manufacturing a solid-state imaging element

26 to 30 are diagrams showing a method of manufacturing the solid state imaging element 82 according to the third embodiment. In Fig. 26, the configuration of the solid state imaging element 82 is the same as that set forth in the method of manufacturing the solid state imaging element 78 in accordance with the second embodiment set forth above with reference to Fig. 20. Since the steps up to FIG. 26 are the same as those from FIGS. 4 to 10 and from FIGS. 17 to 20, detailed description will not be repeated.

In one step of FIG. 26, the insulating film 77 is stacked to be buried in the semiconductor removal region 52, and then the surface of the insulating film 77 is planarized by chemical mechanical polishing (CMP) and wet etching to be stacked. The surface of the insulating film 61 is flush.

Next, as shown in FIG. 27, a recessed portion 81 having a certain depth from the surface is formed in the surface of the insulating film 77 to correspond to a region in which the connection wiring 67 is formed.

Next, as shown in FIG. 28, the through-connection hole 62 penetrates the insulating film 77 and the multilayer wiring layer 41 under the recessed portion 81 to reach the second connection pad 63. In this example, as explained above, the connection hole 62 is formed to reach the uppermost layer metal (ie, the wiring 53d of the third layer metal M13) electrically connected to the multilayer wiring layer 55 of the second semiconductor wafer unit 26. Two connection pads 63. The plurality of connection holes 62 are formed to correspond in number to the number of vertical signal lines of the pixel array 23. The wiring 53d connected to the second connection pad 63 serves as a wiring to correspond to one of the vertical signal lines. In this example, the second connection pads 63 are continuously formed in the laying wiring 53d formed of the third layer metal M13 and corresponding to the vertical signal lines.

Further, an insulating film 77 under the recessed portion 81 is formed in the semiconductor removal region 52 to reach the connection hole 64 of the first connection pad 65. In this example, the connection hole 64 is formed to reach the first connection pad 65 electrically connected to the wiring 40d formed of the third layer metal M3 of the multilayer wiring layer 41 of the first semiconductor wafer unit 22. A plurality of connection holes 64 are formed to correspond in number to the number of vertical signal lines of the pixel array 23. The wiring 40c of the third layer metal connected to the first connection pad 65 serves as a wiring corresponding to one of the vertical signal lines. In this example, the first connection pads 65 are continuously formed in the laying wiring 40d formed of the third layer metal M13 and corresponding to the vertical signal.

Next, as shown in FIG. 29, a connection wiring 67 is formed to electrically connect the second connection pad 63 to the first connection pad 65. That is, a conductive film is formed on the entire rear surface of the insulating film 77 and the first semiconductor substrate 31 to be buried in the recessed portion 81 and the connection hole 62 and the connection hole 64, and then etched back or patterned. The connection wiring 67 is formed. The connection wiring 67 includes a connection conductor 68 and a through connection conductor 69. The connection conductor 68 is buried in the connection hole 64 and connected to the first connection pad 65. The through connection conductor 69 is buried in the through connection hole 62 and connected to the Two connection pads. The connection wiring 67 further includes a connection conductor 71 that electrically connects the connection conductor 68 to the through connection conductor 69. The connection conductor 71 is buried in the recessed portion 81 and planarized to be flush with the surface of the insulating film 77. The connecting conductor 68, the through connecting conductor 69, and the connecting conductor 71 are integrally formed of the same metal to serve as a conductive film. Since the connection wiring 67 is formed by etch back, the connection wiring 67 may be formed of copper (Cu). The connection wiring 67 may be formed of a metal such as tungsten (W), aluminum (Al), or gold (Au) via a barrier metal (TiN or the like).

Next, as shown in FIG. 30, a light shielding film 72 is formed on a region in which light is required to be shielded. As illustrated in the diagram, the light shielding film 72 is formed on the control circuit 24, but the light shielding film 72 may be formed on the pixel transistor. The light shielding film 72 may be formed of a metal such as tungsten (W). A planarization film 73 is formed across the pixel array 23 to cover the light shielding film 72. A color filter 74 on a wafer (for example) of red (R), green (G), and blue (B) is formed on the planarization film 73 to correspond to respective pixels, and a color filter 74 is on the wafer. A wafer upper microlens 75 is formed thereon. In the first semiconductor substrate 31, the pixel array 23 and the control circuit 25 are formed as a finished product. The connection conductor 71 of the connection wiring 67 serves as an electrode pad exposed to the outside. In the second semiconductor substrate 45, the logic circuit 25 is formed as a finished product.

Next, the semiconductor substrates are divided into a plurality of wafers, and thus one of the targets of the back side illumination type solid state imaging device device 82 is obtained, as shown in FIG.

According to the solid-state imaging element of the third embodiment and the method of manufacturing the same, a portion of the first semiconductor wafer unit 22 (that is, a semiconductor portion in which the connection conductor 68 and the through-connection conductor 69 are formed) is completely removed, and the insulating film is provided 77 is buried in the removed semiconductor removal area 52. The recessed portion 81 is formed in the insulating film 77, and the connection conductor 68 and the through-connection conductor 69 are buried in the connection hole 64 and the through-connection hole 62 formed in the insulating film 77 under the recessed portion 81. Since the connection conductors 68 and 69 are away from the side surface of the semiconductor substrate 31 by the insulating film 77, the parasitic capacitance between the semiconductor substrate 31 and the connection conductors 68 and 69 is reduced. Further, the inner side of the semiconductor removal region 52 is buried in the insulating film 77, so that the surface of the semiconductor substrate 31 facing the side wall of the semiconductor removal region 52 can be mechanically and reliably protected in cooperation with the stacked insulating film 61. Therefore, a solid-state imaging element having higher performance can be provided.

Since the connection conductor 71 is buried in the concave portion 81 of the insulating film 77, and the connection conductor 71 is planarized to be flush with the surface of the insulating film 77, a solid-state imaging device having a small surface step can be formed.

In the third embodiment, since the first semiconductor substrate 31 is thinned, the recessed portion 81 is additionally formed in the insulating film 77, and the through-connection hole 62 and the connection hole 64 are formed, thereby reducing the aspect ratio of the hole and The connection holes 62 and 64 are formed with high precision. Therefore, it is possible to manufacture a high-performance solid-state imaging device with high precision.

Although not otherwise illustrated, the same advantages as those of the first embodiment can be obtained.

In the second and third embodiments set forth above, the configuration shown in Figure 2C can be utilized.

In accordance with the embodiments set forth above, the two semiconductor wafers 22 and 26 are joined to each other. Further, according to the solid-state imaging element of the embodiment of the present invention, two or more semiconductor wafer units may be bonded to each other. Even in two or more semiconductor wafer units bonded to each other, the configuration set forth above can be applied, in which the first semiconductor wafer unit 22 including the pixel array 23 and the logic circuit 25 are completely removed. A semiconductor segment in the connection portion between the semiconductor wafer units 26.

In a configuration in which the semiconductor wafer units described above are bonded to each other, a parasitic capacitance such as a ground capacitance adjacent to the coupling capacitor occurs. In particular, since the surface area of the connecting conductor 68 and the through connecting conductor 69 is large, it is preferable to reduce the adjacent coupling capacitance in the gap between the connecting conductors adjacent to the row or in the gap between the adjacent wirings. Here, the gap between the connection conductors means a gap between a pair of adjacent connection conductors when the connection conductor 68 and the through connection conductor 69 are set as a pair of connection conductors. On the other hand, since the area and spacing of the first connection pads 65 and the area and spacing of the second connection pads 63 are larger than one pixel area and one pixel pitch, a practically usable arrangement is preferred.

Next, a reduction in the adjacent coupling capacitance of the pair and an actual usable arrangement will be described in accordance with an embodiment of the present invention.

5. Fourth embodiment Example of configuration of solid-state imaging components

31 to 35 are diagrams showing a semiconductor element (i.e., a MOS solid-state imaging element) according to a fourth embodiment. In particular, FIGS. 31 to 35 show only an arrangement including one wiring connection portion of a connection pad that electrically connects the first semiconductor wafer unit and the second semiconductor wafer unit to each other. Figure 31 is a plan view of a connection pad array. Figure 32 is a cross-sectional view taken along line XXXII-XXXII of Figure 31. Figure 33 is a cross-sectional view taken along line XXXIII-XXXIII of Figure 31. 34 and 35 are exploded plan views of Fig. 31.

In the solid-state imaging element 84 according to the fourth embodiment, as described above, the two semiconductor wafer units 22 and 26 are bonded to each other, the semiconductor portion of a portion of the first semiconductor wafer unit 22 is removed, and is moved via the semiconductor. The connection wiring 67 in the division area 52 connects the two semiconductor wafer units 22 and 26 to each other. In the present embodiment, since several configurations of the above-described embodiments are applied to other configurations than the arrangement of the wiring connection sections, detailed description thereof will not be repeated.

In the fourth embodiment, the wirings 40 [40a, 40b, 40c, and 40d] of the multilayer wiring 41 in the first semiconductor wafer unit 22 are formed in a plurality of layers, in this example, four layers of metal M1 to M4. The first connection pad 65 is formed of the first layer metal M1, and the laying wiring 40d corresponding to the vertical signal line is formed of a metal after the second layer. In the present embodiment, the laying wiring 40d corresponding to the vertical signal line is formed of the fourth layer metal M4. The wirings 53 [53a, 53b, 53c, and 53d] of the multilayer wiring layer 55 in the second semiconductor wafer unit 26 are formed of a plurality of layers, in this example, four layers of metal M11 to M14. The second connection pad 63 is formed of a layer (such as a third layer metal or a fourth layer metal) behind the second layer of metal, in this embodiment, the fourth layer of metal M14 of the uppermost layer. The laying wiring 53d corresponding to the vertical signal line is formed by one metal (in this example, the first layer metal M11) under the metal M14 of the connection pad 63. In the first semiconductor wafer unit 22, the first connection pad 65 formed of the first layer of metal is electrically connected to the fourth layer metal via the via conductor 86 and the connection portion 85 formed of the second layer metal and the third layer metal. The wiring 40d is laid. In the second semiconductor wafer unit 26, the second connection pads 63 formed of the fourth layer of metal are electrically connected to the first layer of metal via the via conductors 88 and the connection portions 87 formed of the third layer of metal and the second layer of metal. The wiring 53d is laid.

Considering the positional deviation of the bonding of the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26, the second connection pad 63 has an area larger than the area of the first connection pad 65. One pair of a first connection pad 65 and a second connection pad 63 are collectively referred to as a connection pad pair 89.

In general, vertical signal lines are placed at each pixel pitch. However, when the pixel pitch is minute, the connection pad pair 89 is relatively larger than the pixel pitch and thus it is difficult to place the wiring. Moreover, since the vertical signal lines are densely arranged, the adjacent coupling capacitance between the vertical signal lines increases and thus a disadvantage occurs. In the present embodiment, one of the connection wiring and the vertical signal line is arranged to prevent this problem. The grounding capacitance is preferably 20 fF or less in one vertical signal line, one connecting conductor or one through connecting conductor. Further, the adjacent coupling capacitor is preferably about 1/10 or less of the ground capacitance, that is, 2 fF or less to avoid a smear phenomenon.

In a plan view, the first connection pad 65 and the second connection pad 63 have an octagonal shape in plan view, and preferably have a regular octagonal shape. The first connection pads and the second connection pads forming a connection pad pair 89 are arranged in a horizontal direction. A plurality of connection pad pairs 89 are arranged in the horizontal direction along which the respective routing wires 40d and 53d are arranged. In this example, four stages of the connection pads 89 are arranged in a vertical direction. That is, the first connection pad 65 and the second connection pad 63 having a regular octagonal shape are alternately arranged in the wiring connection portion between the semiconductor wafer units 22 and 26 in the horizontal direction and the vertical direction. Here, a connection pad array 91 is formed such that a plurality of connection pad pairs 89 are arranged in the horizontal direction and four stages of the connection pads 89 are disposed in the vertical direction. In the following, an octagonal shape will be defined. In some cases, the octagonal first connection pad 65 integrally has a portion protrudingly projecting the protruding portion 65a to supply a connection with the laying wiring 40d (see FIG. 32). In this case, since the degree of the projection is small in consideration of the entire octagonal shape, the projection is incorporated into the category of the octagon.

For example, in a plan view, in the connection pad array 91, the first connection pads 65 and the second connection pads 63 are closely arranged. The first connection pad 65 and the second connection pad 63 may partially overlap each other. The connection conductor 68 and the through connection conductor 69 are respectively connected to the first connection pad 65 and the second connection pad 63, and the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are connected to each other via the connection including the connection conductors 68 and 69. The connection wirings 67 of the connection conductors 71 are electrically connected to each other. The connecting conductor 68 and the through connecting conductor 69 may be formed to have a cross section of the same octagonal shape as the planar surfaces of the corresponding connecting pads 65 and 63. In this example, the connection wiring 67 is formed in the same manner as in the third embodiment. That is, the insulating film 77 is buried in the semiconductor removal region 52, and the connection conductor 65 and the through-connection conductor 63 are formed to penetrate the insulating film 77, and the connection conductor 71 is planarized so that the surface of the connection conductor 71 is The surface of the insulating film 77 is flush.

In the present embodiment, the routing wires 40d and 53d corresponding to the vertical signal lines of the four rows are respectively connected to the first connection pads 65 and the second connection pads 63 of the four stages of the connection pad pair 89. In the first semiconductor wafer unit 22, the first connection pads 65 are formed of a first layer of metal M1, and each of the application wirings 40d is formed of another layer of metal (in this example, a fourth layer of metal M4). Therefore, since the laying wiring 40d can be disposed to straddle under the first connection pad 65, a distance between the adjacent laying wirings 40d can be enlarged. Also, in the second semiconductor wafer unit 26, the second connection pads 63 are formed of the fourth layer metal M14 and each of the laying wirings 53d is formed of another layer of metal (in this example, the first layer metal M11). Therefore, since the laying wiring 53d can be disposed to straddle under the second connection pad 63, a distance between the adjacent laying wirings 53d can be enlarged.

In the present embodiment, the arrangement is implemented such that a vertical signal line corresponding to a plurality of rows of a plurality of stages of the connection pad pair 89 in the vertical direction is disposed in a pitch P of the pair of connection pads 89 in the horizontal direction. In Fig. 31, the arrangement is implemented such that the routing wiring 40d which is a vertical signal line corresponding to four rows of four stages of connection pads 89 in the vertical direction is disposed in a pitch P of the connection pad pair 89. And 53d.

In the solid-state imaging element 84 according to the fourth embodiment, the connection pad array 91 is formed such that the planar surface shapes of the first connection pad 65 and the second connection pad 63 each have an octagonal shape and the first connection pad 65 and the The two connection pads 63 are densely arranged alternately in the horizontal direction and the vertical direction. That is, the dense connection pad array 91 is formed to be located in the wiring connection portion between the two semiconductor wafer units 22 and 26. Since the wirings 40d and 53d which are the vertical signal lines of the four rows are connected to the four stages of the connection pad pair 89 of the connection pad array 91, the gap between the adjacent wirings 40d and the gap between the laying wirings 53d can be Expanded to thereby reduce the adjacent coupling capacitance. In addition, since the insulating film 77 is present between adjacent pairs of connecting conductors, the adjacent coupling capacitance between the pair of connection pads can also be reduced.

Since the connection conductor 68 is connected to the connection pad 65 formed of the first layer metal M1 in the first semiconductor wafer unit 22, the depth of the connection hole is shortened and thus the connection hole is easily handled, and further, the connection conductor 68 is easily buried. .

In the pair of connection pads 89, the area of the connection pads 63 in the second semiconductor wafer unit 26 is larger than the area of the connection pads 65 of the first semiconductor wafer unit 22. The positions of the connection holes 64 and the connection pads 65 in the first semiconductor wafer unit 22 can be precisely matched to each other with reference to the alignment marks formed in the first semiconductor wafer unit 22. On the other hand, when the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are joined to each other, there is an anxiety that a deviation may occur in the bonding. However, since the area of the connection pad 63 is large, the through connection hole 62 and the connection pad 63 can be matched with each other. Therefore, as explained above, the connection between the connection pads 65 and 63 and the connection conductor 64 and the through-connection conductor 69 can be achieved even when the position at which the bonding occurs is deviated.

Since the two rows and four stages of the connection pad pair 89 are alternately arranged in the vertical direction, the direction of the larger connection pads 63 and the smaller connection pads 65, and the connection pads 63 and 65 can be densely arranged. Therefore, even when the pixel pitch is minute due to miniaturization of the pixels, the laying wiring can be laid.

Compared with the configuration in which one of the first connection pad 65 and the second connection pad 63 is disposed in the vertical direction, the first connection pad 65 and the second connection pad 63 are disposed in the horizontal direction. In the state, one of the wiring resistance differences is reduced due to a difference in the wiring length of the four rows of wiring.

The area and spacing of the connection pads 65 and 63 are larger than the area and spacing of the pixels. However, since the wirings 40d and 53d can be laid by the arrangement in which the connection pads 65 and 63 are formed, it is possible to provide a solid-state imaging element having high performance.

In the fourth embodiment, even when the configurations of the connection wirings 67 of the first embodiment and the second embodiment are utilized, the adjacent coupling capacitance can be similarly reduced.

In the fourth embodiment, the same advantages as those of the first to third embodiments can be obtained.

6. Fifth embodiment Configuration example of solid state imaging device

Figure 36 is a diagram showing one of a semiconductor element, i.e., a MOS solid-state imaging element according to a fifth embodiment, in accordance with an embodiment of the present invention. In particular, FIG. 36 shows only the arrangement of one of the connection pads 65 and 63 including the connection pads 65 and 63 that electrically connect the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 to each other.

In the solid-state imaging element 93 according to the fifth embodiment, as explained above, the two semiconductor wafer units 22 and 26 are bonded to each other, the semiconductor portion of a portion of the first semiconductor wafer unit 22 is removed, and is moved via the semiconductor. The connection wiring 67 in the division area 52 connects the semiconductor wafer units 22 and 26 to each other. In the present embodiment, since a plurality of configurations of the above-described embodiments are applied to other configurations than the arrangement of the wiring connection sections, detailed description thereof will not be repeated.

In the fifth embodiment, the connection pad arrays 91A and 91B are disposed while being external, facing each other with the pixel array 23 interposed therebetween in the vertical direction. The laying wirings 40d and 53d corresponding to the vertical signal lines are alternately connected to the connection pad arrays 91A and 91B. In the present embodiment, for example, as in FIG. 31, the pair of connection pads 89 (where the first connection pad 65 and the second connection pad 63 are arranged in the horizontal direction) are horizontally arranged in plural stages. Formal configuration (two levels in this example). For example, the connection pad pairs 89 of the connection pad arrays 91A and 91B are densely arranged. The laying wiring pairs 40d and 53d are alternately connected to the two stages of the connection pad pair 89 of the connection pad arrays 91A and 91B in two rows. Both of the connection pad arrays 91A and 91B are formed in the semiconductor removal regions 52a and 52b shown in Fig. 15B, respectively.

In Fig. 36, the planar surfaces of the connection pads 65 and 63 have an octagonal shape and preferably have a regular octagonal shape. However, since the gap between the wirings can be enlarged, the planar surface of the connection pad can have a rectangular shape or a hexagonal shape (preferably a regular hexagonal shape). In the present embodiment, as explained below, the pair of connection pads 89 can be adapted to one in which (in which the first connection pad 65 and the second connection pad 63) are connected to each other in a vertical direction.

In the solid-state imaging element 93 according to the fifth embodiment, the connection pad arrays 91A and 91B are configured with a pixel array 23 interposed therebetween, and the laying wirings corresponding to the vertical signal lines are alternately connected to each of the plurality of lines (In this example, every two rows) two stages of the connection pad pair 89 of the pad arrays 91A and 91B are connected. In this configuration, it is not necessary to forcibly narrow the gap between the adjacent laying wirings 40d and the gap between the adjacent laying wirings 53d. In other words, the gap between the adjacent laying wirings 40d and the gap between the adjacent laying wirings 53d can be enlarged in a sufficient space. Therefore, the adjacent coupling capacitance can be reduced. Since the difference in wiring length between the laid wirings is reduced, the wiring resistance difference can be further reduced.

The area and spacing of the connection pads 65 and 63 are larger than the area and spacing of the pixels. However, since the wirings 40d and 53d can be laid by the arrangement in which the connection pads are formed, it is possible to provide a solid-state imaging element having high performance.

In the fifth embodiment, even when the configurations of the connection wirings of the first embodiment, the second embodiment, and the third embodiment are utilized, the adjacent coupling capacitance can be similarly reduced.

In the fifth embodiment, the same advantages as those of the first to third embodiments can be obtained.

7. Sixth embodiment Example of configuration of solid-state imaging components

37 and 38 are diagrams showing a semiconductor element (i.e., a MOS solid-state imaging element) according to a sixth embodiment. In particular, FIGS. 37 and 38 show only an arrangement including one of the connection pads 65 and 63 of the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 electrically connected to each other.

In the solid-state imaging element 95 according to the sixth embodiment, as explained above, the two semiconductor wafer units 22 and 26 are bonded to each other, the semiconductor portion of a portion of the first semiconductor wafer unit 22 is removed, and moved via the semiconductor The connection wiring 67 in the division area 52 connects the two semiconductor wafer units 22 and 26 to each other. In the present embodiment, since several configurations of the above-described embodiments are applied to other configurations than the arrangement of the wiring connection sections, detailed description thereof will not be repeated.

In the sixth embodiment, for example, the connection pad array 91 is formed such that the first connection pads 65 and the second connection pads 63 having the same octagonal shape as the octagonal shape of FIG. 31 are in the vertical direction and Alternately arranged in the horizontal direction. The four rows of routing wires 40d and 53d are connected to the four stages of the pad pair 89 of the pad array 91. The first connection pad 65 in the first semiconductor wafer unit 22 is formed of a first layer of metal M1 and the laying wiring 40d connected to the connection pad 65 is formed of a fourth layer of metal M4. The second connection pad 63 in the second semiconductor wafer unit 26 is formed of a fourth layer of metal M14, and the laying wiring 53d connected to the connection pad 63 is formed of the first layer metal M11.

The laying wiring 40d in the first semiconductor wafer unit 22 is disposed to straddle under the unconnected first connection pad 65. Since the area of the connection pad 65 is relatively large, there is a concern that a coupling capacitance may occur between the connection pad 65 and the laying wiring 40d having a different potential and crossing the connection pad 65. Therefore, in the present embodiment, a shield wiring 96 formed of a layer of metal interposed between the first connection pad 65 and the laying wiring 40d is formed between the first connection pad 65 and the laying wiring 40d. That is, a shield wiring 96 formed of a second or third layer metal (in this example, the second layer metal M2) is formed between the first connection pad 65 and the laying wiring 40d. For example, in some cases, as shown in FIG. 38, since the three laying wirings 40d span under the first connection pads 65, the shield wirings 96 are continuously formed into four stages up to the connection pad pair 89. To have a width corresponding to one of the widths of the connection pads 65.

The laying wiring 53d in the second semiconductor wafer unit 26 is disposed to straddle under the unconnected second connection pad 63. Since the area of the second connection pad 63 is also relatively large, there is a concern that a coupling capacitance may occur between the connection pad 63 and the laying wiring 53d having a different potential and crossing the connection pad 63. Therefore, a shield wiring formed of a layer of metal interposed between the second connection pad 63 and the laying wiring 53d is formed between the second connection pad 63 and the laying wiring 53d. That is, a shield wiring formed of a second metal layer or a third layer metal (in this example, the third layer metal M13) is formed between the second connection pad 63 and the laying wiring 53d. For example, in some cases, since the three laying wirings 53d span under the second connection pads 63, the shield wirings are continuously formed up to four stages of the connection pad pair 89 to have a width corresponding to the connection pads 63. One width.

In the solid-state imaging element according to the sixth embodiment, the connection pads 65 having different potentials are prevented from being laid by the shield wiring 96 disposed between the first connection pad 65 and the laying wiring 40d spanning under the connection pad 65. A coupling capacitance occurs between the wirings 40d. Further, the coupling capacitance between the connection pads 63 having different potentials and the laying wiring 53d is prevented by the shield wiring disposed between the second connection pads 63 and the laying wirings 53d crossing under the connection pads 63. Therefore, a solid-state imaging element having higher performance can be realized.

In the sixth embodiment, the advantage of reducing the parasitic capacitance can be obtained as explained in the first to third embodiments.

In the sixth embodiment, this advantage can be obtained from the shield wiring 96 regardless of the shape of the planar surface of the connection pad 65 or the arrangement of the connection pads 65.

8. Seventh embodiment Example of configuration of solid-state imaging components

Figure 39 is a diagram showing one of the semiconductor elements, i.e., one of the MOS solid-state imaging elements according to an embodiment of the present invention, in accordance with an embodiment of the present invention. In particular, FIG. 39 shows only the arrangement of one of the connection pads 65 and 63 including the connection pads 65 and 63 that electrically connect the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 to each other.

In the solid-state imaging element 97 according to the seventh embodiment, as described above, the two semiconductor wafer units 22 and 26 are bonded to each other, the semiconductor portion of a portion of the first semiconductor wafer unit 22 is removed, and is moved via the semiconductor. The connection wiring 67 in the division area 52 connects the two semiconductor wafer units 22 and 26 to each other. In the present embodiment, since several configurations of the above-described embodiments are applied to other configurations than the arrangement of the wiring connection sections, detailed description thereof will not be repeated.

In the seventh embodiment, the first connection pad 65 and the second connection pad 63 are disposed in one of the vertical directions (the so-called longitudinal direction) along which the laying wirings 40d and 53d corresponding to the vertical signal lines extend. A connection pad array 98 is formed such that a plurality of connection pad pairs 99 are arranged in the horizontal direction, wherein the laying wirings 40d and 53d are arranged in a plurality of stages (three stages in this example) in the vertical direction.

For example, as explained in the fourth embodiment, the first connection pad 65 and the second connection pad 63 have an octagonal shape in a plan view, and preferably have a regular octagonal shape. The first connection pad 65 and the second connection pad 63 are electrically connected to each other via a connection wiring 67 including a connection conductor 68, a through connection conductor 69, and a connection conductor 71.

In the first semiconductor wafer unit 22, the wiring 40 of the multilayer wiring layer 41 may be formed of a plurality of layers (for example, four layers of metal M1 to M4). At this time, the first connection pad 65 is preferably formed of the first layer metal M1, and the laying wiring 40d connected to the connection pad 65 is preferably formed of the fourth layer metal M4. The embodiment of the present invention is not limited thereto, and the first connection pad 65 and the laying wiring 40d may be any layer of metal.

In the second semiconductor wafer unit 26, the wiring 53 of the multilayer wiring layer 55 may be formed of a plurality of layers (for example, four layers of metal M11 to M14). At this time, the second connection pad 63 is preferably formed of the fourth layer metal M14, and the laying wiring 53d connected to the connection pad 63 is preferably formed of the first layer metal M11. The embodiment of the present invention is not limited thereto, and the second connection pad 63 and the laying wiring 53d may be any layer of metal. The routing wires 40d and 53d are connected to three stages of the pad pair 99 of the connection pad array 98 every three rows.

In the solid-state imaging element 97 according to the seventh embodiment, the wirings 40d and 53d can be laid by forming the connection pad array 98, in which the pad pair 99 is connected (the first connection pad 65 and the second The connection pads 63 are arranged in the vertical direction) in a plurality of stages. In particular, since the wirings 40d and 53d can be laid even in the case where the connection pads 65 and 63 have an area larger than the pixel area, a solid-state imaging element having high performance can be provided. When the laying wirings 40d and 53d are disposed to cross the connection pads 65 and 63, respectively, a sufficient space can be enlarged to enlarge the gap between the adjacent laying wirings. Therefore, the adjacent coupling capacitance occurring in the gap of the laying wiring can be reduced.

In the seventh embodiment, even when the configurations of the connection wirings of the first embodiment, the second embodiment, and the third embodiment are utilized, the adjacent coupling capacitance can be similarly reduced.

In the seventh embodiment, the same advantages as those of the first to third embodiments can be obtained.

In the example set forth above, the planar surfaces of the connection pads 65 and 63 have an octagonal shape, but may have a rectangular shape or a hexagonal shape (preferably a regular hexagonal shape) or a circular shape. Shape one of the polygonal shapes. The cross-sectional shape of the connecting conductor 68 and the through-connecting conductor 69 may be the same as the shape of the planar surfaces of the connection pads 65 and 63. The shape of the planar surface of the connection pads 65 and 63 and the cross-sectional shape of the connection conductor 68 and the through-connection conductor 69 may be different from each other.

In the solid-state imaging element according to the embodiment explained above, the signal charge is set to electrons, the first conductivity type is set to p-type, and the second conductivity type is set to n-type. The signal charge can be set to a hole in the solid state imaging element. In this case, the conductivity type of the semiconductor substrate and the semiconductor well region or the semiconductor region is reversed, and thus the n-type is set to the first conductivity type and the p-type is set to the second conductivity type. An n-channel transistor and a p-channel transistor can also be applied to the MOS transistor in the logic circuit.

9. Eighth embodiment Configuration example of semiconductor components

Figure 40 is a diagram showing one of semiconductor elements in accordance with an eighth embodiment of the present invention. The semiconductor element 131 according to the eighth embodiment includes a stacked semiconductor wafer 100 in which a first semiconductor wafer unit 101 and a second semiconductor wafer unit 116 are bonded to each other. A first semiconductor integrated circuit and a multilayer wiring layer are formed in the first semiconductor wafer unit 101. A second semiconductor integrated circuit and a multilayer wiring layer are formed in the second semiconductor wafer unit 116. The first semiconductor wafer unit 101 and the second semiconductor wafer unit 116 are bonded to each other such that the multilayer wiring layers face each other. In this example, the semiconductor wafer units are bonded via a protective film 114 and 127 by an adhesive layer 129. Alternatively, the semiconductor wafer units can be bonded to each other by plasma welding.

In the present embodiment, one of the semiconductor segments of one of the first semiconductor wafer units 101 is completely removed to form the semiconductor removal region 52. In the semiconductor removal region 52, a connection wiring 67 is formed to connect the first semiconductor wafer unit 101 to the second semiconductor wafer unit 116. The semiconductor removal region 52 is an entire region including a portion of each of the connection wirings 67 in which the semiconductor integrated circuits are formed and formed in, for example, a peripheral portion of the first semiconductor wafer unit 101.

In the first semiconductor wafer unit 101, a first semiconductor integrated circuit (in this example, the logic circuit 102) is formed in the thinned first semiconductor substrate 103. That is, a plurality of MOS transistors Tr11, Tr12, and Tr13 are formed in one of the semiconductor well regions 104 formed in a semiconductor substrate (for example, a germanium substrate) 103. The MOS transistors Tr11 to Tr13 each include a source/drain region 105 and a gate electrode 106 formed with a gate insulating film interposed therebetween. The MOS transistors Tr11 to Tr13 are isolated by a device isolation region 107.

Representative MOS transistors Tr11 to Tr13 are illustrated. Logic circuit 102 can be formed by a CMOS transistor. Therefore, the plurality of MOS transistors can be configured as an n-channel MOS transistor or a p-channel MOS transistor. Therefore, when an n-channel MOS transistor is formed, a source/drain region is formed in the p-type semiconductor well region. When a p-channel MOS transistor is formed, a p-type source/drain region is formed in the n-type semiconductor well region.

A plurality of wiring layers 111 are formed on the semiconductor substrate 103, and a plurality of layers in which an interlayer insulating film 108 is interposed therebetween are stacked in the multilayer wiring layer. In this example, a plurality of wirings 109 formed of three layers of metal are formed. . The wiring 109 can be formed by, for example, a Cu wiring. The MOS transistors Tr11 to Tr13 are connected to each other via the first layer wiring 109 and the connection conductor 112. Further, the three-layer wirings 109 are connected to each other via a connection conductor.

In the second semiconductor wafer unit 116, a second semiconductor integrated circuit (in this example, the integrated circuit 117) is formed in the second semiconductor substrate 118. That is, a plurality of MOS transistors Tr21, Tr22, and Tr23 are formed in one of the semiconductor well regions 119 formed in a semiconductor substrate (for example, a substrate) 118. The MOS transistors Tr21 to Tr23 each include a source/drain region 121 and a gate electrode 122 which are formed with a gate insulating film interposed therebetween. The MOS transistors Tr21 to Tr23 are isolated by a device isolation region 123.

Representative MOS transistors Tr21 to Tr23 are illustrated. Logic circuit 117 can be formed by a CMOS transistor. Therefore, the plurality of MOS transistors can be configured as an n-channel MOS transistor or a p-channel MOS transistor. Therefore, when an n-channel MOS transistor is formed, a source/drain region is formed in the p-type semiconductor well region. When a p-channel MOS transistor is formed, a p-type source/drain region is formed in the n-type semiconductor well region.

A plurality of wiring layers 126 are formed on the semiconductor substrate 118, and a plurality of layers in which an interlayer insulating film 124 is interposed therebetween are stacked in the multilayer wiring layer. In this example, a plurality of wirings 125 formed of three layers of metal are formed. . The wiring 125 may be formed of, for example, a Cu wiring. The MOS transistors Tr21 to Tr23 are connected to each other via the first layer wiring 125 and the connection conductor 120. Further, the three-layer wirings 125 are connected to each other via the connection conductors 120. The semiconductor substrate 118 of the second wafer unit 116 also serves as a support substrate for one of the thinned first semiconductor wafer units 101.

For example, instead of the logic circuit 102, a semiconductor memory circuit can be used as the first semiconductor integrated circuit. In this case, a logic circuit 117 serving as a second semiconductor integrated circuit is provided to perform signal processing of the semiconductor memory circuit.

In the semiconductor removal region 52, the entire first semiconductor substrate 118 is removed by, for example, etching. One of the stacked insulating films 61 is formed by, for example, a yttrium oxide (SiO ₂ ) film 58 and a tantalum nitride (SiN) film 59 to extend from the bottom surface and the side surface of the semiconductor removal region 52 to the semiconductor substrate 118. The surface is formed. The stacked insulating film 61 protects the surface of the semiconductor substrate 118 and the semiconductor substrate 118 exposed toward the side surface of the semiconductor removal region 52.

In the semiconductor removal region 52, a connection hole 64 is formed to extend from the tantalum nitride film 59 to one of the plurality of wiring layers 111 electrically connected to the first semiconductor wafer unit 101 (in this example, by the third One of the first connection pads 65 of the laying wiring 109d) formed of the layer metal. Further, a through connection hole 62 is formed to penetrate the first semiconductor wafer unit 101 and reach one of the plurality of wiring layers 126 electrically connected to the second semiconductor wafer unit 116 (in this example, formed of a third layer of metal) A second connection pad 63 of the wiring 125d) is laid.

The connection wiring 67 includes a connection conductor 68 buried in the connection holes 64 and 62 and electrically connected to the first connection pad 65, a through connection conductor 69 electrically connected to the second connection pad 63, and an upper end of the electrical connection connection conductor 68. The connecting conductor 71 is connected to the upper end of the connecting conductor 69. The connection conductor 71 exposed outside each connection wiring 67 serves as an electrode pad connected to an external wiring via a bonding wire.

The semiconductor element according to the eighth embodiment can be manufactured using the manufacturing method according to the first embodiment explained above. However, the pixel array and the control circuit of the first semiconductor wafer unit according to the first embodiment are replaced by the first semiconductor integrated circuit, and the logic circuit of the second semiconductor wafer unit is replaced by the second semiconductor integrated circuit.

In the semiconductor element according to the eighth embodiment, the first semiconductor wafer unit 101 and the second semiconductor wafer unit 116 are bonded to each other, and thus are preferably used in forming the first semiconductor integrated circuit and the second semiconductor integrated circuit. Processing technology. Therefore, since the first semiconductor integrated circuit and the second semiconductor integrated circuit can perform, it is possible to provide a semiconductor element having high performance.

Specifically, in the present embodiment, a portion of the first semiconductor wafer unit 101, that is, a semiconductor portion in which the connection conductor 68 and the through-connection conductor 69 are formed, is completely removed. Since the connection conductor 68 and the through-connection conductor 69 are formed in the semiconductor removal region 52, the parasitic capacitance between the semiconductor substrate 104 and the connection conductor 68 and the through-connection conductor 69 can be reduced, thereby providing a solid-state imaging with higher performance. element.

In the eighth embodiment, the semi-finished first semiconductor substrate 104 and the semi-finished second semiconductor substrate 118 are bonded to each other before the wafer is formed, and then the first semiconductor substrate 104 is thinned. That is, the second semiconductor substrate 118 is used as a support substrate of the first semiconductor substrate 104 when the first semiconductor substrate 104 is thinned. Therefore, components can be saved and manufacturing steps can be reduced. In the present embodiment, since the first semiconductor substrate 104 is thinned and the through connection holes 62 and the connection holes 64 are formed in the semiconductor removal region 52 in which the semiconductor segments are removed, the aspect ratio of the holes is reduced and The connection holes 62 and 64 can be formed with high precision. Therefore, it is possible to manufacture a high-performance solid-state imaging device with high precision.

10. Ninth Embodiment Configuration example of semiconductor components

Figure 41 is a diagram showing one of semiconductor elements in accordance with a ninth embodiment of the present invention. The semiconductor element 132 according to the ninth embodiment includes a stacked semiconductor wafer 100 in which the first semiconductor wafer unit 101 and the second semiconductor wafer unit 116 are bonded to each other. A first semiconductor integrated circuit and a multilayer wiring layer are formed in the first semiconductor wafer unit 101. A second semiconductor integrated circuit and a multilayer wiring layer are formed in the second semiconductor wafer unit 116. The first semiconductor wafer unit 101 and the second semiconductor wafer unit 116 are bonded to each other such that the multilayer wiring layers face each other.

In the present embodiment, the semiconductor removal region 52 in which the semiconductor portion of a portion of the first semiconductor wafer unit 101 is completely removed is formed, and is formed to extend from the inner surface of the semiconductor removal region 52 to the rear surface of the semiconductor substrate 103. The insulating film 61 is stacked. A planarization insulating film 77 that is flush with the surface of the stacked insulating film 61 on the semiconductor substrate 103 is formed in the semiconductor removal region 52. The etching rate of the planarized insulating film 77 is different from the etching rate of the tantalum nitride film 59 on the surface of the stacked insulating film 61. For example, the planarized insulating film 77 is formed as an insulating film such as a hafnium oxide film.

The connection hole 64 and the through connection hole 62 are formed to penetrate the insulating film 77 and reach the first connection pad 65 and the second connection pad 63. The connection wiring 67 connecting the first connection pad 65 and the second connection pad 63 is formed to pass through both of the connection holes 64 and 62. The connection wiring 67 includes a connection conductor 68 electrically connected to the first connection pad 65, a through connection conductor 69 electrically connected to the second connection pad 63, and a connection between the upper end of the electrical connection connection conductor 68 and the upper end of the through connection conductor 69. Conductor 71. The connecting conductor 68 and the through connecting conductor 69 are formed to be buried in the connecting holes 64 and 62, respectively. The connection conductor 68, the through-connection conductor 69, and the connection conductor 71 are integrally formed of a metal. The connection conductor 71 is formed on the planarized insulating film 77.

The other configuration is the same as that explained in the eighth embodiment. The constituent elements corresponding to the constituent elements of Fig. 40 are given the same reference numerals, and the description thereof will not be repeated.

The semiconductor element 132 according to the ninth embodiment can be fabricated using the manufacturing method according to the second embodiment set forth above. However, the pixel array and the control circuit of the first semiconductor wafer unit according to the second embodiment are replaced by the first semiconductor integrated circuit, and the logic circuit of the second semiconductor wafer unit is replaced by the second semiconductor integrated circuit.

According to the solid-state imaging element 132 of the ninth embodiment, a portion of the first semiconductor wafer unit 101 (that is, a semiconductor portion in which a region in which the wiring 67 is formed) is completely removed, and the insulating film 77 is buried in the removed In the semiconductor removal region 52. Since the connection conductor 68 and the through connection conductor 69 are buried in the connection hole 64 and the through connection hole 62 formed in the insulating film 77, the connection conductors 68 and 69 are separated from the side surface of the semiconductor substrate 103 by the insulating film 77. Therefore, the parasitic capacitance between the semiconductor substrate 103 and the connection conductors 68 and 69 is reduced. Further, the inner side of the semiconductor removal region 52 is buried in the insulating film 77, and the surface of the side surface of the semiconductor substrate 103 facing the semiconductor removal region 52 can be mechanically and reliably protected in cooperation with the stacked insulating film 61. Therefore, a solid-state imaging element having higher performance can be provided.

In the present embodiment, since the first semiconductor substrate 103 is thinned and the through-connection holes 62 and the connection holes 64 are formed, the aspect ratio of the holes is reduced and the connection holes 62 and 64 can be formed with high precision. Therefore, it is possible to manufacture a high-performance solid-state imaging device with high precision.

Although not otherwise illustrated, the same advantages as those of the eighth embodiment can be obtained.

11. Tenth Embodiment Configuration example of semiconductor components

Figure 42 is a diagram showing one of semiconductor elements in accordance with a tenth embodiment of the present invention. The semiconductor element 133 according to the tenth embodiment includes a stacked semiconductor wafer 100 in which the first semiconductor wafer unit 101 and the second semiconductor wafer unit 116 are bonded to each other. A first semiconductor integrated circuit and a multilayer wiring layer are formed in the first semiconductor wafer unit 101. A second semiconductor integrated circuit and a multilayer wiring layer are formed in the second semiconductor wafer unit 116. The first semiconductor wafer unit 101 and the second semiconductor wafer unit 116 are bonded to each other such that the multilayer wiring layers face each other.

In the present embodiment, the semiconductor removal region 52 in which the semiconductor portion of a portion of the first semiconductor wafer unit 101 is completely removed is formed, and is formed to extend from the inner surface of the semiconductor removal region 52 to the rear surface of the semiconductor substrate 103. The insulating film 61 is stacked. A planarization insulating film 77 which is flush with the surface of the stacked insulating film 61 on the semiconductor substrate 103 is formed in the semiconductor removal region 52, and a self-surface is formed in a portion of the connection wiring 67 corresponding to the insulating film 77. Depth portion 81 of depth.

The connection hole 64 and the through connection hole 62 are formed to penetrate the insulating film 77 under the recessed portion 81 to reach the first connection pad 65 and the second connection pad 63. The connection wiring 67 connecting the first connection pad 65 and the second connection pad 63 is formed to pass through both of the connection holes 64 and 62. The connection wiring 67 includes a connection conductor 68 electrically connected to the first connection pad 65, a through connection conductor 69 electrically connected to the second connection pad 63, and a connection between the upper end of the electrical connection connection conductor 68 and the upper end of the through connection conductor 69. Conductor 71. The connecting conductor 68 and the through connecting conductor 69 are formed to be buried in the connecting holes 64 and 62, respectively. The connection conductor 68, the through-connection conductor 69, and the connection conductor 71 are integrally formed of a metal. The connection conductor 71 is buried in the recessed portion 81 of the insulating film 77 and the surface of the connection conductor 71 is formed to be flush with the surface of the planarization insulating film 77.

The other configuration is the same as that explained in the eighth embodiment. The constituent elements corresponding to the constituent elements of Fig. 40 are given the same reference numerals, and the description thereof will not be repeated.

The semiconductor element 133 according to the tenth embodiment can be fabricated using the manufacturing method according to the third embodiment set forth above. However, the pixel array and the control circuit of the first semiconductor wafer unit according to the third embodiment are replaced by the first semiconductor integrated circuit, and the logic circuit of the second semiconductor wafer unit is replaced by the second semiconductor integrated circuit.

According to the solid-state imaging element 133 of the tenth embodiment, a portion of the first semiconductor wafer unit 101 (that is, a semiconductor portion in which a region in which the wiring 67 is formed) is completely removed, and the insulating film 77 is buried in the removed In the semiconductor removal region 52. The recessed portion 81 is formed in the insulating film 77, and the connection conductor 68 and the through-connection conductor 69 are formed through the connection hole 64 and the through-connection hole 62 formed in the insulating film 77 under the recessed portion 81, and the connection wiring 67 is formed. . Therefore, since the connection conductors 68 and 69 are away from the side surface of the semiconductor substrate 103 by the insulating film 77, the parasitic capacitance between the semiconductor substrate 103 and the connection conductors 68 and 69 is reduced. Further, the inner side of the semiconductor removal region 52 is buried in the insulating film 77, and the surface of the side surface of the semiconductor substrate 103 facing the semiconductor removal region 52 can be mechanically and reliably protected in cooperation with the stacked insulating film 61. Therefore, a solid-state imaging element having higher performance can be provided.

Since the connection conductor 71 is buried in the concave portion 81 of the insulating film 77, and the connection conductor 71 is planarized to be flush with the surface of the insulating film 77, a solid-state imaging device having a small surface step can be formed.

In the tenth embodiment, the first semiconductor substrate 103 is thinned, the concave portion 81 is further formed in the insulating film 77, and the through-connection holes 62 and the connection holes 64 are formed. Therefore, the aspect ratio of the hole is reduced and the connection hole 64 and the through connection hole 62 can be formed with high precision. Therefore, it is possible to manufacture a high-performance solid-state imaging device with high precision.

Although not otherwise illustrated, the same advantages as those of the eighth embodiment can be obtained.

According to the eighth to tenth embodiments explained above, the two semiconductor wafers are bonded to each other. Further, according to the solid-state imaging element of the embodiment of the present invention, three or more semiconductor wafer units can be bonded to each other. Even in three or more semiconductor wafer units bonded to each other, the configuration explained above can be applied, in which the first semiconductor wafer unit including the first semiconductor integrated circuit and the second semiconductor are completely removed a semiconductor segment in a connection portion between the second semiconductor wafer units of the integrated circuit. A memory circuit or another electronic circuit other than the logic circuit can be applied as the semiconductor integrated circuit.

As explained above, the arrangement of the connection pad arrays 91, 91A, 91B, and 98 set forth in the fourth to seventh embodiments is applied to the case where the complete removal is formed therein in which the first to third embodiments are formed. A solid-state imaging element that connects the semiconductor segments in the region of the wiring 67. The arrangement of the connection pad arrays 91, 91A, 91B, and 98 can be applied to the semiconductor elements according to the eighth to tenth embodiments. The arrangement of the connection pad arrays 91, 91A, 91B, and 98 is not limited thereto, but can be applied to a case where the semiconductor in the vicinity of the connection wiring is not removed when another wafer or wafer is bonded and the connection wiring is formed. For example, the arrangement of the connection pad arrays 91, 91A, 91B, and 98 is suitable for a solid-state imaging element or a semiconductor integrated circuit (semiconductor element) in which the semiconductor section is not removed. A connection wiring is formed by penetrating the semiconductor substrate and burying the connection conductor 68 and the through-connection conductor 69 with the insulating film interposed therebetween.

43 and 44 are diagrams of a solid-state imaging element in which a connection wiring is formed without removing a semiconductor segment and a connection pad arrangement is applied. The solid-state imaging element 135 according to the present embodiment has a configuration in which the semiconductor is not removed in the region in which the connection wiring 67 is formed in the second embodiment shown in Fig. 16 explained above. Section. In the present embodiment, the connection hole 64 penetrating the first semiconductor substrate 31 and reaching the first connection pad 65 is formed. Further, a through-connection hole 62 penetrating the first semiconductor wafer 22 including the semiconductor substrate 31 and reaching the second connection pad 63 is formed. An insulating film 136 which is insulated from the semiconductor substrate 31 is formed on the inner surface of each of the connection hole 64 and the through connection hole 62. A connection wiring is formed such that the connection conductor 68 and the through connection conductor 69 are buried in the connection hole 64 and the through connection hole 62 to be respectively connected to the first connection pad 65 and the second connection pad 63, and are connected to each other by the connection conductor 71 connection. The other configuration is the same as that of the second embodiment. The same constituent elements as those of the constituent elements shown in Fig. 16 are given the same reference numerals, and the description thereof will not be repeated.

On the other hand, as shown in Fig. 44, in the solid-state imaging element 135 according to the present embodiment, the arrangement of the wiring connection portions including the connection pads 63 and 65 has the same configuration as that shown in Fig. 31. . That is, the connection pad array 91 is configured such that the connection pad pairs 89 formed by the octagonal connection pads 63 and 65 are densely arranged in four stages. Other detailed configurations are the same as those described with reference to FIG. The same constituent elements as those of the constituent elements shown in FIG. 31 are given the same reference numerals, and the description thereof will not be repeated.

In the solid-state imaging element 135, as explained with reference to FIG. 31, the gap between the adjacent wirings 40d and the gap between the laying wirings 53d is enlarged, thereby reducing the adjacent coupling capacitance.

45 and 46 are diagrams in which a connection wiring is formed without removing a semiconductor section and a connection pad arrangement is applied to one semiconductor element of a semiconductor integrated circuit. The solid-state imaging element 137 according to the present embodiment has a configuration in which the semiconductor is not removed in the region in which the connection wiring 67 is formed in the ninth embodiment shown in Fig. 41 explained above. Section. In the present embodiment, the connection hole 64 penetrating the first semiconductor substrate 31 and reaching the first connection pad 65 is formed. Further, a through-connection hole 62 penetrating the first semiconductor wafer 22 including the semiconductor substrate 31 and reaching the second connection pad 63 is formed. An insulating film 136 which is insulated from the semiconductor substrate 31 is formed on the inner surface of each of the connection hole 64 and the through connection hole 62. A connection wiring is formed such that the connection conductor 68 and the through connection conductor 69 are buried in the connection hole 64 and the through connection hole 62 to be respectively connected to the first connection pad 65 and the second connection pad 63, and are connected to each other by the connection conductor 71 connection. The other configuration is the same as that of the sixth embodiment. The same constituent elements as those of the constituent elements shown in FIG. 41 are given the same reference numerals, and the description thereof will not be repeated.

On the other hand, as shown in Fig. 46, in the present embodiment, the arrangement of the wiring connecting portions including the connection pads 63 and 65 has the same configuration as that shown in Fig. 31. That is, the connection pad array 91 is configured such that the connection pad pairs 89 formed by the octagonal connection pads 63 and 65 are densely arranged in four stages. Other detailed configurations are the same as those described with reference to FIG. The same constituent elements as those of the constituent elements shown in FIG. 31 are given the same reference numerals, and the description thereof will not be repeated.

In the solid-state imaging element 137, as explained with reference to FIG. 31, the gap between the adjacent wirings 40d and the gap between the laying wirings 53d is enlarged, thereby reducing the adjacent coupling capacitance.

In a solid-state imaging element in which a connection wiring is formed without removing a semiconductor segment including an integrated circuit and a semiconductor element, the fifth embodiment (FIG. 36), the sixth embodiment (FIG. 37 and FIG. 38), the seventh embodiment (Fig. 39) or the like is applied to the arrangement of the connection pads.

In the solid-state imaging element according to the embodiments set forth above, it is necessary to stabilize the potential of the semiconductor substrate or the semiconductor well region in which the pixel array 23 of the first semiconductor wafer unit 22 is formed. That is, it is necessary to stabilize the potential (so-called substrate potential) of the semiconductor substrate or the semiconductor well region in the vicinity of the through-connection conductor 69 and the connection conductor 68 even when the potentials of the through-connection conductor 69 and the connection conductor 68 are changed. In order to stabilize the substrate potential, in this example, a contact unit is formed in the semiconductor well region 32 by an impurity diffusion layer. The contact unit is connected to one of the electrode pad units formed in the vicinity of the first semiconductor wafer unit 22 via the connection conductor 44 and the wiring 40. A supply voltage or a ground voltage (0 V) is applied to the semiconductor well region 32 via the contact unit by supplying, for example, a supply voltage VDD or a ground voltage (0 V) to the electrode pad unit. Therefore, the substrate potential of the semiconductor well region is stabilized. For example, when the semiconductor substrate or semiconductor well region is an n-type, the supply voltage is supplied. When the semiconductor substrate or the semiconductor well region is a p-type, a ground voltage is supplied.

In the solid-state imaging element according to the embodiments described above, a protective diode is mounted such that the transistor in the logic circuit is not subjected to the processing of the connection wiring 67 formed by the through-connection conductor 69 and the connection conductor 68. The plasma is damaged. When the connection wiring 67 is formed, the connection holes 62 and 65 reaching the pads 63 and 65 are formed by plasma etching. However, excess plasma ions are charged to the connection pads 63 in the logic circuit, particularly in the plasma processing. When the charged excess plasma ions are applied to the transistors in the circuit via the wiring 53, the transistors are damaged by the so-called plasma. Use a protective diode to prevent plasma damage.

In the present embodiment, a protection diode is formed in each of the logic circuits forming each row of circuit cells of the row signal processing circuit 5. As explained above, the laying wiring corresponding to each of the vertical signal lines is connected to the through-connection conductor 69 and the connection conductor 68 of each of the connection wirings 67 via each of the connection pads 63 and 65. In the second semiconductor wafer unit 26, a protective diode is formed for each of the row of circuit cells of the MOS transistor in which the row circuit unit is formed. Each of the protective diodes is connected to the same laying wiring to which the gate electrode of the MOS transistor of the row circuit unit is connected. The MOS transistor connected to the self-circuit unit of the protective diode system of the laying wiring is mounted close to the connection pad 63. In the plasma processing, the charge of the excess plasma ions that has been charged in the connection pad unit 63 in the logic circuit flows to the protection diode without causing damage in the row of circuit units. Therefore, plasma damage to the row circuit unit can be prevented in the process of connecting the wiring 67. In addition, the same protective diode can be provided to not only prevent plasma damage to the row circuit unit but also prevent plasma damage to the MOS transistor forming another peripheral circuit.

A specific example will be explained with reference to the schematic diagram of FIG. Here, the example is applied to the solid-state imaging element 135 in which the semiconductor section is not removed in the region of the connection wiring 67 explained above in FIG. In this example, the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are electrically connected to each other via the connection wiring 67. In the first semiconductor wafer unit 22, the connection conductor 68 of the connection wiring 67 penetrates the first semiconductor substrate 31 and is connected to the first connection pad 65 formed of the first layer metal M1 of the multilayer wiring layer 41. The first connection pad 65 is connected to the fourth layer metal via one of the first layer metal M1 extension portion 65a, a conduction conductor 88, the second layer metal M2, a conduction conductor 88, the third layer metal M3 and a conduction conductor 88. The wiring 4d is formed by M4. The laying wiring 40d corresponds to a vertical signal line as explained above.

In the second semiconductor wafer unit 26, the connection conductor 69 of the connection wiring 67 penetrates the first semiconductor substrate 22 and is connected to the second connection pad 63 formed of the fourth layer metal M14 of the multilayer wiring layer 55. The second connection pad 63 is connected to the routing wiring 53d formed of the first layer metal M11 via a via conductor 88, a third layer metal M13, a via conductor 88, a second layer metal M12, and a via conductor 88. The laying wiring 53d corresponds to a vertical signal line as explained above.

The connection pads 65 and 63 are preferably formed of, for example, an Al film. The reason for using the Al film is as follows. That is, the connection hole 64 and the through connection hole 62 which respectively bury the connection conductor 68 and the through connection conductor 69 are formed by plasma etching using a CF gas. Since the plasma treatment is over-etched and the connection pads 65 and 63 are exposed to the plasma, one of the reactants can be attached to the surfaces of the connection pads 65 and 63 as a Cu film without being removed. The electrical connection between the connection pads 65 and 63 and the connection conductor 68 and the through connection conductor 69 can be achieved satisfactorily by Cu due to the reactants. However, in the case of the Al film, since the reactants are not attached, the electrical connection between the connection pads 65 and 63 and the connection conductor 68 and the through connection conductor 69 can be satisfactorily achieved.

In the case of an Al film, a film configuration having a Ti film or a TiN film on the Al film is provided. A metal (M2 to M4) other than the metal M1 of the connection pad 65 and a metal (M13 to M11) other than the metal M14 of the connection pad 63 are formed of a Cu film.

For example, as explained below, when the connection wiring 67 is disposed between a comparator and a calculation loop, one of the calculation loops is formed at a high speed to form a MOS transistor connected to the vertical signal line. The MOS electro-crystal system is formed by a high-speed transistor Tr21 that operates at a high speed. The high speed transistor Tr21 is also referred to as a minimum transistor and the gate insulating film is thin. Therefore, the high speed transistor Tr21 is connected to the laying wiring 53d serving as a vertical signal line in the second semiconductor wafer 26.

In the plasma processing, an excessive current flows to the laying wiring 53d via the connection pad 63, and the gate insulating film of the high-speed transistor Tr21 forming the calculation loop can be damaged, that is, damaged. Therefore, one of the protective diodes D21 having one pn junction is connected to the region of the laying wiring 53d close to the connection pad 63 instead of the high speed transistor Tr21. Even when excessive current flows to the laying wiring 53d in the plasma processing, excess current can flow to the substrate via the protective diode D21, and damage to the high-speed transistor Tr21 can be prevented by the protective diode D21.

In the sixth embodiment (see FIG. 38) set forth above, by the first connection pad 65 and the laying wiring (vertical signal line) 40d having a different potential and immediately below the first connection pad 65 The shield wiring 96 is placed to prevent adjacent coupling capacitance from occurring. Although not illustrated, the adjacent coupling capacitance is prevented from occurring by arranging the shield wiring between the second connection pad 63 and the laying wiring (vertical signal line) 53d having a different potential and immediately below the second connection pad 63.

In the solid-state imaging element described above, for the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26, it is preferable to electrically shield the gap between the adjacent laying wirings and the adjacent laying wiring and the connecting conductor or the through-connecting conductor. The gap between them. Further, depending on the arrangement of the connection pads, it is preferable to electromagnetically shield the gap between the connection conductor and the through-connection conductor adjacent to each other, the gap between the adjacent connection conductors, and the gap between the adjacent connection conductors. In this case, the corresponding shielded wiring can be configured using the metal wiring of the layers of the multilayer wiring layer.

Although not illustrated, the shield wiring is disposed by other layer metals interposed between adjacent laying wirings in the same layer as the laying wiring or in the vicinity of the laying wiring. Apply the ground potential to the shield wiring. Therefore, the adjacent coupling capacitance between the adjacent laying wirings can be reduced.

When the connection pad and the laying wiring are formed of the same layer of metal, the other layer between the adjacent connecting conductor 68 and the laying wiring 40d in the same layer as the laying wiring 40d or in the vicinity of the wiring 40d Metal to configure the shield wiring. Further, the shield wiring is disposed by a metal interposed between the adjacent through-connection conductor 69 and the laid wiring 53d in another layer in the same layer as the wiring 53d or in the vicinity of the wiring 53d. Apply the ground potential to the shield wiring. Therefore, the adjacent coupling capacitance between the adjacent laying wiring 40d and the connecting conductor 68 and between the adjacent laying wiring 53d and the through connecting conductor 69 can be reduced.

In the connection wiring region in which the plurality of connection wirings 67 are formed, the adjacent coupling capacitance can be reduced by forming a conductive semiconductor impurity region to surround the through-connection conductor and the connection conductor with an insulating film interposed therebetween. That is, the adjacent coupling capacitance between the adjacent through-connection conductors and the connection conductors between adjacent connection conductors or adjacent to the connection conductors can be reduced. 48 and 49 (cross-sectional views taken along the line XXXXIX-XXXXIX of Fig. 49) are schematic illustrations of this example. In this example, the solid state imaging element 135 of Figure 43 is used.

In Figs. 48 and 49, the pair of connection pads 89 are alternately arranged opposite to those shown in Fig. 37. In the connection wiring region, a p-type semiconductor region 151 is formed in a region surrounding the connection conductor 68 and the through-connection conductor 69 of the semiconductor substrate 31 and grounds the p-type semiconductor region 151. The p-type semiconductor region 151 is electrically isolated from the connection conductor 68 and the through-connection conductor 69 by the insulating film 136. In this configuration, the grounded p-type semiconductor region 151 acts as a shield and thus reduces the adjacent coupling capacitance between the adjacent connecting conductor 68 and the through connecting conductor 69. When an impurity diffusion layer (ie, a p-type semiconductor region) is used as a device isolation region for isolating the photodiode PD of each pixel, the p-type semiconductor region can be simultaneously formed by the p-type semiconductor region of the device isolation region. 151.

When the grounded p-type semiconductor region 151 is used as a shield layer, the ground capacitance tends to increase. The ground capacitance is suppressed by controlling the film thickness t1 of one of the insulating films 136. The film thickness t1 can be set to be in the range from 50 nm to 300 nm, for example, set to about 100 nm. The larger the film thickness t1 is, the smaller the grounding capacitance [fF] is. However, when the film thickness t1 is equal to or greater than 300 nm, the ground capacitance hardly changes.

In the configuration of the connection pad pair 99 shown in FIG. 39, as in FIG. 49, the connection conductor 68 and the through-connection conductor 69 are disposed adjacent to each other in the vertical direction. As in FIG. 50, the connection conductors 68 are disposed adjacent to each other in the lateral direction, and as in FIG. 51, the through-connection conductors 69 are disposed adjacent to each other in the lateral direction. In FIGS. 50 and 51, the same constituent elements as those of the constituent elements of FIG. 49 are given the same reference numerals and the description thereof will not be repeated.

Although not illustrated, one contact unit (substrate contact unit) formed of an impurity diffusion layer is formed in the p-type semiconductor region 151 so that the p-type semiconductor region 151 is adjacent to the connection conductor 68 and the through-connection conductor 69. The potential (also known as the substrate potential) is stable. The contact unit is formed to surround the electrode pad corresponding to the connection wiring region of the plurality of connection pad arrays and connectable to the first semiconductor wafer unit 22. By supplying the ground voltage (0 V) to the electrode pad, the substrate potential of the connection conductor 68 and the p-type semiconductor region 151 in the vicinity of the through-connection conductor 69 can be stabilized.

The semiconductor substrate 31 of the first semiconductor wafer unit 22 is formed by setting an n-type semiconductor substrate as a starting material. The semiconductor substrate 45 of the second semiconductor wafer unit 26 is formed by setting a p-type semiconductor substrate as a starting material. When the control circuit 24 and the pixel array 23 shown in FIG. 2B are formed in the first semiconductor wafer unit 22, there is n between the p-type semiconductor well region of the pixel array 23 and the p-type semiconductor well region of the control circuit 24. Type substrate. Therefore, in the first semiconductor wafer unit 22, a voltage for stabilizing the corresponding potential is supplied from the electrode pads to the p-type semiconductor well region, the n-type semiconductor substrate, and the p-type semiconductor region 151 via the substrate contact unit. In the second semiconductor wafer unit 26, a voltage for stabilizing the corresponding potential is supplied to the p-type semiconductor substrate and the n-type semiconductor well region in which the p-channel MOS transistor is formed via the respective substrate contact units.

When the substrate contact units in the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are both connected to, for example, the electrode pads on the surface of the first semiconductor wafer unit 22, via separate through-connection conductors, connection conductors And a layer of metal wiring to achieve the connection.

When the substrate contact units in the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are both connected to, for example, the electrode pads on the surface of the second semiconductor wafer unit 26, the through-connecting conductors and the connecting conductors are separately connected. And a layer of metal wiring to achieve the connection.

Next, an insertion portion of the connection wiring 67 formed by the connection conductor 68 and the through-connection conductor 69 explained above on one of the circuits of the solid-state imaging element will be explained. Figure 52 is a schematic illustration of one of the main units of the solid state imaging device. As explained above, the solid-state imaging element includes a pixel array 3 in which a plurality of pixels 2 are arranged in a matrix form. The row signal processing circuit 5 is connected to the vertical signal line 9 corresponding to 2 rows of each pixel. The row signal processing circuit 5 includes a row of ADC units 13. The row ADC unit 13 converts an analog signal into a digital signal over time from the start of the conversion to determine that a reference voltage (lamp voltage) is the same as one of the signal voltages to be processed. In principle, the row ADC unit 13 includes a comparator (voltage comparator) 14 and a calculation loop 15. The row ADC unit 13 supplies the lamp voltage to the comparator 14 and starts the calculation with a reference signal supplied to one of the calculation loops 15. By comparing one of the analog image signals input via the vertical signal line 9, the row ADC unit 13 performs AD conversion until a pulse signal is obtained.

In the present embodiment, the connection wiring 67 is disposed at a position (1) between the comparator 14 and the calculation circuit 15 in FIG. In this case, the circuit configuration of the comparator 14 is formed by the pixel array 3 and the first semiconductor wafer unit 22. The second semiconductor wafer unit 26 has a circuit configuration after the calculation loop 15. The control circuit can be formed in the first semiconductor wafer unit 22 or the second semiconductor wafer unit 26. The first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 may be connected to each other by a connection wiring 67 including a connection conductor 68 and a through connection conductor 69.

Since the calculation loop 15 performs the processing quickly, even for the transistor of the calculation loop 15, it is required to operate one of the high speed transistors at high speed. High-speed transistors must be fabricated with an advanced device. According to the configuration set forth above, the first semiconductor wafer unit 22 having the circuit configuration up to the comparator 14 and the second semiconductor wafer unit 26 having the circuit configuration after the calculation loop 15 can be respectively controlled by several advanced devices Made separately.

In Fig. 52, the performance (image quality) of the solid-state imaging element can be considered to place the connection wiring 67 at the position (3) or the position (2). That is, the connection wiring 67 may be disposed at a position (3) between the pixel array 3 and the line signal processing circuit 5. In this case, the pixel array 3 is formed in the first semiconductor wafer unit 22, and a signal processing circuit including the row signal processing circuit 5 is formed in the second semiconductor wafer unit 26. The first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are then connected to each other by a connection wiring 67 including a connection conductor 68 and a through connection conductor 69.

Further, the connection wiring 67 may be disposed at the position (2) of the output of the calculation circuit 15. In this case, the circuit configuration up to the calculation loop 15 and the pixel array 3 is formed in the first semiconductor wafer unit 22. In the second semiconductor wafer unit 26, a signal processing circuit after the output of the calculation loop 15 is formed. Then, the first semiconductor wafer unit 22 and the second semiconductor wafer unit 26 are connected to each other by a connection wiring 67 including a connection conductor 68 and a through connection conductor 69.

Providing a configuration of the protection diode D21 described above, wherein the configuration of the p-type semiconductor region 151 in the vicinity of the connection wiring 67 in FIGS. 48 and 51, the configuration of the substrate contact unit can be used for The configuration of each shielded wiring that is adjacent to the coupling capacitor is reduced and the like is applied to the embodiments set forth above.

12. Eleventh Embodiment Example of an electronic device

The solid-state imaging element according to the above-described embodiments of the present invention can be applied to an electronic device such as a camera system (such as a digital camera or a video camera), a mobile phone having an imaging function, and other devices having an imaging function.

Figure 53 is a diagram showing one of the cameras as an example of an electronic device according to an eleventh embodiment of the present invention. The camera according to the present embodiment is an example of a video camera capable of imaging a still image and a video. The camera 141 according to the present embodiment includes a solid-state imaging element 142, an optical system 143 that directs incident light to one of the light-receiving sensor units of the solid-state imaging element 142, and a shutter element 144. The camera 141 includes a drive circuit 145 that drives one of the solid state imaging elements 142, and a signal processing circuit 146 that processes one of the outputs from the solid state imaging element 142.

One of the solid-state imaging elements according to the embodiments set forth above is applied as the solid-state imaging element 142. An optical system (optical lens) 143 images image light (incident light) from a subject on an imaging surface of one of the solid state imaging elements 142. Therefore, signal charges are accumulated in the solid-state imaging element 142 for a predetermined period. Optical system 143 can be an optical lens system that includes one of a plurality of optical lenses. The shutter element 144 controls one of the light-emitting period and one of the light-shielding period of the solid-state imaging element 142. The drive circuit 145 supplies a drive signal for controlling one of the solid-state imaging element 142 transfer operation and one shutter operation of the shutter element 144. The signal transmission of the solid-state imaging element 142 is performed by a drive signal (timing signal) supplied from the drive circuit 145. Signal processing circuit 146 performs various signal processing. The image signal that has been subjected to signal processing is stored in a storage medium such as a memory or output to a monitor.

In an electronic device such as the camera according to the eleventh embodiment, the solid-state imaging element 142 can be realized and thus an electronic device with high reliability can be provided.

The present invention contains the subject matter related to the subject matter disclosed in Japanese Priority Patent Application No. 2010-279833, filed on Dec. Incorporated herein.

It will be understood by those skilled in the art that various modifications, combinations, sub-combinations and changes can be made without departing from the scope of the appended claims.

1. . . Solid-state imaging element

2. . . Pixel

3. . . Pixel array

4. . . Vertical drive circuit

5. . . Line signal processing circuit

6. . . Horizontal drive circuit

7. . . Output circuit

8. . . Control circuit

9. . . Vertical signal line

10. . . Horizontal signal line

11. . . Semiconductor substrate

12. . . Input/output terminal

13. . . Row ADC unit

14. . . Comparators

15. . . Calculation loop

20. . . Metal oxide semiconductor solid-state imaging element

twenty one. . . Metal oxide semiconductor solid-state imaging element

twenty two. . . First semiconductor wafer unit

twenty three. . . Pixel array

twenty four. . . Control circuit

25. . . Logic circuit

26. . . Second semiconductor wafer unit

27. . . Stacked semiconductor wafer

28. . . Solid-state imaging element

30. . . Unit pixel

31. . . Semiconductor substrate

31a. . . surface

31b. . . Back surface

32. . . Semiconductor well area

33. . . Source/bungee area

34. . . N-type semiconductor region

35. . . P-type semiconductor region

36. . . Gate electrode

38. . . Device isolation region

39. . . Interlayer insulating film

40. . . wiring

40a. . . wiring

40b. . . wiring

40c. . . wiring

40d. . . wiring

41. . . Multilayer wiring layer

42. . . Protective film

43a. . . Insulating film

43b. . . Insulating film

44. . . Connecting conductor

45. . . Second semiconductor substrate

45a. . . surface

46. . . P-type semiconductor well region

47. . . For n-type source/drain regions

48. . . Gate electrode

49. . . Interlayer insulating film

50. . . Device isolation region

52. . . Semiconductor removal area

52a. . . Semiconductor removal area

52b. . . Semiconductor removal area

53. . . wiring

53a. . . wiring

53b. . . wiring

53c. . . wiring

53d. . . wiring

54. . . Connecting conductor

55. . . Multilayer wiring layer

56. . . Protective film

57. . . Adhesive layer

58. . . Cerium oxide film

59. . . Tantalum nitride film

61. . . Stacked insulating film

62. . . Through connection hole

63. . . Second connection pad

64. . . Connection hole

65. . . First connection pad

65a. . . Connecting protrusion/extension

67. . . Connection wiring

68. . . Connecting conductor

69. . . Through connection conductor

71. . . Connecting conductor

72. . . Light masking film

73. . . Flattened film

74. . . Color filter

75. . . Microlens on wafer

77. . . Flattened insulating film

78. . . Solid-state imaging element

81. . . Sag part

82. . . Solid-state imaging element

84. . . Solid-state imaging element

85. . . Connection part

86. . . Conduction conductor

87. . . Connection part

88. . . Conduction conductor

89. . . Connection pad pair

91. . . Connection pad array

91A. . . Connection pad array

91B. . . Connection pad array

93. . . Solid-state imaging element

95. . . Solid-state imaging element

96. . . Shielded wiring

97. . . Solid-state imaging element

98. . . Connection pad array

99. . . Connection pad pair

100. . . Stacked semiconductor wafer

101. . . First semiconductor wafer unit

102. . . Logic circuit

103. . . Semiconductor substrate

104. . . Semiconductor well area

105. . . Source/drain region

106. . . Gate electrode

107. . . Device isolation region

108. . . Interlayer insulating film

109a. . . wiring

109b. . . wiring

109c. . . wiring

109d. . . wiring

111. . . Multilayer wiring layer

112. . . Connecting conductor

114. . . Protective film

116. . . Second semiconductor wafer unit

117. . . Integrated circuit

118. . . Second semiconductor substrate

119. . . Semiconductor well area

120. . . Connecting conductor

121. . . Source/drain region

122. . . Gate electrode

123. . . Device isolation region

124. . . Interlayer insulating film

125. . . wiring

125a. . . wiring

125b. . . wiring

125c. . . wiring

125d. . . wiring

126. . . Wiring layer

127. . . Protective film

129. . . Adhesive layer

131. . . Semiconductor component

132. . . Semiconductor component

133. . . Semiconductor component

135. . . Solid-state imaging element

136. . . Insulating film

137. . . Solid-state imaging element

141. . . camera

142. . . Solid-state imaging element

143. . . Optical system

144. . . Shutter element

145. . . Drive circuit

146. . . Signal processing circuit

151. . . Metal oxide semiconductor solid-state imaging element

152. . . Semiconductor wafer

153. . . Pixel array

154. . . Control circuit

155. . . Logic circuit

D21. . . Protective diode

FD. . . Floating diffusion

M1. . . metal

M2. . . metal

M3. . . metal

M4. . . metal

M11. . . metal

M12. . . metal

M13. . . metal

M14. . . metal

P. . . spacing

PD. . . Photodiode

Tr1. . . Metal oxide semiconductor transistor

Tr2. . . Metal oxide semiconductor transistor

Tr3. . . Metal oxide semiconductor transistor

Tr4. . . Metal oxide semiconductor transistor

Tr6. . . Metal oxide semiconductor transistor

Tr7. . . Metal oxide semiconductor transistor

Tr8. . . Metal oxide semiconductor transistor

Tr11. . . Metal oxide semiconductor transistor

Tr12. . . Metal oxide semiconductor transistor

Tr13. . . Metal oxide semiconductor transistor

Tr21. . . Metal oxide semiconductor transistor

Tr22. . . Metal oxide semiconductor transistor

Tr23. . . Metal oxide semiconductor transistor

T1. . . Film thickness

1 is a diagram showing an overall configuration of an example of a MOS solid-state imaging element applied to an embodiment of the present invention;

2A to 2C are schematic views of a solid-state imaging element according to an embodiment of the present invention and a solid-state imaging element according to the related art;

Figure 3 is a diagram showing an overall configuration of main units of a solid-state imaging element according to a first embodiment of the present invention;

Figure 4 is a diagram showing an example of a process (part 1) of manufacturing one of the solid-state imaging elements according to the first embodiment;

Figure 5 is a diagram showing an example of a process (part 2) of manufacturing one of the solid-state imaging elements according to the first embodiment;

Figure 6 is a diagram showing an example of a process (part 3) of manufacturing one of the solid-state imaging elements according to the first embodiment;

Figure 7 is a diagram showing an example of a process (part 4) of manufacturing one of the solid-state imaging elements according to the first embodiment;

Figure 8 is a diagram showing an example of a process (part 5) of manufacturing one of the solid-state imaging elements according to the first embodiment;

Figure 9 is a diagram showing an example of a process (part 6) of manufacturing one of the solid-state imaging elements according to the first embodiment;

Figure 10 is a diagram showing an example of a process (part 7) of manufacturing one of the solid-state imaging elements according to the first embodiment;

Figure 11 is a diagram showing an example of a process (part 8) of manufacturing one of the solid-state imaging elements according to the first embodiment;

Figure 12 is a diagram showing an example of a process (part 9) of manufacturing one of the solid-state imaging elements according to the first embodiment;

Figure 13 is a diagram showing an example of a process (part 10) of manufacturing one of the solid-state imaging elements according to the first embodiment;

Figure 14 is a diagram showing an example of a process (part 11) of manufacturing one of the solid-state imaging elements according to the first embodiment;

15A and 15B are schematic plan views showing the position of a semiconductor removal region according to an embodiment of the present invention;

Figure 16 is a diagram showing an overall configuration of main units of a solid-state imaging element according to a second embodiment of the present invention;

Figure 17 is a diagram showing an example of a process (part 1) of manufacturing one of the solid-state imaging elements according to the second embodiment;

Figure 18 is a diagram showing an example of a process (part 2) of manufacturing one of the solid-state imaging elements according to the second embodiment;

Figure 19 is a diagram showing an example of a process (part 3) of manufacturing one of the solid-state imaging elements according to the second embodiment;

Figure 20 is a diagram showing an example of a process (part 4) of manufacturing one of the solid-state imaging elements according to the second embodiment;

Figure 21 is a diagram showing an example of a process (part 5) of manufacturing one of the solid-state imaging elements according to the second embodiment;

Figure 22 is a diagram showing an example of a process (part 6) of manufacturing one of the solid-state imaging elements according to the second embodiment;

Figure 23 is a diagram showing an example of a process (part 7) of manufacturing one of the solid-state imaging elements according to the second embodiment;

Figure 24 is a diagram showing an example of a process (part 8) of manufacturing one of the solid-state imaging elements according to the second embodiment;

Figure 25 is a diagram showing an overall configuration of main units of a solid-state imaging element according to a third embodiment of the present invention;

Figure 26 is a diagram showing an example of a process (part 1) of manufacturing one of the solid-state imaging elements according to the third embodiment;

Figure 27 is a diagram showing an example of a process (part 2) of manufacturing one of the solid-state imaging elements according to the third embodiment;

Figure 28 is a diagram showing an example of a process (part 3) of manufacturing one of the solid-state imaging elements according to the third embodiment;

Figure 29 is a diagram showing an example of a process (part 4) of manufacturing one of the solid-state imaging elements according to the third embodiment;

Figure 30 is a diagram showing an example of a process (part 5) of manufacturing one of the solid-state imaging elements according to the third embodiment;

Figure 31 is a diagram showing an overall configuration of a main unit of a solid-state imaging element according to a fourth embodiment of the present invention;

Figure 32 is a schematic cross-sectional view taken along line XXXII-XXXII of Figure 31;

Figure 33 is a schematic cross-sectional view taken along line XXXIII-XXXIII of Figure 31;

Figure 34 is an exploded plan view showing one of the first connection pads of Figure 31;

Figure 35 is an exploded plan view showing one of the second connection pads of Figure 31;

Figure 36 is a diagram showing an overall configuration of main units of a solid-state imaging element according to a fifth embodiment of the present invention;

Figure 37 is a diagram showing an overall configuration of main units of a solid-state imaging element according to a sixth embodiment of the present invention;

Figure 38 is a schematic cross-sectional view taken along line XXXVIII-XXXVIII of Figure 37;

Figure 39 is a diagram showing an overall configuration of a main unit of a solid-state imaging element according to a seventh embodiment of the present invention;

Figure 40 is a diagram showing an overall configuration of a semiconductor element according to an eighth embodiment of the present invention;

Figure 41 is a diagram showing an overall configuration of a semiconductor element according to a ninth embodiment of the present invention;

Figure 42 is a diagram showing an overall configuration of a semiconductor element according to a tenth embodiment of the present invention;

43 is a diagram showing an overall configuration of another example of a solid-state imaging element in which one of the connection pads is disposed in accordance with an embodiment of the present invention;

Figure 44 is a schematic plan view showing an example of a connection pad arrangement in the solid-state imaging element of Figure 43;

Figure 45 is a diagram showing an overall configuration of still another example of a solid-state imaging element in which one of the connection pads is disposed in accordance with an embodiment of the present invention;

Figure 46 is a schematic plan view showing an example of a connection pad arrangement in the solid-state imaging element of Figure 45;

47 is a diagram showing an overall configuration of a solid-state imaging element including a protective diode according to an embodiment of the present invention;

Figure 48 is a schematic cross-sectional view showing one of main units in an example of a connection wiring region in accordance with an embodiment of the present invention;

Figure 49 is a schematic cross-sectional view taken along line XXXXIX-XXXXIX of Figure 48;

Figure 50 is a schematic cross-sectional view showing one of main units in an example of a region of a connecting conductor adjacent to each other according to an embodiment of the present invention;

Figure 51 is a schematic cross-sectional view showing one of main units in an example of a configuration of a region of a through-connecting conductor adjacent to each other in accordance with an embodiment of the present invention;

Figure 52 is a view showing a position of insertion of a connection wiring on a circuit between semiconductor wafers according to an embodiment of the present invention; and

Figure 53 is a diagram showing an overall configuration of an electronic device according to an eleventh embodiment of the present invention.

twenty two. . . First semiconductor wafer unit

twenty three. . . Pixel array

twenty four. . . Control circuit

25. . . Logic circuit

26. . . Second semiconductor wafer unit

27. . . Stacked semiconductor wafer

28. . . Solid-state imaging element

30. . . Unit pixel

31. . . Semiconductor substrate

31a. . . surface

31b. . . Back surface

32. . . Semiconductor well area

33. . . Source/bungee area

34. . . N-type semiconductor region

35. . . P-type semiconductor region

36. . . Gate electrode

38. . . Device isolation region

39. . . Interlayer insulating film

40a. . . wiring

40b. . . wiring

40c. . . wiring

40d. . . wiring

41. . . Multilayer wiring layer

42. . . Protective film

43a. . . Insulating film

43b. . . Insulating film

44. . . Connecting conductor

45. . . Second semiconductor substrate

45a. . . surface

46. . . P-type semiconductor well region

47. . . For n-type source/drain regions

48. . . Gate electrode

49. . . Interlayer insulating film

50. . . Device isolation region

52. . . Semiconductor removal area

52a. . . Semiconductor removal area

52b. . . Semiconductor removal area

53a. . . wiring

53b. . . wiring

53c. . . wiring

53d. . . wiring

54. . . Connecting conductor

55. . . Multilayer wiring layer

56. . . Protective film

57. . . Adhesive layer

58. . . Cerium oxide film

59. . . Tantalum nitride film

61. . . Stacked insulating film

62. . . Through connection hole

63. . . Second connection pad

64. . . Connection hole

65. . . First connection pad

67. . . Connection wiring

68. . . Connecting conductor

69. . . Through connection conductor

71. . . Connecting conductor

72. . . Light masking film

73. . . Flattened film

74. . . Color filter

75. . . Microlens on wafer

FD. . . Floating diffusion

M1. . . metal

M2. . . metal

M3. . . metal

M11. . . metal

M12. . . metal

M13. . . metal

PD. . . Photodiode

Tr1. . . Metal oxide semiconductor transistor

Tr2. . . Metal oxide semiconductor transistor

Tr3. . . Metal oxide semiconductor transistor

Tr4. . . Metal oxide semiconductor transistor

Tr6. . . Metal oxide semiconductor transistor

Tr7. . . Metal oxide semiconductor transistor

Tr8. . . Metal oxide semiconductor transistor

Claims (30)

A semiconductor component configured as a backside illuminated solid-state imaging device, comprising: a stacked semiconductor component formed by bonding two or more semiconductor wafer units to each other, and wherein the stacked semiconductor component Forming at least one pixel array and a first multilayer wiring layer in a first semiconductor substrate are formed in a first semiconductor wafer unit, and a logic circuit and a second multilayer wiring layer are formed in a second a semiconductor wafer cell; at least a portion of the first semiconductor wafer cell being removed in the semiconductor removal region, wherein the semiconductor removal region is configured to have a surface lower than the first semiconductor a surface of one of the substrates; and a plurality of connection wirings formed in the semiconductor removal region and connecting the first semiconductor wafer unit and the second semiconductor wafer unit to each other. The semiconductor device of claim 1, wherein the plurality of connection wires comprise a first connection conductor connected to a first connection pad, the first connection pad being connected to the first plurality of layers in the first semiconductor wafer unit One of wiring layers inside the wiring layer, a through connection conductor penetrating the first semiconductor wafer unit and connected to a second connection pad, the second connection pad being connected to the second plurality of layers in the second semiconductor wafer unit One of the wiring layers and a second connecting conductor that connects the first connecting conductor and the through connecting conductor to each other. A semiconductor element according to claim 2, wherein a protective insulating film serving as an anti-reflection film is formed to extend from a surface of the semiconductor removal region to a surface of one of the semiconductor substrates in which the pixel array is formed. The semiconductor device of claim 3, wherein in the first semiconductor wafer unit, the first connection pad is formed of a first layer of metal of the first multilayer wiring layer and is connected to the first connection pad The wiring is formed of a layer of metal after a second layer of metal. A semiconductor component according to claim 4, wherein a shield wiring is formed of a layer of metal interposed between the first connection pad and the wiring. The semiconductor device of claim 3, further comprising: an insulating film buried in the semiconductor removal region; and the first connection conductor and the through connection conductor penetrating the insulating film. The semiconductor device of claim 3, wherein the first connection pads and the second connection pads each having an octagonal shape are alternately arranged in a horizontal direction and a vertical direction, and the first connection pads are disposed along the horizontal direction The two connection pads are arranged in a plurality of stages along the vertical direction to form an array of connection pads, wherein the area of the second connection pads is larger than the area of the first connection pads, and the routing connections corresponding to the vertical signal lines respectively And connecting the first connection pads and the second connection pads in the plurality of stages. The semiconductor component of claim 7, wherein the array of connection pads are disposed to face each other with a space therebetween The array of pixels, and wherein the wires corresponding to the vertical signal lines are alternately connected to the array of connection pads. The semiconductor device of claim 3, further comprising: a connection pad array, wherein the first connection pad and the second connection pad pair disposed along a vertical direction in the connection pad array are disposed along the vertical direction and a horizontal direction, And the first connection pads and the second connection pad pairs are arranged in a plurality of stages along the vertical direction, wherein the wires respectively corresponding to the vertical signal lines are connected to the first connection pads and the first plurality of stages arranged in the plurality of stages Two connection pad pairs. The semiconductor device of claim 2, further comprising: an array of connection pads, wherein the first connection pads and the second connection pads each having an octagonal shape in the connection pad array are alternately arranged in a horizontal direction and a vertical direction The first connection pad and the second connection pad pair disposed along the horizontal direction are disposed in a plurality of stages along the vertical direction, wherein an area of the second connection pad is set to be larger than an area of the first connection pad, And wherein the wires respectively corresponding to the vertical signal lines are connected to the first connection pads and the second connection pad pairs configured in the plurality of stages. The semiconductor device of claim 2, further comprising: a connection pad array, wherein the first connection pad and the second connection pad pair disposed along a vertical direction in the connection pad array are disposed along the vertical direction and a horizontal direction, And the first connection pad and the second connection pad pair are arranged in a plurality of stages along the vertical direction, The wires respectively corresponding to the vertical signal lines are connected to the first connection pads and the second connection pad pairs arranged in the plurality of stages. The semiconductor component of claim 1, wherein the semiconductor removal region comprises a surface of the first multilayer wiring layer of the first semiconductor wafer unit that is lower than a surface of the semiconductor substrate of the first semiconductor wafer unit. A method of fabricating a semiconductor component configured as a backside illuminated solid state imaging device, comprising: bonding two or more semiconductor wafers to each other, including at least one of the pixel arrays and a first multilayer wiring Forming a first semiconductor wafer in a region serving as a first semiconductor wafer unit and a logic circuit thereof and a second multilayer wiring layer forming one of the regions serving as a second semiconductor wafer unit a semiconductor wafer; forming a semiconductor removal region by completely removing a first semiconductor substrate that serves as a portion of the region of the first semiconductor wafer unit in the first semiconductor wafer, wherein the semiconductor removal region a surface of the first multilayer wiring layer including the first semiconductor wafer unit, which is lower than a surface of the semiconductor substrate of the first semiconductor wafer unit; forming the first semiconductor wafer connected to the semiconductor removal region a plurality of connection wirings of the unit and the second semiconductor wafer unit; and dividing the semiconductor wafers formed into a finished product into a plurality of wafers. The method of claim 13, wherein the forming the connection wiring comprises: forming a connection hole and wearing a first connection pad connected to one of the first multilayer wiring layers connected to the first semiconductor wafer unit Passing through the first semiconductor wafer unit and reaching the connection to the second semiconductor wafer a through connection hole of one of the second connection pads of the second multilayer wiring layer; and forming a connection connection to the first connection pad and the second connection in the connection hole and the through connection hole respectively One of the pads is a first connecting conductor and a through connecting conductor, and forms a second connecting conductor connecting the first connecting conductor and the through connecting conductor to each other. The method of claim 14, further comprising: after the forming the semiconductor removal region, extending from an exposed surface of the semiconductor removal region to a surface of the semiconductor wafer in which the pixel array is formed A protective insulating film serving as one of an anti-reflection film is formed. The method of claim 15, wherein the first connection pad is formed of a first layer of metal of the first multilayer wiring layer, and wherein the wiring connected to the first connection pad is made of a second layer of metal A layer of metal is formed later. The method of claim 15, further comprising: after forming the protective insulating film, an insulating film is buried in the semiconductor removal region; and forming the connection hole and the through connection hole penetrating the insulating film . An electronic device comprising: a solid-state imaging element; an optical system that directs incident light to one of the solid-state imaging elements; a signal processing circuit that processes a signal output from the solid state imaging device, wherein the solid state imaging device configured as a backside illuminated solid state imaging device comprises: a stacked semiconductor component by two or two Forming a plurality of semiconductor wafer units bonded to each other, and forming at least one pixel array and a first multilayer wiring layer in the first semiconductor substrate in the stacked semiconductor element are formed in a first semiconductor wafer unit and a logic circuit and a second multilayer wiring layer are formed in a second semiconductor wafer unit, a semiconductor removal region, wherein the first semiconductor substrate of a portion of the first semiconductor wafer unit is removed in the semiconductor removal region Removing, wherein the semiconductor removal region includes a surface of the first multilayer wiring layer of the first semiconductor wafer unit, which is lower than a surface of the semiconductor substrate of the first semiconductor wafer unit, and a plurality of connection wirings Formed in the semiconductor removal region and connected to the first semiconductor wafer unit and the second semiconductor wafer unit. The electronic device of claim 18, wherein in the solid imaging element, a protective insulating film serving as an anti-reflection film is formed to extend from an exposed surface of the semiconductor removal region to a pixel in which the semiconductor array is formed a surface of the substrate, wherein the plurality of connection wires comprise: a first connection conductor connected to a first connection pad, the first connection a pad is connected to one of the first plurality of wiring layers in the first semiconductor wafer unit, a through connection conductor penetrating the first semiconductor wafer unit and connected to a second connection pad, the second The connection pad is connected to one of the wirings of the second multilayer wiring layer in the second semiconductor wafer unit, and a second connection conductor that connects the first connection conductor and the through connection conductor to each other. The electronic device of claim 19, wherein the solid state imaging device comprises: an insulating film buried in the semiconductor removal region, and the first connection conductor and the through connection conductor penetrating the insulating film. The electronic device of claim 19, wherein the solid-state imaging device comprises an array of connection pads, wherein the first connection pads and the second connection pads each having an octagonal shape in the connection pad array are horizontally and vertically Alternately disposed, and the first connection pad and the second connection pad pair disposed along the horizontal direction are disposed in a plurality of stages along the vertical direction, wherein an area of the second connection pad is set to be larger than an area of the first connection pad And wherein the wires respectively corresponding to the vertical signal lines are connected to the first connection pads and the second connection pad pairs configured in the plurality of stages. The electronic device of claim 18, wherein the connection wires comprise: a first connection conductor connected to a first connection pad, the first connection pad being connected to the first plurality of layers in the first semiconductor wafer unit wiring One of the wirings inside the layer, a through connecting conductor penetrating the first semiconductor wafer unit and connected to a second connection pad, the second connection pad being connected to the second multilayer wiring in the second semiconductor wafer unit One of the wirings inside the layer, and a second connecting conductor that connects the first connecting conductor and the through connecting conductor to each other. The electronic device of claim 22, wherein the solid-state imaging device comprises an array of connection pads, wherein the first connection pads and the second connection pads each having an octagonal shape in the connection pad array are horizontally and vertically The direction of the first connection pad and the second connection pad disposed along the horizontal direction are arranged in a plurality of stages along the vertical direction, wherein an area of the second connection pad is set to be larger than the first connection pad The area, and the wiring corresponding to the vertical signal line, respectively, is connected to the first connection pad and the second connection pad pair configured in the plurality of stages. The electronic device of claim 22, wherein the solid-state imaging device comprises: a connection pad array, wherein the first connection pad and the second connection pad disposed along a vertical direction in the connection pad array are along the vertical direction and a horizontal Directional configuration, and the first connection pads and the second connection pad pairs are arranged in a plurality of stages along the vertical direction, wherein the wires respectively corresponding to the vertical signal lines are connected to the first connections configured in the plurality of stages The pad is paired with the second connection pad. The electronic device of claim 18, wherein the semiconductor removal region comprises the first A surface of one of the first plurality of wiring layers of the semiconductor wafer unit, which is lower than a surface of the semiconductor substrate of the first semiconductor wafer unit. A semiconductor device comprising: a stacked semiconductor device formed by bonding two or more semiconductor wafer units to each other, and at least one first semiconductor integrated circuit and one in the stacked semiconductor device a plurality of wiring layers are formed in a first semiconductor wafer unit, and a second semiconductor integrated circuit and a second multilayer wiring layer are formed in a second semiconductor wafer unit; and a semiconductor removal region, a first semiconductor substrate of one of the first semiconductor wafer units is completely removed in the semiconductor removal region; and a plurality of connection wirings, wherein the plurality of connection wirings comprise a first connection conductor, a through connection conductor, and Electrically connecting the upper end of the first connecting conductor and the through connecting conductor to one of the second connecting conductors, and wherein the plurality of connecting wires are formed in the semiconductor removing region and the first semiconductor wafer unit and the second The semiconductor wafer units are connected to each other. The semiconductor device of claim 26, wherein the first connection conductor is electrically connected to a first connection pad, the first connection pad being connected to one of the first plurality of wiring layers in the first semiconductor wafer unit And wherein the through-connection conductor penetrates the first semiconductor wafer unit and is electrically connected to a second connection pad, and the second connection pad is connected to one of the interior of the second multilayer wiring layer in the second semiconductor wafer unit wiring. The semiconductor component of claim 27, further comprising: a connection pad array, wherein the first connection pad and the second connection pad in the connection pad array each have an octagonal shape and are alternately arranged in a horizontal direction and a vertical direction, and are disposed first along the horizontal direction The connection pad and the second connection pad pair are arranged in a plurality of stages along the vertical direction, wherein the area of the second connection pad is larger than the area of the first connection pad, and wherein the wires respectively corresponding to the vertical signal lines are connected to The first connection pads and the second connection pad pairs of the plurality of stages are configured. The semiconductor device of claim 27, further comprising: a connection pad array, wherein the first connection pad and the second connection pad pair disposed along a vertical direction in the connection pad array are disposed along the vertical direction and a horizontal direction, And the first connection pads and the second connection pad pairs are arranged in a plurality of stages along the vertical direction, wherein the wires respectively corresponding to the vertical signal lines are connected to the first connection pads and the first plurality of stages arranged in the plurality of stages Two connection pad pairs. A semiconductor device comprising: a first semiconductor segment including a pixel region and a first wiring layer at one side of the first semiconductor segment; and a second semiconductor segment included in the first a second wiring layer at one side of the second semiconductor segment, the first semiconductor segment and the second semiconductor segment being separated by an individual first wiring layer of the first semiconductor segment and the second semiconductor segment And the second wiring layer side faces and are fixed together; a conductive material including a first connecting conductor and a through connecting guide And a second connecting conductor electrically connecting the upper end of the first connecting conductor and the through connecting conductor, wherein the through connecting conductor extends to the second wiring of the second semiconductor section via the first semiconductor section a layer, and wherein the conductive material is disposed to electrically connect the first wiring layer and the second wiring layer; a thin film region which is a portion of the first semiconductor segment and compared to the pixel of the first semiconductor segment The zone is thinner; wherein the electrically conductive material is located in the film zone.