KR101918293B1 - Semiconductor device, manufacturing method thereof, and electronic apparatus - Google Patents

Abstract

A semiconductor device of the present invention is a semiconductor device comprising: a laminated semiconductor chip in which at least two semiconductor chip parts are laminated, at least a pixel array and a multilayer wiring layer are formed in a first semiconductor chip part, and a logic circuit and a multilayer wiring layer are formed in a second semiconductor chip part A semiconductor removing region in which a part of the semiconductor portion of the first semiconductor chip portion is completely removed; and a plurality of connecting portions formed in the semiconductor removing region and connecting the first semiconductor chip portion and the second semiconductor chip portion Wiring, and is configured as a back-illuminated solid-state imaging device.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device, a manufacturing method thereof, and an electronic device.

The present invention relates to a semiconductor device such as a solid-state imaging device, a manufacturing method thereof, and an electronic apparatus such as a camera provided with the solid-state imaging device.

As the solid-state imaging device, an amplifying solid-state imaging device typified by a MOS type image sensor such as CMOS (Complementary Metal Oxide Semiconductor) is known. Further, a charge transfer type solid-state imaging device typified by a CCD (Charge Coupled Device) image sensor is known. These solid-state imaging devices are widely used in digital still cameras, digital video cameras, and the like. 2. Description of the Related Art In recent years, as a solid-state imaging device mounted on a mobile device such as a camera-equipped cellular phone or a PDA (Personal Digital Assistants), a MOS type image sensor is widely used because of low power supply voltage and power consumption.

The MOS type solid-state image pickup device includes a pixel array (pixel region) in which a unit pixel is formed of a photodiode and a plurality of pixel transistors that are photoelectric conversion units, the plurality of unit pixels are arranged in a two-dimensional array, Respectively. The plurality of pixel transistors are formed of MOS transistors and are composed of four transistors including a transfer transistor, a reset transistor, three transistors of an amplification transistor, or a selection transistor.

Conventionally, in such a MOS solid-state image pickup device, a solid-state image pickup device in which a semiconductor chip in which a pixel array in which a plurality of pixels are arranged and a semiconductor chip in which a logic circuit for signal processing is formed are electrically connected to each other to constitute one device, There are suggestions. For example, Japanese Patent Laid-Open Publication No. 2006-49361 discloses a back-illuminated type image sensor chip having a micro pad for each pixel cell, a signal processing chip having a signal processing circuit and a micro pad, And a semiconductor module connected thereto.

WO2006 / 129762 discloses a semiconductor image sensor in which a first semiconductor chip having an image sensor, a second semiconductor chip having an analog / digital converter array, and a third semiconductor chip having a memory element array are stacked, A sensor module is disclosed. The first semiconductor chip and the second semiconductor chip are connected through bumps which are conductive connecting conductors. The second semiconductor chip and the third semiconductor chip are connected to each other by a through contact penetrating the second semiconductor chip.

As disclosed in Japanese Patent Application Laid-Open No. 2006-49361, various techniques have been proposed for mixing heterogeneous circuit chips such as an image sensor chip and a logic circuit for performing signal processing. In the prior art, through-hole connection holes are formed in a state in which the functional chips are almost completed, and the chips are connected to each other, or the chips are connected to each other through bumps.

The applicant of the present application has previously proposed a semiconductor device in which a semiconductor chip portion having a pixel array and a semiconductor chip portion having a logic circuit are stuck together so that their performance can be sufficiently exhibited to achieve high performance, An imaging device is proposed. This solid-state imaging device is a semiconductor device in which a first semiconductor chip portion having a pixel array in a semi-finished product state and a second semiconductor chip portion having a logic circuit are brought into contact with each other to thin the first semiconductor chip portion, . The connection includes a connection conductor for connecting to a required wiring of the first semiconductor chip portion, a through conductor for passing through the first semiconductor chip portion to the required wiring of the second semiconductor chip portion, and a connection conductor for connecting both connection conductors Thereby forming a connection wiring. Thereafter, the solid state image pickup device is formed into a finished product and then formed into a chip.

Incidentally, in this solid-state imaging device, the connection conductors and the through-connection conductors are formed so as to be embedded in the through holes passing through the silicon substrate of the first semiconductor chip portion through the insulating film. The connecting conductors and the through-hole connecting conductors have a relatively large cross sectional area. Therefore, when the parasitic capacitance formed between the connection conductors and the through-hole connecting conductors and the silicon substrate can not be ignored, this parasitic capacitance causes a decrease in the driving speed of the circuit, and a factor of hindering high performance in the solid- Respectively.

In the solid-state imaging device having a structure in which the semiconductor chip portions to be connected are connected by a connecting conductor and a through-hole connecting conductor, a pair of the above-mentioned conductors (connecting conductors and through- Conductor) is connected. At this time, the ground capacitance and the adjacent coupling capacitance are generated as the parasitic capacitance. For example, the ground capacitance is the parasitic capacitance between the wiring and the semiconductor substrate which is the ground potential. The adjacent coupling capacitance is the parasitic capacitance between neighboring routing wirings or between neighboring pairs of conductors. The ground capacity can be solved by energizing the power supply or by providing a buffer circuit to allow current to flow. However, the adjacent coupling capacity can not be solved because it is interference with the adjacent column.

The problem of such a parasitic capacitance can also occur in a semiconductor device in which semiconductor chip portions each having a semiconductor integrated circuit are stuck together, and between the both semiconductor chip portions are connected by a connecting conductor and a through-hole connecting conductor.

SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to provide a semiconductor device, such as a solid-state imaging device, and a method of manufacturing the semiconductor device, in which parasitic capacitance is reduced and high performance is achieved. The present invention also provides an electronic apparatus such as a camera provided with the solid-state imaging device.

A semiconductor device according to the present invention is a semiconductor device comprising a semiconductor chip having a plurality of semiconductor chips, at least a first semiconductor chip having a pixel array and a multilayer wiring layer formed thereon, and a second semiconductor chip having a logic circuit and a multi- Respectively. The first semiconductor chip portion has a semiconductor removing region in which a part of the semiconductor portion is completely removed. The semiconductor device of the present invention is configured as a back-illuminated solid-state imaging device having a plurality of connection wirings for connecting the first semiconductor chip portion and the second semiconductor chip portion in the semiconductor removal region.

In the semiconductor device of the present invention, a semiconductor removal region in which a part of the semiconductor portion of the first semiconductor chip on which the pixel array is formed is entirely formed, and a connection wiring for connecting between the first and second semiconductor chip portions in the semiconductor removal region . Thus, the parasitic capacitance between the connection wiring and the semiconductor can be reduced.

A manufacturing method of a semiconductor device according to the present invention has a step of bonding two semiconductor wafers including at least a first semiconductor wafer and a second semiconductor wafer. In the first semiconductor wafer, a pixel array and a multilayer wiring layer are formed in a region where the first semiconductor chip is added. In the second semiconductor wafer, a logic circuit and a multilayer wiring layer are formed in a region where the second semiconductor chip is added. Next, there is a step of forming a semiconductor removing region by removing all the semiconductor portions of a region of the first semiconductor wafer to which the first semiconductor chip is to be attached. A step of forming a plurality of connection wirings for connecting between the first semiconductor chip portion and the second semiconductor chip portion in the semiconductor removal region and a step of forming a chip into a finished product to form a chip, .

In the method of manufacturing a semiconductor device according to the present invention, a semiconductor portion of a part of a first semiconductor chip portion in which a pixel array is formed is entirely removed after two or more semiconductor wafers are bonded, Thereby forming connection wirings for connecting between the second semiconductor chip portions. Thereby, the back-illuminated solid-state imaging device in which the parasitic capacitance between the connection wiring and the semiconductor is reduced is manufactured.

An electronic apparatus according to the present invention includes a solid-state imaging device, an optical system for guiding incident light to the photoelectric conversion portion of the solid-state imaging device, and a signal processing circuit for processing an output signal of the solid-state imaging device. The solid-state imaging device has a laminated semiconductor chip in which at least two semiconductor chip portions are laminated, at least a pixel array and a multilayer wiring layer are formed in the first semiconductor chip portion, and a logic circuit and a multilayer wiring layer are formed in the second semiconductor chip portion. The first semiconductor chip portion has a semiconductor removing region in which a part of the semiconductor portion is completely removed. The solid-state imaging device of the present invention is configured as a back-illuminated solid-state imaging device having a plurality of connection wirings connecting a first semiconductor chip portion formed in a semiconductor removal region and a second semiconductor chip portion.

In the electronic apparatus of the present invention, the back-illuminated solid-state imaging device having the above-described configuration is provided as the solid-state imaging device. Therefore, in the solid-state imaging device, the parasitic capacitance between the semiconductor and the connecting wiring connecting between the first and second semiconductor chip portions can be reduced.

A semiconductor device according to the present invention is a semiconductor device in which two or more semiconductor chip portions are fused together and at least a first semiconductor integrated circuit and a multilayer wiring layer are formed on a first semiconductor chip portion and a second semiconductor integrated circuit And a multilayer wiring layer formed thereon. The first semiconductor chip portion has a semiconductor removing region in which a part of the semiconductor portion is completely removed. Further, the semiconductor device of the present invention has a plurality of connection wirings for connecting the first semiconductor chip portion formed in the semiconductor removal region and the second semiconductor chip portion.

In the semiconductor device of the present invention, a semiconductor removing region in which a part of the semiconductor portion of the first semiconductor chip portion is completely removed is formed, and between the first and second semiconductor chip portions in each of which the semiconductor integrated circuit is formed, A connection wiring is formed. Thus, the parasitic capacitance between the connection wiring and the semiconductor can be reduced.

According to the semiconductor device of the present invention, since the parasitic capacitance between the semiconductor device and the connection wiring connecting between the first and second semiconductor chip portions is reduced, the back-illuminated solid- can do.

According to the semiconductor device manufacturing method of the present invention, it is possible to reduce the parasitic capacitance between the semiconductor device and the connection wiring connecting between the first and second semiconductor chip parts, and it is possible to provide a high- An imaging device can be manufactured.

According to the electronic apparatus according to the present invention, by providing the back-illuminated solid-state imaging device with an attached chip, which has reduced parasitic capacitance and achieves high performance, it is possible to provide an electronic apparatus such as a high-quality camera.

According to the semiconductor device of the present invention, the parasitic capacitance between the semiconductor and the connection wiring connecting the first and second semiconductor chip portions is reduced, so that the performance of the semiconductor integrated circuit device by the flip chip can be improved .

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic structural view showing an example of a MOS solid-state imaging device to which the present invention is applied; Fig.
Figs. 2A to 2C are schematic diagrams of a solid-state imaging device according to an embodiment of the present invention and a solid-state imaging device according to a conventional example; Fig.
3 is a schematic structural view of a main part showing a solid-state imaging device according to a first embodiment of the present invention;
Fig. 4 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the first embodiment (manufacturing step 1). Fig.
Fig. 5 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the first embodiment (manufacturing step 2). Fig.
6 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the first embodiment (manufacturing step 3).
Fig. 7 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the first embodiment (manufacturing step 4). Fig.
Fig. 8 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the first embodiment (manufacturing step 5). Fig.
Fig. 9 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the first embodiment (manufacturing step 6). Fig.
10 is a manufacturing process chart (manufacturing step 7) showing a manufacturing method example of the solid-state imaging device according to the first embodiment;
11 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the first embodiment (manufacturing step 8).
12 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the first embodiment (manufacturing step 9).
Fig. 13 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the first embodiment (manufacturing step 10). Fig.
Fig. 14 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the first embodiment (manufacturing step 11). Fig.
15A and 15B are schematic plan views showing positions of semiconductor removing regions according to the present invention;
16 is a schematic configuration view of a main portion showing a solid-state imaging device according to a second embodiment of the present invention;
Fig. 17 is a manufacturing process chart showing a manufacturing method example of the solid-state imaging device according to the second embodiment (manufacturing step 1). Fig.
Fig. 18 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the second embodiment (manufacturing step 2). Fig.
Fig. 19 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the second embodiment (manufacturing step 3). Fig.
Fig. 20 is a manufacturing process chart showing a manufacturing method example of the solid-state imaging device according to the second embodiment (manufacturing step 4). Fig.
Fig. 21 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the second embodiment (manufacturing step 5). Fig.
Fig. 22 is a manufacturing process chart (manufacturing process 6) showing a manufacturing method example of the solid-state imaging device according to the second embodiment. Fig.
23 is a manufacturing process chart (manufacturing step 7) showing a manufacturing method example of the solid-state imaging device according to the second embodiment;
Fig. 24 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the second embodiment (manufacturing step 8). Fig.
25 is a schematic configuration view of a main portion showing a solid-state imaging device according to a third embodiment of the present invention;
Fig. 26 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the third embodiment (manufacturing step 1). Fig.
Fig. 27 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the third embodiment (manufacturing step 2). Fig.
28 is a manufacturing process chart (manufacturing step 3) showing a manufacturing method example of the solid-state imaging device according to the third embodiment;
Fig. 29 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the third embodiment (manufacturing step 4). Fig.
30 is a manufacturing process diagram showing a manufacturing method example of the solid-state imaging device according to the third embodiment (manufacturing step 5).
31 is a schematic structural view of a main part showing a solid-state imaging device according to a fourth embodiment of the present invention;
32 is a schematic cross-sectional view taken along the line XXXII-XXXII of Fig. 31;
33 is a schematic cross-sectional view taken along line XXXIII-XXXIII of FIG. 31;
34 is an exploded plan view showing the first connection pad in Fig.
35 is an exploded plan view showing the second connection pad in Fig. 31;
36 is a schematic structural view of a main portion showing a solid-state imaging device according to a fifth embodiment of the present invention;
37 is a schematic structural view of a main portion showing a solid-state imaging device according to a sixth embodiment of the present invention;
38 is a schematic cross-sectional view taken along line XXXVIII-XXXVIII of FIG. 37;
39 is a schematic configuration view of a main portion showing a solid-state imaging device according to a seventh embodiment of the present invention;
40 is a schematic structural view showing a semiconductor device according to an eighth embodiment of the present invention;
41 is a schematic structural view showing a semiconductor device according to a ninth embodiment of the present invention;
42 is a schematic structural view showing a semiconductor device according to a tenth embodiment of the present invention;
43 is a schematic configuration view showing another example of the solid-state imaging device to which the layout of the connection pads according to the present invention is applied;
44 is a schematic plan view showing a layout example of connection pads in the solid-state imaging device of Fig. 43;
45 is a schematic structural view showing another example of a semiconductor device to which a layout of connection pads according to the present invention is applied;
FIG. 46 is a schematic plan view showing a layout example of a connection pad in the semiconductor device of FIG. 45; FIG.
47 is a schematic configuration view showing an embodiment of a solid-state imaging device having a protection diode according to the present invention;
48 is a schematic sectional view of a main part showing an example of a region of a connection wiring according to the present invention;
49 is a schematic cross-sectional view taken along line XXXXIX-XXXXIX of FIG. 48;
50 is a schematic cross-sectional view of a main part showing an example of a region of a neighboring connecting conductor according to the present invention;
51 is a schematic cross-sectional view of a main portion showing a region configuration example of a neighboring through-hole conductor according to the present invention;
FIG. 52 is a schematic view showing the insertion position of a connection wiring between semiconductor chips according to the present invention on a circuit; FIG.
53 is a schematic structural view showing an electronic apparatus according to an eleventh embodiment of the present invention;

Hereinafter, a mode for carrying out the invention (hereinafter referred to as an embodiment mode) will be described. The description will be made in the following order.

1. Outline of MOS solid-state imaging device

2. First Embodiment (Configuration Example of Solid-State Imaging Device and Example of Manufacturing Method Thereof)

3. Second Embodiment (Configuration Example of Solid-State Imaging Device and Example of Manufacturing Method Thereof)

4. Third Embodiment (Configuration Example of Solid-State Imaging Device and Example of Manufacturing Method Thereof)

5. Fourth Embodiment (Configuration example of solid-state imaging device)

6. Fifth Embodiment (Configuration Example of Solid-State Imaging Device)

7. Sixth Embodiment (Configuration example of solid-state imaging device)

8. Seventh Embodiment (Configuration example of solid-state imaging device)

9. Eighth embodiment (Configuration example of semiconductor device)

10. Ninth embodiment (Configuration example of semiconductor device)

11. Tenth Embodiment (Configuration example of semiconductor device)

12. Eleventh Embodiment (Configuration Example of Electronic Apparatus)

1. Outline of MOS solid-state imaging device

Fig. 1 shows a schematic configuration of a MOS solid-state image pickup device applied to a semiconductor device of the present invention. This MOS solid-state imaging device is applied to the solid-state imaging device of each embodiment. As shown in Fig. 1, the solid-state imaging device 1 of the present embodiment is a solid-state imaging device in which pixels 2 including a plurality of photoelectric conversion portions are regularly arranged in a two-dimensional array on a semiconductor substrate 11, for example, a silicon substrate A pixel array (so-called pixel region) 3, and a peripheral circuit portion. The pixel 2 includes, for example, a photodiode as a photoelectric conversion section and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors may be composed of three transistors, for example, a transfer transistor, a reset transistor and an amplifying transistor. In addition, a selection transistor may be added to constitute four transistors. Since the equivalent circuit of the unit pixel is a general configuration, detailed description is omitted. The pixel 2 can be configured as one unit pixel. The pixel 2 may have a shared pixel structure. This pixel sharing structure is composed of a plurality of photodiodes, a plurality of transfer transistors, one floating diffusion to be shared, and one pixel transistor sharing one another. That is, in the shared pixel, the photodiode and the transfer transistor constituting a plurality of unit pixels share one pixel transistor.

The peripheral circuit section is constituted by a vertical driving circuit 4, a column signal processing circuit 5, a horizontal driving circuit 6, an output circuit 7, a control circuit 8, and the like.

The control circuit 8 receives data for instructing the input clock, the operation mode, and the like, and also outputs data such as internal information of the solid-state image pickup device. In other words, in the control circuit 8, the criteria of the operation of the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6, etc. are determined based on the vertical synchronization signal, the horizontal synchronization signal, And generates a clock signal or a control signal. Then, these signals are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

The vertical drive circuit 4 is constituted by, for example, a shift register, selects a pixel drive wiring, supplies pulses for driving the pixels to the selected pixel drive wiring, and drives the pixels on a row-by-row basis. That is, the vertical drive circuit 4 selectively scans each pixel 2 of the pixel array 3 in the vertical direction sequentially in a row unit and supplies the vertical signal line 9 to the photoelectric conversion section 3 of each pixel 2, For example, a pixel signal based on the signal charge generated in response to the amount of light received by the photodiode, to the column signal processing circuit 5.

The column signal processing circuit 5 performs signal processing such as noise elimination for each pixel column of the signal output from the pixel 2 for each row, which is arranged for each column, for example, of the pixel 2. That is, the column signal processing circuit 5 performs signal processing such as CDS, signal amplification, and AD conversion for removing the fixed pattern noise inherent to the pixel 2. A horizontal selection switch (not shown) is provided between the horizontal signal line 10 and the output terminal of the column signal processing circuit 5.

The horizontal drive circuit 6 is constituted by, for example, a shift register and successively outputs horizontal scan pulses to sequentially select each of the column signal processing circuits 5, And outputs the pixel signal to the horizontal signal line 10. [

The output circuit 7 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 5 via the horizontal signal line 10 and outputs them. For example, only buffering may be performed, black level adjustment, column correction, various digital signal processing, and the like may be performed. The input / output terminal 12 exchanges signals with the outside.

Fig. 2 shows a basic schematic structure of a MOS solid-state image pickup device according to the present invention. 2A, a conventional MOS solid-state image pickup device 151 includes a pixel array 153, a control circuit 154, and a logic circuit 155 for signal processing in one semiconductor chip 152 ). Usually, the image sensor 156 is constituted by the pixel array 153 and the control circuit 154. 2B, the MOS solid-state image pickup device 20 according to the embodiment of the present invention includes a pixel array 23 and a control circuit 24 in the first semiconductor chip portion 22 And a logic circuit 25 including a signal processing circuit for signal processing the second semiconductor chip portion 26 is mounted. The first and second semiconductor chip portions 22 and 26 are electrically connected to each other to constitute a MOS solid-state image pickup device 20 as one semiconductor chip. 2C, the MOS solid-state image pickup device 21 according to another embodiment of the present invention is configured such that the pixel array 23 is mounted on the first semiconductor chip portion 22 and the second semiconductor chip portion 26, a control circuit 24 and a logic circuit 25 including a signal processing circuit are mounted. The first and second semiconductor chip portions 22 and 26 are electrically connected to each other to constitute a MOS solid-state image pickup device 21 as one semiconductor chip.

Although not shown, depending on the configuration of the MOS solid-state image pickup device, two or more semiconductor chip parts may be joined together. For example, in addition to the above-described first and second semiconductor chip portions, a semiconductor chip portion having a memory element array and a semiconductor chip portion having other circuit elements may be added so that three or more semiconductor chip portions are joined together, May be used as the MOS solid-state imaging device.

2. First Embodiment

Configuration Example of Solid-State Imaging Device

3 shows a first embodiment of a semiconductor device according to the present invention, that is, a MOS solid-state imaging device. The solid-state imaging device 28 according to the first embodiment includes a first semiconductor chip portion 22 in which a pixel array 23 and a control circuit 24 are formed and a second semiconductor chip portion 22 in which a logic circuit 25 is formed. And a laminated semiconductor chip 27 on which a semiconductor chip 26 is bonded. The first semiconductor chip portion 22 and the second semiconductor chip portion 26 are brought into contact with each other so that the multilayer wiring layers 41 and 55 face each other. In this example, the adhesion is made of the adhesive layer 57 through the protective films 42 and 56. In addition, plasma bonding may be used.

In this embodiment, a semiconductor removing region 52 is formed by completely removing the semiconductor portion of a part of the first semiconductor chip portion 22. In the semiconductor removing region 52, the first semiconductor chip portion 22, And a connection wiring 67 for connecting the second semiconductor chip portion 26 are formed. The semiconductor removing region 52 is an entire region including a portion where each connecting wiring 67 connected to the routing wiring 40d corresponding to each vertical signal line of the pixel array 23 is formed, And is formed outside the pixel array 23 as shown in Fig. The semiconductor removing region 52 corresponds to a so-called electrode pad region. 15A, a semiconductor removing region 52 is formed outside the pixel array 23 in the vertical direction.

The first semiconductor chip portion 22 includes a pixel array 23 composed of a photodiode PD and a plurality of pixel transistors Tr1 and Tr2 which are photoelectric conversion portions, A control circuit 24 composed of MOS transistors Tr3 and Tr4 is formed. The pixel transistors Tr1 and Tr2, and the MOS transistors Tr3 and Tr4 are respectively represented. On the surface 31a side of the semiconductor substrate 31 is formed a multilayered structure in which wiring 40 (40a, 40b, 40c) composed of a plurality of metal layers (M1 to M3) in this embodiment is disposed via an interlayer insulating film 39 A wiring layer 41 is formed. The pixel transistors Tr1 and Tr2 and the MOS transistors Tr3 and Tr4 of the control circuit 24 will be described in detail in the following manufacturing method.

In the second semiconductor chip portion 26, the logic circuit 25 composed of the MOS transistors Tr6 to Tr8 is formed on the second semiconductor substrate 45. [ On the surface 45a side of the semiconductor substrate 45 is formed a multilayered structure in which a plurality of wiring lines 53 (53a, 53b, 53c) made of three metal layers M11 to M13 in this example are arranged via an interlayer insulating film 49 A wiring layer 55 is formed. The MOS transistors Tr6 to Tr8 will be described in detail in the following manufacturing method.

In the semiconductor removing region 52 of the first semiconductor chip portion 22, the entirety of the first semiconductor substrate 31 is removed by, for example, etching. A laminated insulating film 61 made of, for example, a silicon oxide (SiO ₂ ) film 58 and a silicon nitride (SiN) film 59 is formed to extend from the bottom surface and the side surface of the semiconductor removing region 31 to the surface of the semiconductor substrate . The laminated insulating film 61 is a protective insulating film for protecting the semiconductor substrate 31 exposed on the side surface of the concave portion of the semiconductor removing region 52 and also serves as an antireflection film in a pixel.

In the semiconductor removing region 52, the routing wiring 40d formed of the silicon nitride film 59, the wiring of the multilayer wiring layer 41 in the first semiconductor chip portion 22, the third metal M3 in this example, A connection hole 64 reaching the first connection pad 65 electrically connected to the first connection pad 65 is formed. The required wiring of the multilayer wiring layer 55 in the second semiconductor chip portion 26 through the multilayer wiring layer 41 of the first semiconductor chip portion 22, in this example, by the third layer metal M13 And a through-hole 62 reaching the second connection pad 63 electrically connected to the routing wiring 53d is formed.

The connection wiring 67 includes a connection conductor 68 embedded in the connection holes 64 and 62 and electrically connected to the first connection pad 65 and a connection conductor 68 electrically connected to the second connection pad 63 Through conductor 69 and a connecting conductor 71 electrically connecting at the upper ends of both conductors 68 and 69. [

A light shielding film 72 is formed on the back surface 31b side of the first semiconductor chip portion 22 which becomes the light incident surface of the photodiode 34 and covers a region requiring light shielding. A planarization film 73 is formed so as to cover the light shielding film 72. An on chip color filter 74 is formed on the planarization film 73 to correspond to each pixel, State imaging device 28 is formed. The connection conductor 71 exposed to the outside of the connection wiring 67 becomes an electrode pad for connecting the external wiring with the bonding wire.

Example of Manufacturing Method of Solid State Imaging Device

4 to 14 show a manufacturing method of the solid-state imaging device 28 according to the first embodiment.

4, an image sensor in a semi-finished state, that is, a pixel array 23 and a control circuit 24 (hereinafter, referred to as " semiconductor substrate " ). That is, a photodiode PD, which is a photoelectric conversion portion of each pixel, is formed in a region where each chip of the semiconductor substrate (for example, a silicon substrate) 31 is provided, and a source of each pixel transistor / Drain region 33 is formed. The semiconductor well region 32 is formed by introducing a first conductivity type, for example, a p-type impurity, and the source / drain region 33 is formed by introducing an impurity of the second conductivity type, for example, . The photodiode PD and the source / drain region 33 of each pixel transistor are formed by ion implantation on the substrate surface.

The photodiode PD is formed with an n-type semiconductor region 34 and a p-type semiconductor region 35 on the substrate surface side. A gate electrode 36 is formed on the surface of the substrate constituting the pixel through the gate insulating film and the pixel transistors Tr1 and Tr2 are formed by the gate electrode 36 and the pair of source / In Fig. 4, a plurality of pixel transistors are represented by two pixel transistors Tr1 and Tr2. The pixel transistor Tr1 adjacent to the photodiode PD corresponds to the transfer transistor, and its source / drain region corresponds to the floating diffusion FD. Each unit pixel 30 is separated into an element isolation region 38. [ The element isolation region 38 is formed in a STI (Shallow Trench Isolation) structure in which an insulating film such as a SiO ₂ film is buried in a groove formed in a substrate, for example.

On the other hand, on the control circuit 24 side, a MOS transistor constituting a control circuit is formed on the semiconductor substrate 31. In Fig. 4, MOS transistors constituting the control circuit 23 are represented by MOS transistors Tr3 and Tr4. Each of the MOS transistors Tr3 and Tr4 is formed by an n-type source / drain region 33 and a gate electrode 36 formed through a gate insulating film.

Subsequently, a first-layer interlayer insulating film 39 is formed on the surface of the semiconductor substrate 31, a connection hole is formed in the interlayer insulating film 39, and a connection conductor 44 connecting to the required transistor is formed. . In forming the connection conductors 44 having different heights, a first insulating thin film 43a, for example, a silicon oxide film and a second insulating thin film 43b serving as an etching stopper are formed on the entire surface including the transistor upper surface, A silicon nitride film is laminated. A first-layer interlayer insulating film 39 is formed on the second insulating thin film 43b. Then, a connection hole having a different depth to the first interlayer insulating film 39 is selectively formed up to the second insulating thin film 43b serving as an etching stopper. Subsequently, a connection hole is formed by selectively etching the first insulating thin film 43a and the second insulating thin film 43b having the same film thickness at each portion so as to be continuous to the respective connection holes. Then, the connection conductors 44 are embedded in the respective connection holes.

Subsequently, wirings 40 (40a, 40b, 40c) made of metal (M1 to M3) in three layers in this embodiment, through the interlayer insulating film 39 are formed so as to be connected to the respective connecting conductors 44 A multilayer wiring layer 41 is formed. The wiring 40 is formed of copper (Cu). Normally, each copper wiring is covered with a barrier metal film for preventing Cu diffusion. For this reason, a cap film of copper wiring 40, a so-called protective film 42, is formed on the multilayer wiring layer 41. The first semiconductor substrate 31 having the pixel array 23 and the control circuit 24 in the semi-finished product state is formed by the processes up to now.

On the other hand, as shown in Fig. 5, a logic circuit 25 including a signal processing circuit for signal processing in the semi-finished product state is formed in a region where each chip of the second semiconductor substrate (semiconductor wafer) 45 is added do. That is, a plurality of MOS transistors constituting a logic circuit are formed in the p-type semiconductor well region 46 on the surface side of the semiconductor substrate (for example, the silicon substrate) 45 so as to be separated into the element isolation regions 50 . Here, a plurality of MOS transistors are represented by MOS transistors Tr6, Tr7, and Tr8. Each of the MOS transistors Tr6, Tr7 and Tr8 is formed with a pair of n-type source / drain regions 47 and a gate electrode 48 formed through a gate insulating film. In the logic circuit 25, a CMOS transistor can be used. The element isolation region 50 is formed in an STI structure in which an insulating film such as a SiO ₂ film is embedded in a groove formed in a substrate, for example.

Subsequently, a first interlayer insulating film 49 is formed on the surface of the semiconductor substrate 45, a connection hole is formed in the interlayer insulating film 49, and a connection conductor 54 connecting to the required transistor is formed. . At the time of forming the connection conductors 54 having different heights, a first insulating thin film 43a, for example, a silicon oxide film and a second insulating thin film (an insulating film) 43b, for example, a silicon nitride film. A first-layer interlayer insulating film 49 is formed on the second insulating thin film 43b. Then, a connection hole having a different depth to the first interlayer insulating film 39 is selectively formed up to the second insulating thin film 43b serving as an etching stopper. Subsequently, a connection hole is formed by selectively etching the first insulating thin film 43a and the second insulating thin film 43b having the same film thickness at each portion so as to be continuous to the respective connection holes. Then, the connection conductors 44 are embedded in the respective connection holes.

Subsequently, wirings 53 (53a, 53b, 53c) of three layers of metal (M11 to M13) in this embodiment are formed through the interlayer insulating film 49 so as to be connected to the respective connecting conductors 54 A multilayer wiring layer 55 is formed. The wiring 53 is formed of copper (Cu). A cap film of a copper wiring 53, a so-called protective film 56 is formed on the interlayer insulating film 49 in the same manner as described above. The second semiconductor substrate 45 having the logic circuit 25 in the semi-finished product state is formed by the above processes.

Next, as shown in Fig. 6, the first semiconductor substrate 31 and the second semiconductor substrate 45 are bonded so that the multilayer wiring layers 41 and 55 are opposed to each other. The interlacing is, for example, plasma bonding and bonding by an adhesive. In this example, an adhesive is used. 7, an adhesive layer 58 is formed on one of the bonding surfaces of the first and second semiconductor substrates 31 and 45, and the adhesive layer 58 is formed Overlay the two together. That is, the first and second semiconductor substrates 31 and 45 are bonded.

A plasma TEOS film, a plasma SiN film, a SiON film (block film), and a SiON film are formed on the bonding surfaces of the first semiconductor wafer 31 and the second semiconductor wafer 45, respectively, Or a film of SiC or the like is formed. The joint surfaces formed with this film are subjected to plasma treatment to overlap and then annealed to bond them together. It is preferable that the attaching process is performed by a low-temperature process at 400 DEG C or lower which does not affect the wiring or the like.

Next, as shown in Fig. 8, the first semiconductor substrate 31 is thinned by grinding and polishing from the backside 31b side of the first semiconductor substrate 31. Next, as shown in Fig. This thinning is performed so that the photodiodes PD face each other. After thinning, a p-type semiconductor layer for suppressing dark current is formed on the back surface of the photodiode PD. The thickness of the semiconductor substrate 31 is, for example, about 600 占 퐉, for example, to about 3 to 5 占 퐉. Conventionally, such thinning is performed by attaching separately prepared supporting substrates. However, in this embodiment, the first semiconductor substrate 31 is thinned by using the second semiconductor substrate 45 on which the logic circuit 25 is formed as a supporting substrate. When the back surface 31b of the first semiconductor substrate 31 is configured as a back-illuminated solid-state imaging device, it becomes a light incidence surface.

Next, as shown in Fig. 9, in the first and second semiconductor substrates 31 and 45 bonded together, a part of the semiconductor portion of the region where the first semiconductor chip is added after completion, that is, 31 are removed to form a semiconductor removing region 52. [ This semiconductor removing region 52 is an entire region including a portion where each connection wiring connected to the routing wiring 40d corresponding to each vertical signal line of the pixel array is formed. As shown in Fig. 15A, (23). In Fig. 15A, the semiconductor removing region 52 is formed outside the pixel array 23 in the vertical direction.

10, a silicon oxide (SiO ₂ ) film 58 (a silicon oxide film) is formed from the inner surface of the semiconductor removing region 52 to the back surface (light incident surface) of the control circuit 24 and the pixel array 23 And a silicon nitride (SiN) film 59 are deposited. The laminated insulating film 61 serves as a protective film for the semiconductor side surface of the semiconductor removing region 52 and also serves as an antireflection film in the pixel array 23.

11, a second semiconductor substrate 45 is formed through the multilayer wiring layer 41 of the first semiconductor substrate 31 from the laminated insulating film 61 in the semiconductor removing region 52. Then, The through-hole 62 reaching the second connection pad 63 connected to the wiring 53 of the multilayer wiring layer 55 is formed. The through hole 62 in this example reaches the second connection pad 63 electrically connected to the wiring 53d formed by the uppermost layer of the multilayer wiring layer, that is, the third metal M13. A plurality of through-hole connection holes 62 are formed corresponding to the vertical signal lines of the pixel array 23. The wiring 53d formed of the third layer metal M13 connected to the second connection pad 63 serves as a routing wiring corresponding to the vertical signal line. In the illustrated example, the second connection pad 63 is formed of the third-layer metal M13 and is formed continuously to the routing wiring 53d corresponding to the vertical signal line.

Next, as shown in FIG. 12, in the semiconductor removing region 52, a first insulating film 61 is formed, which is connected to the wiring 40 of the multilayer wiring layer 41 of the first semiconductor substrate 31, The connection holes 64 reaching the connection pads 65 of the connection pads 65 are formed. In this example, a connection hole 64 reaching the first connection pad 65 electrically connected to the wiring 40d by the third metal M3 of the multilayer wiring layer 41 is formed. A plurality of connection holes 64 are formed corresponding to the vertical signal lines of the pixel array 23. The wiring 40d formed of the third layer metal M3 connected to the first connection pad 65 serves as a routing wiring corresponding to the vertical signal line. In the illustrated example, the first connection pad 65 is formed of the third layer metal M3 and is formed continuously to the routing wiring 40d corresponding to the vertical signal line.

Next, as shown in Fig. 13, a connection wiring 67 for electrically connecting the first connection pad 65 and the second connection pad 63 is formed. That is, after the conductive film is formed on the back surface of the first semiconductor substrate 31 so as to be embedded in the both connection holes 62 and 64, the connection wiring 67 is formed by performing etchback and patterning. The connection wiring 67 includes a connection conductor 68 which is embedded in the connection hole 64 and connected to the first connection pad 65 and a connection conductor 68 which is embedded in the through hole 62 to be connected to the second connection pad 65 And a through-hole connecting conductor 69. The connecting wiring 67 has a connecting conductor 71 for electrically connecting the connecting conductor 68 and the through-hole connecting conductor 69 on the exposed lower surface of the semiconductor removing region. The connecting conductor 68, the through-hole connecting conductor 69 and the connecting conductor 71 are integrally formed of the same metal. The connection wiring 67 can be formed of tungsten (W) through a barrier metal (TiN or the like), or a patternable metal such as aluminum (Al) or gold (Au).

Next, as shown in Fig. 14, a light shielding film 72 is formed on a region to be shielded. The light-shielding film 72 is typically formed on the control circuit 24 in the figure, but it can also be formed on the pixel transistor. As the light shielding film 72, for example, a metal such as tungsten (W) can be used. A planarization film 73 is formed over the pixel array 23 so as to cover the light-shielding film 72. An on-chip color filter 74 of red (R), green (G), and blue (B) is formed on the flattening film 73 in correspondence with each pixel, (75). In the first semiconductor substrate 31, the pixel array 23 and the control circuit 25 are in a finished state. The connection conductor 71 of the connection wiring 67 becomes an electrode pad exposed to the outside. In the second semiconductor substrate 45, the logic circuit 25 becomes a finished product.

Subsequently, each chip is divided to obtain a desired back-illuminated solid-state imaging device 28 shown in Fig. The solid-state image pickup device 28 is connected to the external wiring by wire bonding with respect to the electrode pad by the connection conductor 71 of the connection wiring 67.

According to the solid-state imaging device and the manufacturing method thereof according to the first embodiment, the pixel array 23 and the control circuit 24 are formed in the first semiconductor chip portion 22, and the pixel array 23 and the control circuit 24 are formed in the second semiconductor chip portion 26 And forms a logic circuit 25 for signal processing. Since the functions of the pixel array and the logic functions are formed on different chip portions and are made to coincide with each other, optimum process techniques can be used for each of the pixel array 23 and the logic circuit 25. Therefore, the performance of each of the pixel array 23 and the logic circuit 25 can be sufficiently exhibited, and a high-performance solid-state imaging device can be provided.

In this embodiment, in particular, a part of the first semiconductor chip portion 22, that is, the semiconductor portion of the region where the connecting conductor and the through-hole conductor are formed is entirely removed. The connecting conductor 68 and the through-hole connecting conductor 69 are formed in the semiconductor removing region 52 from which the semiconductor portion is removed. Therefore, the connecting conductor 68 and the connecting conductor 69 are provided between the semiconductor substrate 31 The parasitic capacitance of the solid-state imaging device can be reduced, and the performance of the solid-state imaging device can be further improved.

Only the pixel array 23 that receives light may be formed on the side of the first semiconductor chip portion 22 and the control circuit 24 and the logic circuit 25 may be separately formed on the side of the second semiconductor chip portion 22, (Not shown). Thus, it is possible to independently select the optimum process technology for manufacturing the semiconductor chip portions 22 and 26, and reduce the area of the product module.

The first semiconductor substrate 31 having the pixel array 23 and the control circuit 24 and the second semiconductor substrate 45 having the logic circuit 25 are stuck together in a semi- And the first semiconductor substrate 31 is thinned. That is, the second semiconductor substrate 45 is used as a support substrate for thinning the first semiconductor substrate 31. Thereby, it is possible to save the member and reduce the manufacturing process.

Since the first semiconductor substrate 31 is thinned and the through hole 62 and the connection hole 64 are formed in the semiconductor removing region 52 from which the semiconductor portion is removed, The aspect ratio of the hole is reduced, and the connection holes 62 and 64 can be formed with high accuracy. Therefore, a high-performance solid-state imaging device can be manufactured with high accuracy.

3. Second Embodiment

Configuration Example of Solid-State Imaging Device

16 shows a second embodiment of a semiconductor device, i.e., a MOS solid-state imaging device, according to the present invention. The solid-state imaging device 78 according to the second embodiment includes a first semiconductor chip portion 22 in which a pixel array 23 and a control circuit 24 are formed and a second semiconductor chip portion 22 in which a logic circuit 25 is formed. And a laminated semiconductor chip 27 on which a semiconductor chip 26 is bonded. The first semiconductor chip portion 22 and the second semiconductor chip portion 26 are brought into contact with each other so that the multilayer wiring layers 41 and 55 face each other.

In the present embodiment, a semiconductor removing region 52 is formed by removing all of the semiconductor portions of the first semiconductor chip portion 22 from the inner surface of the semiconductor removing region 52 to the rear surface 31b of the semiconductor substrate 31 A laminated insulating film 61 is formed. A planarized insulating film 77 is formed in the semiconductor removing region so as to be flat on the surface of the laminated insulating film on the semiconductor substrate 31. The insulating film 77 has an etching rate different from that of the silicon nitride film 59 on the front surface side of the laminated insulating film 61. For example, the insulating film 77 is formed of an insulating film such as a silicon oxide film.

A connection hole 64 and a through hole 62 reaching the first connection pad 65 and the second connection pad 63 are formed through the insulating film 77, 64 and 62. The connection wiring 67 connects the first and second connection pads 65 and 63 to each other. The connection wiring 67 includes a connection conductor 68 electrically connected to the first connection pad 65 so as to fill in the connection holes 64 and 62 and a connection conductor 68 electrically connected to the second connection pad 63 And a connecting conductor 71 for electrically connecting the two conductors 68 and 69 at the upper end thereof. The connecting conductor 68, the through-hole connecting conductor 69 and the connecting conductor 71 are integrally formed by the required metal. The connection conductors 71 are formed on the planarized insulating film 77.

Since the other structures are the same as those described in the first embodiment, the same reference numerals are given to the parts corresponding to those in Fig. 3, and redundant description is omitted.

Example of Manufacturing Method of Solid State Imaging Device

17 to 24 show a manufacturing method of the solid-state imaging device 78 according to the second embodiment.

Fig. 17 shows the structure of Fig. 10 in the manufacturing process of the solid-state imaging device 28 of the first embodiment described above. The process leading to FIG. 17 is the same as the process shown in FIG. 4 to FIG. 10 described above, so that detailed description is omitted.

17, a silicon oxide (SiO ₂ ) film 58 and a silicon nitride (SiO ₂ ) film are formed from the inner surface of the semiconductor removing region 52 to the back surface (light incident surface) of the control circuit 24 and the pixel array 23 SiN) film 59 is formed by deposition.

18, an insulating film 77 such as a silicon oxide film, for example, is deposited on the entire back surface of the semiconductor substrate 31 so as to fill the inside of the semiconductor removing region 52. Next, as shown in Fig.

Next, as shown in Fig. 19, the insulating film 77 is polished to a required thickness by a chemical mechanical polishing (CMP) method.

20, the insulating film 77 is etched up to the silicon nitride film 59 by a wet etching method using hydrofluoric acid, and is planarized to have a flat surface with the silicon nitride film 59. Next, as shown in Fig. At this time, the silicon nitride film 59 becomes an etching stopper film.

Next, as shown in Fig. 21, in the semiconductor removing region 52, a wiring line (not shown) is formed in the multilayer wiring layer 55 of the second semiconductor substrate 45 through the insulating film 77 and the multilayer wiring layer 41 (62) reaching the second connection pad (63) connected to the second connection pad (53d). The through-hole 62 in this example is connected to the second connection pad 63 electrically connected to the wiring 53d formed by the uppermost layer of the multilayer wiring layer 55, that is, the third metal M13, It reaches. A plurality of through-hole connection holes 62 are formed corresponding to the vertical signal lines of the pixel array 23. The wiring 53d formed of the third layer metal M13 connected to the second connection pad 63 serves as a routing wiring corresponding to the vertical signal line. In the illustrated example, the second connection pad 63 is formed of the third-layer metal M13 and is formed continuously to the routing wiring 53d corresponding to the vertical signal line.

22, a connection hole 64 reaching the first connection pad 65 from the insulating film 77 is formed in the semiconductor removal region 52. Then, as shown in Fig. The connection hole 64 in this example reaches the second connection pad 65 electrically connected to the wiring 40d by the third metal M3 of the multilayer wiring layer 41. [ A plurality of connection holes 64 are formed corresponding to the vertical signal lines of the pixel array 23. The wiring 40d formed of the third layer metal M3 connected to the first connection pad 65 serves as a routing wiring corresponding to the vertical signal line. In the illustrated example, the first connection pad 65 is formed of the third layer metal M3 and is formed continuously to the routing wiring 40d corresponding to the vertical signal line.

Next, as shown in Fig. 23, a connection wiring 67 for electrically connecting the first connection pad 65 and the second connection pad 63 is formed. That is, a conductive film is formed on the insulating film 77 and the entire back surface of the first semiconductor substrate 31 so as to be embedded in the both connection holes 62 and 64, and etched back and patterned to form the connection wiring 67, . The connection wiring 67 includes a connection conductor 68 which is embedded in the connection hole 64 and connected to the first connection pad 65 and a connection conductor 68 which is embedded in the through hole 62 to be connected to the second connection pad 65 And a through-hole connecting conductor 69. The connecting wiring 67 has a connecting conductor 71 for electrically connecting the connecting conductor 68 and the through-hole connecting conductor 69 on the planarized insulating film 77. The connecting conductor 68, the through-hole connecting conductor 69 and the connecting conductor 71 can be integrally formed of the same metal film as the conductive film. The connection wiring 67 can be formed of tungsten (W) through a barrier metal (TiN or the like), or a patternable metal such as aluminum (Al) or gold (Au).

Next, as shown in Fig. 24, a light shielding film 72 is formed on a region to be shielded. The light-shielding film 72 is typically formed on the control circuit 24 in the figure, but it can also be formed on the pixel transistor. As the light shielding film 72, for example, a metal such as tungsten (W) can be used. A planarization film 73 is formed over the pixel array 23 so as to cover the light-shielding film 72. An on-chip color filter 74 of red (R), green (G), and blue (B) is formed on the flattening film 73 in correspondence with each pixel, (75). In the first semiconductor substrate 31, the pixel array 23 and the control circuit 25 are in a finished state. The connection conductor 71 of the connection wiring 67 becomes an electrode pad exposed to the outside. In the second semiconductor substrate 45, the logic circuit 25 becomes a finished product.

Subsequently, each chip is divided to obtain a desired back-illuminated solid-state image pickup device 78 shown in Fig.

The solid-state imaging device 78 according to the second embodiment and the manufacturing method thereof can be used as the semiconductor device in the region where the first semiconductor chip portion 22, that is, the connecting conductor 68 and the through- And the insulating film 77 is buried in the removed semiconductor removing region 52. The connection conductors 68 and 69 are connected to the insulating film 77 since the connection holes 64 formed in the insulating film 77 and the connection conductors 68 and the through-hole conductors 69 are buried in the through- The parasitic capacitance between the connecting conductors 68 and 69 and the semiconductor substrate 31 can be reduced. Since the semiconductor removing region 52 is filled with the insulating film 77, the surface of the semiconductor substrate 31 that comes in contact with the sidewall of the semiconductor removing region 52 cooperates with the laminated insulating film 61 to mechanically and reliably protect can do. Therefore, the performance of the solid-state imaging device can be improved.

Since the first semiconductor substrate 31 is made thinner to form the through hole 62 and the connection hole 64 in this embodiment, the aspect ratio of the hole is reduced and the connection holes 62 and 64 are formed with high accuracy, 64 can be formed. Therefore, a high-performance solid-state imaging device can be manufactured with high accuracy.

In addition, although the explanation is omitted, the same effect as described in the first embodiment is obtained.

4. Third Embodiment

Configuration Example of Solid-State Imaging Device

Fig. 25 shows a third embodiment of the semiconductor device, that is, the MOS solid-state imaging device according to the present invention. The solid-state imaging device 82 according to the third embodiment includes a first semiconductor chip portion 22 in which a pixel array 23 and a control circuit 24 are formed and a second semiconductor chip portion 22 in which a logic circuit 25 is formed. And a laminated semiconductor chip 27 on which a semiconductor chip 26 is bonded. The first semiconductor chip portion 22 and the second semiconductor chip portion 26 are brought into contact with each other so that the multilayer wiring layers 41 and 55 face each other.

In the present embodiment, a semiconductor removing region 52 is formed by completely removing the semiconductor portion of a part of the first semiconductor chip portion 22. The semiconductor removing region 52 is formed from the inner surface of the semiconductor removing region 52 to the back surface of the semiconductor substrate 31 A laminated insulating film 61 is formed. A planarized insulating film 77 which is a flat surface with the surface of the laminated insulating film 61 on the semiconductor substrate 31 is formed in the semiconductor removing region 52 and a planarized insulating film 77 corresponding to the connecting wiring 67 of the insulating film 77 A concave portion 81 having a depth required from the surface is formed in the portion. The insulating film 77 is formed of an insulating film such as a silicon oxide film whose etch rate is different from that of the silicon nitride film 59 on the front surface side of the laminated insulating film 61, for example.

A connection hole 64 and a through hole 62 reaching the first connection pad 65 and the second connection pad 63 are formed through the insulating film 77 under the concave portion 81 . And a connection wiring 67 for connecting between the first and second connection pads 65 and 63 through the both connection holes 64 and 62 is formed. The connection wiring 67 includes a connection conductor 68 electrically connected to the first connection pad 65 so as to fill in the connection holes 64 and 62 and a connection conductor 68 electrically connected to the second connection pad 63 And a connecting conductor 71 for electrically connecting the two conductors 68 and 69 at the upper end thereof. The connecting conductor 68, the through-hole connecting conductor 69 and the connecting conductor 71 are integrally formed by the required metal. The connecting conductor 71 is embedded in the concave portion 81 of the insulating film 77 and the surface of the connecting conductor 71 is formed to be flat on the surface of the insulating film 77.

Since the other structures are the same as those described in the first embodiment, the same reference numerals are given to the parts corresponding to those in Fig. 3, and redundant description is omitted.

Example of Manufacturing Method of Solid State Imaging Device

26 to 30 show a manufacturing method of the solid-state imaging device 82 according to the third embodiment.

Fig. 26 shows the structure as shown in Fig. 20 in the manufacturing process of the solid-state imaging device 78 of the second embodiment described above. The process leading to Fig. 26 is the same as the process from Fig. 17 to Fig. 20 via Fig. 4 to Fig. 10 described above, and thus the detailed description will be omitted.

26, after the insulating film 77 is deposited so as to fill the semiconductor removing region 52, the surface of the insulating film 77 is removed by chemical mechanical polishing (CMP) and wet etching to remove the surface of the laminated insulating film 61 And flattened to be flat.

Next, as shown in Fig. 27, a concave portion 81 having a depth required from the surface is formed on the surface side of the insulating film 77, corresponding to the region where the connection wiring 67 is to be formed.

Next, as shown in Fig. 28, a through-hole 62 penetrating through the insulating film 77 and the multilayer wiring layer 41 under the concave portion 81 and reaching the second connection pad 63 is formed. The through-hole 62 of this example is electrically connected to the metal of the uppermost layer of the multilayer wiring layer 55 of the second semiconductor chip 26, that is, the wiring 53d of the third metal M13, And reaches the second connection pad 63 which is the second connection pad. A plurality of through-hole connection holes 62 are formed corresponding to the vertical signal lines of the pixel array 23. The wiring 53d connected to the second connection pad 63 serves as a routing wiring corresponding to the vertical signal line. In the illustrated example, the second connection pad 63 is formed of the third-layer metal M13 and is formed continuously to the routing wiring 53d corresponding to the vertical signal line.

A connection hole 64 reaching the first connection pad 65 from the insulating film 77 under the recessed portion 81 is formed in the semiconductor removal region 52. [ The connection hole 64 of this example is connected to the second connection pad 65 electrically connected to the wiring 40d by the third metal M3 of the multilayer wiring layer 41 of the first semiconductor chip portion 22 It reaches. A plurality of connection holes 64 are formed corresponding to the vertical signal lines of the pixel array 23. The third-layer metal wiring 40c connected to the first connection pad 65 becomes the routing wiring corresponding to the vertical signal line. In the illustrated example, the first connection pad 65 is formed of the third layer metal M3 and is formed continuously to the routing wiring 40d corresponding to the vertical signal line.

Next, as shown in Fig. 29, a connection wiring 67 for electrically connecting the first connection pad 65 and the second connection pad 63 is formed. That is, a conductive film is formed on the insulating film 77 and on the entire surface of the back surface of the semiconductor substrate 31, so as to be embedded in the concave portion 81 and both the connection holes 62 and 64, Wiring 67 is formed. The connection wiring 67 includes a connection conductor 68 which is embedded in the connection hole 64 and connected to the first connection pad 65 and a connection conductor 68 which is embedded in the through hole 62 to be connected to the second connection pad 65 And a through-hole connecting conductor 69. The connecting wire 67 has a connecting conductor 71 for electrically connecting the connecting conductor 68 and the through-hole conductor 69 to each other. The connecting conductor 71 is embedded in the concave portion 81 and is planarized so as to be flat on the surface of the insulating film 77. The connecting conductor 68, the through-hole connecting conductor 69 and the connecting conductor 71 can be integrally formed of the same metal film as the conductive film. Since the connection wiring 67 is formed of an etch-back, it can be formed of copper (Cu). The connection wiring 67 can be formed of a metal such as tungsten (W) or aluminum (Al) or gold (Au) through a barrier metal (TiN or the like).

Next, as shown in Fig. 30, a light shielding film 72 is formed on a region to be shielded. The light-shielding film 72 is typically formed on the control circuit 24 in the figure, but it can also be formed on the pixel transistor. As the light shielding film 72, for example, a metal such as tungsten (W) can be used. A planarization film 73 is formed over the pixel array 23 so as to cover the light-shielding film 72. An on-chip color filter 74 of red (R), green (G), and blue (B) is formed on the flattening film 73 in correspondence with each pixel, (75). In the first semiconductor substrate 31, the pixel array 23 and the control circuit 25 are in a finished state. The connection conductor 71 of the connection wiring 67 is an electrode pad exposed to the outside. In the second semiconductor substrate 45, the logic circuit 25 becomes a finished product.

Subsequently, each chip is divided to obtain a desired back-illuminated solid-state imaging device 82 shown in Fig.

According to the solid-state imaging device and the manufacturing method thereof according to the third embodiment, all of the semiconductor portions of the region where the first semiconductor chip portion 22, that is, the connecting conductor 68 and the through-hole conductor 69 are formed, And the insulating film 77 is buried in the removed semiconductor removing region 52. A concave portion 81 is formed in the insulating film 77 and a connecting hole 64 formed in the insulating film 77 under the concave portion 81 and a connecting conductor 68 and a through- The conductor 69 is embedded. The both connecting conductors 68 and 69 are separated from the side surface of the semiconductor substrate 31 by the insulating film 77 and the parasitic capacitance between the connecting conductors 68 and 69 and the semiconductor substrate 31 can be reduced . Since the semiconductor removing region 52 is filled with the insulating film 77, the surface of the semiconductor substrate 31 that comes in contact with the sidewall of the semiconductor removing region 52 cooperates with the laminated insulating film 61 to mechanically and reliably protect can do. Therefore, the performance of the solid-state imaging device can be improved.

Since the connecting conductor 71 is embedded in the concave portion 81 of the insulating film 77 and the connecting conductor 71 is flattened to be flat on the surface of the insulating film 77, can do.

In the third embodiment, the first semiconductor substrate 31 is made thinner and the recessed portion 81 is formed in the insulating film 77 to form the through-hole 62 and the connection hole 64 Therefore, the aspect ratio of the hole becomes smaller, and the connection holes 62 and 64 can be formed with high accuracy. Therefore, a high-performance solid-state imaging device can be manufactured with high accuracy.

In addition, although the explanation is omitted, the same effect as described in the first embodiment is obtained.

In the second and third embodiments described above, the configuration of Fig. 2C may be employed.

In each of the above-described embodiments, the two semiconductor chip portions 22 and 26 are joined together. Further, the solid-state imaging device of the present invention may have a configuration in which two or more semiconductor chip portions are mated. The connection between the first semiconductor chip portion 22 having the pixel array 23 and the second semiconductor chip portion 26 having the logic circuit 25 for signal processing can be achieved The above-described configuration in which the semiconductor portion is completely removed is applied.

In the above-described structure in which the semiconductor chip portion is attached, parasitic capacitance such as a ground capacitance and an adjacent coupling capacitance is generated. Particularly, since the connecting conductors 68 and the through-hole conductors 69 have a large surface area, it is desirable to reduce the adjacent coupling capacitance between adjacent connecting conductors of a column, Do. Here, the term " connecting conductor spacing " refers to the distance between the adjacent connecting conductors when the connecting conductor 68 and the through-hole connecting conductor 69 are paired. On the other hand, the area and pitch of the first connection pad 65 and the area and pitch of the second connection pad 63 are larger than the pixel area and the pixel pitch, and thus a layout that can be practically used is desired.

Next, a reduction in the adjacent coupling capacity of the pair and a practically usable layout are explained according to one embodiment.

5. Fourth Embodiment

Configuration Example of Solid-State Imaging Device

31 to 35 show a fourth embodiment of the semiconductor device, that is, the MOS solid-state imaging device according to the present invention. This drawing shows only the layout of a wiring connection portion including a connection pad for electrically connecting between the first and second semiconductor chip portions. 31 is a plan view of the connection pad array, Fig. 32 is a sectional view taken along line XXXII-XXXII of Fig. 31, and Fig. 33 is a sectional view taken along line XXXIII-XXXIII of Fig. 34 and 35 are exploded plan views of Fig.

In the solid-state imaging device 84 according to the fourth embodiment, two semiconductor chip portions 22 and 26 are stuck together, and a semiconductor portion of a part of the first semiconductor chip portion 22 is removed , And between the semiconductor chip portions 22 and 26 via the connection wiring 67 in the semiconductor removing region 52. In the present embodiment, any configuration other than the layout of the wiring connection portions can be applied to any one of the above-described embodiments, and thus the detailed description thereof will be omitted.

In the fourth embodiment, the wiring 40 (40a, 40b, 40c, 40d) of the multilayer wiring layer 41 in the first semiconductor chip portion 22 is composed of a plurality of layers M4). The first connection pad 65 is formed of the first layer metal M1 and the routing wiring 40d corresponding to the vertical signal line is formed of the second layer or later metal. In this example, the routing wiring 40d corresponding to the vertical signal line is formed of the fourth layer metal M4. The wiring 53 (53a, 53b, 53c, 53d) of the multilayer wiring layer 55 in the second semiconductor chip portion 26 is formed of a plurality of layers (M11 to M14) . The second connection pad 63 is formed of the second or later layer, for example, the third or fourth layer, in this example, the fourth layer M14 of the uppermost layer. The routing wiring 53d corresponding to the vertical signal line is formed of a metal lower than the metal M14 of the connection pad 63, that is, the first layer metal M11 in this example. In the first semiconductor chip portion 22, the first connection pad 65 formed of the first-layer metal is electrically connected to the second-layer and third-layer metal via the connecting portion 85 and the via conductor 86, And is electrically connected to the routing wiring 40d by the metal. In the second semiconductor chip portion 26, the second connection pad 63 formed of the fourth layer metal is connected to the first connection pad 63 via the connection portion 87 formed by the third layer and the second layer metal and the via conductor 88, And is electrically connected to the routing wiring 53d by metal.

The second connection pad 63 is formed in a wider area than the first connection pad 65 in consideration of any misalignment of the first and second semiconductor chip portions 22 and 26. The first and second connection pads 65 and 63 forming a pair are collectively referred to as a connection pad pair 89.

Normally, vertical signal lines are arranged for each pixel pitch. However, if the pixel pitch is made finer, the pitch of the connection pad pairs 89 becomes relatively larger than the pixel pitch, and wiring becomes difficult. At the same time, the vertical signal lines are densely arranged, and the capacity of the adjacent coupling between the vertical signal lines becomes large, resulting in inconvenience. The present embodiment is a layout of a connection wiring and a vertical signal line for avoiding it. It is preferable that the large ground capacitance in one vertical signal line, one connection conductor, or one through-hole connection conductor is 20 fF or less. In order to avoid the streaking phenomenon, it is preferable that the adjacent coupling capacitance is about 1/10 or less of the large ground capacitance, that is, 2fF or less.

The first and second connection pads 65 and 63 are formed into an octagonal shape, preferably a tetragonal shape when viewed in a plan view. The first and second connection pads constituting the connection pad pair 89 are arranged in the horizontal direction. The plurality of connection pad pairs 89 are arranged in a plurality of rows in the horizontal direction in which the routing wirings 40d and 53d are arranged and arranged in a plurality of stages in the vertical direction. That is, first and second connection pads 65 and 63, which are regular hexagons, are alternately arranged in the horizontal direction and the vertical direction, respectively, at the wiring connection portions of both semiconductor chip portions 22 and 26. Here, a plurality of connection pad pairs 89 are arranged in the horizontal direction, and a connection pad array 91 formed by arranging the connection pad pairs 89 in four stages in the vertical direction is constituted. Here, an octagon is defined. The octagonal first connection pad 65 may have a protruding connection portion 65a for partially protruding in order to provide connection with the routing wiring 40d (see FIG. 32). The shape in this case falls into the category of octagonal because the amount of protrusion is small in terms of the total octagonal shape.

In the connection pad array 91, the first and second connection pads 65 and 63 are densely arranged, for example, in a plan view. The first and second connection pads 65 and 63 may be arranged so that they partially overlap each other. A connection conductor 71 connected to the first and second connection pads 65 and 63 and a connection conductor 68 connected to the first and second connection pads 65 and 63, The first and second semiconductor chip portions 22 and 26 are electrically connected to each other through the connection wirings 67. [ The connecting conductor 68 and the through-hole conductor 69 can be formed so that their cross-sectional shapes are octagonal to the planar shapes of the corresponding connection pads 65 and 63, respectively. The connection wiring 67 in this example is formed in the same manner as in the third embodiment. That is, the insulating film 77 is buried in the semiconductor removing region 52, and the connecting conductor 65 and the through-hole connecting conductor 63 are formed so as to penetrate the insulating film 77. The surface of the connecting conductor 71 becomes the insulating film 77 and the flat surface thereof.

The routing wirings 40d and 53d corresponding to the vertical signal lines in each of the four rows are connected to the first and second connection pads 65 and 63 of the four connection pad pairs 89 . In the first semiconductor chip portion 22, the first connection pad 65 is formed of the metal M1 of the first layer, and each of the routing wirings 40d is formed of metal of the other layers, in this example, Metal M4. Therefore, the routing wiring 40d can be wired across the first connection pad 65, and the distance between neighboring routing wirings 40d can be widened. Similarly, in the second semiconductor chip portion 26, the second connection pad 63 is formed of the fourth layer metal M14, and each routing wiring 53d is formed of a metal of the other layers, that is, 1 Layer metal M11. Therefore, the routing wiring 53d can be wired so as to cross under the second connection pad 63, so that the distance between the neighboring routing wirings 53d can be widened.

In this embodiment, a plurality of columns of vertical signal lines corresponding to the plurality of stages of connection pad pairs 89 in the vertical direction are laid out within one pitch P of the horizontal directions of the connection pad pairs 89. 31, routing wirings 40d and 53d corresponding to the four vertical signal lines corresponding to the four stages of the connection pad pairs 89 in the vertical direction are arranged in one pitch P of the connection pad pairs 89 Respectively.

The solid-state imaging device 84 according to the fourth embodiment has the first and second connection pads 65 and 63 formed in an octagonal planar shape, and the first and second connection pads 65 And 63 are arranged alternately densely in the horizontal and vertical directions. That is, a dense connection pad array 91 is formed at the wiring connection portions of the both semiconductor trenches 22, 26. The routing wirings 40d and 52d corresponding to the vertical signal lines in each of the four columns are connected to the four connection pad pairs 89 of the connection pad array 91. Therefore, The interval between the adjacent coupling portions 53d is widened, and the adjacent coupling capacity can be reduced. Further, since the insulating film 77 is present between the pair of adjacent connecting conductors, the capacity of the adjacent coupling between the pair of connecting conductors can be reduced.

Since the connection conductor 68 is connected to the connection pad 65 made of the first layer metal M1 in the first semiconductor chip portion 22, the depth of the connection hole is shortened, And the connection conductor 68 can be easily inserted.

The area of the connection pad 63 of the second semiconductor chip portion 26 is formed larger than the area of the connection pad 65 of the first semiconductor chip portion 22 side in the connection pad pair 89. [ The position of the connection hole 64 in the first semiconductor chip portion 22 and the connection pad 65 can be precisely adjusted based on the alignment mark formed on the first semiconductor chip portion 22. [ On the other hand, when the first semiconductor chip portion 22 and the second semiconductor chip portion 26 are mated with each other, there is a fear that the misalignment may be caught. However, since the area of the connection pad 63 is large, And the connection pad 63 can be aligned with each other. Thus, as described above, connection pads 65 and 63 can be connected to the connection conductor 64 and the through-hole conductor 69 even if there is a misalignment.

Since the connection pad pairs 89 of the two rows and four columns are alternately arranged in the horizontal and vertical directions so as to reverse the directions of the large and small connection pads 63 and 65, . This makes it possible to route the routing wiring even if the pixel pitch becomes finer with the miniaturization of the pixel.

In the configuration in which the pair of first and second connection pads 65 and 63 are arranged in the horizontal direction, a configuration in which first and second paired first and second connection pads 65 and 63 are arranged in the vertical direction The difference in wiring resistance due to the difference in wiring length in the routing wiring of four columns is smaller.

The areas and pitches of the connection pads 65 and 63 are larger than the area and pitch of the pixels but the routing of the wirings 40d and 53d becomes possible by arranging the connection pads 65 and 63 as described above , A high-performance solid-state imaging device can be provided.

Even in the fourth embodiment, the adjacent coupling capacitance can likewise be reduced by employing the configuration of the connection wiring 67 of the first and second embodiments.

The fourth embodiment has the same effects as those described in the first to third embodiments.

6. Fifth Embodiment

Configuration Example of Solid-State Imaging Device

Fig. 36 shows a fifth embodiment of the semiconductor device, that is, the MOS solid-state imaging device according to the present invention. This drawing shows only the layout of the wiring connection portion including the connection pads 65 and 63 for electrically connecting between the first and second semiconductor chip portions 22 and 26.

In the solid-state imaging device 93 according to the fifth embodiment, the two semiconductor chip portions 22 and 26 are brought into contact with each other, the semiconductor portion of a part of the first semiconductor chip portion 22 is removed , And between the semiconductor chip portions 22 and 26 via the connection wiring 67 in the semiconductor removing region 52. In the present embodiment, any configuration other than the layout of the wiring connection portions can be applied to any one of the above-described embodiments, and thus the detailed description thereof will be omitted.

In the fifth embodiment, the connection pad arrays 91A and 91B are arranged on both outer sides opposing each other in the vertical direction with the pixel array 23 sandwiched therebetween, and the connection pad arrays 91A and 91B are alternately arranged vertically And the routing wirings 40d and 53d corresponding to the signal lines are connected. 31, a pair of connection pads 89 in which first and second connection pads 65 and 63 are arranged in a horizontal direction are arranged in a plurality of rows in the vertical direction, In the example, they are arranged in two stages. The connection pad pairs 89 of each of the connection pad arrays 91A and 91B are arranged, for example, densely. Then, the routing wirings 40d and 53d of the upper and lower rows are alternately connected to the connection pad pairs 89 of the two ends of the connection pad arrays 91A and 91B by two columns. Both connection pad arrays 91A and 91B are formed in the semiconductor removal regions 52a and 52b shown in Fig. 15B.

36, the planar shape of the connection pads 65 and 63 is an octagonal shape, preferably a hexagonal shape. However, the width of the wiring lines can be increased, Hexagonal). The present embodiment can also be applied to a configuration in which the connection pad pairs 89 are replaced with connection pad pairs in which first and second connection pads 65 and 63 to be described later are arranged in the vertical direction.

According to the solid-state imaging device 93 of the fifth embodiment, the connection pad arrays 91A and 91B sandwich and arrange the pixel array 23, and the routing wiring corresponding to the vertical signal line is divided into a plurality of columns, And is connected to two connection pad pairs 89 of two connection pads arrays 91A and 91B alternately for each column. With this configuration, it is not necessary to make the spaces between the neighboring routing wirings 40d and the routing wirings 53d too small. In other words, the space between adjacent routing wirings 40d and the routing wirings 53d can be widened with a margin. Therefore, the adjacent coupling capacity can be reduced. Further, the wiring length between the routing wirings becomes smaller, and the wiring resistance difference can be further reduced.

The area and pitch of the connection pads 65 and 63 are larger than the area and pitch of the pixels. However, routing of the wirings 40d and 53d becomes possible by arranging the layout of the connection pads as described above, Device can be provided.

Even in the fifth embodiment, the adjacent coupling capacity can be reduced similarly by adopting the configuration of the connection wiring of the first, second, and third embodiments.

The fifth embodiment achieves the effects described in the first to third embodiments in addition to the above.

7. Sixth Embodiment

Configuration Example of Solid-State Imaging Device

37 and 38 show a sixth embodiment of the semiconductor device, that is, the MOS solid-state image pickup device according to the present invention. This drawing shows only the layout of the wiring connection portion including the connection pads 65 and 63 for electrically connecting between the first and second semiconductor chip portions 22 and 26.

In the solid-state imaging device 95 of the sixth embodiment, two semiconductor chip portions 22 and 26 are stuck together, a semiconductor portion of a part of the first semiconductor chip portion 22 is removed, The semiconductor chip portions 22 and 26 are connected to each other through the connection wiring 67 in the semiconductor removing region 52. In the present embodiment, any configuration other than the layout of the wiring connection portions can be applied to any one of the above-described embodiments, and thus the detailed description thereof will be omitted.

In the sixth embodiment, for example, a connection pad array 91 in which the first and second connection pads 65 and 63 of regular octagonal shape as shown in Fig. 31 are alternately arranged vertically and horizontally is formed, Routing wirings 40d and 53d for every four columns are connected to connection pad pairs 89 of four stages of the connection pad array 91. [ The first connection pad 65 of the first semiconductor chip portion 22 is formed of the first metal M1 and the routing wiring 40d connected to the connection pad 65 is connected to the fourth metal layer M4). The second connection pad 63 of the second semiconductor chip portion 26 is formed of the fourth metal M14 and the routing wiring 53d connected to the connection pad 63 is formed of a metal M11).

The routing wiring 40d in the first semiconductor chip portion 22 is wired across the other first connection pad 65 which is not connected. There is a possibility that a coupling capacitance is generated between the routing wirings 40d having different potentials across the connection pads 65 because the connection pad 65 has a relatively large area. For this reason, in the present embodiment, between the first connection pad 65 and the required routing wiring 40d, a metal layer of the layer between the first connection pad 65 and the routing wiring 40d A shield wiring 96 is formed. That is, between the first connection pad 65 and the routing wiring 40d, a shield wiring 96 composed of a metal M2 of the second layer or the third layer, that is, the second layer in this example, is formed. 38, since the three routing wirings 40d may be crossed under the first connection pad 65, the shield wirings 96 may have a width corresponding to the width of the connection pads 65 And is formed continuously to each of the four connection pad pairs 89. [

Although not shown, the routing wiring 53d in the second semiconductor chip portion 26 is wired across the other second connection pad 63 which is not connected. Since the second connection pad 63 has a large area, there is a possibility that a coupling capacitance is generated between the routing wirings 53d having different potentials across the connection pad 63. [ Therefore, the metal shield wiring of the layer between the second connection pad 63 and the routing wiring 53d is formed between the second connection pad 63 and the required routing wiring 53d. That is, between the second connection pad 63 and the routing wiring 53d, shield wirings of the third layer or the second layer, that is, the third layer metal M13 in this example, are formed. Since the three routing wirings 53d may cross under the second connection pad 63, the shield wiring may have a width corresponding to the width of the connection pad 63, 89 as shown in Fig.

According to the solid-state imaging device of the sixth embodiment, by the shielding wiring 96 disposed between the first connection pad 65 and the routing wiring 40d across the connection pad 65 , The generation of coupling capacitance between the connection pads 65 having different potentials and the routing wiring 40d is avoided. The connection pads 63 and the routing wirings 53d with different potentials are connected by the shield wiring disposed between the second connection pads 63 and the routing wirings 53d across the connection pads 63 The generation of coupling capacity is avoided. Therefore, the performance of the solid-state imaging device can be further improved.

In the sixth embodiment, other effects such as reduction in parasitic capacitance as described in the first to third embodiments are achieved.

In the sixth embodiment, the effect of the shield wiring 96 is achieved regardless of the planar shape of the connection pad 65 or the layout of the connection pad 65.

8. Seventh Embodiment

Configuration Example of Solid-State Imaging Device

Fig. 39 shows a seventh embodiment of the semiconductor device, that is, the MOS solid-state imaging device according to the present invention. This drawing shows only the layout of the wiring connection portion including the connection pads 65 and 63 for electrically connecting between the first and second semiconductor chip portions 22 and 26.

The solid-state imaging device 97 according to the seventh embodiment is configured such that the two semiconductor chip portions 22 and 26 are stuck together and the semiconductor portion of a part of the first semiconductor chip portion 22 is removed , And between the semiconductor chip portions 22 and 26 via the connection wiring 67 in the semiconductor removing region 52. In the present embodiment, any configuration other than the layout of the wiring connection portions can be applied to any one of the above-described embodiments, and thus the detailed description thereof will be omitted.

In the seventh embodiment, the paired first and second connection pads 65 and 63 are arranged in the vertical direction (so-called longitudinal direction) in which the routing wirings 40d and 53d corresponding to the vertical signal lines extend . A plurality of connection pad pairs 99 are arranged in the horizontal direction in which the routing wirings 40d and 53d are arranged and arranged in three stages in the vertical direction so that the connection pad array 98 is configured do.

The first and second connection pads 65 and 63 are formed, for example, in an octagonal shape, preferably a square octagonal shape in plan view, as described in the fourth embodiment. The first and second connection pads 65 and 63 are connected to each other via the connection wiring 67 made up of the connection conductor 68, the through conductor 69 and the connection conductor 71 And is electrically connected.

In the first semiconductor chip portion 22, the wiring 40 of the multilayer wiring layer 41 can be composed of a plurality of layers, for example, four layers of metal (M1 to M4). It is preferable that the first connection pad 65 is formed of the first metal M1 and the routing wiring 40d connected to the connection pad 65 is formed of the fourth metal M4 Do. In addition, the first connection pad 65 and the routing wiring 40d may be formed of any layer of metal.

In the second semiconductor chip portion 26, the wiring 53 of the multilayer wiring layer 55 can be composed of a plurality of layers, for example, four layers of metal (M11 to M14). It is preferable that the second connection pad 63 is formed of the fourth metal M14 and the routing wiring 53d connected to the connection pad 63 is formed of the first metal M11 Do. In addition, the second connection pad 63 and the routing wiring 53d may be formed of any layer of metal. The routing wirings 40d and 53d are connected to the connection pad pairs 99 of the three stages of the connection pad array 98 by three columns.

The solid-state image pickup device 97 according to the seventh embodiment has the connection pad array (the connection pad array) in which the connection pad pairs 99 in which the first and second connection pads 65 and 63 are arranged in the vertical direction are arranged in plural stages 98), routing of the wirings 40d, 53d becomes possible. Particularly, even if the connection pads 65 and 63 are larger than the pixel area, routing of the wirings 40d and 53d becomes possible, and a high-performance solid-state imaging device can be provided. When the routing wirings 40d and 53d are arranged to cross the connection pads 65 and 63, respectively, the adjacent routing wirings can be widened with a margin, and the adjacent coupling capacity occurring between the routing wirings can be reduced have.

Even in the seventh embodiment, the adjacent coupling capacitance can be reduced similarly by adopting the configuration of the connection wiring of the first, second, and third embodiments.

The seventh embodiment achieves the effects described in the first to third embodiments.

In the above example, the planar shape of the connection pads 65 and 63 is an octagonal shape. Alternatively, a polygonal shape such as a quadrangle, a hexagon (preferably, a hexagonal shape), a circle, or the like can be used. The cross-sectional shape of the connecting conductor 68 and the through-hole conductor 69 can be formed to have a planar shape of the connection pads 65 and 63. The planar shape of the connection pads 65 and 63 and the cross-sectional shape of the connection conductor 68 and the through-hole conductor 69 may be different from each other.

In the solid-state imaging device according to the above-described embodiment, the signal charge is electron, the first conductivity type is p-type, and the second conductivity type is n-type. However, . In this case, the conductivity type of each semiconductor substrate, the semiconductor well region, or the semiconductor region is reversed, and the n-type is the first conductivity type and the p-type is the second conductivity type. An n-channel transistor and a p-channel transistor can also be applied to a MOS transistor in a logic circuit.

9. Eighth Embodiment

Configuration Example of Semiconductor Device

Fig. 40 shows an eighth embodiment of the semiconductor device according to the present invention. The semiconductor device 131 according to the eighth embodiment is configured with the first semiconductor chip portion 101 and the second semiconductor chip portion 116 with the laminated semiconductor chip 100 interposed therebetween. In the first semiconductor chip portion 101, a first semiconductor integrated circuit and a multilayer wiring layer are formed. In the second semiconductor chip portion 116, a second semiconductor integrated circuit and a multilayer wiring layer are formed. The first semiconductor chip portion 101 and the second semiconductor chip portion 116 are brought into contact with each other so that the multilayer wiring layers are opposed to each other. In this embodiment, the adhesion is performed by the adhesive layer 129 through the protective films 114 and 127. In addition, plasma bonding may be used.

In this embodiment, a semiconductor removing region 52 is formed by removing all the semiconductor portions of a part of the first semiconductor chip 101. A connection wiring 67 for connecting the first semiconductor chip portion 101 and the second semiconductor chip portion 116 is formed in the semiconductor removal region 52. [ The semiconductor removing region 52 is an entire region including a portion where each connection wiring 67 of the semiconductor integrated circuit is formed and is formed in the peripheral portion of the semiconductor chip portion 101, for example.

In the first semiconductor chip 101, a first semiconductor integrated circuit, in this example, the logic circuit 102, is formed on the thinned first semiconductor substrate 103. That is, a plurality of MOS transistors Tr11, Tr12, and Tr13 are formed in a semiconductor well region 104 formed in a semiconductor substrate (for example, a silicon substrate) Each of the MOS transistors Tr11 to Tr13 has a pair of source / drain regions 105 and a gate electrode 106 formed through a gate insulating film. Each of the MOS transistors Tr11 to Tr13 is separated by the element isolation region 107. [

The MOS transistors Tr11 to Tr13 are represented by representations. The logic circuit 102 may be a CMOS transistor. Therefore, the plurality of MOS transistors can be configured as an n-channel MOS transistor or a p-channel transistor. Therefore, when an n-channel MOS transistor is formed, a source / drain region is formed in the p-type semiconductor well region. When a p-channel MOS transistor is formed, a p-type source / drain region is formed in the n-type semiconductor well region.

On the semiconductor substrate 103, a multilayer wiring layer 111 in which a plurality of layers (in this example, three layers of metal-made wirings 109) are stacked is formed by using an interlayer insulating film 108. [ The wiring 109 may be a Cu wiring, for example. Each of the MOS transistors Tr11 to Tr13 is connected to the required first layer wiring 109 via the connection conductor 112. [ Further, the three layers of wirings 109 are interconnected through a connecting conductor.

In the second semiconductor chip portion 116, a second semiconductor integrated circuit, in this example, the logic circuit 117, is formed on the second semiconductor substrate 118. That is, a plurality of MOS transistors Tr21, Tr22, and Tr23 are formed in a semiconductor well region 119 formed in a semiconductor substrate (for example, a silicon substrate) Each of the MOS transistors Tr21 to Tr23 has a pair of source / drain regions 121 and a gate electrode 122 formed through a gate insulating film. Each of the MOS transistors Tr21 to Tr23 is separated by the element isolation region 123. [

The MOS transistors Tr21 to Tr23 are shown as representatives. The logic circuit 117 can be composed of a CMOS transistor. Therefore, the plurality of MOS transistors can be configured as an n-channel MOS transistor or a p-channel transistor. Therefore, when an n-channel MOS transistor is formed, a source / drain region is formed in the p-type semiconductor well region. When a p-channel MOS transistor is formed, a p-type source / drain region is formed in the n-type semiconductor well region.

On the semiconductor substrate 118, a multilayer wiring layer 126 is formed in which a plurality of wiring lines 125 made of metal, in this embodiment, three layers, are laminated via an interlayer insulating film 124. The wiring 125 may be, for example, a Cu wiring. Each of the MOS transistors Tr21 to Tr23 is connected to the required first layer wiring 125 through the connection conductor 120. [ The three wiring layers 125 are connected to each other via the connection conductor 120. The semiconductor substrate 118 of the second chip portion 116 also serves as a support substrate of the thinned first semiconductor chip portion 101.

The first semiconductor integrated circuit may be a semiconductor memory circuit instead of the logic circuit 102, for example. In this case, the logic circuit 117 serving as the second semiconductor integrated circuit is provided for signal processing of the semiconductor memory circuit.

In the semiconductor removing region 52, all of the first semiconductor substrate 118 is removed by, for example, etching. The bottom surface of the semiconductor removal area 52, to extend from the side surface to the surface of the semiconductor substrate 118, for example, layered insulating film by a silicon oxide (SiO ₂₎ film 58 and a silicon nitride (SiN) film 59 ( 61 are formed. The laminated insulating film 61 protects the semiconductor substrate 118 exposed on the surface of the semiconductor substrate 118 and the side surface of the semiconductor removing region 52.

The semiconductor removing region 52 is electrically connected to the required wiring of the multilayer wiring 111 in the first semiconductor chip portion 101 from the silicon nitride film 59, A connection hole 64 reaching the first connection pad 65 is formed. It is also possible to use a wiring which is electrically connected to the required wiring of the multilayer wiring layer 126 in the second semiconductor chip portion 116 through the first semiconductor chip portion 101, A through-hole 62 reaching the connection pad 63 of the second connection pad 62 is formed.

The connection wiring 67 is provided with a connection conductor 68 connected to the first connection pad 65 and a connection conductor 68 connected to the second connection pad 63 so as to embed in the connection holes 64, A connecting conductor 69 and a connecting conductor 71 for electrically connecting the both conductors 68 and 69 at the upper end. The connection conductors 71 exposed to the outside of the respective connection wirings 67 serve as electrode pads for connecting the external wirings via the bonding wires.

The semiconductor device according to the eighth embodiment can be manufactured by using the manufacturing method according to the first embodiment described above. However, the pixel array and the control circuit in the first semiconductor chip portion of the first embodiment may be replaced by a first semiconductor integrated circuit, and the logic circuit in the second semiconductor chip portion may be replaced by a second semiconductor integrated circuit .

According to the semiconductor device of the eighth embodiment, since the first and second semiconductor chip portions 101 and 116 are joined to each other, the first and second semiconductor integrated circuits are formed with the optimum process technology Can be used. Therefore, the performance of each of the first integrated circuit and the second integrated circuit can be sufficiently exhibited, and a high-performance semiconductor device can be provided.

In this embodiment, in particular, all of the semiconductor portions of the region where the first semiconductor chip portion 101, that is, the connecting conductor 68 and the through-hole conductor 69 are formed, are all removed. The parasitic capacitance between the connecting conductor 68 and the through-hole connecting conductor 69 and the semiconductor substrate 104 is reduced because the connecting conductor 68 and the through-hole connecting conductor 69 are formed in the semiconductor removing region 52 And the performance of the semiconductor device can be further improved.

In the eighth embodiment, in manufacturing, the first semiconductor substrate 104 and the second semiconductor substrate 118 before chip formation are joined together in a semi-finished state to thin the first semiconductor substrate 104 have. That is, the second semiconductor substrate 118 is used as a support substrate for thinning the first semiconductor substrate 104. Thereby, it is possible to save the member and reduce the manufacturing process. Since the first semiconductor substrate 104 is made thin and the connection hole 64 and the through hole 62 are formed in the semiconductor removal region 52 from which the semiconductor portion is removed, The aspect ratio of the hole is reduced, and the connection hole can be formed with high accuracy. Therefore, a high-performance semiconductor device can be manufactured with high accuracy.

10. Ninth Embodiment

Configuration Example of Semiconductor Device

41 shows a ninth embodiment of the semiconductor device according to the present invention. The semiconductor device 132 of the ninth embodiment is configured by including a first semiconductor chip portion 101 and a second semiconductor chip portion 116 and a laminated semiconductor chip 100 bonded to each other. In the first semiconductor chip portion 101, a first semiconductor integrated circuit and a multilayer wiring layer are formed. In the second semiconductor chip portion 116, a second semiconductor integrated circuit and a multilayer wiring layer are formed. The first semiconductor chip portion 101 and the second semiconductor chip portion 116 are brought into contact with each other so that the multilayer wiring layers are opposed to each other.

In this embodiment, a semiconductor removing region 52 is formed by completely removing the semiconductor portion of a part of the first semiconductor chip portion 101, and the semiconductor removing region 52 is formed from the inner surface of the semiconductor removing region 52 to the back surface of the semiconductor substrate 103 A laminated insulating film 61 is formed. A planarized insulating film 77 is formed in the semiconductor removing region 52 to have a flat surface with the surface of the laminated insulating film 61 on the semiconductor substrate 103. The insulating film 77 is formed of an insulating film such as a silicon oxide film having a different etch rate from the silicon nitride film 59 on the front surface side of the laminated insulating film 61 as described above.

A connection hole 64 and a through hole 62 reaching the first connection pad 65 and the second connection pad 63 are formed through the insulating film 77, respectively. And a connection wiring 67 for connecting between the first and second connection pads 65 and 63 through the both connection holes 64 and 62 is formed. The connection wiring 67 includes a connection conductor 68 electrically connected to the first connection pad 65, a through connection conductor 69 electrically connected to the second connection pad 63, Is formed by a connecting conductor (71) which electrically connects the upper and lower electrodes (68, 69) at the upper end. The connecting conductor 68 and the through-hole connecting conductor 69 are formed so as to fill in the connecting holes 64 and 62, respectively. The connecting conductor 68, the through-hole connecting conductor 69 and the connecting conductor 71 are integrally formed by the required metal and the connecting conductor 71 is formed on the planarized insulating film 77. [

Since the other structures are the same as those described in the eighth embodiment, the same reference numerals are given to the parts corresponding to those in Fig. 40, and redundant description is omitted.

The semiconductor device 132 according to the ninth embodiment can be manufactured by using the manufacturing method according to the second embodiment described above. However, the pixel array and the control circuit in the first semiconductor chip portion of the second embodiment may be replaced by a first semiconductor integrated circuit, and the logic circuit in the second semiconductor chip portion may be replaced by a second semiconductor integrated circuit .

According to the semiconductor device 132 of the ninth embodiment, a part of the first semiconductor chip portion 101, that is, the semiconductor portion of the region where the connection wiring 67 is formed is entirely removed, The insulating film 77 is embedded in the insulating film 52. The connection conductors 68 and 69 are buried in the insulating film 77 and the connection conductors 68 and 69 are connected to the insulating film 77 ) From the side surface of the semiconductor substrate 103. Thus, the parasitic capacitance between the connection conductors 68, 69 and the semiconductor substrate 103 can be reduced. Since the semiconductor removing region 52 is filled with the insulating film 77, the surface of the semiconductor substrate 103 which contacts the sidewall of the semiconductor removing region 52 cooperates with the laminated insulating film 61 to mechanically secure can do. Therefore, higher performance of the semiconductor device can be achieved.

Since the first semiconductor substrate 103 is made thinner to form the through hole 62 and the connection hole 64 in this embodiment, the aspect ratio of the hole is reduced and the connection holes 62, 64 can be formed. Therefore, a high-performance semiconductor device can be manufactured with high accuracy.

In addition, although the description is omitted, the effect as described in the eighth embodiment is achieved.

11. Tenth Embodiment

Configuration Example of Semiconductor Device

Fig. 42 shows a tenth embodiment of the semiconductor device according to the present invention. The semiconductor device 133 of the tenth embodiment is constituted by a laminated semiconductor chip 100 in which a first semiconductor chip portion 101 and a second semiconductor chip portion 116 are joined. In the first semiconductor chip portion 101, a first semiconductor integrated circuit and a multilayer wiring layer are formed. In the second semiconductor chip portion 116, a second semiconductor integrated circuit and a multilayer wiring layer are formed. The first semiconductor chip portion 101 and the second semiconductor chip portion 116 are brought into contact with each other so that the multilayer wiring layers are opposed to each other.

In this embodiment, a semiconductor removing region 52 is formed by completely removing the semiconductor portion of a part of the first semiconductor chip portion 101, and the semiconductor removing region 52 is formed from the inner surface of the semiconductor removing region 52 to the back surface of the semiconductor substrate 103 A laminated insulating film 61 is formed. A flattened insulating film 77 which becomes a flat surface with the surface of the laminated insulating film 61 on the semiconductor substrate 103 is buried in the semiconductor removing region 52 and the flattened insulating film 77 corresponding to the connecting wiring 67 of the insulating film 77 A concave portion 81 having a depth required from the surface is formed in the portion.

A connection hole 64 and a through hole 62 reaching the first connection pad 65 and the second connection pad 63 are formed through the insulating film 77 under the concave portion 81 . And a connection wiring 67 for connecting between the first and second connection pads 65 and 63 through the two connection holes 64 and 62 is formed. The connection wiring 67 includes a connection conductor 68 electrically connected to the first connection pad 65, a through connection conductor 69 electrically connected to the second connection pad 63, And a connection conductor 71 for electrically connecting the conductors 68 and 69 at the upper end. The connecting conductor 68 and the through-hole connecting conductor 69 are formed so as to fill in the connecting holes 64 and 62, respectively. The connecting conductor 71 is integrally formed in the concave portion 81 of the insulating film 77. The connecting conductor 71 is formed integrally with the required metal, And the surface of the connecting conductor 71 is formed so as to be flat on the surface of the insulating film 77.

Since the other structures are the same as those described in the eighth embodiment, the same reference numerals are given to the parts corresponding to those in Fig. 40, and redundant description is omitted.

The semiconductor device 133 according to the tenth embodiment can be manufactured by using the manufacturing method according to the third embodiment described above. However, the pixel array and the control circuit in the first semiconductor chip portion of the third time are replaced with the first semiconductor integrated circuit, and the logic circuit in the second semiconductor chip portion is replaced with the second semiconductor integrated circuit .

According to the semiconductor device 133 of the tenth embodiment, a part of the first semiconductor chip portion 101, that is, the semiconductor portion of the region where the connection wiring 67 is formed is entirely removed, The insulating film 77 is embedded in the insulating film 52. A concave portion 81 is formed in the insulating film 77 and the connecting conductor 68 and the connecting conductor 68 are connected to each other through the connecting hole 64 formed in the insulating film 77 under the concave portion 81 and the through- A connection conductor 69 is formed, and a connection wiring 67 is formed. The both connecting conductors 68 and 69 are separated from the side surface of the semiconductor substrate 103 by the insulating film 77 and the parasitic capacitance between the connecting conductors 68 and 69 and the semiconductor substrate 103 can be reduced . Since the semiconductor removing region 52 is filled with the insulating film 77, the surface of the semiconductor substrate 103 which contacts the sidewall of the semiconductor removing region 52 cooperates with the laminated insulating film 61 to mechanically secure can do. Therefore, higher performance of the semiconductor device can be achieved.

Since the connecting conductor 71 is embedded in the concave portion 81 of the insulating film 77 and the connecting conductor 71 is planarized so as to be flat on the surface of the insulating film 77, .

In the tenth embodiment, the through-hole 62 and the connection hole 64 are formed by thinning the first semiconductor substrate 103 and forming the concave portion 81 in the insulating film 77 . Therefore, the aspect ratio of the hole becomes small, and the connection hole 64 and the through-hole 62 can be formed with high accuracy. Therefore, a high-performance semiconductor device can be manufactured with high accuracy.

In addition, although the description is omitted, the effect as described in the eighth embodiment is achieved.

In the eighth to tenth embodiments described above, two semiconductor chip portions are fused together. Further, the semiconductor device of the present invention may have a configuration in which three or more semiconductor chip portions are fused together. In the connection portion between the first semiconductor chip having the first semiconductor integrated circuit and the second semiconductor chip portion having the second semiconductor integrated circuit in the configuration in which three or more semiconductor chip portions are attached, One configuration applies.

As the semiconductor integrated circuit, in addition to the logic circuit, a memory circuit and other electric circuits can be applied.

In the above example, the layout of the connection pad arrays 91, 91A, 91B, and 98 described in the fourth to seventh embodiments is the same as the layout of the connection wiring 67 shown in the first to third embodiments Solid-state imaging device in which all the semiconductor portions of the solid-state imaging device are removed. The layout of the connection pad arrays 91, 91A and 91B and 98 is also applicable to the semiconductor devices of the eighth to tenth embodiments. The layout of the connection pad arrays 91, 91A and 91B and 98 is not limited to those described above, but may be applied to the case where the connection wirings are formed by joining other wafers or chips and the semiconductor around the connection wirings is not removed can do. For example, the solid-state imaging device or the semiconductor integrated circuit described above in which the connecting conductor 68 and the through-hole conductor 69 are buried through the semiconductor substrate through the insulating film and without removing the semiconductor portion, (Semiconductor device) and the like.

43 and 44 show an embodiment of a solid-state imaging device in which connection wirings are formed without removing the semiconductor portion and the connection pad layout is applied. The solid-state imaging device 135 of the present embodiment is configured so as not to remove the semiconductor in the region where the connection wiring 67 is formed in the second embodiment shown in Fig. 16 described above. A connection hole 64 that penetrates the first semiconductor substrate 31 and reaches the first connection pad 65 and a second connection pad 64 that extends from the first semiconductor substrate 31 to the first connection pad 65 are formed in the connection wiring region in this embodiment, A through-hole 62 penetrating the semiconductor chip 22 and reaching the second connection pad 63 is formed. An insulating film 136 for insulating the semiconductor substrate 31 is formed on the inner surfaces of the connection hole 64 and the through hole 62, respectively. The connection conductor 68 and the through-hole conductor 69 are embedded in the connection hole 65 and the through-hole 62 so as to connect the first connection pad 65 and the second connection pad 63 And a connection wiring connected to the connection conductor 71 is formed. Since the other structures are the same as those described in the second embodiment, the parts corresponding to those in Fig. 16 are denoted by the same reference numerals and the duplicate description will be omitted.

44, in the solid-state imaging device 135 of the present embodiment, the layout of the wiring connection portions including the connection pads 63 and 65 is configured similarly to that shown in Fig. 31 . That is, a connection pad array 91 in which connection pad pairs 89 formed by octagonal connection pads 63 and 65 are densely arranged in four stages is constituted. Since the other detailed configurations are the same as those described with reference to FIG. 31, the same reference numerals are given to the parts corresponding to those in FIG. 31, and the redundant description is omitted.

The solid-state imaging device 135 also has a wider spacing between the adjacent routing wirings 40d and the routing wirings 53d as described in Fig. 31, and the adjacent coupling capacity can be reduced.

45 and 46 show an embodiment of a semiconductor device having a semiconductor integrated circuit in which connection wirings are formed without removing the semiconductor portion and the connection pad layout is applied. In the ninth embodiment shown in FIG. 41 described above, the semiconductor device 137 of the present embodiment is configured such that the semiconductor in the region where the connection wiring 67 is formed is not removed. A connection hole 64 that penetrates the first semiconductor substrate 31 and reaches the first connection pad 65 and a second connection pad 64 that extends from the first semiconductor substrate 31 to the first connection pad 65 are formed in the connection wiring region in this embodiment, A through-hole 62 penetrating the semiconductor chip 22 and reaching the second connection pad 63 is formed. An insulating film 136 for insulating the semiconductor substrate 31 is formed on the inner surfaces of the connection hole 64 and the through hole 62, respectively. The connection conductor 68 and the through-hole conductor 69 are embedded in the connection hole 65 and the through-hole 62 so as to connect the first connection pad 65 and the second connection pad 63 And a connection wiring connected to the connection conductor 71 is formed. Since the other structures are the same as those described in the sixth embodiment, the same reference numerals are given to the parts corresponding to those in FIG. 41, and the redundant description is omitted.

On the other hand, as shown in Fig. 46, in this embodiment, the layout of the wiring connection portion including the connection pads 63 and 65 is configured similarly to that shown in Fig. That is, a connection pad array 91 in which connection pad pairs 89 formed by octagonal connection pads 63 and 65 are densely arranged in four stages is constituted. Since the other detailed configurations are the same as those described with reference to FIG. 31, the same reference numerals are given to the parts corresponding to those in FIG. 31, and the redundant description is omitted.

31, the distance between the adjacent routing wirings 40d and the routing wirings 53d is widened, and the adjacent coupling capacity can be reduced in this semiconductor device 137 as well.

In the semiconductor device having the solid-state imaging device and the integrated circuit in which the connection wiring is formed without removing the semiconductor portion, the layout of the connection pad is the same as that of the fifth embodiment (Fig. 36), the sixth embodiment 38), the seventh embodiment (Fig. 39), or the like can be applied.

In the above-described embodiment of the solid-state imaging device, it is necessary to stabilize the potential of the semiconductor substrate or semiconductor well region on which the pixel array 23 of the first semiconductor chip 22 is formed. That is, the potential change of the through-hole connecting conductor 69 and the connecting conductor 68 at the time of operation is also equal to the potential of the semiconductor substrate or semiconductor well region around the through-hole connecting conductor 69 and the connecting conductor 68 Substrate potential) must be stable and stable. In order to stabilize the substrate potential, a contact portion made of an impurity diffusion layer is formed in the semiconductor well region 32, and this contact portion is connected to the first semiconductor chip portion 22 ) Formed on the periphery of the electrode pad portion. By supplying a fixed voltage, for example, a power supply voltage VDD or a ground voltage (0 V) to the electrode pad portion, a power supply voltage or a ground voltage (0 V) is applied to the semiconductor well region 32 through the contact portion, The substrate potential of the well region is stabilized. For example, if the semiconductor substrate or semiconductor well region is n-type, a power supply voltage is supplied, and if the semiconductor substrate or semiconductor well region is p-type, a ground potential is applied.

In the above-described embodiment of the solid-state imaging device, the transistors on the logic circuit side are not subjected to plasma damage during formation of the connection wirings 67 comprising the through-hole connecting conductors 69 and the connecting conductors 68 A protection diode is provided. In the formation of the connection wirings 67, the connection holes 62, 65 reaching the pad portions 63, 65 are formed by the plasma etching. Excessive plasma ions at the time of plasma processing, And is charged to the connection pad 63. When the charging of excessive plasma ions is applied to the transistor on the logic side through the wiring 53, the transistor is subjected to so-called plasma damage. The protection diode is to prevent this plasma damage.

In this embodiment, a protection diode is formed for each logic circuit constituting each column circuit portion of the column signal processing circuit 5. [ As described above, the routing wiring corresponding to each vertical signal line is connected to the through-hole conductor 69 and the connection conductor 68 of each connection wiring 67 via the connection pads 63 and 65, respectively. In the second semiconductor chip portion 26, a protection diode is formed on the semiconductor substrate 45 on which the MOS transistor of the column circuit portion is formed for each column circuit portion. Each protection diode is connected to the same routing wiring to which the gate electrode of the MOS transistor of the column circuit portion is connected. The protection diode connected to the routing wiring is provided closer to the connection pad 63 than the MOS transistor of the column circuit portion. During plasma processing, electric charges due to excessive plasma ions charged on the connection pad portion 63 on the logic circuit side flow through the protection diode and do not damage the column circuit portion. Therefore, plasma damage to the column circuit portion at the time of processing the connection wiring 67 can be avoided. In addition to avoiding plasma damage of the column circuit portion, a similar protection diode can be provided to avoid plasma damage of the MOS transistors constituting other peripheral circuits.

A more specific example will be described in detail with reference to a schematic diagram of FIG. Here, there is shown an example in which the present invention is applied to the solid-state imaging device 135 in which the semiconductor in the region for forming the connection wiring 67 shown in Fig. 43 described above is not removed. In this example, the first semiconductor chip portion 22 and the second semiconductor chip portion 26 are electrically connected through the connection wiring 67. [ In the first semiconductor chip portion 22, the connection conductor 68 of the connection wiring 67 passes through the first semiconductor substrate 31 and is electrically connected to the first metal layer M1 of the first layer metal M1 of the multilayer wiring layer 41 To the connection pad 65 of the memory cell array. The first connection pad 65 is connected to the first metal layer M1 via the extended portion 65a of the first metal M1, the via conductor 88, the second metal M2, the via conductor 88, Via the via conductor M3 and the via conductor 88 to the routing wiring 40d of the fourth layer metal M4. The routing wiring 40d corresponds to a vertical signal line as described above.

In the second semiconductor chip portion 26, the through-hole conductor 69 of the connection wiring 67 penetrates the first semiconductor chip portion 22 and is electrically connected to the fourth layer metal M14 of the multilayer wiring layer 55 And is connected to the second connection pad 63. The second connection pad 63 is electrically connected to the first connection pad 63 by using the via conductor 88, the third layer metal M13, the via conductor 88, the second layer metal M12 and the via conductor 88, Layer wiring M11 of the first conductivity type. The routing wiring 53d corresponds to the vertical signal line in the same manner as described above.

The connection pads 65 and 63 are preferably formed of, for example, an Al film. The use of an Al film is for the following reasons. The connecting hole 64 for inserting the connecting conductor 68, the through-hole conductor 69, and the through-hole 62 are formed by plasma etching using CF gas. This plasma processing is overetching, and the connection pads 65 and 63 are exposed to the plasma. If the Cu film is a Cu film, the reactant that can not be removed adheres to the surfaces of the connection pads 65 and 63. The electrical connection between the connecting conductor 68 by Cu and the through-hole connecting conductor 69 and the connecting pads 65 and 63 can not be satisfactorily performed by this reactant. On the other hand, in the case of the Al film, since the reactant does not adhere, the electrical connection between the connecting conductor 68 and the through-hole connecting conductor 69 and the connecting pads 65 and 63 can be satisfactorily performed. In the case of the Al film, the film structure includes a Ti film or a TiN film thereon. The metals M13 to M11 of the connection pad 65 other than the metal Ml and the metal M14 of the connection pad 63 are formed of a Cu film.

As described later, when the connection wiring 67 is provided between the comparator and the counter circuit, for example, the formation of the MOS transistor constituting the counter circuit of high-speed operation is connected to the vertical signal line. This MOS transistor is composed of a high-speed transistor Tr21 driven at a high speed. The high-speed transistor Tr21 has a thin gate insulating film and is also referred to as a minimum transistor. Therefore, the high-speed transistor Tr21 is connected to the routing wiring 53d serving as the vertical signal line on the second semiconductor chip 26 side.

An excessive current flows through the routing wiring 53d through the connection pad 63 during plasma processing and damage such as destruction of the gate insulating film of the high-speed transistor Tr21 constituting the counter circuit may be reduced. Therefore, the protection diode D21 having the pn junction is connected to the portion of the routing wiring 53d closer to the connection pad 63 than the high-speed transistor Tr21. With this protection diode D21, even if an excessive current is generated in the routing wiring 53d during plasma processing, an excessive current flows to the substrate side through the protection diode D21 and damage to the high-speed transistor Tr21 can be prevented have.

38), the shield wiring 96 is provided between the first connection pad 65 and the routing wiring (vertical signal line) 40d having different potentials that intersect directly under the first connection pad 65. [ To avoid the occurrence of the adjacent coupling capacity. Although not shown, a shield wiring may be disposed between the second connection pad 63 and a routing wiring (vertical signal line) 53d having a different potential across the region from the second connection pad 63 to generate the adjacent coupling capacitance Respectively.

In the above-described solid-state image pickup device, it is also possible to electromagnetically shield between adjacent routing wirings, neighboring routing wirings and connecting conductors or through-hole conductors in the first and second semiconductor chip portions 22 and 26 desirable. It is also preferable that, in response to the arrangement of the pair of connection pads, electromagnetic shielding is carried out between the neighboring connecting conductors and between the adjacent connecting conductors, or between the neighboring connecting conductors. In these cases, it is possible to arrange the shield wirings corresponding to each of them by using the metal wirings of the required layers of the multilayer wiring layers.

Although not shown, a shield wiring made of a metal of another layer adjacent to the routing wiring or a copper wiring close to the routing wiring is disposed between neighboring routing wirings. A ground potential is given to the shield wiring. As a result, the adjacent coupling capacitance between adjacent routing wirings can be reduced.

When the connection pads and the routing wirings are formed of a copper layer, it is preferable to form a copper layer between the adjacent connection conductors 68 and the routing wirings 40d in the same layer as the wirings 40d, And the shield wiring by the metal of the layer is arranged. A shield wiring made of a metal of another layer adjacent to the wiring 53d or in the vicinity of the wiring 53d is disposed between the adjacent through-hole conductor 69 and the routing wiring 53d. These ground wirings are given ground potentials. This makes it possible to reduce the adjacent coupling capacitances between the adjacent routing wiring 40d and the connecting conductor 68 and between the adjacent routing wiring 53d and the through-hole conductor 69, respectively.

In the connection wiring region in which the plurality of connection wirings 67 are formed, a required conductive semiconductor impurity region is formed so as to surround the through-connection conductors and the connection conductors through the insulating film, thereby reducing the adjacent coupling capacitance. That is, it is possible to reduce the adjacent coupling capacity between the neighboring through-hole conductors and the connecting conductors, between adjacent through-hole conductors, or between neighboring connecting conductors. Figs. 48 and 49 (cross-sectional view taken along the line XXXXIX-XXXXIX in Fig. 49) schematically show one example thereof. This example is applied to the solid-state imaging device 135 of Fig.

In Figs. 48 and 49, the connection pad pairs 89 are arranged so as to be alternately inverted as shown in Fig. In the connection wiring region, a p-type semiconductor region 151 is formed in a region surrounding the connection conductor 68 and the through-hole conductor 69 of the semiconductor substrate 31, and the p-type semiconductor region 151 is grounded . Each of the connecting conductors 68 and the through-hole conductors 69 and the p-type semiconductor region 151 are electrically separated by the insulating film 136. [ In this configuration, the grounded p-type semiconductor region 151 serves as a shield layer, and the adjacent coupling capacitance between the adjacent connecting conductor 68 and the through-hole connecting conductor 69 can be reduced. The p-type semiconductor region 151 is an element isolation region for isolating the photodiode PD of each pixel. When the impurity diffusion layer, that is, the p-type semiconductor region is used, the p-type semiconductor region 151 is formed simultaneously with the p- .

Here, when the grounded p-type semiconductor region 151 is used as the shield layer, the large ground capacitance tends to increase. This suppression of the ground capacitance is performed by controlling the film thickness t1 of the insulating film 136. [ The film thickness t1 may be 50 nm or more and 300 nm or less, for example, about 100 nm. As the film thickness t1 is increased, the ground capacitance [fF] decreases, but when the film thickness becomes 300 nm or more, the ground capacitance is hardly changed.

In the arrangement of the pair of connection pads 99 as shown in Fig. 39, the structure between the neighboring connecting conductors 68 in the longitudinal direction and the through conductors 69 is as shown in Fig. The constitution between the neighboring connecting conductors 68 in the transverse direction and the neighboring through connecting conductors 69 is the configuration shown in Fig. 50 and Fig. 51, respectively. In Figs. 50 and 51, the parts corresponding to those in Fig. 49 are denoted by the same reference numerals, and redundant description is omitted.

Although not shown in the figure, the p-type semiconductor region 151 is provided with a contact made of an impurity diffusion layer to stabilize the potential of the p-type semiconductor region 151 around the connection conductor 68 and the through- (Substrate contact portion) is formed. This contact portion can be formed so as to surround the connection wiring region corresponding to a plurality of connection pad arrays and can be connected to the electrode pads on the first semiconductor chip portion 22. [ By supplying a ground voltage (0 V) to this electrode pad, the substrate potential of the p-type semiconductor region 151 around the connecting conductor 68 and the through-hole conductor 69 is stabilized.

The semiconductor substrate 31 of the first semiconductor chip portion 22 is formed using an n-type semiconductor substrate as a starting material. The semiconductor substrate 45 of the second semiconductor chip portion 26 uses a p-type semiconductor substrate as a starting material. When the control circuit 24 and the pixel array 23 shown in Fig. 2B are formed in the first semiconductor chip 22, the p-type semiconductor well region of the pixel array 23 and the control circuit 24 ) Between the p-type semiconductor well regions of the n-type substrate. Therefore, in the first semiconductor chip portion 22, the voltage for stabilizing the potential of each of the p-type semiconductor well region, the n-type semiconductor substrate, and the p-type semiconductor region 151 through the electrode pad to the substrate contact portion, . Also in the second semiconductor chip portion, voltages corresponding to the potential stabilization are supplied to the n-type semiconductor well regions where the p-type semiconductor substrate and the p-channel MOS transistor are formed through the substrate contact portions, respectively.

When the substrate contact portions of the first semiconductor chip portion 22 and the second semiconductor chip portion 26 are all connected to the electrode pads on the surface of the first semiconductor chip portion 22, A connecting conductor, and a metal wiring of a required layer.

When the substrate contact portions of the first semiconductor chip portion 22 and the second semiconductor chip portion 26 are all connected to the electrode pad of the end surface of the second semiconductor chip portion 26, And a connection conductor, and a metal wiring of a necessary layer.

Next, the insertion locations of the connection wirings 67 by the above-described connection conductors 68 and the through-connection conductors 69 on the circuit of the solid-state imaging device will be described. 52 schematically shows a main part of the solid-state imaging device. The solid-state imaging device has a pixel array 3 in which a plurality of pixels 2 are arranged in a matrix, and a vertical signal line 9 corresponding to each column of pixels 2 is connected to a column signal processing circuit 5 are connected. The column signal processing circuit 5 has a column ADC section 13. The column ADC section 13 converts the analog signal into a digital signal based on the time from the start of the conversion until the reference voltage (lamp voltage) and the signal voltage to be processed coincide with each other. In principle, the comparator 14 and the counting circuit 15 supply the ramp voltage to the comparator 14 and start counting with the clock signal supplied to the counting circuit 15. The analog image signal inputted through the vertical signal line 9 is compared with the ramp voltage, and the AD conversion is performed by counting until the pulse signal is obtained.

In this embodiment, the connection wiring 67 can be disposed at the position 1 between the comparator 14 and the counter circuit 15 in Fig. In this case, the circuit configuration up to the comparator 14 is formed in the first semiconductor chip portion 22 together with the pixel array 3. [ The circuit configuration of the second semiconductor chip portion 26 after the counter circuit 15 is formed. The control circuit can be formed in the first semiconductor chip portion 22 or the second semiconductor chip portion 26. [ The first and second semiconductor chip portions 22 and 26 are connected to each other by a connection wiring 67 formed of a connection conductor 68 and a through-hole conductor 69.

Since the counter circuit 15 has a high processing speed, a high-speed transistor capable of high-speed driving is also required as the transistor constituting the counter circuit 15. High-speed transistors need to be manufactured by state-of-the-art equipment. The first semiconductor chip portion 22 having the circuit configuration up to the comparator 14 and the second semiconductor chip portion 26 having the circuit configuration after the counter circuit 15 by the high- Each of which can be produced by dividing by an optimum facility.

When the performance (image quality) of the solid-state imaging device is taken into consideration, the connection wiring 67 can be disposed at the position (3) or the position (2) in Fig. That is, the connection wiring 67 can be disposed at the position 3 between the pixel array 3 and the column signal processing circuit 5. In this case, the pixel array 3 is formed in the first semiconductor chip portion 22, and the signal processing circuit including the column signal processing circuit 5 is formed in the second semiconductor chip portion 26. The first and second semiconductor chip portions 22 and 26 are connected to each other by a connection wiring 67 formed of a connection conductor 68 and a through-hole conductor 69.

Further, the connection wiring 67 can be disposed at the position 2 of the output of the counter circuit 15. In this case, the circuit configuration up to the counter circuit 15 is formed in the first semiconductor chip portion 22 together with the pixel array 3. [ In the second semiconductor chip portion 26, a signal processing circuit after the output of the counter circuit 15 is formed. The first and second semiconductor chip portions 22 and 26 are connected to each other by a connection wiring 67 formed of a connection conductor 68 and a through-hole conductor 69.

The configuration in which the above-described protection diode D21 is provided, the configuration in which the p-type semiconductor region 151 is provided around the connection wiring 67 in Figs. 48 to 51, the configuration of the substrate contact portion, And the like can be applied to each of the above embodiments.

12. Eleventh Embodiment

Examples of electronic devices

The above-described solid-state image pickup device according to the present invention can be applied to, for example, a camera system such as a digital camera or a video camera, a cellular phone having an image pickup function, or an electronic apparatus such as another apparatus having an image pickup function .

52 shows an eleventh embodiment applied to a camera as an example of an electronic apparatus according to the present invention. The camera according to the present embodiment is an example of a video camera capable of capturing still images or moving images. The camera 141 of this embodiment has a solid-state imaging device 142, an optical system 143 for guiding incident light to the light-receiving sensor portion of the solid-state imaging device 142, and a shutter device 144. The camera 141 also has a drive circuit 145 for driving the solid state image pickup device 142 and a signal processing circuit 146 for processing the output signal of the solid state image pickup device 142.

The solid-state imaging device 142 is applied to any one of the solid-state imaging devices of the above-described embodiments. The optical system (optical lens) 143 images the normal light (incident light) from the subject on the imaging surface of the solid-state imaging device 142. Thus, signal charges are accumulated in the solid-state imaging device 142 for a predetermined period of time. The optical system 143 may be an optical lens system composed of a plurality of optical lenses. The shutter device 144 controls the light irradiation period and the light shielding period to the solid-state imaging device 142. The drive circuit 145 supplies a drive signal for controlling the transfer operation of the solid-state imaging device 142 and the shutter operation of the shutter device 144. The signal from the solid-state imaging device 142 is transferred by the driving signal (timing signal) supplied from the driving circuit 145. The signal processing circuit 146 performs various kinds of signal processing. The video signal subjected to the signal processing is stored in a storage medium such as a memory or is output to a monitor.

According to the electronic apparatus such as the camera according to the eleventh embodiment, the solid-state imaging device 142 can be provided with high performance, and highly reliable electronic apparatus can be provided.

Claims (19)

A multilayer semiconductor chip in which two or more semiconductor chip parts are laminated, at least a pixel array and a multilayer wiring layer are formed in the first semiconductor chip part, a logic circuit and a multilayer wiring layer are formed in the second semiconductor chip part,
A semiconductor removing region in which a part of the semiconductor portion of the first semiconductor chip portion is completely removed,
A plurality of connection wirings formed in the semiconductor removal region and connecting the first semiconductor chip portion and the second semiconductor chip portion,
A protective insulating film which extends from the exposed surface of the semiconductor removing region to the surface of the semiconductor substrate on which the pixel array is formed and also serves as an antireflection film;
And an insulating film embedded in the semiconductor removing region,
Wherein the connection wiring includes:
A connection conductor connected to a first connection pad which penetrates the insulating film and is connected to a required wiring in the multilayer wiring layer in the first semiconductor chip;
A through-hole connecting conductor which is connected to a second connection pad which is connected to a necessary wiring in the multilayer wiring layer in the second semiconductor chip portion through the first semiconductor chip portion and the insulating film,
And a connecting conductor for connecting the connecting conductor and the through-hole conductor. A multilayer semiconductor chip in which two or more semiconductor chip parts are laminated, at least a pixel array and a multilayer wiring layer are formed in the first semiconductor chip part, a logic circuit and a multilayer wiring layer are formed in the second semiconductor chip part,
A semiconductor removing region in which a part of the semiconductor portion of the first semiconductor chip portion is completely removed,
A plurality of connection wirings formed in the semiconductor removal region and connecting the first semiconductor chip portion and the second semiconductor chip portion,
And a protective insulating film extending from the exposed surface of the semiconductor removing region to the surface of the semiconductor substrate on which the pixel array is formed and also serving as an antireflection film,
Wherein the connection wiring includes:
A connection conductor connected to a first connection pad connected to a required wiring in the multilayer wiring layer in the first semiconductor chip portion,
A through-hole connecting conductor which is connected to a second connecting pad which is connected to a necessary wiring in the multilayer wiring layer in the second semiconductor chip portion through the first semiconductor chip portion,
And a connecting conductor connecting the connecting conductor and the through-hole conductor,
The first connection pads and the second connection pads each having an octagonal shape are alternately arranged in the horizontal direction and the vertical direction and the pair of first and second connection pads arranged in the horizontal direction are arranged in a vertical A plurality of connection pad arrays arranged in a plurality of stages,
The area of the second connection pad is set larger than the area of the first connection pad,
Wherein the solid-state imaging device is a back-illuminated solid-state image pickup device in which necessary wiring corresponding to each of the vertical signal lines is connected to the first and second connection pads constituting the plurality of pairs of stages. 3. The method of claim 2,
The connection pad array is disposed on both outer sides opposite to each other with the pixel array interposed therebetween,
And wiring lines corresponding to the respective vertical signal lines are alternately connected to the connection pad arrays on the outer sides. The method according to claim 2 or 3,
In the first semiconductor chip portion,
Wherein the first connection pad is formed of a first layer metal of a multilayer wiring layer and the wiring to be connected to the first connection pad is formed of a second layer or later metal. 5. The method of claim 4,
And a metal shield wiring is formed in the layer between the first connection pad and the required wiring. A first semiconductor wafer having a pixel array and a multilayer wiring layer formed in a region where a first semiconductor chip is to be added and a second semiconductor wafer having a logic circuit and a multilayer wiring layer formed in a region where a second semiconductor chip is to be provided, A step of attaching two or more semiconductor wafers,
A step of forming a semiconductor removing region by removing all the semiconductor portions of a region of the first semiconductor wafer to which the first semiconductor chip is to be attached,
Forming a protective insulating film serving as an antireflection film extending from an exposed surface of the semiconductor removing region to a surface of a semiconductor wafer on which a pixel array is formed;
A step of embedding an insulating film in the semiconductor removing region,
Forming a connection hole through the protective insulating film and the insulating film in the semiconductor removal region to reach a first connection pad connected to a required wiring of the multilayer wiring layer in the first semiconductor chip portion;
A through-hole connecting to a second connection pad, which penetrates the first semiconductor chip portion, the protective insulating film, and the insulating film and is connected to a required wiring of the multilayer wiring layer in the second semiconductor chip portion, A step of forming a hole,
A connection conductor and a through-hole conductor which are connected to the first connection pad and the second connection pad in the connection hole and the through-hole, respectively, and a connection conductor connecting the connection conductor and the connection conductor The process,
And a step of forming a chip into a finished product,
Wherein the back-illuminated solid-state imaging device is manufactured. The method according to claim 6,
The first connection pad is formed of a first layer metal of the multilayer wiring layer,
Wherein the wiring to be connected to the first connection pad is formed of a metal of a second layer or later. A solid-
An optical system for guiding incident light to the photoelectric conversion unit of the solid-state imaging device,
And a signal processing circuit for processing an output signal of the solid-state imaging device,
The solid-
A multilayer semiconductor chip in which two or more semiconductor chip parts are laminated, at least a pixel array and a multilayer wiring layer are formed in the first semiconductor chip part, a logic circuit and a multilayer wiring layer are formed in the second semiconductor chip part,
A semiconductor removing region in which a part of the semiconductor portion of the first semiconductor chip portion is completely removed,
And a plurality of connection wirings formed in the semiconductor removal region and connecting the first semiconductor chip portion and the second semiconductor chip portion,
A protective insulating film which extends from the exposed surface of the semiconductor removing region to the surface of the semiconductor substrate on which the pixel array is formed and also serves as an antireflection film;
And an insulating film embedded in the semiconductor removing region,
Wherein the connection wiring includes:
A connection conductor connected to a first connection pad which penetrates the insulating film and is connected to a required wiring in the multilayer wiring layer in the first semiconductor chip;
A through-hole connecting conductor which is connected to a second connection pad which is connected to a necessary wiring in the multilayer wiring layer in the second semiconductor chip portion through the first semiconductor chip portion and the insulating film,
And a connecting conductor for connecting the connecting conductor and the through-hole conductor. A solid-
An optical system for guiding incident light to the photoelectric conversion unit of the solid-state imaging device,
And a signal processing circuit for processing an output signal of the solid-state imaging device,
The solid-
A multilayer semiconductor chip in which two or more semiconductor chip parts are laminated, at least a pixel array and a multilayer wiring layer are formed in the first semiconductor chip part, a logic circuit and a multilayer wiring layer are formed in the second semiconductor chip part,
A semiconductor removing region in which a part of the semiconductor portion of the first semiconductor chip portion is completely removed,
A plurality of connection wirings formed in the semiconductor removal region and connecting the first semiconductor chip portion and the second semiconductor chip portion,
And a protective insulating film extending from the exposed surface of the semiconductor removing region to the surface of the semiconductor substrate on which the pixel array is formed and also serving as an antireflection film,
Wherein the connection wiring includes:
A connection conductor connected to a first connection pad connected to a required wiring in the multilayer wiring layer in the first semiconductor chip portion,
A through-hole connecting conductor which is connected to a second connecting pad which is connected to a necessary wiring in the multilayer wiring layer in the second semiconductor chip portion through the first semiconductor chip portion,
And a connecting conductor for connecting the connecting conductor and the through-hole connecting conductor
The first connection pads and the second connection pads each having an octagonal shape are alternately arranged in the horizontal direction and the vertical direction and the pair of first and second connection pads arranged in the horizontal direction are arranged in a vertical A plurality of connection pad arrays arranged in a plurality of stages,
The area of the second connection pad is set larger than the area of the first connection pad,
And a back-illuminated solid-state image pickup device in which necessary wiring corresponding to each vertical signal line is connected to the first and second connection pads constituting the plural-stage arranged pairs. delete delete delete delete delete delete delete delete delete delete

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