TWI466173B - A reverse optical proximity correction method - Google Patents

Description

Reverse optical proximity correction method

The invention is generally related to non-volatile memory. More specifically, the invention relates to anti-fuse memory cell structures.

Over the past 30 years, anti-fuse technology has attracted significant attention from many inventors, IC designers, and manufacturers. The antifuse can change the structure of the conductive state, or in other words, change the state from non-conducting to conductive electronic devices. The binary states may correspond to one of high resistance and low resistance in response to electrical stress, such as programming voltage or current. There have been many attempts to develop and apply antifuse in the microelectronics industry, but the most successful antifuse applications to date have been available in FGPA devices manufactured by Actel and Quicklogic, and in DRAM devices manufactured by Micron. See the redundancy or select programming.

The process of antifuse development is summarized by the published US patents as follows.

The development of antifuse is described in U.S. Patent No. 3,423,646, which discloses the formation of a film which is an array of horizontal and vertical conductors. A diode PROM has a thin dielectric (aluminum oxide) at the intersection between the conductors. Such NVM memory is programmed by perforating the dielectric in a portion of the intersection. The diode can be formed to act like an open circuit until a voltage of sufficient amplitude and duration is applied to the intersection to cause the formation of an aluminum oxide intermediate layer, at which point the device acts like a tunneling diode.

U.S. Patent No. 3,634,929 discloses an intermetallic semiconductor antifuse array having a structure consisting of a thin dielectric capacitor (AlO ₂ , using a two conductor (Al) located above and connected to the semiconductor diode. Composition of SiO ₂ or Si ₃ N ₄ ).

A programmable dielectric ROM memory structure using MOS capacitors and MOS switching elements is shown in U.S. Patent No. 4,322,822 (McPherson). This cell is formed as a capacitor having a standard gate oxide connected to the gate of the MOS transistor using a buried contact on the substrate. In order to reduce the oxide breakdown voltage, the breakdown voltage of the anti-fuse capacitor must be smaller than that of the MOS switch, and a V-shaped groove in the capacitor region is proposed. Since a capacitor is formed between the polysilicon gate and the grounded p-type substrate, the breakdown voltage must be applied to the capacitor via the access transistor. The gate/drain and gate/source edges of the access transistor are located in the second field oxide, much thicker than the gate oxide in the channel region, which greatly improves the gate/S-D breakdown voltage.

U.S. Patent No. 4,507,757 (McElroy) proposes a method of reducing the gate oxide breakdown voltage by accumulating junction collapse. Although the original McElroy idea used a gated diode to locally cause a cumulative collapse, it intensified the electron breakdown by sequentially reducing the dielectric breakdown voltage. In fact, other and perhaps more important components are introduced or have the current anti-fuse technology: (a) Double gate oxide anti-fuse: the access transistor gate oxide is thicker than the anti-fuse dielectric. McElroy's dual gate oxide processing steps are: initial gate oxidation, etching for thinner gate oxide regions, and subsequent gate oxidation. This program is now used in standard CMOS technology for "I/O" and "1T" devices. (b) "Common gate" (planar DRAM, etc.) anti-fuse connection in which the access transistor is connected to the anti-fuse diffusion (drain) node and all anti-fuse gates are connected together. This is in contrast to the McPherson configuration and results in denser cells due to the elimination of buried contacts. (c) Restrict the resistor between the common anti-fuse gate and the external ground. (d) Two-terminal anti-fuse MOS device (semi-transistor): McElroy concludes that only two terminals are required in the anti-fuse capacitor: D and G. The source is not actually required for anti-fuse programming or operation and can be completely insulated from the active region. In addition to being used for accumulating crashes, block connections do not play any role. Therefore, limiting the source role to collect the carrier from the cumulative crash should increase the local substrate potential to bias the emitter of the parasitic n-p-n device formed by D, B, and S forward.

No. 4,543,594 (Mohsen) proposed that the anti-fuse design is suitable for redundancy repair before 1985, which is not suitable for redundancy repair. While such an application requires much lower density than the PROM, it is easier to supply the external high voltage required to destroy the oxide without the need for this voltage to actually pass through the transistor. Mohsen's antifuse structure consists of a thin oxide (50-150A SiO ₂ ) polycrystalline tantalum capacitor over the doped region. He believes that germanium from the substrate or germanium from the electrode using the polysilicon electrode is melted into the pinhole in the insulating layer to provide the conductor, and his experimental data shows that the oxide layer is about 100 A thick and has a thickness of 10 to 500 um ² . At the area between the two, fusion occurs at a voltage of 12 to 16 volts. The current must cause this fusion to be less than 0.1 uA/um ^{2 of the} capacitor area and the resulting melt link has a resistance of about 0.5 to 2K ohms. Once melted, it can handle up to 100 microamps of current for about one second at room temperature before the link is restored to open fuse. Considering electron migration wear, once melted, the predicted wear life of the bond is substantially greater than 3E8 hours.

The possibility of self-recovery of the antifuse under current stress appears as Apply this technique to major roadblocks in such areas where constant fuse stress is required, such as PROM, PLD, and FPGA. The problem of the anti-fuse recovery is addressed later in U.S. Patent No. 4,823,181 to Mo. Actel teaches the implementation of reliable programmable low-impedance anti-fuse components by using an ONO structure that replaces cerium oxide. Actel's method requires a resistor contact after breaking the dielectric. This is accomplished by either using heavily doped diffusion or by placing the ONO dielectric between the two metal electrodes (or the germanide layer). The necessity of an arsenic-doped bottom diffusion electrode is modified later in U.S. Patent No. 4,899,205, which is to allow any of the top polysilicon or bottom diffusion to be highly doped.

U.S. Patent No. 5,019,878 teaches The programming voltage in the range of ten to fifteen volts is applied from the drain to the source to reliably form the molten filament across the channel region. It is possible to apply a gate voltage to control the melting of a particular transistor. In U.S. Patent No. 5,672,994, IBM found similar effects by providing channel antifuse. They found that using 0.5um technology, the bVDSS of the nmos transistor will be not only at 6.5V At the level of S-D, once S-D breakdown occurs, it creates permanent damage that causes thousands of ohms of leakage between the source and the drain.

U.S. Patent No. 5,241,496 issued to Micron And DRAM cells based on antifuse (trench and stack) are disclosed in U.S. Patent No. 5,110,754. In U.S. Patent No. 5,742,555, the Micron incorporates a well-to-gate capacitor as an anti-fuse. U.S. Patent No. 6,087,707 proposes to incorporate an N-well coupled antifuse as a method of eliminating undercut defects associated with polysilicon etch. U.S. Patent Application Serial No. 2002/0027,822 proposes a similar anti-fuse structure, but removes the n+ region to create an asymmetric ("unbalanced") high voltage storage using the N-well as a drain electrode. Take the transistor.

U.S. Patent No. 6,515,344 proposes a set of P+/N+ The anti-fuse configuration uses a minimum size gate implementation between two opposite types of diffusion regions.

NMOS antifuse has been established using standard deep N-well processing In the insulated P-well. An example of a deep N-well based antifuse is disclosed in U.S. Patent No. 6,611,040.

U.S. Patent Application No. 2002,0074,616 and 2004, 0023, 440 discloses other deep N-well anti-fuse. These antifuse consists of capacitors characterized by direct tunneling currents rather than Fowler Nordheim currents. These applications demonstrate that antifuse performance is generally improved for thinner gate oxide capacitors (about 20 A, which is typically used for 0.13 um process transistors).

U.S. Patent No. 6,580,145 discloses the use of double gates A new version of the traditional anti-fuse structure for oxides, with thicker gate oxide for nmos (or pmos) access transistors and thinner gate oxide for capacitors. The N-well (or P-well) is used as the bottom plate of the anti-fuse capacitor.

U.S. Patent No. 6,597,234, the disclosure of which is incorporated herein by reference. Do not destroy the S-G and D-G dielectric regions of the transistor to create a short-circuit through the source gate of the gate.

U.S. Patent Application Serial No. 2004,0004,269 discloses An antifuse is established from a MOS transistor having a gate connected to the gate of the capacitor, degraded by a thinner gate oxide, and heavily doped under the via via an additional implant (diode). A breakdown voltage is applied to the bottom plate of the capacitor.

In U.S. Patent No. 6,667,902 (Peng), Peng attempts to improve a typical planar DRAM-type antifuse array by introducing a "column programming line" that is connected to the capacitor and runs parallel to the word line. If decoded, the column programming line minimizes exposure of the access transistor to high programmed voltages, which can occur additionally via programmed cells. Peng and Fong, in U.S. Patent No. 6,671,040, further improve their array by adding a variable voltage control programming current that is said to control the extent of gate oxide collapse, allowing for multi-level or analog storage applications.

Recently, U.S. Patent Application No. 2003/0202376 Peng shows a memory array using a single transistor structure. In the proposed memory cell, Peng eliminates LLD diffusion from normal NMOS transistors. The intersection array structure is crossed by a vertical polycrystalline gate The horizontal active area (S/D) strip is formed. The drain contacts are shared between adjacent cells and connected to the horizontal word line. The source area also shares and remains floating. Peng assumes that if the LDD diffusion is omitted, the gate oxide collapse location will be far enough away from the drain region and a local N+ region will be generated instead of a D-G (drain-gate) short circuit. If such a region is generated, the programmed cell can be detected by positively biasing the gate and sensing the gate to drain current. To reduce the possibility of a G-D or S-D (source-drain) short circuit, Peng proposes to increase the gate oxide thickness at the edges of G-D and S_D by modifying the gate sidewall oxidation process. The array of Peng requires both source and drain regions to be present in the memory cells, to couple the column word lines to the transistor drain regions, and to form row bit lines from the transistor gates. This unusual connection must be very specific for Peng's programming and reading methods, and it is necessary to apply the decoded high voltage (8V in 1.8V processing) to all the bucks except the one to be programmed. line. The decoded high voltage (8V) is applied to the gate to the row to be programmed while keeping the other gates at 3.3V.

Although Peng implements the intersection memory architecture, his array CMOS process modifications (LDD cancellation, thicker gate oxide at the edge) are required and have the following disadvantages: (a) All column decoders, row decoders, and sense amplifiers must switch over a large voltage range: 8V/3.3 V/0V or 8V/1.8V/0V. (b) During the programming operation, the 3.3V row driver is effectively shorted to the 8V column driver or the 0V driver via the programmed cell. This imposes many limitations on the size of the array, affecting the size of the drive and impacting the reliability and efficiency of the programming. (c) Each programming operation requires biasing all of the active regions of the array (except for the programmed columns) to 8V. This leads to a large N++ junction Leakage current and again limit the size of the array. (d) Assuming that the gate oxide break point is sufficiently far from the drain region, the breakdown does not occur at 8V bias. At the same time, the transistor must operate correctly with a 1.8V bias - connected to the channel region. There are no significant process modifications, which are not achievable. (e) Peng assumes that if LDD is not present, the gate oxide will not rupture at the source or drain edge. However, the most probable location for S/D edge system oxide collapse is known in the art due to defects and electric field concentrations around the sharp edges.

Peng in US Patent Application No. 2003/0206467 The number attempts to solve some of these high voltage switching problems. The high resistive voltages on the word lines and bit lines are now replaced by "floating" word lines and bit lines, and have changed the limits of the channel-to-source and drain-to-drain regions. Although floating word lines and bit lines may alleviate high voltage switching problems, they do not address any of the basic problems mentioned above. In addition, they introduce serious coupling problems between the switching and floating lines.

Today, anti-fuse development focuses on 3-dimensional film structures And specific metal materials. All of these anti-fuse technologies require additional processing steps that are not available in standard CMOS processes, and anti-fuse applications are prohibited in typical VLSI and ASIC designs where programmability can help overcome the duration of the continuous shrink device and the fixed rise. The issue of wafer development costs. Therefore, there is a clear need in the industry for a reliable anti-fuse structure using a standard CMOS process.

All prior art anti-fuse cells and arrays require special The processing steps or the exposure of the MOS switching element to one of the high voltages leads to manufacturability and reliability problems. In addition to being very suspicious in turn In addition to the manufacturable Peng's single crystal cell, they are also limited to low-density memory applications.

Therefore, it is desirable to provide a suitable implementation in standard CMOS technology. A simple and reliable, high density, anti-fuse array architecture without any additional processing steps.

Embodiments of the present invention provide a reverse optical proximity correction (OPC) method. The method includes providing a reference pattern of a semiconductor structure; selecting an area of the reference pattern for area reduction by photolithography; and, reversing at least one corner of the area to form a reference pattern A reverse OPC imaging pattern with a smaller area. In accordance with an embodiment of the present embodiment, reversing the at least one corner includes subtracting a predefined rectangular shape from the at least one angular region of the area, and selecting to include identifying an anti-fuse transistor programming area.

In another embodiment of this embodiment, the method further includes fabricating the mask using the reverse OPC imaging pattern and subsequently fabricating the semiconductor structure using the mask in photolithography. In this embodiment, the resulting fabricated semiconductor structure has a substantially different shape than the reference pattern. The reference pattern of the semiconductor structure may correspond to an active region of an antifuse transistor of a memory cell, wherein a portion of the active region of the antifuse transistor is made of a thin gate oxide and has a thin gate Covered by a thick gate oxide of greater oxide thickness. In this embodiment, the area of the reference pattern corresponds to the thin gate oxide of the antifuse transistor.

According to another embodiment of the present embodiment, the method can be further Including applying optical proximity correction to other portions of the reference pattern to correct for photolithography distortion.

Reviewing the specific implementation of the present invention in conjunction with the accompanying drawings Other embodiments and features of the present invention will become apparent to those skilled in the art.

10‧‧‧Optoelectronics

12‧‧‧Anti-fuse device

14‧‧‧ gate

16‧‧‧ top board

18, 118, 416, 502, 802, 852, 1002, 1052, 1102, 1152, 2010, 2034 ‧ ‧ active area

20, 306‧‧‧Thin gate oxide

22, 24, 110, 410, 706‧‧‧ diffused areas

100, 400, 500, 600, 800, 850, 880, 900, 950‧‧‧ anti-fuse transistors

102, 402‧‧‧Variable thickness gate oxide

104, 404‧‧‧Substrate channel area

106, 406, 504, 702, 804, 854, 1004, 1008‧‧‧ polysilicon gate

108, 408‧‧‧ sidewall spacers

109‧‧‧ Field oxide region

114, 412‧‧‧LDD area

116, 420, 516, 708, 806, 856, 1006, 2012 ‧ ‧ bit line contacts

120, 513, 808, 858, 902, 952, 1012‧‧‧ OD2 masks

121, 710‧‧

300‧‧‧Intermediate gate oxide

302‧‧‧Channel area

304‧‧‧Small oxide region

414, 506, 602‧‧‧ thick gate oxide regions

418, 512, 610, 906, 956, 1014‧‧‧ thin gate oxide regions

508, 604, 860, 908‧‧‧ first thick gate oxide segment

510, 606‧‧‧Second thick gate oxide segment

514, 904, 954‧‧‧ rectangular openings

608‧‧‧third gate oxide segment

612‧‧‧Dashed diamond area

700, 1000, 1050, 1100, 1150‧‧‧2 transistor anti-fuse memory cells

704‧‧‧gate oxide

809‧‧‧"L"-shaped opening

859, 1013‧‧‧ rectangular opening

862, 864, 884, 886, 888, 890, 958, 960 ‧ ‧ sections

1010, 1054, 1154‧‧‧Common source/dip diffusion region

2000‧‧‧Active Area Pattern

2002‧‧‧ angular expansion

2014, 2016‧‧‧ Polycrystalline 矽 word line

2018‧‧‧OD2 mask area

2020, 2022‧‧‧ area

2030‧‧‧Reverse OPC imaging pattern

2032‧‧‧Reverse angle

2036, 2038‧‧‧Rolling thin gate oxide region

BL‧‧‧ bit line

Vcp‧‧‧ cell screen voltage

VCP0, VCP1, VCP2, VCP3‧‧‧ logical cell board

WL‧‧‧ word line

WL0, WL1, WL2, WL3‧‧‧ logic word lines

Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings in which FIG. 1 is a circuit diagram of a DRAM-type anti-fuse cell; FIG. 2 is a DRAM-type anti-fuse cell of FIG. Figure 3 is a cross-sectional view of the DRAM-type anti-fuse cell of Figure 2 taken along line xx; Figure 4 is a cross-sectional view of an anti-fuse transistor according to an embodiment of the present invention; Figure 5a is a diagram 4 is a planar arrangement of the antifuse transistor; FIG. 5b is a plan view showing the antifuse transistor of FIG. 4 of another OD2 mask configuration; FIG. 6 is for forming an antifuse transistor of the present invention. Flowchart of a method of variable thickness gate oxide; Figures 7a-7c depict the formation of a variable thickness gate oxide in accordance with the steps of the flow chart of Figure 6; Figure 8a is a plan view of an antifuse transistor according to an embodiment of the present invention; Figure 8b is a cross-sectional view of the antifuse transistor of Figure 8a taken along line AA; Figure 9 is an antifuse of Figure 8a An enlarged planar arrangement of crystals; FIG. 10 is a plan view of a memory array using the antifuse transistor of FIG. 8a in accordance with an embodiment of the present invention; and FIG. 11 is an antifuse transistor in accordance with another embodiment of the present invention. FIG. 12 is a plan view of a memory array using the antifuse transistor of FIG. 11 in accordance with an embodiment of the present invention; FIG. 13a is a two transistor antifuse memory cell according to an embodiment of the present invention. Figure 13b is a cross-sectional view of the two-crystal anti-fuse memory cell of Figure 13a taken along line BB; Figure 14 is a second embodiment of Figures 13a and 13b, in accordance with an embodiment of the present invention. Planar arrangement of a memory array of crystal anti-fuse memory cells; Figure 15 is a plan layout of a memory array using a two-crystal anti-fuse memory cell in accordance with another embodiment of the present invention; 20 is another anti-fuse memory according to an embodiment of the present invention Planar arrangement of cells; Figures 21-24 are another two cells according to an embodiment of the present invention Planar arrangement of crystal anti-fuse memory cells; Figure 25 is a mask pattern with OPC for the active area of the anti-fuse transistor; Figure 26 shows the initiative with the mask pattern of Figure 25. Figure of the anti-fuse transistor of the region; Figure 27 is a mask pattern with reverse OPC for the active region of the anti-fuse transistor according to the present embodiment; Figure 28 shows the mask with the use of Figure 27 A diagram of an antifuse transistor of an active region of a pattern fabrication; and FIG. 29 is a flow diagram summarizing a reverse OPC method for fabricating a semiconductor structure having a reduced area in accordance with the present embodiment.

In general, the present invention provides variable thickness gate oxide anti-fuse transistor devices that can be used in non-volatile, one-time programmable (OTP) memory array applications. Antifuse transistors can be fabricated using standard CMOS technology and configured as standard transistor components with source diffusion, gate oxide, and polysilicon gates. The variable gate oxide under the polysilicon gate is composed of a thick gate oxide region and a thin gate oxide region, wherein the thin gate oxide region functions as a local breakdown voltage region. During the programming operation, the polysilicon gate and the conductive path between the channel regions can be formed in the local breakdown voltage region. In a memory array application, the word line read current applied to the polysilicon gate can be sensed through the channel of the antifuse transistor through a bit line connected to the source diffusion. More specifically, the present invention provides points The off-channel MOS structure is used as an effective method for anti-fuse cells of OTP memory.

In the following description, the term MOS is used to mean any FET or MIS transistor, semi-transistor, or capacitor structure. To simplify the description of the embodiments, references to gate oxides after this point are understood to include dielectric materials, oxides, or combinations of oxides and dielectric materials.

As previously discussed, a DRAM-type memory array using a planar capacitor instead of a storage capacitor as an anti-fuse is known as shown in U.S. Patent No. 6,667,902. 1 is a circuit diagram of such a memory cell, and FIGS. 2 and 3 respectively show a plan view and a cross-sectional view of the known anti-fuse memory cell of FIG. 1. The memory cell of FIG. 1 includes a transfer or access transistor 10 for coupling the bit line BL to the bottom plate of the anti-fuse device 12. The word line WL is coupled to the gate of the access transistor 10 to turn it on, and the cell screen voltage Vcp for programming the anti-fuse device 12 is coupled to the top plate of the anti-fuse device 12.

As can be seen from Figures 2 and 3, the arrangement of the access transistor 10 and the anti-fuse device 12 is very straightforward and simple. The gate 14 of the access transistor 10 and the top plate 16 of the anti-fuse device 12 are constructed using the same polysilicon layer, which extends across the active region 18. In the active region 18 below each polysilicon layer, a thin gate oxide 20, also referred to as a gate dielectric, for electrically isolating the polysilicon from the active region below is formed. Diffusion regions 22 and 24 are on either side of gate 14, wherein diffusion region 24 is coupled to the bit line. Although not shown, those skilled in the art will appreciate that standard CMOS processing can be applied, such as sidewall spacer formation, lightly doped diffusion. (LDD), and diffusion and gate degeneration. While conventional single transistor and capacitor cell configurations are widely used, only transistor anti-fuse cells are preferred due to the semiconductor array area savings that can be achieved for high density applications. Such transistor-only antifuse must be reliable and simple to manufacture in a low cost CMOS process.

Figure 4 shows that any of the embodiments can be used in accordance with an embodiment of the present invention. A cross-sectional view of an antifuse transistor fabricated in a standard CMOS process. In the presently shown example, the antifuse transistor is almost identical to a simple thick gate oxide, or an input/output MOS transistor with a floating diffusion termination. The disclosed anti-fuse transistor, also known as a split-channel capacitor or a semi-transistor, can be reliably programmed such that the fuse link between the polysilicon gate and the substrate can be predictably confined to a particular region of the device. . The cross-sectional view of Figure 4 is taken along the length of the channel of the device, which in the presently described embodiment is a p-channel device. Those skilled in the art will appreciate that the present invention can be implemented as an n-channel device.

The anti-fuse transistor 100 includes a channel region formed in the substrate A variable thickness gate oxide 102, a polysilicon gate 106, a sidewall spacer 108, a field oxide region 109, a diffusion region 110, and an LDD region 114 in the diffusion region 110 are formed on 104. The bit line contact 116 is shown in electrical contact with the diffusion region 110. The variable thickness gate oxide 102 is composed of a thick oxide and a thin gate oxide such that a portion of the length of the channel is covered by the thick gate oxide and the remainder of the length of the channel is covered by the thin gate oxide cover. Typically, the thin gate oxide is capable of undergoing an area where the oxide collapses. On the other hand, the thick gate in contact with the diffusion region 110 The pole oxide edge defines an access edge that prevents the gate oxide from collapsing and the current between the gate 106 and the diffusion region 110 for programming the antifuse transistor. The distance in which the thick oxide portion extends into the channel region depends on the mask level, and the thick oxide portion is formed to be at least as long as the minimum length of the high voltage transistor formed on the same wafer.

In a preferred embodiment, the diffusion region 110 is via a bit Line contact 116 is connected to the bit line, or other line for sensing current from polysilicon gate 106, and may be doped to conform to a programming voltage or current. The diffusion region 110 is formed adjacent to the thick oxide portion of the variable thickness gate oxide 102. In order to additionally protect the edges of the anti-fuse transistor 100 from high voltage or current leakage damage, a resistor protection oxide (RPO), also known as a germanide-protected oxide, may be introduced during the process to additionally metal particles and The edges of the sidewall spacers 108 are separated. This RPO is preferably used during the deuteration process to prevent only a portion of the diffusion region 110 and a portion of the polysilicon gate 106 from being deuterated.

As we all know, it is known that deuterated transistors have higher leakage. Flow, and therefore has a lower breakdown voltage. Thus having a non-deuterated diffusion region 110 will reduce leakage current. Diffusion region 110 can be for low voltage transistors or high voltage transistors or a combination of the two to cause the same or different diffusion curve doping.

A simplified plan view of the anti-fuse transistor 100 is shown in the figure 5a. Bit line contact 116 can be used as a visual reference point to locate the plan view using the corresponding cross-sectional view of FIG. The active area 118 is a device area that forms the channel area 104 and the diffusion area 110, which is borrowed during the process Defined by the OD mask. The dashed outline 120 defines the area in which the thick gate oxide is to be formed via the OD2 mask during the process. More specifically, this area surrounded by dashed outline 120 specifies the area where thick oxide is to be formed. OD simply refers to an oxide-defining mask that is used to define a region of oxide to be formed on a substrate during a CMOS process, and OD2 refers to a second oxide-defining mask that is different from the first oxide-defining mask. cover. Details of the CMOS process steps for fabricating the anti-fuse transistor 100 will be discussed later. In accordance with an embodiment of the invention, the area of the thin gate oxide defined by the edge of active region 118 and the rightmost edge of the OD2 mask is minimized. In the presently shown embodiment, this area can be minimized by offsetting the rightmost OD2 mask edge toward the parallel edges of the active area 118.

Figure 5b is another depiction of the antifuse 100 of Figure 5a. in In Figure 5a, the OD2 mask 120 is shown as possibly extending over a large area covering all of the memory array. As previously discussed, the OD2 mask 120 defines the area in which the thick gate oxide is to be formed. An opening 121 defining a region in which no thick gate oxide is to be formed is formed in the OD2 mask 120. Instead, the thin gate oxide will grow in the area defined by the opening 121. Those skilled in the art will appreciate that in a memory array configuration in which a plurality of anti-fuse memory cells 100 are arranged in columns, a rectangular opening can overlap all of the memory cells to define for each active region 118. Thin gate oxide region.

The programming of the anti-fuse transistor 100 is based on gate oxide Crash to form a permanent link between the gate and the lower channel. Gate oxide breakdown conditions (voltage or current and time) are mainly determined by i) gate dielectric Thickness and composition, ii) defect density, and iii) gate area, gate/diffusion perimeter. The thick and thin gate oxide combination of the antifuse transistor 100 is combined in the thin gate oxide portion of the device, particularly in the oxide collapse region, resulting in a local drop gate breakdown voltage. In other words, the disclosed structure assumes that oxide collapse is limited to the thinner gate oxide portion.

In addition, the anti-fuse transistor embodiment of the present invention utilizes Types are prohibited for gate oxide design layout and CMOS fabrication design rules to enhance gate oxide breakdown performance. All gate oxide processing steps in today's CMOS process assume that the gate oxide thickness is uniform and optimized for the active gate region. By introducing a variable thickness gate oxide device into a standard CMOS process, additional defects and electric field disturbances are created at the boundary between the thick and thin gate oxides. Such defects may include, but are not limited to, oxide thinning, plasma etch at the boundary, residues from the cleaning process, and different thermal oxidation rates between the unmasked and partially masked regions. Caused by the depression. All of these effects increase the trap and defect density of the thin oxide boundary, resulting in increased leakage current and locally reducing the breakdown voltage. Therefore, a low voltage, tight anti-fuse structure can be produced without any process modification.

In a typical CMOS process, the diffusion region, LDD, And channel implantation is different for thin gate oxide transistors and thick gate oxide transistors. According to an embodiment of the present invention, if the generated threshold voltage of the thin gate oxide is not greater than the threshold voltage of the thick gate oxide, the diffusion region of the anti-fuse transistor, the LDD, and the thin gate oxide channel implant Can be any type; corresponding to the low voltage type of thin gate oxide, or corresponding to High voltage type of thick gate oxide (I/O oxide), or both.

Production from a standard CMOS process in accordance with an embodiment of the present invention The method of producing a variable thickness gate oxide is a well known two-step oxidation process. A flow chart outlining this process is shown in Figure 6, while Figures 7a-7c show the stages of variable thickness gate oxide formation corresponding to the specific steps in the process.

First, in step 200, the intermediate gate oxide is in the The OD mask grows in all active zones determined by the mask. In Figure 7a, this is shown as intermediate gate oxide 300 on the substrate, formed over channel region 302. In a subsequent step 202, the intermediate gate oxide 300 is removed from all of the specified thin gate oxide regions using an OD2 mask. Figure 7b shows the residual portion of the intermediate gate oxide 300 and the future thin oxide region 304. In the final gate oxide formation step 204, the thin oxide is again grown in all of the active regions originally defined by the OD mask. In FIG. 7c, thin gate oxide 306 grows over intermediate gate oxide 300 and thin oxide region 304. In this embodiment, the thick gate oxide is formed by a combination of removing the intermediate gate oxide and growing the thin gate oxide over the residual intermediate gate oxide.

As a result, it is covered by the OD2 mask during step 202. The resulting thick gate oxide region will have a gate oxide thickness that is a combination of intermediate gate oxide 300 and last thin gate oxide 306. The same procedure can be extended for more than two oxidation steps, or other equivalent procedures can be used to create two or more gate oxide thicknesses on the same die, which are masked by at least one thick gate oxide OD2 Decide.

Typically, the OD2 mask is considered to be a non-critical mask step The use of a low resolution mask and design rules requires a large edge of the OD2 mask over the active gate region and, in particular, no OD2 mask that ends in the active gate region. According to the present invention, the OD2 mask ends in the active gate region, which produces a thicker gate oxide (i.e., diffusion junction) on the drain and a comparison on the opposite side. Separation channel anti-fuse structure of thin gate oxide (either channel or non-connected source side). In principle, this technique requires that the gate length (polysilicon line width) should be greater than the minimum process and depends on the actual OD2 mask tolerance, otherwise no process or mask level changes are required. The minimum gate length for the split channel antifuse structure can be approximated as the sum of the minimum gate lengths for thick and thin gate oxides. Those skilled in the art will appreciate that accurate calculations can be generated based on mask tolerances, and the gate length can be minimized by tightening the OD2 mask tolerance.

Once the variable thickness gate oxide has been formed, the step can be 206 uses an additional standard CMOS processing step to complete the anti-fuse transistor structure shown in FIG. For example, this can include the formation of polysilicon gates, LDD regions, sidewall spacers, RPOs, and diffusion regions, as well as deuteration. In accordance with a preferred embodiment of the disclosed process, a deuteration step is employed to deuterate the polysilicon gate and floating diffusion regions of the antifuse transistor. The RPO is formed in advance over the diffusion region to protect it from deuteration. As mentioned previously, deuterated floating diffusion regions will enhance oxide collapse in this region.

One problem that is considered with respect to the above described antifuse transistors is retention, or reliability, or unprogrammed cells. Anti-fuse memory cell system Programming is accomplished by forming a conductive path between the polysilicon gate and the via through a thin gate oxide. The generated programming state can be detected in a read operation by applying a read voltage to the gate and sensing the voltage of the bit line to which the antifuse is connected. Typical read voltages range from 1.5V to 2.0V depending on the process technology. This voltage may exceed the maximum voltage of the DC bias allowed by the gate of the low voltage transistor portion of the cell (eg, 1V device is 1.1V). In other words, the read voltage may be high enough to program the cells that remain in the unprogrammed state. One factor that maximizes the reliability of the final programmed anti-fuse cell is to minimize the area of the thin gate oxide of the variable thickness gate oxide.

Figure 8a shows that it can be used in accordance with an embodiment of the present invention A plan view of an antifuse transistor that minimizes the thin gate oxide area fabricated in any standard CMOS process. For example, it can be used in the manufacturing steps outlined in Figure 6. Figure 8b shows a cross-sectional view of the antifuse transistor of Figure 8a taken along line A-A. The antifuse 400 of Figure 8a is very similar to the antifuse 100 shown in Figure 5a, except that the area of the variable thickness gate oxide below the polysilicon gate is minimized.

The anti-fuse transistor 400 includes a channel region formed in the substrate Variable thickness gate oxide 402, polysilicon gate 406, sidewall spacer 408, diffusion region 410, and LDD region 412 in diffusion region 410 on 404. The variable thickness gate oxide 402 is composed of a thick oxide and a thin gate oxide such that a major region of the channel length is covered by the thick gate oxide and a small portion of the length of the channel is formed by the thin gate oxide Covered. As shown in Figure 8a, the thick gate oxide region 414 covers most of the active region 416 below the polysilicon gate 406, except for small squares. Thin gate oxide region 418. The anti-fuse transistor 400 can be a non-volatile memory cell and thus will have a bit line contact 420 in electrical contact with the diffusion region 410. The formation of the shape and size of the thick gate oxide region 414 and the thin gate oxide region 418 will be discussed in greater detail below.

Figure 9 is an enlarged plan view of the antifuse transistor of Figure 8a, To emphasize the planar geometry of variable thickness gate oxides. The anti-fuse transistor 500 is comprised of an active region 502 having overlapping polysilicon gates 504. In Figure 9, the shaded portion of the polysilicon gate has been removed to clarify the characteristics below it. A variable thickness gate oxide is formed between the active region 502 and the polysilicon gate 504 and is comprised of a thick gate oxide region 506. According to this embodiment, the thick gate oxide region 506 can be considered to be at least two rectangular segments. Those skilled in the art will appreciate that the outlines of the sections visually decompose the thick gate oxide shape into a rectangular shape. A first thick gate oxide segment 508 extends from the first end of the channel region coincident with the leftmost edge of the polysilicon gate 504 to the second end of the channel region. Section 508 can be considered to be a rectangular shaped area having a width that is less than the width of the channel area. The second thick gate oxide segment 510 is adjacent the first segment 508 and extends a predetermined distance of the channel length from the same first end of the channel region. The second thick gate oxide segment 510 has a width substantially equal to the difference between the channel width and the width of the first segment 508.

Because the second thick gate oxide segment 510 is in the channel region The middle end, as it is section 508 and 510 on both sides and the edge of active zone 502 on the other two sides, the residual area is also rectangular in shape. This residual region is a thin gate oxide region 512. In the OD2 mask While 513 defines the region in which the thick oxide is to be formed, the OD2 mask 513 has a rectangular opening 514 in which the thick oxide is not formed. The thin gate oxide will grow in the area defined by the opening 514. Stated another way, the area outside the rectangular profile 514 forms a region of thick gate oxide. Dotted dashed line 513 may represent the OD2 mask used during the process, positioned such that the angle of opening 514 overlaps the corner of active region 502 below polysilicon gate 504. The size of the opening 514 can be selected to any size, but with a preferred size set, as will be described with reference to FIG. In a single transistor anti-fuse memory cell, bit line contacts 516 are formed for electrical connection to bit lines (not shown).

Figure 10 is an anti-melting of Figure 9 in accordance with an embodiment of the present invention. A planar arrangement of memory arrays composed of filament cells. The memory array has anti-fuse memory cells arranged in rows and columns, wherein polysilicon gates 504 formed as continuous polysilicon lines extend over active regions 502 of each of the anti-fuse memory cells in a column. Each polysilicon line is associated with logic word lines WL0, WL1, WL2, and WL3. In the presently illustrated embodiment, each active region 502 has a polysilicon gate 504 to form a two antifuse transistor that shares the same bit line contact 516 and active region 502.

In the area used to define the thin gate oxide to be grown The opening 514 in the OD2 mask 513 is rectangular in shape and is sized and positioned such that each of its four corners overlaps the angular region of the four antifuse transistor active regions 502 to define a thin gate Oxide region 512. Ideally, the thin gate oxide has at least one dimension below the minimum feature size of the process which can be obtained by the overlap between the two mask regions. A mask area is a diffusion mask, also referred to as an active area mask, and a second mask area is a rectangular opening 514 in the OD2 mask 513. Both masks are of non-critical width, meaning that they are larger than the minimum allowable width. Thus, by locating the overlap of the two masks, the area of the thin gate oxide region 512 can have a size that is nearly equal to or lower than the minimum feature size for a custom process or technique. Thus, the size of the rectangular shaped opening 514 is selected based on the spacing between the horizontally adjacent active regions 502 and the spacing between the vertically adjacent active regions 502 such that the corners of the opening 514 and the diffusion mask used to define the active region 502 The area of overlap between is less than or equal to the minimum feature size of the fabrication technique.

The size of the opening 514 is selected to be square or rectangular The thin gate oxide region 512 is minimized. Those skilled in the art will appreciate that the selected dimensions take into account alignment errors and manufacturing anomalies, such as becoming an edge of a 90 degree angle. The high accuracy for the fabrication of the thin gate oxide region 512 can be obtained by using a high level mask. High grade masks are provided by the use of higher quality glass, materials, and/or mask printing equipment.

Therefore, the size of the minimized feature can be greatly improved The reliability of the anti-fuse cell is programmed at the end of the gate oxide region 512. The shape of the thin gate oxide region 512 is rectangular or square, resulting in a minimized area. According to other embodiments, instead of having a single rectangular opening 514 that overlaps four antifuse active regions 502 as shown in FIG. 10, a plurality of smaller openings may be used. For example, the opening can be shaped to overlap only the two horizontally adjacent active regions 502. Alternatively, the opening can be shaped to overlap only two perpendicularly adjacent active regions 502. In addition, it is possible to use a thin gate oxide region in size than desired. Fields 512 are larger individual rectangles to overlap with active regions 502. While any number of rectangles of any size are contemplated by the previously shown embodiments, the thin gate oxide may be triangular in shape.

Anti-fuse electro-crystalline system is programmed by destroying thin gate oxide The thin gate oxide at the thin/thick gate oxide boundary is preferred. This is accomplished by applying a sufficiently high voltage difference between the gate and the channel of the cell to be programmed, and if there are other cells, applying a substantially lower voltage difference across all of the provided cells. Thus, once a permanent conductive link is formed, current applied to the polysilicon gate will flow through the link and channel to the diffusion region, which can be sensed by conventional sense amplifier circuitry. For example, a VPP high voltage level can be applied to the polysilicon gate 504 while a lower voltage, such as ground, is applied to its corresponding bit line. Unprogrammed memory cells will have bit lines that are biased to a voltage higher than ground, such as VDD. Although a programming circuit is not shown, those skilled in the art will appreciate that such a circuit can be coupled to a bit line and incorporated into a word line driver circuit. Reading the anti-fuse memory cell can be accomplished by pre-charging the bit line to ground and applying a read voltage, such as VDD, to the polysilicon gate. A programmed antifuse with a conductive link pulls its bit line to VDD. The end programming antifuse lacking a conductive link will behave like a switching capacitor with very low leakage current. Therefore, even if there is a change, the bit line voltage does not substantially change. The voltage change can be sensed by the bit line sense amplifier.

Figure 11 is an antifuse electric power according to another embodiment of the present invention. The enlarged planar arrangement of the crystals. The anti-fuse transistor 600 is substantially identical to the anti-fuse transistor 500 and thus has the same active region 502, polysilicon gate The pole 504 and the bit line contact 516. The anti-fuse transistor 600 has a variable thickness gate oxide of a different shape. The thick gate oxide region 602 can be considered to consist of at least two rectangular segments and a triangular segment. A first thick gate oxide region 604 extends from the first end of the channel region coincident with the leftmost edge of the polysilicon gate 504 to the second end of the channel region. Section 604 can be considered to be a rectangular shaped area having a width that is less than the width of the channel area. The second thick gate oxide segment 606 is adjacent the first segment 604 and extends a predetermined distance of the channel length from the same first end of the channel region. The second thick gate oxide segment 606 has a width substantially equal to the difference between the channel width and the width of the first segment 604. The third gate oxide section 608 is triangular in shape and has a 90 degree side adjacent to the first thick gate oxide section 604 and the second thick gate oxide section 606. Section 606 can include section 608 such that the predetermined distance is set by the hypotenuse of section 608. The remaining triangular regions having 90 degree sides formed by the edges of the active regions 502 are thin gate oxide regions 610.

The dotted diamond region 612 defines the OD2 mask 513 An opening in which a thin gate oxide is grown. Stated another way, the area outside the diamond profile 612 and within the OD2 mask 513 forms a region of thick gate oxide. The dashed outline 612 is an opening in the OD2 mask 513 used during the process and is positioned such that the edge of the opening 612 overlaps the corner of the active region 502 below the polysilicon gate 504. In the presently shown embodiment, opening 612 is a 45 degree rotated version of opening 514 of FIG. The size of the opening 612 can be selected to any size, but with a preferred size set, as will be described with reference to FIG.

Figure 12 is an inverse of Figure 11 in accordance with an embodiment of the present invention. A planar arrangement of memory arrays composed of fuse cell cells. The memory array has anti-fuse memory cells arranged in rows and columns, wherein polysilicon gates 504 formed as continuous polysilicon lines extend over active regions 502 of each of the anti-fuse memory cells in a column. The arrangement configuration of the polysilicon gate 504 with respect to the active region 502 is identical to that shown in FIG.

In the area used to define the thin gate oxide to be grown The opening 612 in the OD2 mask 513 is diamond-shaped in shape and is sized and positioned such that each of its four edges overlaps the angular region of the four anti-fuse transistor active regions 502 to define a thin gate Polar oxide region 610. Ideally, each of the thin gate oxide regions 610 is below the minimum feature size of the process. The overlap is between the two mask regions, one is also referred to as the diffuser mask of the active region mask, and the second is the OD2 mask 513 having the diamond shaped opening 612. It should be noted that the opening 612 is associated with other characteristics, i.e., the polysilicon gate 504 and the active region 502, which are defined by lines that are at 90 degrees to each other, are considered to be rhomboidal. Thus, in relation to such characteristics, the opening 612 is diamond shaped and preferably has a defined line at 45 degrees associated with the defined line of the polysilicon gate or active region 502.

Again, the two masks are all non-critical width, meaning that Equal to greater than the minimum allowable width. Thus, by locating the overlap of the two masks, the area of the thin gate oxide region 610 can have a size that is nearly equal to or lower than the minimum feature size for a custom process or technique. Thus, the size of the diamond shaped opening 612 is selected based on the spacing between the horizontally adjacent active regions 502 and the spacing between the vertically adjacent active regions 502 such that at the corners of the opening 612 and The overlap area between the diffusion masks used to define the active region 502 is less than or equal to the minimum feature size of the fabrication technique.

The size of the diamond opening 612 is selected to be a triangular shape The thin gate oxide region 610 is minimized. The selected dimensions take into account alignment errors and manufacturing anomalies, and high-grade masks can be used to tighten manufacturing tolerances.

Embodiments of the previously described non-volatile memory cells Regarding a single anti-fuse transistor memory cell. The variable thickness gate oxide can have a thick gate oxide substantially equivalent to the gate oxide for a high voltage transistor on the same wafer. Similarly, a variable thickness gate oxide can have a thin gate oxide substantially equivalent to a gate oxide for a low voltage transistor on the same wafer. Of course, both thick and thin gate oxide regions can have a thickness that is tailored only to the memory array.

According to other embodiments of the present invention, the access transistor can be An antifuse transistor is formed in series to provide a ditectic antifuse cell. Figures 13a and 13b are plots of two transistor anti-fuse memory cells in accordance with an embodiment of the present invention.

Figure 13a shows an embodiment according to the invention having A plan view of a two transistor anti-fuse memory cell 700 that minimizes the thin gate oxide area fabricated by any standard CMOS process. Figure 13b shows a cross-sectional view of memory cell 700 of Figure 13a taken along line B-B. The dimorphic anti-fuse memory cell 700 is comprised of an access transistor in series with an antifuse transistor. The structure of the antifuse transistor can be identical to that of the transistors shown in Figures 8a through 12. For this example, assume an anti-fuse transistor and The transistors shown in Figure 8b are identical, and thus the same reference numerals indicate the same previously described characteristics. More specifically, the structure of the variable thickness gate oxide is the same as that shown in FIG. 8b except that the diffusion region 410 does not have a bit line contact formed thereon.

The access transistor has a much overlap with the gate oxide 704 Crystal gate 702. A system that forms one side of the gate oxide 704 shares a diffusion region 410. Another diffusion region 706 is formed on the other side of the gate oxide 704, which will have bit line contacts 708 formed thereon. The two diffusion regions can have an LDD region adjacent to the vertical edges of the gate oxide 704. Those skilled in the art will appreciate that the diffusion region 706 can be doped identically to the diffusion region 410, but can be doped differently depending on the desired operating voltage to be used.

Variable thickness gate oxide 402 with previously described There are thick gate oxide regions and thin oxide regions. The thickness of the thick gate oxide region 704 will be the same as the thickness of the thick gate oxide region of the variable thickness gate oxide 402. In one embodiment, the access transistor can be fabricated using a high voltage transistor process, or the same process used to form the thick gate oxide region of the variable thickness gate oxide 402. The polysilicon gate 702 can be formed simultaneously with the polysilicon gate 406.

Operation and previous description of two-crystal anti-fuse memory cells The operation of a single transistor anti-fuse cell is similar. Programming an anti-fuse transistor requires applying a high voltage to the VCP polysilicon line while keeping the bit line grounded. The access transistor is turned on to couple the shared diffusion region to ground (via the bit line).

Figure 14 is a diagram of Figure 13a and in accordance with an embodiment of the present invention. The planar arrangement of the memory array consisting of 13b diode-anti-fuse memory cells. The memory array has memory cells arranged in rows and columns, wherein polysilicon gates 406 formed as continuous polysilicon lines extend over active regions 416 of each of the anti-fuse memory cells in a column. Each polysilicon line is associated with logic cell plates VCP0, VCP1, VCP2, and VCP3. The polysilicon gate 702 is formed as a continuous polysilicon line extending over the active region 416 of each of the anti-fuse memory cells in a column. These polysilicon lines are associated with logic word lines WL0, WL1, WL2, and WL3. In the presently illustrated embodiment, each active region 416 has two pairs of polysilicon gates 406/702 to form a two antifuse transistor that shares the same bit line contact 708 and active region 416.

In the area used to define the thin gate oxide to be grown The opening 710 in the OD2 mask 513 is rectangular in shape and is sized and positioned such that each of its four corners overlaps the angular region of the four anti-fuse transistor active regions 416 to define a thin gate Oxide region 418. The same related mask overlap criteria described with respect to the embodiment of Figure 10 are applied to this embodiment. The dimensions of the rectangular shaped opening 710 are selected based on the spacing between the horizontally adjacent active regions 416 and the spacing between the vertically adjacent active regions 416 such that between the corners of the opening 710 and the diffusion mask used to define the active region 416. The overlap area is less than or equal to the minimum feature size of the fabrication technique.

The embodiment of Figure 14 is configured to have separately controlled cells Meta-boards VCP0, VCP1, VCP2, and VCP3, which allow for improved control Prevent accidental programming of unselected cells. In another embodiment, VCP0, VCP1, VCP2, and VCP3 can be connected to a common node. In such an embodiment, a particular programming sequence is used to prevent accidental programming of unselected cells. The programming sequence for this alternative embodiment begins by precharging all word lines and bit lines to a high voltage level, after which the common cell board is driven to the programming voltage VPP. Using the embodiment of Figure 13b, for example, this would result in pre-charging the diffusion region 410 to a high voltage level. The word line to be programmed is selected by deselecting all other word lines, that is, by driving them to a low voltage level. The bit line voltage connected to the selected memory cell is then driven to a low voltage level, such as ground.

Figure 15 is a diagram showing a second crystal according to another embodiment of the present invention. A planar arrangement of memory arrays composed of bulk anti-fuse memory cells. The memory array of Figure 15 is identical to the memory array of Figure 14 except that the diamond shaped opening 712 in the OD2 mask 513 is used to define a thin gate oxide region of a variable thickness gate oxide. The same related mask overlap criteria described with respect to the embodiment of Figure 12 are applied to this embodiment.

In a previously disclosed embodiment of the invention, a thick gate oxygen One of the segments has a length that extends from one end of the channel region to the other end of the channel region. According to another embodiment, the length of this thick gate oxide segment is slightly reduced such that it does not extend completely across the full length of the channel region. Figure 16 is a plan layout of an antifuse transistor in accordance with another embodiment of the present invention. In FIG. 16, the anti-fuse transistor 800 includes an active region 802, a polysilicon gate 804, and a bit line contact 806. The active region 802 below the polysilicon gate 804 is the channel region of the anti-fuse transistor 800. In the present embodiment, the OD2 mask 808 defines a region in which the thick oxide is to be formed, and includes an "L" shaped opening 809 in which the thin gate oxide overlapping the active region 802 will grow. This embodiment is similar to the embodiment shown in Figure 9, except that a thick gate oxide segment (i.e., 508) extends to a top edge of the channel region and a second predetermined distance for adjacent oxide segments. The first predetermined distance (ie, 510). Thus, the thin gate oxide will grow between the first predetermined distance and the top edge of the channel region, and between the second predetermined distance and the top edge of the channel region.

The previously described embodiment of the anti-fuse transistor has a fixed The channel area of the width. According to other embodiments, the channel region may have a variable width that spans the length of the channel region. Figure 17a is a plan layout of an antifuse transistor in accordance with another embodiment of the present invention. In FIG. 17a, the anti-fuse transistor 850 includes an active region 852, a polysilicon gate 854, and a bit line contact 856. The active region 852 below the polysilicon gate 854 is the channel region of the anti-fuse transistor 850. In the present embodiment, the OD2 mask 858 defines a region in which the thick oxide is to be formed, and includes a rectangular opening 859 in which the thin gate oxide overlapping the active region 852 will grow. The active region below the polysilicon gate 854 is "L"-shaped, and the rectangular opening 859 has a bottom edge that ends at a predetermined distance from the top edge of the channel region.

Figure 17b shows the shadow without the polysilicon gate 854 The same anti-fuse transistor 850 is depicted to depict the thick gate oxide region of the channel region. In the present embodiment, the first thick gate oxide segment 860 extends from the diffusing edge of the channel region to a first predetermined distance defined by the bottom edge of the rectangular opening 859. The second thick gate oxide segment is L-shaped and includes Secondary segments 862 and 864. Those skilled in the art will appreciate that the outline of the sub-sections visually decomposes the shape of the thick gate oxide segments to form a rectangular shape. The secondary section 862 extends a first predetermined distance from the diffusing edge of the channel region while the secondary section 864 extends a second predetermined distance from the diffusing edge of the channel region. The second predetermined distance is between the first predetermined distance and the diffusing edge of the channel region. The thin gate oxide region extends from the first predetermined distance of the first gated oxide region 860 and from the secondary segment 862 to the top edge of the channel region.

Figure 18a is an anti-fuse according to another embodiment of the present invention The planar arrangement of the transistors. In Fig. 18a, the antifuse transistor 880 includes the same characteristics as those of Fig. 17. In the present embodiment, the active region below the polysilicon gate 854 is "T"-shaped, and the rectangular opening 859 has a bottom edge that ends at a predetermined distance from the top edge of the channel region. Figure 18b shows the same anti-fuse transistor 880 without the shadow of polysilicon gate 854 to depict the thick gate oxide region of the channel region.

In this embodiment, there is a first thick gate oxide segment and The second gate oxide segment. The first thick gate oxide segment is L-shaped and includes secondary segments 884 and 886. The second thick gate oxide section is L-shaped and includes secondary sections 888 and 890. The secondary section 886 extends a first predetermined distance from the diffusing edge of the channel region, the first predetermined distance corresponding to the bottom edge of the rectangular opening 859. The secondary section 884 extends a second predetermined distance from the diffusing edge of the channel region, wherein the second predetermined distance is between the first predetermined distance and the diffusing edge of the channel region. The secondary sections 888 and 890 of the second thick gate oxide section are identically configured as sub-sections 884 and 886, respectively. The first predetermined distance of the thin gate oxide from the secondary segments 886 and 890 Extend to the top edge of the channel area.

In the previously described embodiments of Figures 17a and 18a, thin The gate oxide region extends from the bottom edge of the rectangular opening 859 to the top edge of the channel region. Because the channel region has a variable width, wherein the portion adjacent the diffusion edge is larger than the portion adjacent the top edge of the channel region, the overall thin gate oxide region can be smaller than the anti-fuse embodiment shown in Figure 5a. According to other embodiments, the thin gate oxide of the antifuse transistor embodiment of Figures 17a and 18a is further minimized by applying an OD2 mask having rectangular or diamond shaped openings as shown in Figures 9 and 11.

Figure 19 is an antifuse electric power according to another embodiment of the present invention. The planar arrangement of the crystals. The anti-fuse transistor 900 is similar to the anti-fuse transistor 850 of FIG. 17b except that the OD2 mask 902 includes a rectangular opening 904 that is shaped and positioned for drawing the thin gate oxide region 906. In the presently illustrated embodiment, the thick gate oxide includes a first thick gate oxide segment 908 and a second thick gate oxide segment having sub-segments 862 and 864. Sub-sections 862 and 864 are identical to the sub-sections of the embodiment of Figure 17b. However, due to the overlapping angle of the rectangular opening 904 and the channel region, the first thick gate oxide segment 908 extends only a predetermined distance of the channel length from the diffusion edge. Thus, the thick gate oxide section 908 is shorter in length than the secondary section 862. Thus, the anti-fuse transistor 900 has a thinner gate oxide region that is smaller than the embodiment of Figure 17a. The application of the OD2 mask 902 having a rectangular opening 904 can be applied to the anti-fuse transistor 880 of Figure 18b having the same result.

By applying a diamond shaped opening in the OD2 mask, as previously The thin gate oxide area of the anti-fuse transistors 850 and 880 is further reduced as depicted in FIG. Figure 20 is a plan layout of an antifuse transistor in accordance with another embodiment of the present invention. The anti-fuse transistor 950 is similar to the anti-fuse transistor 880 of FIG. 18b except that the OD2 mask 952 includes a rectangular opening 954 that is shaped and positioned for drawing the thin gate oxide region 956. In the presently illustrated embodiment, the thick gate oxide comprises first and second thick gate oxide segments. The first thick gate oxide section includes sub-sections 888 and 890 which are identical to the sub-sections of the embodiment of Figure 18b. The second thick gate oxide section includes sub-sections 958 and 960.

Due to the overlap of the diamond shaped opening 954 and the channel area, The second thick gate oxide sub-section 960 extends only from the diffusion edge to a predetermined distance of the channel length, which is defined by the oblique boundary of the diamond-shaped opening 954. Thus, antifuse transistor 950 can have a thiner gate oxide region that is smaller than the embodiment of FIG. The application of the OD2 mask 952 having a diamond shaped opening 954 can be applied to the antifuse transistor 850 of Figure 17b having the same result. It should be noted that the dimensions of the secondary sections 958 and 960 are chosen such that the hypotenuse of the opening 954 does not overlap the channel area covered by the secondary section 958.

In describing the rectangular and diamond-shaped openings in the OD2 mask Other opening shapes with equal effectiveness can be used. For example, the opening in the OD2 mask can be hexagonal, octagonal, or even substantially circular after the OPC is added. Additionally, the rectangular opening can be rotated at any angle associated with the polysilicon gate.

The previously described embodiments of Figures 16-20 relate to a single transistor anti-fuse memory cell. The embodiment of Figures 16-20 can be applied to two electric A crystal anti-fuse cell in which an access transistor is formed in series with an antifuse transistor. 21-24 depict various embodiments of a two-crystal anti-fuse memory cell with a minimized oxide area.

21 is a second transistor anti-melting according to an embodiment of the present invention. The planar arrangement of the wire crystal.

In accordance with other embodiments of the present invention, an access transistor can be formed in series with an antifuse transistor to provide a ditectic antifuse cell. Figures 13a and 13b are plots of a two transistor anti-fuse memory cell of an embodiment having a variable width in a channel region in accordance with the present invention. The dimorphic anti-fuse memory cell 1000 is similar to the ditectic cell 700 of Figure 13a. The access transistor includes an active region 1002, a polysilicon gate 1004, and a bit line contact 1006. The antifuse transistor includes an active region 1002 and a polysilicon gate 1008. The common source/drain diffusion region 1010 is shared between the access transistor and the antifuse transistor. A variable thickness gate oxide having a thick gate oxide region and a thin gate oxide region under the polysilicon gate 1008 and covering the channel region. The OD2 mask 1012 depicts the area in which the thick gate oxide is to be formed, and includes a rectangular opening 1013 that overlaps the active region 852 where the thin gate oxide will grow. The thin gate oxide region 1014 covers the bottom edge of the rectangular opening 1013 and the channel region between the top edges of the channel region.

In Figure 21, the channel region of the anti-fuse transistor has a variable width. In the embodiment of Figure 22, the channel region of the anti-fuse transistor has a fixed width but is smaller in width than the remaining portion of the active region and the access transistor. More specifically, a two-crystal anti-fuse memory cell 1050 is similar to memory cell 1000 except that active region 1052 is shaped such that common source/drain diffusion region 1054 now has a variable width, leaving the channel region of the antifuse transistor unchanged, but less than the width. Take the channel area of the transistor.

Figure 23 is another replacement of the two-crystal anti-fuse memory cell. Generation examples. The two-crystal anti-fuse memory cell 1100 is similar to the two-crystal anti-fuse memory cell 1000 of FIG. 21 except that the active region 1102 is formed such that the anti-fuse transistor has a "T"-shaped channel region. Not the "L"-channel area. 24 is similar to the embodiment of FIG. 23 except that the two-crystal anti-fuse memory cell 1150 has an active region 1152 shaped such that the anti-fuse transistor has a fixed width channel region. The common source/drain diffusion region 1154 is "T"-shaped such that it has a narrower portion.

Figure 21-24 shows the implementation of the two-crystal anti-fuse memory cell An OD2 mask having a rectangular or diamond shaped opening that is positioned to minimize the thin gate oxide region of the antifuse transistor can be used.

Standards can be used as shown in the currently described embodiments The CMOS process produces a single transistor anti-fuse memory cell with high reliability and a two-crystal anti-fuse memory cell. The masks and OD2 masks used to define the active regions may be non-critical in size, but the overlapping of alignments between particular regions may result in thin oxide regions having dimensions that are less than the minimum feature size of the process technology.

More specifically, standard CMOS processes will require a set of features that define the various features of the currently described anti-fuse memory cell embodiments. Mask. Each mask will have a different quality level depending on the characteristics to be defined. Typically, a higher level of mask is used to define smaller dimension features. The following is an example level of masking used in a standard CMOS process where a higher number indicates a higher mask level.

1. N-well, P-well, Vtp, Vtn, thick gate oxide (OD2) mask

2. Source/drain implant mask

3. Contact through hole mask

4. 2nd metal layer mask

5. Diffusion, thin oxide, contacts, and 1st metal layer mask

6. Polysilicon mask

High-grade masks, such as level 6, for low-level masks, such as level 1, will differ in terms of better glass, materials, or contain better printing equipment to make them. Different mask levels are used because certain features do not require high precision and other features are required. As can be appreciated, the work and cost for manufacturing a high level mask is substantially more than that required for a low level mask. For example, the lowest level mask can range from $3k to $5k, while the highest level mask can range from $100k to $300k.

It should be noted that the design rules are set for a particular feature to ensure that a particular region for features defined by the mask covers not only that particular region but also portions of the adjacent features. In fact, adjacent features really control where the implant occurs. For example, the OD2 shape will completely cover 10 transistor areas, which are defined by diffusion. Therefore, it does not matter where the actual mask shape ends. There is an error to allow the boundary system OD2 to be a low-level master. The reason, and therefore, the mask cost is low. In addition, when only 0.1 micron is used, the partial alignment machine achieves a tolerance of 0.06 micrometers, which is believed to be sufficient for ion implantation masks. For the fabrication of the antifuse transistors and memory arrays shown in Figures 4 through 15, the mask shape termination is important for defining thin gate oxide regions. Current grade OD2 masks for typical CMOS processes can be used to define the thin gate oxide regions of the described anti-fuse memory cells. However, the error boundaries must be taken into account, resulting in memory cells with a certain minimum size.

According to an embodiment of the invention, the use has a corresponding The OD2 mask of the level of the mask level (Level 2) of the source/drain implant of the same process is used to fabricate the anti-fuse memory cells of Figures 4-15. The OD2 mask level is equivalent to the mask level (level 5) for diffusion implantation of the same process to achieve smaller size memory cells with high reliability. Therefore, by using a high-grade OD2 mask to obtain a higher density memory array, the yield is improved, the performance is improved, and the reliability is high. Improve accuracy by ensuring that mask alignment is done with the highest possible accuracy. By using superior photolithographic equipment, photolithographic methods, and/or different light wavelengths and different mask types, any possible combination of them results in high alignment accuracy.

Use a higher level of optical with high precision alignment The OD2 mask presents advantages to the presently disclosed anti-fuse cell embodiments. More specifically, a mask shape termination that is more accurately formed using a high level OD2 mask is advantageously used to minimize particular features, such as thin oxide regions. Because the anti-fuse transistors 500 and 600 should have a minimum size of thin gate oxide regions (512 and 610), the use of high-grade OD2 masks The thin gate oxide region is allowed to be minimized to improve reliability beyond the same anti-fuse cells fabricated using standard low grade OD2 masks.

For the embodiment of Figure 5a, the OD2 shape terminal/edge is A more precise overlap under the polysilicon gate 106 allows for minimizing the thin oxide regions under the polysilicon gate. In particular, the thin oxide region will be rectangular in shape with two opposite sides defined by the width of the active region below the polysilicon gate, and the shape termination and polysilicon of the OD2 mask under the polysilicon gate. The other two opposite sides defined by the edge of the gate. The addition of high precision alignment minimizes thin oxide regions.

For example, for a 0.20 micron thin oxide region size, it will be An improvement from +/- 0.1 microns to +/- 0.06 microns would allow for a smaller oxide size of 0.04 microns, thereby reducing the size to 0.16 microns. This will improve the yield and reliability of the anti-fuse memory cells alone, since both yield and reliability are directly related to the total area of the thin gate oxide. The improvement in yield and reliability can be seen even when the alignment is improved to +/- 0.08 microns for the 90nm and 65nm processes. A high grade OD2 mask can be used in the process described in Figure 6 for use in the fabrication of thin and thick gate oxide regions for antifuse transistors.

The presently described embodiments of the present invention are described as having thin and thick gates An anti-fuse transistor for a polar oxide. Those skilled in the art will appreciate that previous semiconductor fabrication techniques may use different dielectric materials to form thin gate oxides to add to or replace oxides. Those skilled in the art will appreciate that in the same manner as previously described for OD2 masks used to define thin gate oxide regions of antifuse transistors, masks for depositing or growing dielectrics may have There is a shaped opening that is positioned to overlap the active area.

Those skilled in the art will understand that having an opening to define a thin The OD2 mask of the gate oxide region may be a combination of sub-mask shapes of smaller units of a common pattern of repeated patterns, each having a complete opening defined therein, or an opening portion defined therein, such that A matching of adjacent tilts will result in a closed opening.

The previously described embodiment illustrates how an OD2 mask can be targeted The thin gate oxide region of the antifuse transistor is minimized and oriented. According to other embodiments, the active region of an antifuse transistor that is stamped with a thin gate oxide of a fixed shape and size can be minimized. The presently described techniques utilize undesired imaging errors and distortion effects that typically occur during optical photolithography processing when fabricating semiconductor structures having deep submicron dimensions.

The semiconductor process includes patterning of the mask to define the correspondence The shape of the structure of the semiconductor structure to be formed on the semiconductor substrate. When the lens is combined, light of various wavelengths including ultraviolet light (UV) is projected via a mask for defining a shape on the substrate. Finer details of using smaller wavelengths of light to resolve patterns are well known in the art. Unfortunately, imaging errors and distortions will result in the creation of patterns that are substantially different from the desired reference shape. For example, the geometric outer corners of the diffusing region polygons in the design may end up having rounded corners in the manufacturing device. In effect, the resulting outer corners have edges that exhibit shrinkage relative to the reference polygon design. The internal angle may suffer from the opposite effect of any acute angle defined by the resulting internal angular loss, subject to spheronization and having an edge that extends beyond the original intended reference design edge. To compensate for these optical lithography distortions, optical proximity correction (OPC) is used to change the reference design The shape of the edge compensates for this imaging error. OPC techniques are well known in the art, and each processing node may have a particular OPC strategy for ensuring that the resulting fabricated semiconductor structure has the shape that conforms as closely as possible to the original reference shape. For example, experimental results or simulations will provide a known range of distortion for a particular shape. Once the type and amount of distortion can be predicted, a better OPC strategy can be used. Sample applications for OPC are now available.

Manufactured by reference to the antifuse transistor of FIG. 10 An active region 502 having a substantially geometric rectangular shape for a sub-micron process would require a mask having the shape shown in FIG. Figure 25 shows an active area pattern 2000 that will be formed on a mask. It is immediately noted that the four outer corners of the rectangular shape are enlarged by an angular extension 2002 having a rectangular shape. Such outer corners form a 90 degree angle with their intersecting edges that enclose the area. These outer corners are different from the inner angles present in the polygonal shape, such as the L-shaped active region 852 of Figure 17a, which has an internal angle at an angle of 270 degrees to the intersecting edge that encloses the region. In an L-shaped polygonal shape, the inner angle may have a polygon removed therefrom to compensate for the distortion discussed previously. Finally, the purpose of OPC is to fabricate semiconductor structures having shapes as close as possible to the reference shape.

Referring to Figure 25, it is shown in the secured area of the active area As a result, the shape is as close as possible to the mask pattern of the active region of the antifuse transistor after the OPC process of the original reference shape. The ideal quasi-shape for the active area of pattern 2000 has a rectangle that shows the outer corners in dashed lines. Additional rectangular shapes 2002 are added to the corners for specific processing and manufacturing nodes. Assuming that the lithographic distortion produces a severely rounded edge in a fabricated structure of known amplitude, which may be selected by selecting a rectangular shape 2002 The dimensions and their placement relative to the original reference shape are compensated for. In this example, the rectangular shape 2002 is a square. The resulting OPC modified pattern 2000 is applied to a mask used to fabricate the active region of the antifuse transistor. It can be observed that the overall shape of the OPC modified pattern 2000 has a larger area than the reference reference area.

Figure 26 is an OPC modified pattern that has been used in the process. An example diagram of an antifuse transistor produced after 2000. In the examples shown so far, other structures of antifuse transistors have been fabricated. The anti-fuse transistor is similar to the anti-fuse transistor 100 shown in Figures 4 and 5, as shown in the memory array diagram of Figure 10, configured in a back-to-back configuration. The anti-fuse transistor includes an active area 2010 having a bit line contact 2012 and a portion of the polycrystalline germanium word lines 2014 and 2016. The OD2 mask region 2018 shown in the dashed line defines the region in which the thick gate oxide is formed, while the regions 2020 and 2022 of the active region 2010 outside the OD2 mask region 2018 have thin gate oxides formed thereon. Things. They are also referred to as thin gate oxide regions of anti-fuse transistors. As shown in Figure 26, the active zone 2010 has a substantially rectangular shape with a defined angle. This is due to the use of OPC modified active area pattern 2000 during the process.

Oxidation of thin gates, as in other embodiments previously discussed The object areas 2020 and 2022 are minimized to promote gate oxide collapse. Thus, in accordance with another embodiment of the present invention, a reverse OPC technique is used to further minimize the area of the semiconductor structure. In the reverse OPC technique of the presently described embodiment, instead of using OPC to obtain a semiconductor structure that substantially has the original reference shape, the reference shape region is removed or intended to be omitted. Area. Since most photolithographic distortions result in semiconductor structures having area reduction associated with the reference shape, this effect is advantageously used to further reduce the selected area of the semiconductor structure. This is in complete contrast to the use of OPC for maintaining the desired reference shape.

Figure 27 shows the oxidation of a thin gate electrode according to this embodiment. The reference shape of the active region of the antifuse transistor after the reverse OPC processing for the purpose of minimizing the area of the object region. The original rectangle pattern includes the outer corners shown in dashed lines. The reverse OPC imaging pattern 2030 includes a reverse angle 2032 that removes or subtracts the area of the original rectangular pattern from the reference pattern. For example, the reverse angle appears as a depression in the reference pattern. It is assumed that the degree and characteristics of the distortion are known in advance by either of the experiments or simulations, so that the area reduction can be predetermined based on the size or shape of the reverse angle. Thus the reverse angle 2032 can be square or rectangular in shape. Thus, the inverse OPC pattern 2030 has a total area that is reduced relative to the baseline pattern.

Figure 28 is a diagram showing the reverse OPC pattern 2030 of Figure 27 A diagram of an antifuse transistor produced after a process known to have a photolithographic distortion effect is used. The same structures of Fig. 26 are presented with the same reference numerals. As shown in FIG. 28, the resulting active region 2034 has spheronized thin gate oxide regions 2036 and 2038. The total area of the thin gate oxide regions 2036 and 2038 is less than the total area of the thin gate oxide regions 2020 and 2022. The reverse OPC technique is advantageously used in an environment where it is not possible to narrow the area of interest via the arrangement of the reference pattern, for example, due to design rules. It should be noted that a combination of normal OPC and reverse OPC can be used for any reference shape. Normal OPC can be used to help maintain the baseline pattern His partial shape, while the reverse OPC can minimize the area of a particular area of the reference pattern by more distorting the characteristic portion of the reference pattern.

29 is an overview of the reverse OPC method according to the present embodiment. Flow chart. It is assumed for this method that the amount of photolithography distortion of a particular process is known. The method begins with designing a reference pattern for a semiconductor structure starting at 2050, typically by using a layout application on a computer workstation. For example, this can be the rectangular active area of the antifuse transistor shown in FIG. The selected region of the semiconductor structure is then identified for area reduction at 2052. The amount of area reduction can be limited by the minimum and maximum values. For example, this can be the area of the active region of the antifuse transistor to be covered by the thin gate oxide. At 2054, at least one selected angular region of the selected region of the reference pattern is inverted, which can be accomplished by subtracting the rectangular region from the reference pattern.

At 2056, processing at least one selected corner region is reversed A secondary process of identifying at least one geometric angle of the selected region may be included. The geometric angle is typically the common point of the two intersecting lines of the pattern, which form a 90 degree angle with each other. Depending on the shape or size of the selected region, it may only be necessary to reverse an outer corner region containing the geometric angle. Then at 2058, the size of at least one reverse corner region is set. The dimensions of the reverse corner regions may differ from one another, but are based on known photolithographic distortions currently processed to ensure that the resulting regions fall within the set minimum and maximum values, and/or do not violate current processing. Other design rules. In another enhancement, the area-reduced analog fabrication structure can be displayed on the display terminal to allow the user to see what the resulting structural shape is. When the user manually adjusts the position and size of the reverse angle, they may also have dynamic viewing changes. Ability.

Once the selected corner region is reversed, the use at 2060 is called A reverse corner region (etc.) of the reverse OPC imaging pattern produces a mask. In the present example, the mask used to fabricate the active region of the antifuse transistor can include the reverse OPC pattern 2030 shown in FIG. Finally, at 2062, the active zone structure having the resulting shape similar to the active zone 2034 produced in FIG. 28 is fabricated using the active zone mask fabricated at 2060.

Applying the previously disclosed reverse OPC technique to a rectangular shape Structure. A reverse OPC embodiment can be used for polygons having outer corners, where such polygons can be viewed as a collection of rectangular shapes. This example is illustrated by the example embodiment of Figure 19, in which the polygonal shape is segmented into a collection of cumulative rectangular shapes.

Therefore, the reverse OPC technique of this embodiment uses normal OPC The distortion that is attempted to compensate to reduce the area of the selected region of the semiconductor structure. This is achieved by reversing the angle of the geometry. In other embodiments, finer control of the distortion can be achieved by reversing more angles to achieve a step pattern at the location of the original geometric angle.

Reverse OPC technology can be used in conjunction with the previously described embodiments to reduce the thin gate oxide region of the antifuse transistor.

The above embodiments of the present invention are merely considered as examples. Variations, modifications, and variations may be applied to a particular embodiment by those skilled in the art without departing from the scope of the invention as defined by the appended claims.

2012‧‧‧ bit line contacts

2014, 2016‧‧‧ Polycrystalline 矽 word line

2018‧‧‧OD2 mask area

2034‧‧‧active area

2036, 2038‧‧‧Rolling thin gate oxide region

Claims (10)

A method of reverse optical proximity correction (OPC), comprising: providing a reference pattern of a semiconductor structure, the reference pattern being rectangular in shape; and selecting an area of the reference pattern for area reduction by optical lithography distortion An area; the at least one corner of the area is reversed to form a reverse OPC image pattern having a smaller area than the reference pattern; the semiconductor structure is fabricated to have an area corresponding to the at least one corner of the circle . The reverse optical proximity correction (OPC) method of claim 1, wherein inverting the at least one corner comprises subtracting a predefined rectangular shape from the at least one angular region of the area. The reverse optical proximity correction (OPC) method of claim 1, wherein the selecting comprises identifying an anti-fuse transistor programming area. The reverse optical proximity correction (OPC) method of claim 1 further includes fabricating the mask using the reverse OPC imaging pattern. The reverse optical proximity correction (OPC) method of claim 4, further comprising fabricating the semiconductor structure using the mask in photolithography. A reverse optical proximity correction (OPC) method according to claim 5, wherein the manufactured semiconductor structure produced has a shape substantially different from the reference pattern. Reverse Optical Proximity Correction (OPC) as in claim 6 The method wherein the reference pattern of the semiconductor structure corresponds to an active region of an antifuse transistor of a memory cell. The reverse optical proximity correction (OPC) method of claim 7, wherein the active region portion of the antifuse transistor is made of a thin gate oxide and has a greater thickness than the thin gate oxide. Covered by thick gate oxides. The reverse optical proximity correction (OPC) method of claim 8, wherein the area of the reference pattern corresponds to the thin gate oxide of the antifuse transistor. The Reverse Optical Proximity Correction (OPC) method of claim 1, further comprising applying optical proximity correction to other portions of the reference pattern for photo lithography distortion correction.