KR101700736B1 - A reverse optical proximity correction method - Google Patents

Abstract

A method of fabricating an anti-fuse memory cell having a semiconductor structure with a minimized area. The method includes providing a reference pattern of a semiconductor structure, and applying an inverse OPC technique that includes inverting selected edges of the reference pattern. Reverse OPC techniques use photolithographic distortions to provide an intentionally distorted pattern of production of a reference pattern. By inverting the edges of the geometric reference pattern, the resulting distortion pattern will have a reduced area relative to the original reference pattern. This technique is advantageous in reducing the area of the selected area of the semiconductor structure, which would otherwise not be possible with common design parameters.

Description

[0001] The present invention relates to a reverse optical proximity correction method,

The present invention relates generally to non-volatile memory. More particularly, the present invention relates to anti-fuse memory cell structures.

Over the past three decades, anti-fuse technology has attracted the attention of many inventors, IC designers and producers. An anti-fuse is a structure that can change the state of conduction, that is, an electrical device that changes state from non-conductive to conductive. Equally, the binary states can be either high resistance or low resistance, in response to an electrical stress such as a programming voltage or current. Although many attempts have been made to develop and apply anti-fuses in the microelectronics industry, most successful anti-fuse applications to date have included FPGA devices manufactured by Actel and Quicklogic, And in the redundancy or optional programming used in DRAM devices by Micron.

The development of the anti-fuse can be summarized as indicated by the following US patents.

Anti-fuse technology development began with U.S. Patent No. 3,423,646, which is capable of forming thin films built of arrays of horizontal and vertical conductors having thin dielectrics (aluminum oxide) at their crossings between conductors A diode PROM is disclosed. Such non-volatile memory has been programmed through perforation of the dielectric at some of the intersections. The formable diode will operate as an open circuit until a sufficient magnitude of voltage and duration is applied to the intersection to cause the formation of an aluminum oxide interlayer, and at the time the aluminum oxide intermediate layer is formed, the device will be operated as a tunneling diode It will work.

US 3,634,929 discloses an intermetallic semiconductor anti-fuse array wherein the structure of the anti-fuse comprises a thin dielectric material utilizing two (aluminum) conductors connected to a semiconductor diode and located above the semiconductor diode And a capacitor (AlO2, SiO2 or Si3N4).

U.S. Patent No. 4,322,822 (Mcpherson) has a programmable dielectric ROM memory structure using MOS capacitors and MOS switching elements. This cell was formed with a standard gate-oxide-over-substrate capacitor with a gate connected to a MOS transistor using a buried contact. A V-shaped grove in the capacitor area has been proposed for the anti-fuse capacitor and accordingly to lower the oxide breakdown voltage which needs to be smaller for the MOS switch. Since the capacitor is formed between the poly gate and the grounded p-type substrate, a rupture voltage must be applied to the capacitor through the access transistor. The gate / drain and gate / source edges of the access transistors are located in a second field oxide much thicker than the gate oxide of the channel region, which greatly improves the gate / source-drain breakdown voltage.

U.S. Pat. No. 4,507,757 (McElroy) proposed a method for lowering the gate oxide breakdown voltage through avalanche junction breakdown. Although the original McElory's ideas have advanced with respect to the use of gated diodes to induce local avalanche breakdown and in turn reduce the dielectric breakdown voltage by enhanced electron tunneling, He actually introduced or embodied elements of other and perhaps more important anti-fuse technologies: (a) Dual gate oxide anti-fuse: thicker access transistor gate oxide than anti-fuse dielectric. McIlroy's dual gate oxime process steps are: initial gate oxidation, etch areas for thinner gate oxide, and subsequent gate oxidation. This process is now used for standard CMOS technologies for "input / output (I / O)" and "1T (transistor)" devices. (b) As a "common-gate" (planar DRAM-like) anti-fuse connection, the access transistor connects the anti-fuse diffusion (drain) node and all the anti-fuse gates are connected to each other. This is contrary to Mr. McPherson's arrangement and causes a much denser cell because the landfill contact is removed. (c) Limiting the resistance between the common anti-fuse gate and external ground. (d) Two-terminal anti-fuse MOS device (half transistor: McLaughlin concluded that only two terminals are needed in the anti-fuse capacitor: drain (D) and gate (G) Can be completely isolated from the active area without the actual need for anti-fuse programming or operation. The bulk connection does not play any role except for avalanche breakdown. When the local substrate potential increases and becomes forward biased to the emitter of the parasitic npn device formed by the drain D, base B and source S, the carriers are collected from the abelenate breakdown .

When U.S. Pat. No. 4,543,594 (Mohsen) proposed an anti-fuse design suitable for redundancy restoration, it was less than 1985. Since such an application requires much less density than the PROM, it was easier to supply the external high voltage needed to rupture the oxide without actually passing this voltage through the access transistor. Mohsen's anti-fuse structure consists of a thin oxide (50-150 Å SiO ₂ ) polysilicon capacitor on the doped region. He believed that the silicon from the substrate, from the substrate from which the silicon or polysilicon electrode was used, was used to melt into the pin holes in the insulating layer to provide a conductor and his test data showed that the oxide layer had a thickness of about 100 A thick And a fusion takes place at a voltage of 12 to 16 volts in the case of having an area of 10 to 500 [mu] m < ² >. The current required to cause this fusion is less than 0.1 uA / um ² when calculated for each capacitor region, and the resulting fused link has a resistance of approximately 0.5 to 2 K ohms. The link, when fused, can handle voltages from room temperature to 100 milliamperes for approximately one second before healing with an open fuse. Considering electromigration wear-out, the expected wear-life of the link is substantially greater than 3E8 hours when fused.

The possibility of anti-fuse self-healing under current stress appears to be a major hurdle in the application of this technology in such areas as PROMs, PLDs, and FPGAs where constant fuse stress is required . The anti-fuse recovery problem was subsequently solved by U.S. Pat. No. 4,823,181 by Moessen and others of Actel. Actel taught how to implement a reliable programmable low-impedance anti-fuse element by using an ONO structure instead of silicon dioxide. Actel's method required ohmic contact after dielectric breakdown. This was accomplished by using a high concentration doping diffusion or by placing the ONO dielectric between two metal electrodes (or silicide layers). The need for an arsenic-doped lower diffusion electrode was later amended by U.S. Patent No. 4,899,205, where top-poly or bottom-diffusion was allowed to be highly doped.

U.S. Patent No. 5,019,878 teaches that the application of a programming voltage in the range of 10 to 15 volts from drain to source when the drain is suicided stably forms a melt filament across the channel region. The gate voltage can be applied by specific transistors to control the green light. IBM has found a similar effect by proposing a channel anti-fuse in U.S. Patent No. 5,672,994. In 0.5 um technology, BVDSS for nmos transistors is not only about 6.5V, but also when source-drain punch through occurs, it causes permanent damage and causes leakage of several kilo ohms between source and drain. .

U.S. Patent Nos. 5,241,496 and 5,110,754, which belong to Micron Corporation, disclose DRAM cell-based anti-fuses (trenches and stacks). In 1996, Micron developed a method for removing undercut defects associated with polysilicon etching in US Pat. Nos. 5,742,555 and 6,087,707, which proposed an N-well coupled antifuse as an anti- And a well-to-gate capacitor. U.S. Patent Publication No. 2002/0027822 proposed a similar anti-fuse structure, but has n + regions that have been removed to produce an asymmetric ("unbalanced") high-voltage access transistor using the N-well as the drain electrode.

U.S. Patent No. 6,515,344 proposed a range of P + / N + anti-fuse configurations and implemented a minimum size gate between two opposite type diffusion regions.

The NMOS anti-fuses were constructed with isolated deep P-wells using a standard deep N-well process. An example of deep N-well based anti-fuses is disclosed in U.S. Patent No. 6,611,040.

U.S. Patent Publication Nos. 2002/0074616 and 2004/0023440 disclose other deep N-well anti-fuses. These anti-fuses are made up of capacitors featuring a direct tunneling current rather than a Fowler Nordheim current. These applications confirm that anti-fuse performance is generally improved in the case of thinner gate oxide capacitors (typically 20 A, typically applied to transistors in a 0.13 um process).

U.S. Patent No. 6,580,145 discloses a new type of conventional anti-fuse structure utilizing dual gate oxides with thicker gate oxides used in nmos (or pmos) access transistors and thinner gate oxides used in capacitors. The N-well (or P-well) is used as the bottom plate of the anti-fuse capacitor.

The idea of creating a source-drain short across a gate by individually breaking the source-gate and drain-gate dielectric regions of the transistor is disclosed in U.S. Patent No. 6,597,234.

U.S. Patent Publication No. 2004/0004269 discloses a method of fabricating a semiconductor device comprising a MOS transistor having a high concentration doping down the channel through additional implantation (of a diode) and a gate connected to the gate of the capacitor, degenerated by a thinner gate oxide The disclosed anti-fuse is disclosed. A rupture voltage is applied to the bottom plate of the capacitor.

In U.S. Patent No. 6,667,902 (Peng), Peng describes a conventional flat DRAM-like anti-aliasing device by introducing "row program lines " that connect to capacitors and run parallel to the word lines. An attempt was made to improve the fuse array. Once decoded, the row program lines may minimize exposure of the access transistors to a high programming voltage, which may occur through already programmed cells in other cases. Peng and Fong have improved their arrays by adding a variable voltage that further controls the programming current in U.S. Patent No. 6,671,040, which allegedly controls the degree of gate oxide breakdown , Allowing multi-level or analog storage applications.

Most recently, U.S. Patent Publication No. 2003/0202376 (Peng) shows a memory array using a single transistor structure. In the proposed memory cell, Fung removed the LDD diffusion from the normal NMOS transistor. The cross-point array structure is formed of horizontal active area (S / D) stripes across vertical poly gate stripes. The drain contacts are shared between adjacent cells and are connected to horizontal word lines. The source regions are also shared and remain in a floating state. Mr. Feng assumed that if the LDD diffusion is omitted, the gate oxide breakdown location will be far enough away from the drain region and a local N + region will be created instead of the D-G (drain-gate) short. If such an area is created, the programmed cells can be detected by biasing the gate positively and sensing the gate as the drain current. To reduce the G-D (gate-drain) or S-D (source-drain) shorting problem, Feng proposed to increase the gate oxide thickness at the G-D and S-D edges through modification of the gate sidewall oxidation process. The array of Fung's requires both the source and drain regions to appear in the memory cells, the row word lines connected to the transistor drain regions, and the column bit lines formed from the transistor gates. Such uncommon connections must be very specific to Peng's programming and reading methods and require decoded high voltages (8V in a 1.8V process) applied to all drain lines except those that are programmed. The decoded high voltage (8V) is applied to the gates of the column to be programmed, while the other gates remain at 3.3V.

Although Peng achieves a cross-point memory structure, its array requires CMOS process modifications (LDD removal, a thicker gate oxide at the edge) and has the following disadvantages: (a) , Column decoders, and sense amplifiers all have to switch a wide range of voltages: 8V / 3.3V / 0V or 8V / 1.8V / 0V. (b) During program operation, 3.3V column drivers are effectively shorted to 8V row drivers or 0V drivers through the programmed cells. This causes many limitations on the array size, affecting the driver size and affecting the reliability and efficiency of programming. (c) Each program operation requires all array active areas (except the programmed row) to be biased to 8V. This results in large N ++ junction leakage currents, and again limits array size. (d) It is assumed that the gate oxide breaking spot is positioned sufficiently far from the drain region, so that no punch through occurs at the 8V bias. At the same time, the transistor must operate correctly at-1.8V biasing connected to the channel region. This is impossible without significant process modifications. (e) Peng speculated that the gate oxide would not be destroyed on the source or drain edge if LDD were not present. However, it is known to those of ordinary skill in the art that the S / D edges are the most likely locations for oxide breakdown due to field concentration and defects around the sharp edges.

Peng has attempted to solve some of the high voltage switching problems in U.S. Patent Application Publication No. 2003/0206467. The high breakdown voltage on the word lines and bit lines is now replaced by the "floating" word lines and bit lines, and the constraints on the distance from the channel to the source and drain regions have changed. Although floating word lines and bit lines can alleviate high voltage switching related problems, they do not address any of the fundamental problems described above. In addition they introduce serious coupling problems between switched and floated lines.

Today, anti-fuse developments are concentrated around three-dimensional thin film structures and special intermetallic materials. All of these anti-fuse techniques require additional processing steps that are not available in standard CMOS processes, thus prohibiting anti-fuse applications in typical VLSI and ASIC designs where programmability, And can help overcome the problems of cycle times and ever-increasing chip development costs. There is therefore a clear industry need for reliable anti-fuse structures that utilize standard CMOS processes.

All prior art anti-fuse cells and arrays require special processing steps or undergo high voltage exposure of the MOS switching elements, resulting in manufacturability and reliability problems. In addition, they are limited to low-density memory applications and Peng's single transistor cell is an exception, which in turn has a very suspicious production potential.

Therefore, it is desirable to provide a simple, reliable, high density, anti-fuse array structure suitable for implementation in standard CMOS technology without additional processing steps.

One aspect of the invention provides an inverse optical proximity correction (OPC) method. The method includes: providing a reference pattern of a semiconductor structure; Selecting a region of the reference pattern for area reduction by photolithographic distortion; And inverting at least one corner region of the region to form an inverse OPC imaging pattern having an area smaller than the reference pattern. According to embodiments of the present aspects, inverting the at least one edge region comprises removing a predetermined rectangular shape from the at least one corner region of the region, And identifying the anti-fuse transistor programming region.

In another embodiment of this aspect, the method further comprises fabricating a mask plate having the reverse OPC imaging pattern, and subsequently fabricating the semiconductor structure using the mask plate in a photolithographic process. In this embodiment, the resulting fabricated semiconductor structure has a shape that is substantially different from the reference pattern. The reference pattern of the semiconductor structure may correspond to an active region of an anti-fuse transistor of a memory cell, wherein a portion of the active region of the anti-fuse transistor comprises a thin gate oxide and a thinner gate oxide It is covered with thick gate oxide. In this embodiment, the region of the reference pattern corresponds to the thin gate oxide of the anti-fuse transistor.

According to another embodiment of the present aspect, the method may further comprise applying optical proximity correction to other portions of the reference pattern to correct for photolithographic distortion.

Other aspects and features of the present invention will become apparent to those skilled in the art after reviewing the following description of specific embodiments of the invention in conjunction with the accompanying drawings.

Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings.
1 is a circuit diagram of a DRAM-type anti-fuse cell.
Figure 2 is a planar layout of the DRAM-type anti-fuse cell of Figure 1;
3 is a cross-sectional view along line xx of the DRAM-type anti-fuse cell of FIG.
4 is a cross-sectional view of an anti-fuse transistor according to one embodiment of the present invention.
Figure 5 is a planar layout of the anti-fuse transistor of Figure 4;
FIG. 5B is a planar layout of the anti-fuse transistor of FIG. 4 showing an alternate OD2 mask configuration.
6 is a flow chart of a method of forming a deformable thickness gate oxide for an anti-fuse transistor of the present invention.
Figures 7A-7C illustrate the formation of the deformable thickness gate oxide in connection with the steps of the flow diagram of Figure 6;
8A is a planar layout of an anti-fuse transistor according to an embodiment of the present invention.
8B is a cross-sectional view along line AA of the anti-fuse transistor of FIG. 8A.
Figure 9 is an enlarged planar layout of the anti-fuse transistor of Figure 8A.
Figure 10 is a planar layout of a memory array using the anti-fuse transistor of Figure 8A in accordance with an embodiment of the present invention.
11 is an enlarged planar layout of an anti-fuse transistor according to another embodiment of the present invention.
Figure 12 is a planar layout of a memory array using the anti-fuse transistor of Figure 11 in accordance with one embodiment of the present invention.
13A illustrates a planar layout of a two-transistor anti-fuse memory cell according to one embodiment of the present invention.
13B is a cross-sectional view taken along line BB of the two-transistor anti-fuse memory cell of FIG. 13A.
Figure 14 is a planar layout of a memory array using the 2-transistor anti-fuse memory cells of Figures 13A and 13B, in accordance with an embodiment of the invention.
15 is a planar layout of a memory array using a two-transistor anti-fuse memory cell according to an alternative embodiment of the present invention.
Figures 16-20 are planar layouts of alternate anti-fuse cells in accordance with embodiments of the present invention.
Figures 21-24 are planar layouts of alternative 2-transistor anti-fuse memory cells in accordance with embodiments of the present invention.
Figure 25 is a mask pattern with OPC for the active area of the anti-fuse transistor.
26 is a view showing an anti-fuse transistor having an active region fabricated using the mask pattern of FIG. 25. FIG.
Figure 27 is a mask pattern with an inverse OPC for the active area of an anti-fuse transistor, in accordance with the present invention.
28 is a view showing an anti-fuse transistor having an active region fabricated using the mask pattern of FIG. 27;
Figure 29 is a flow diagram summarizing an inverse OPC method for the fabrication of a semiconductor structure with reduced area, in accordance with the present invention.

Generally, the present invention provides a gate oxide anti-fuse transistor device of a deformable thickness that can be employed in non-volatile, one-time-programmable (OTP) memory array applications. The anti-fuse transistor can be fabricated with standard CMOS technology and consists of standard transistor elements with source diffusion, gate oxide and polysilicon gates. The deformable gate oxide underlying the polysilicon gate is comprised of a thick gate oxide region and a thin gate oxide region, wherein the thin gate oxide region operates as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region may be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, the word line read current applied to the polysilicon gate can be sensed through the bit line coupled to the source diffusion through the channel of the anti-fuse transistor. More particularly, the present invention provides an efficient method of utilizing isolated channel MOS structures such as anti-fuse cells suitable for OTP memories.

In the following description, the term MOS is used to refer to any FET or MIS transistor, half-transistor or capacitor structure. In order to simplify the description of the embodiments, it should be understood that reference to gate oxides from this point onwards includes dielectric materials, oxides, or combinations of oxides and dielectric materials.

As previously discussed, DRAM-type memory arrays that use planar capacitors as anti-fuses instead of storage capacitors are already known, as shown in U.S. Patent No. 6,667,902. 1 is a circuit diagram of such a memory cell, while FIGS. 2 and 3 show plan and cross-sectional views, respectively, of the known anti-fuse memory cell of FIG. The memory cell of FIG. 1 includes a pass or access transistor 10 for coupling the bit line BL to the lower plate of the anti-fuse device 12. The word line WL is connected to the gate of the access transistor 10 to turn it on and the cell plate voltage Vcp is applied to the top plate of the anti- Respectively.

It can be seen from FIGS. 2 and 3 that the layout of the access transistor 10 and the anti-fuse device 12 is very intuitive and simple. The gate 14 of the access transistor 10 and the top plate 16 of the anti-fuse device 12 consist of the same layer of polysilicon, which extends across the active area 18. [ A thin gate oxide 20, also known as a gate dielectric, is formed in the active region 18 under each polysilicon layer, and the thin gate oxide 20 serves to electrically isolate the polysilicon from the bottom active region . On one side of the gate 14 is a diffusion region 22, 24, wherein the diffusion region 24 is coupled to the bit line. Although not shown, those of ordinary skill in the art will appreciate that standard CMOS processing, such as sidewall spacer formation, lightly doped diffusions (LDD), and diffusion and gate silicidation, can be applied . Although conventional single transistor and capacitor cell configurations are widely used, transistor-only anti-fuse cells are more preferred because of semiconductor array area savings that can be obtained in high-density applications . Such transistor-only anti-fuses should be simple enough to be fabricated in a reliable and low-cost CMOS process.

In accordance with one embodiment of the present invention, Figure 4 shows a cross-sectional view of an anti-fuse transistor that may be fabricated with any standard CMOS process. In the present example, the anti-fuse transistor is almost identical to a simple thick gate oxide or an input / output MOS transistor with one floating diffusion terminal. The disclosed anti-fuse transistor is also referred to as a split-channel capacitor or half-transistor and can be reliably programmed so that the fuse-link between the polysilicon gate and the substrate can be localized to a particular area of the device as expected have. The cross-sectional view of FIG. 4 is taken along the channel length of the device, and the presently described embodiment is a p-channel device. One of ordinary skill in the art will appreciate that the present invention may be implemented as an n-channel device.

The anti-fuse transistor 100 includes a substrate channel region 104, a polysilicon gate 106, sidewall spacers 108, a field oxide region 109, a diffusion region 110, And a deformable thickness gate oxide (102) formed on the LDD region (114). The bit line contact 116 appears to be in electrical contact with the diffusion region 110. The deformable thickness gate oxide 102 is comprised of a thick oxide and a thin gate oxide such that a portion of the channel length is covered by the thick gate oxide and the remaining portion of the channel length is covered by the thin gate oxide. Generally, the thin gate oxide is a region where oxide breakdown can occur. On the other hand, the thick gate oxide edge that meets diffusion region 110 defines an access edge, where oxide breakdown is prevented and the current between gate 106 and diffusion region 110 is programmed anti- - Flows for fuse transistors. The distance that the thick oxide portion extends into the channel region depends on the mask grade, but the thick oxide portion is preferably formed to be at least as long as the minimum distance of the high voltage transistor formed on the same chip.

In a preferred embodiment, the diffusion region 110 is connected to the bit line through the bit line contact 116 or to another line for sensing current from the polysilicon gate 106 and to receive programming voltages or currents Lt; / RTI > This diffusion region 110 is formed close to the thick oxide portion of the deformable thickness gate oxide 102. To further protect the anti-fuse transistor 100 from high voltage damage or current leakage, a resistor protection oxide (RPO), also known as a salicide protect oxide, is introduced during the fabrication process So that the metal particles can be further spaced from the edge of the sidewall spacer 108. Preferably, this RPO is used during the salicidation process to prevent only the portion of the diffusion region 110 and the portion of the polysilicon gate 106 from being salicided.

It is well known that salicided transistors are known to have higher leakage and hence lower breakdown voltage. Thus, having a non-salicided diffusion region 110 will reduce leakage. Diffusion region 110 may be doped for low voltage transistors or high voltage transistors or a combination of the two and yield the same or different diffusion profiles.

A simplified top view of the anti-fuse transistor 100 is shown in FIG. The bit line contact 116 may be used as a visual reference point to align the orientation of the corresponding cross section of FIG. 4 with the plan view. The active region 118 is the region of the device in which the channel region 104 and the diffusion region 110 are formed, which is defined by an OD mask during the fabrication process. Dashed outline 120 defines areas where a thick gate oxide is formed through the OD2 mask during the fabrication process. More specifically, the region defined by the outline 120 of the dashed line designates the regions where the thick oxide is formed. OD simply refers to the oxide definition mask used during the CMOS process to define regions on the substrate on which the oxide is to be formed and OD2 refers to the second oxide definition mask different from the first one. The details of the CMOS process steps for fabricating the anti-fuse transistor 100 will be discussed later. According to one embodiment of the present invention, the thin gate oxide regions bounded by the edges of the active region 118 and the rightmost edge of the OD2 mask are minimized. In the presently-shown embodiment, this region can be minimized by moving the rightmost OD2 mask edge towards the parallel edge of the active region 118. [

5B is an alternative view of the anti-fuse 100 of FIG. 5A. In Fig. 5A, the OD2 mask 120 appears as a large area that can be extended to cover the entire memory area. As previously discussed, the OD2 mask 120 defines regions in which a thick gate is to be formed. Openings 121 defining regions where no thick gate oxide is formed are formed in the OD2 mask 120. [ Instead, a thin gate oxide will be grown into the area defined by the openings 121. One of ordinary skill in the art will recognize that in a memory array configuration in which a plurality of anti-fuse memory cells 100 are arranged in rows, one rectangular opening overlaps all memory cells, 0.0 > 118 < / RTI > may be defined.

Programming of the anti-fuse transistor 100 is based on a gate oxide breakdown that forms a permanent link between the gate and the underlying channel. The gate oxide breakdown conditions (voltage or current and time) mainly depend on i) gate dielectric thickness and composition, ii) defect density, and iii) gate area, gate / diffusion perimeter. The combined thick and thin gate oxide of the anti-fuse transistor 100 causes a locally lowered gate breakdown voltage, especially an oxide breakdown zone in the thin gate oxide portion of the device. In other words, the structure disclosed above ensures that the oxide breakdown is confined to the thinner gate oxide portion.

Additionally, the anti-fuse transistor embodiments of the present invention utilize a CMOS manufacturing design rule that was typically prohibited for gate oxide design layout and formation to promote gate oxide breakdown performance. In today's CMOS processes, all gate oxide processing steps have been estimated and optimized to have a uniform gate oxide thickness in the active gate region. By introducing deformable thick gate oxide devices into a standard CMOS flow, additional defects and electric field disturbances were created at the interface between the thick and thin gate oxides. These defects may include, but are not limited to: oxide thinning, silicon plasma etching at the boundary, residues from the cleaning process, between the unmasked regions and the partially masked regions Silicon recess due to different thermal oxidation rates of silicon. All of these effects increase the trap and defect density at thin oxide boundaries, resulting in increased leakage and locally lowered breakdown voltage. Thus, without any process modifications, low voltage, dense anti-fuse structures can be created.

In a typical CMOS process, the diffusion regions, LDD and channel implantation are different for thin gate oxite and thick gate oxide transistors. According to one embodiment of the invention, the diffusion regions, LDD and thin gate oxide channel implantation of the anti-fuse transistors may be of one of the following: a low voltage type corresponding to a thin gate oxide, or a thick gate oxide (I / O oxide), or both, assuming that the resulting thin gate oxide threshold voltage is not greater in magnitude than the thick gate oxide threshold voltage.

A method for producing a deformable thickness gate oxide from a standard CMOS process in accordance with an embodiment of the present invention utilizes a well known two-step oxidation process. A flow chart outlining this process is shown in Fig. 6, and Figs. 7A-7C show various stages of deformation-capable thick gate oxide formation corresponding to the specific steps of the process.

First, in step 200, an intermediate gate oxide is grown in all of the active areas defined by the OD mask. In FIG. 7A, this is shown as the formation of the intermediate gate oxide 300 on the substrate, over the channel region 302. In a subsequent step 202, the intermediate gate oxide 300 is removed from all designated thin gate oxide regions using an OD2 mask. 7B shows the remaining portions of the intermediate gate oxide 300 and the future thin oxide region 304. FIG. In the final gate oxide formation step 204, a thin oxide is again grown in all active areas as previously defined by the OD mask. 7C, a thin gate oxide 306 is grown on the intermediate gate oxide 300 and the thin oxide region 304. In this embodiment, the thick gate oxide is formed by a combination of removing the intermediate gate oxide and growing a thin gate oxide on the remaining intermediate gate oxide.

As a result, the thick gate oxide region formed by the OD2 mask covered during step 202 will have a gate oxide thickness that is the combination of the intermediate gate oxide 300 and the final thin gate oxide 306. [ The same process can be extended for two or more oxidation steps or other equivalent processes can be used to produce two or more gate oxide thicknesses on the same die, determined by at least one thick gate oxide mask (OD2) have.

Typically, the OD2 mask is considered as a non-critical masking step, a low-resolution mask is used, design rules require a large margin of the OD2 mask over the active gate regions, Lt; RTI ID = 0.0 > OD2 < / RTI > According to the present invention, the OD2 mask is terminated in the active gate region to provide a thicker gate oxide on the drain (i.e., diffusion contact) side and a thinner gate oxide on the opposite side (channel or non-connected source side) Resulting in a separate-channel anti-fuse structure. In principle, this technique requires that the gate length (polysilicon line width) be greater than the process minimum and depends on the actual OD2 mask tolerances, but otherwise, any process change or mask grade change Do not ask. The minimum gate length for the isolated channel anti-fuse structure can be approximated by the sum of the minimum gate lengths of the thick and thin gate oxide. One of ordinary skill in the art will appreciate that the exact calculations can be made based on mask tolerances and the gate length can be minimized by making the OD2 mask tolerances strict.

Once the deformable thickness gate oxide is formed, additional standard CMOS processing steps may be employed in step 206 to complete the anti-fuse transistor structure as shown in FIG. This may include, for example, the formation of polysilicon gates, LDD regions, sidewall spacers, RPO, and diffusion regions, and salicylation. In accordance with a preferred embodiment of the presently discussed process, a saliasing step is included to cause the floating diffusion region of the anti-fuse transistor and the polysilicon gate to be salicided. The RPO is preformed over the diffusion region, which is for protection from the salicidation process. As previously mentioned, the salicided floating diffusion region will enhance the oxide breakdown in the region.

One issue to consider for the aforementioned anti-fuse transistors is the reliability, or retention, of un-programmed cells. The described anti-fuse memory cell is programmed by forming a conductive channel between the polysilicon gate and the channel through a thin gate oxide. The resulting programmed state can be detected by applying a read voltage to the gate in a read operation and sensing the voltage of the bit line to which the anti-fuse is connected. Typical read voltages are 1.5 V to 2.0 V depending on the process technology. This voltage may exceed the maximum voltage allowed for the DC bias on the gate of the low voltage transistor portion of the cell (e.g., 1.1V for 1V devices). In other words, the read voltage may be high enough to program the cells that remain unprogrammed. One factor to maximize the reliability of unprogrammed anti-fuse cells is to minimize the area of the thin gate oxide of the deformable thickness gate oxide.

Figure 8a shows a top view of an anti-fuse transistor having a minimized thin gate oxide region that may be fabricated in any standard CMOS process, in accordance with an embodiment of the invention. For example, the manufacturing steps shown in Fig. 6 can be used. Figure 8b shows a cross-sectional view of the anti-fuse transistor of Figure 8a taken along line A-A. The anti-fuse 400 of FIG. 8A is similar to the anti-fuse 100 shown in FIG. 5A except that the area of the thin gate oxide of the deformable thickness gate oxide under the polysilicon gate is minimized. Very similar.

The anti-fuse transistor 400 includes a deformable thickness gate oxide 402, a polysilicon gate 406, sidewall spacers 408, a diffusion region 410, And an LDD region 412 in the LDD region 410. The deformable thickness gate oxide 402 is comprised of a thick oxide and a thin gate oxide such that most of the channel length is covered by the thick gate oxide and a small fraction of the channel area is covered by the thin gate oxide. 8A, the thick gate oxide region 414 covers most of the active region 416 underneath the polysilicon gate 406 except for a small square thin oxide region 418. As shown in FIG. The anti-fuse transistor 400 may be a non-volatile memory cell and thus may have a bitline contact 420 in electrical contact with the diffusion region 410. The formation of the shape and size of the thick gate oxide region 414 and the thin gate oxide region 418 is discussed in more detail below.

Figure 9 is an enlarged plan view of the anti-fuse transistor of Figure 8A for emphasizing the planar geometry of the deformable thickness gate oxide. The anti-fuse transistor 500 is comprised of an active region 502 having a polysilicon gate 504 that overlies the top. In Fig. 9, shading from the polysilicon gate was controlled to clearly indicate the features at the bottom. The deformable thickness gate oxide is formed between the active region 502 and the polysilicon gate 504 and includes a thick gate oxide region 506. According to this embodiment, the thick gate oxide region 506 may be considered as at least two right angle segments. One of ordinary skill in the art will appreciate that the delineation of the segments is a visual division into the component perpendicular to the thick gate oxide shape. The first thick gate oxide segment 508 extends from the first end of the channel region to the second end of the channel region, consistent with the leftmost edge of the polysilicon gate 504. Segment 508 may be viewed as a rectangular area having a width less than the width of the channel area. The second thick gate oxide segment 510 is adjacent to the first segment 508 and extends from the same first end of the channel region to a predetermined distance of the channel length. The second thick gate oxide segment 510 has a width substantially equal to the difference between the channel width and the width of the first segment 508.

Also, because the second thick gate oxide segment 510 is terminated in the channel region, the remaining region is separated by two edges by the segments 508, 510 and by two edges of the active region 502 It is rectangular in shape as it is bordered by the sides. This remaining region is a thin gate oxide region 512. The OD2 mask 513 defines the areas in which a thick oxide is formed, while the OD2 mask 513 has the right opening 514 where no thick oxide is formed. The thin gate oxide will grow into the area defined by the opening 514. Alternately, regions outside of the right outline 514 are where thick gate oxide is formed. Outlined line 513 of the dashed line may indicate the OD2 mask used during the fabrication process so that the corner of the opening 514 overlaps the edge of the active area 502 below the polysilicon gate 504. The dimensions of the opening 514 can be selected to any size, but have a preferred set of dimensions, as will be discussed with reference to FIG. In a single transistor anti-fuse memory cell, a bit line contact 516 is formed for electrical connection to a bit line (not shown).

10 is a planar layout of a memory array including the anti-fuse memory cell of FIG. 9, in accordance with an embodiment of the invention. The memory array has anti-fuse memory cells arranged in rows and columns, wherein the polysilicon gates 504 formed of successive polysilicon lines are connected to each anti-fuse memory cell Lt; RTI ID = 0.0 > 502 < / RTI > Each polysilicon line is associated with a logical word line (WL0, WL1, WL2, WL3). In the presently-shown embodiment, each active region 502 has two polysilicon gates 504, and two anti-fuse transistors 506, Are formed.

The openings 514 in the OD2 mask 513 to define the regions where the thin gate oxide is grown are in a rectilinear shape and each of its four corners has four anti-fuse transistor active regions 502 , And thin gate oxide regions 512 are defined. The gate oxide regions < RTI ID = 0.0 > 512 < / RTI > Ideally, the thin gate oxide region has at least one dimension less than the minimum feature size of the fabrication process, which can be obtained through an overlap between the two mask regions. The one mask area is a diffusion mask, also referred to as an active area mask, and the second mask area is a rectangular opening 514 in the OD2 mask 513. [ Both masks are made of a non-critical width, which means they are greater than the minimum allowable width. Thus, by positioning the overlap of the two masks, the area of the thin gate oxide regions 512 can have dimensions that are approximately equal to or less than the minimum interconnect width of a particular fabrication process or technology. Thus, the dimensions of the right-angled opening 514 are selected based on the spacing between the horizontally adjacent active areas 502 and the spacing between the vertically adjacent active areas 502, thereby defining the active areas 502 The overlap region between the diffusion mask and the edges of the opening 514 is equal to or less than the minimum interconnect width of the fabrication technique.

The dimensions of the opening 514 are selected to minimize the square or rectangular thin gate oxide regions 512. One of ordinary skill in the art will appreciate that the selected dimensions will take into account manufacturing exceptions and alignment errors such as cornering of 90 degree edges. A high degree of accuracy for the fabrication of the thin gate oxide region 512 can be obtained by using a high grade mask. High grade masks are provided by higher quality retention, materials, and / or mask printing installations.

Thus, the reliability of the unprogrammed anti-fuse cells with the thin gate oxide region 512 of this minimized interconnect width is greatly improved. The shape of the thin gate oxide region 512 is rectangular, or square, so that the minimized region is derived. According to alternative embodiments, instead of having a single right-angled opening 514 that overlaps with four anti-fuse active areas 502 as shown in FIG. 10, a number of smaller openings may be used . For example, the one opening may be shaped to overlap only two horizontally adjacent active regions 502. [ Alternatively, the one opening may be shaped to overlap only two vertically adjacent active regions 502. Further, individual rectangles that are larger in size than the preferred thin gate oxide region 512 may be used to overlap each active region 502. Though any size and any number of rectangles are contemplated by the previously shown embodiments, the thin gate oxide may be triangular in shape.

The anti-fuse transistors are preferably programmed by rupturing the thin gate oxide at a thin / thick gate oxide boundary. This is accomplished by applying a sufficiently high voltage difference between the channel and gate of the cells to be programmed, and a substantially lower voltage difference over all other cells, if any. Thus, when a permanent conductive link is formed, the current applied to the polysilicon gate will flow through the link and the channel to the diffusion region, which can be sensed by conventional sense amplifier circuits. For example, a VPP high voltage level may be applied to the polysilicon gate 504, while a lower voltage, such as ground, is applied to its corresponding bit line. The memory cells that should not be programmed will have their bit lines biased to a voltage higher than ground, e.g., VDD. Although a programming circuit is not shown, one of ordinary skill in the art will appreciate that such circuits may be combined with bit lines and included in word line driving circuits. Reading the anti-fuse memory cell may be accomplished by precharging the bit lines to ground and applying a read voltage such as VDD to the polysilicon gates. A programmed anti-fuse with a conductive link will pull its corresponding bit line to VDD. Unprogrammed anti-fuses without a conductive link will behave like switched capacitors with very low leakage current characteristics. Thus, the bit line voltage will not substantially change, even if there is a change. The voltage change can be sensed by the bit line sense amplifier.

11 is an enlarged planar layout of an anti-fuse transistor according to another embodiment of the present invention. The anti-fuse transistor 600 is substantially identical to the anti-fuse transistor 500 and thus has the same active region 502, polysilicon gate 504, and bitline contact 516. The anti-fuse transistor 600 has a gate oxide of a deformable thickness of another shape. The thick gate oxide region 602 may appear to consist of at least two right angle segments and a triangle segment. The first thick gate oxide segment 604 extends from the first end of the channel region to the second end of the channel region, consistent with the leftmost edge of the polysilicon gate 504. Segment 604 may be viewed as a rectangular area having a width less than the width of the channel region. A second thick gate oxide segment 606 is adjacent to the first segment 604 and extends from the same first end of the channel region to a predetermined distance of the channel length. The second thick gate oxide segment 606 has a width substantially equal to the difference between the channel width and the width of the first segment 604. The third gate oxide segment 608 is triangular in shape and has its 90 degree sides adjacent to the first thick gate oxide segment 604 and the second thick gate oxide segment 606. Segment 606 may include segment 608 such that the predetermined distances are set by the diagonal edge of segment 608. [ The remaining triangular region having 90 degrees sides formed by the edges of the active region 502 is a thin gate oxide region 610.

A dotted diamond shaped region 612 defines openings in the OD2 mask 513 within which a thin gate oxide is grown. Alternating areas outside the diamond-shaped outline 612 are where a thick gate oxide is formed. The dotted outline 612 is the OD2 mask used during the fabrication process and the corner of the opening 612 is positioned to overlap the edge of the active area 502 below the polysilicon gate 504. [ In the presently-shown embodiment, the opening 612 is in the form of an opening 514 of FIG. 9 rotated. The dimensions of the opening 612 may be selected to any size, but have a preferred set of dimensions, as will be discussed with reference to Fig.

Figure 12 is a planar layout of a memory array including the anti-fuse memory cell of Figure 11 according to one embodiment of the present invention. The memory array has anti-fuse memory cells arranged in rows and columns, wherein the polysilicon gates 504 formed of successive polysilicon lines are connected to each anti-fuse memory cell Lt; RTI ID = 0.0 > 502 < / RTI > The layout configuration of the polysilicon gates 504 for the active region 502 is the same as that shown in Fig.

The openings 612 in the OD2 mask 513 to define the regions in which the thin gate oxide is grown are diamond-shaped and each of its four corners is surrounded by the edges of the four anti-fuse transistor active regions 502 Regions are overlapped and sized to define thin gate oxide regions (610). Ideally, the thin gate oxide region 610 is less than the minimum feature size of the fabrication process. An overlap is between two mask areas, one mask area is a diffusion mask, also referred to as an active area mask, and the second mask area is an OD2 mask 513 with diamond-shaped openings 612. Note that the openings 612 are considered diamond-shaped with respect to other features, such as polysilicon gates 504 and active regions 502, defined as lines of mutual 90 degrees. Thus, with respect to these features, the openings 612 are diamond-shaped and are defined as lines that are 45 degrees to the defining lines of polysilicon gates or active regions 502. [

Again, both masks are made of non-critical width, which means they are larger than the minimum allowable width. Thus, by locating the overlap of the two masks, the area of the thin gate oxide regions 610 can have dimensions that are approximately equal to or less than the minimum interconnect width of a particular fabrication process or technology. Accordingly, the dimensions of the diamond-shaped opening 612 are selected based on the spacing between the horizontally adjacent active areas 502 and the spacing between the vertically adjacent active areas 502, thereby forming the active areas 502 The overlap region between the diffusion mask for defining and the edges of the opening 612 is equal to or less than the minimum interconnect width of the fabrication technique.

The dimensions of the diamond-shaped opening 612 are selected to minimize the triangular shaped thin gate oxide regions 610. The selected dimensions will take into account manufacturing exceptions and alignment errors, and a high grade mask can be used to tighten fabrication tolerances.

Embodiments of the non-volatile memory cell described above relate to a single anti-fuse transistor memory cell. The deformable thickness gate oxide may have a thick gate oxide that is substantially the same as the gate oxide used for high voltage transistors on the same chip. Likewise, the deformable thickness gate oxide may have a thin gate oxide that is substantially the same as the gate oxide used in the low voltage transistors on the same chip. Of course, both the thick and thin gate oxide regions may have thicknesses tailored for the memory array only.

According to further embodiments of the present invention, the access transistor may be formed in series with the anti-fuse transistors and thus a 2-transistor anti-fuse cell may be provided. 13A and 13B illustrate a two-transistor anti-fuse memory cell according to one embodiment of the present invention.

13A shows a top view of a two-transistor anti-fuse memory cell 700 having a minimized thin gate oxide region that can be fabricated with any standard CMOS process in accordance with an embodiment of the invention. Figure 13B shows a cross-sectional view of the memory cell 700 of Figure 13A taken along line B-B. The two-transistor anti-fuse memory cell 700 includes an anti-fuse transistor and a contiguous access transistor. The structure of the anti-fuse transistor is the same as that shown in Figs. 8A to 12. In this example, it is assumed that the anti-fuse transistor is the same as that shown in Fig. 8B, so that the same reference numerals denote the same previously described features. More specifically, the structure of the deformable thickness gate oxide is the same as that shown in Fig. 8B, except that the diffusion region 410 does not have a bit line contact formed thereon.

The access transistor has a polysilicon gate 702 that overlies the gate oxide 704. What is formed on one side of the gate oxide 704 is the shared diffusion region 410. Another diffusion region 706 is formed on the other side of the gate oxide 704, which will have a bit line contact 708 formed thereon. Both diffusion regions may have LDD regions adjacent to the vertical edges of gate oxide 704. [ A person of ordinary skill in the art will appreciate that the diffusion region 706 may be doped identically to the diffusion region 410, but may be otherwise doped depending on the desired operating voltage to be used.

As described above, the deformable thickness gate oxide 402 has a thick gate oxide region and a thin gate oxide region. The thickness of the gate oxide 704 will be equal to the thickness of the thick gate oxide region of the deformable thickness gate oxide 402. In one embodiment, the access transistor may be fabricated using the same process as the process used to form the thick gate oxide region of the high voltage transistor process or the deformable thickness gate oxide 402. Polysilicon gate 702 may be formed concurrently with polysilicon gate 402.

The operation of the two-transistor anti-fuse memory cell is similar to that of the previously described single transistor anti-fuse cell. Programming of the anti-fuse transistor requires high voltage application to the VCP polysilicon lines while the bit lines are held at ground. The access transistor is turned on to couple the shared diffusion region (via the bit line) to ground.

Figure 14 is a planar layout of a memory array including the 2-transistor anti-fuse memory cells of Figures 13A and 13B according to one embodiment of the present invention. The memory array has anti-fuse memory cells arranged in rows and columns, wherein the polysilicon gates 406 formed in successive polysilicon lines are connected to each anti-fuse memory 406 in a row, Lt; RTI ID = 0.0 > 416 < / RTI > Each polysilicon line is associated with a logic cell plate (VCP0, VCP1, VCP2, VCP3). Polysilicon gates 702 formed from successive polysilicon lines extend onto the active areas 416 of each anti-fuse memory cell in a row. These polysilicon lines are associated with the logical word lines WL0, WL1, WL2, and WL3. In the presently-shown embodiment, each active region 416 has two pairs of polysilicon gates 406/702, with two anti-gates 406/702 sharing the same bit line contact 708 and active region 416, - Fuse transistors are formed.

The openings 710 in the OD2 mask 513 to define the areas where the thin gate oxide is grown are in a rectangular and rectangular shape and each of its four corners has four anti-fuse transistor active areas 416 ), And thin gate oxide regions 418 are defined. The same relative mask overlap criterion as described in the embodiment of Fig. 10 applies to this embodiment. The dimensions of the right-angled opening 710 are selected based on the spacing between the horizontally adjacent active areas 416 and the spacing between the vertically adjacent active areas 416 and thus define the active areas 416 The overlap region between the diffusion mask and the edges of the opening 710 is equal to or less than the minimum interconnect width of the fabrication technique.

The embodiment of FIG. 14 is configured with separate controlled cell plates VCP0, VCP1, VCP2, VCP3, which allows improved control to prevent unintended programming of unselected cells. In an alternative embodiment, the cell plates VCP0, VCP1, VCP2, VCP3 may be connected to a common node. In such an embodiment, a particular programming order is used to prevent unintended programming of unselected cells. The programming sequence of the alternative embodiment begins with precharging all the word lines and bit lines to a high voltage level, after which the common cell plate is driven with the programming voltage VPP. For example, using the embodiment of FIG. 13B, this will cause diffusion region 410 to be precharged to a high voltage level. A word line to be programmed is selected, which is accomplished by deselecting all of the other word lines, e. G. By driving them at a low voltage level. Thereafter, the bit line voltage coupled to the selected memory cell is driven to a low voltage level, e. G., Ground.

15 is a planar layout of a memory array including a two-transistor anti-fuse memory cell according to an alternative embodiment of the present invention. The memory array of FIG. 15 is the same as that of FIG. 14, except that the diamond-shaped opening 712 in the OD2 mask 513 is used to define the thin gate oxide regions of the deformable thickness gate oxide. The same relative mask overlap criterion as described in the embodiment of Fig. 12 applies to this embodiment.

In the previously disclosed embodiments of the present invention, one of the thick gate oxide segments has a length extending from one end of the channel region to the other end of the channel region. According to an alternative embodiment, the length of this thick gate oxide segment is slightly reduced, so as not to extend completely across the complete length of the channel region. 16 is a planar layout of an anti-fuse transistor according to an alternative embodiment of the present invention. 16, the anti-fuse transistor 800 includes an active region 802, a polysilicon gate 804, and a bit line contact 806. The active region 802 under the polysilicon gate 804 is the channel region of the anti-fuse transistor 800. In this embodiment, the OD2 mask 808 defines an area in which a thick oxide is to be formed and includes an "L" -shaped opening 809 that overlaps the active area 802, into which a thin gate oxide Will grow. This embodiment is similar to the first embodiment except that one thick gate oxide segment (i. E., 508) extends to a first predetermined distance between the channel region upper edges and to a second predetermined distance relative to the adjacent thick gate oxide segment (i. E., 510) Is similar to that shown in Fig. Thus, a thin gate oxide will be grown between the first predetermined distance and the upper edge of the channel region, and between the second predetermined distance and the upper edge of the channel region.

Previously described embodiments of the anti-fuse transistor have channel regions of constant width. According to further embodiments, the channel region may have a deformable width over the length of the channel region. 17A is a planar layout of an anti-fuse according to an alternative embodiment of the present invention. 17A, the anti-fuse transistor 850 includes an active region 852, a polysilicon gate 854, and a bit line contact 856. The active region 852 under the polysilicon gate 854 is the channel region of the anti-fuse transistor 850. In this embodiment, the OD2 mask 858 defines a region within which a thick oxide is to be formed and includes a rectangular opening 859 that overlaps the active region 852, into which a thin gate oxide is grown will be. The active region under the polysilicon gate 854 is in the " L "-type and the right-angled opening 859 has a lower edge terminating at a predetermined distance from the top edge of the channel region.

FIG. 17B shows the same anti-fuse transistor 850 without masking the polysilicon gate 854 to illustrate the thick gate oxide segment of the channel region. In this embodiment, the first thick gate oxide segment 860 extends from the diffusion edge of the channel region to a first predetermined distance defined by the lower edge of the right opening 859. The second thick gate oxide segment is L-shaped and includes two sub-segments 862, 864. One of ordinary skill in the art will appreciate that the delineation of the segments is a visual division into the component perpendicular to the thick gate oxide shape. The sub-segment 862 extends a first predetermined distance from the diffusion edge of the channel region, while the sub-segment 864 extends a second predetermined distance from the diffusion edge of the second predetermined distance channel region. The second predetermined distance is between the diffusion edge of the channel region and the first predetermined distance. The thin gate oxide region extends from the first predetermined distance of the first thick gate oxide segment 860 and the sub-segment 862 to the top edge of the channel region.

18A is a planar layout of an anti-fuse transistor according to an alternative embodiment of the present invention. In Fig. 18A, the anti-fuse transistor 880 includes the same features as those in Fig. In this embodiment, the active region under the polysilicon gate 854 is in the "T" -shape and the right-angled opening 859 has a lower edge that terminates at a predetermined distance from the top edge of the channel region. FIG. 18B shows the same anti-fuse transistor 880 without covering the polysilicon gate 854 to illustrate the thick gate oxide segments in the channel region.

In this embodiment, there is a first thick gate oxide segment and a second thick gate oxide segment. The first thick gate oxide segment is L-shaped and includes two sub-segments 884, 886. The second thick gate oxide segment is L-shaped and comprises two sub-segments 888, 890. The sub-segment 886 extends from the diffusion edge of the channel region to a first predetermined distance, and the first predetermined distance corresponds to the lower edge of the right-angled opening 859. The sub-segment 884 extends from the diffusion edge of the channel region to a second predetermined distance, wherein the second predetermined distance is between the first predetermined distance and the diffusion edge of the channel region. The sub-segments 888 and 890 of the second thick gate oxide segment are configured identically to the sub-segments 884 and 886, respectively. A thin gate oxide region extends from the first predetermined distance of the sub-segments 886, 890 to the top edge of the channel region.

In the previously described embodiments of Figures 17A and 18A, a thin gate oxide region extends from the lower edge of the right opening 859 to the upper edge of the channel region. Since the channel region has a variable width that is larger than the portion near the upper edge of the channel region near the diffusion edge, the entirety of the thin gate oxide region is more susceptible than the anti-fuse embodiment shown in FIG. 5A Can be small. In further embodiments, the thin gate oxide of the anti-fuse transistor embodiments of FIGS. 17A and 18A is further minimized by applying an OD2 mask with square or diamond-shaped openings shown in FIGS.

19 is a planar layout of an anti-fuse transistor according to an alternative embodiment of the present invention. The anti-fuse transistor 900 is similar to the anti-fuse transistor 900 of FIG. 17B except that the OD2 mask 902 is positioned and shaped to describe the thin gate oxide region 906, (850). In the presently-shown embodiment, the thick gate oxide comprises a first thick gate oxide segment 908 having sub-segments 862 and 864 and a second thick gate oxide segment. The sub-segments 862 and 864 are the same as in the embodiment of Fig. 17B. However, due to the rectangular opening 904 and the overlapping edges of the channel region, the first thick gate oxide segment 908 extends only from the diffusion edge to a predetermined distance of the channel length. Thus, the thick gate oxide segment 908 is shorter in length than the sub-segment 862. Thus, the anti-fuse transistor 900 has a thinner gate oxide region, which is smaller than the embodiment of Fig. 17A. The application of the OD2 mask 902 with the right-angled openings 904 may be applied with the same result to the anti-fuse transistor 880 of FIG. 18B.

Additional reduction in the thin gate oxide region of the anti-fuse transistors 850, 880 can be obtained by applying diamond-shaped openings, as shown previously in FIG. 20 is a planar layout of an anti-fuse transistor according to an alternative embodiment of the present invention. The anti-fuse transistor 950 is similar to the anti-fuse transistor 950 of FIG. 18B except that the OD2 mask 952 is positioned and shaped to describe the thin gate oxide region 956, (880). In the presently disclosed embodiment, the thick gate oxide comprises first and second thick gate oxide segments. The first thick gate oxide segment includes sub-segments 888, 890, which are the same as in the embodiment of Figure 18b. The second thick gate oxide segment includes sub-segments 958,960.

Segment 960 extends only a predetermined distance of the channel length from the diffusion edge due to the diamond-shaped opening 954 and the overlap of the channel region, It is defined by diagonal edges. Thus, the anti-fuse transistor 950 has a thinner gate oxide region, which is smaller than the embodiment of FIG. The application of the OD2 mask 952 with the diamond-shaped opening 954 may be applied with the same result as the anti-fuse transistor 850 of FIG. 17B. The dimensions of sub-segments 958 and 960 are selected such that the diagonal edges of opening 954 do not overlap with the channel regions covered by sub-segment 958. [

Although orthogonal and diamond-shaped openings have been disclosed in the OD2 mask, other open shapes can be used to have the same effect. For example, the openings in the OD2 mask may be hexagonal-shaped, octagonal-shaped, or even substantially rounded after the OPC is added. Further, the right angle opening can be rotated at any angle relative to the polysilicon gate.

The embodiments previously described in Figures 16-20 relate to single transistor anti-fuse memory cells. The embodiments of Figures 16-20 are applicable to 2-transistor anti-fuse cells, where the access transistor is formed in series with the anti-fuse transistor. 21-24 illustrate various embodiments of a two-transistor anti-fuse memory cell with minimized thin gate oxide regions.

21 is a planar layout of a two-transistor anti-fuse transistor according to one embodiment of the present invention.

According to further embodiments of the present invention, to provide a two-transistor anti-fuse transistor, an access transistor may be formed in series with the anti-fuse transistor. 13A and 13B are illustrations of a two-transistor anti-fuse memory cell according to an embodiment of the invention, wherein the channel region has a deformable width. The two-transistor anti-fuse memory cell 1000 is similar to the two-transistor cell 700 of FIG. 13A. The access transistor includes an active region 1002, a polysilicon gate 1004, and a bit line contact 1006. The anti-fuse transistor includes an active region 1002, a polysilicon gate 1008, A common source / drain diffusion region 1010 is shared between the access transistor and the anti-fuse transistor. Covering the channel region under the polysilicon gate 1008 is a deformable thick gate oxide having a thick gate oxide region and a thin gate oxide region. The OD2 mask 1012 shows the areas where the thick gate oxide is to be formed and includes a square-shaped opening 1013 that overlaps the active area 852 within which a thin gate oxide will be grown. The thin gate oxide region 1014 covers the channel region between the lower edge of the right opening 1013 and the upper edge of the channel region.

In Fig. 21, the channel region of the anti-fuse transistor has a deformable width. In the embodiment of Figure 22, the channel region of the anti-fuse transistor has a constant width, but the width of the channel of the access transistor and the rest of the active region is smaller. More specifically, the two-transistor anti-fuse memory cell 1050 is fabricated such that the common source / drain diffusion region 1054 now has a deformable width, the channel region of the anti-fuse transistor is constant but less than the channel region of the access transistor Except that the active region 1052 is shaped such that the width is small.

Figure 23 is another alternative embodiment of a two-transistor anti-fuse memory cell. The two-transistor anti-fuse memory cell 1100 is similar to the two-transistor anti-fuse memory cell 1100 except that the active region 1102 is shaped such that the anti-fuse transistor has a "T" Transistor anti-fuse memory cell 1000 of FIG. 24 shows that the two-transistor anti-fuse memory cell 1150 has an active region 1152 shaped to have a channel region of constant width, with the anti-fuse transistor having an active region 1152, . The common source / drain diffusion region 1154 is "T" -shaped so that it has a narrower width portion.

The two-transistor anti-fuse memory cell embodiments of FIGS. 21-24 may use OD2 masks with orthogonal or diagonal-shaped openings positioned to minimize the thin gate oxide regions of the anti-fuse transistors.

As shown in the presently described embodiments, a single transistor anti-fuse memory cell and a two-transistor anti-fuse memory cell with high reliability can be fabricated using standard CMOS processes. The masks defining the active regions and the OD2 masks may be of non-critical size, but the overlapped position between certain regions may lead to a thin oxide region of the same size smaller than the minimum interconnect width of the process technology.

More specifically, a standard CMOS process will require a series of masks that define various features of the anti-fuse memory cell embodiments described herein. Each mask will have different quality classes depending on the features to be defined. In general, higher grade masks are used to define features of smaller size. The following is an exemplary class of masks used in a standard CMOS process, where higher numbers refer to higher class masks.

1. N-well, P-well, Vtp, Vtn, thick gate oxide (OD2) masks

2. Source / drain implant masks

3. Contact Via Mask

4. Metal two-layer mask

5. Diffusion, thin oxide, contact and metal one-layer masks

6. Polysilicon mask

The difference between a high grade mask, such as grade level 6, and a low grade mask, such as grade level 1, will be better use of printing equipment, better glass, or materials related to making it. Different mask grades are used because certain features do not require high accuracy, while others require high accuracy. As can be appreciated, the effort and cost of producing a high grade mask is substantially greater than that required for a low grade mask. For example, the lowest rating mask may range from $ 3k to $ 5k, while the highest rating mask may range from $ 100k to $ 300k.

It should be noted that the design rules for certain features are set to ensure that a particular area for that feature defined by mask covers does not cover only that particular area but has some overlap on adjacent features. In practice, adjacent features precisely control where the implant occurs. For example, the OD2 form will completely cover the IO transistor area, which is defined by diffusion. Therefore, it does not matter where the actual mask shape is terminated. This is a major reason why the OD2 mask is a low grade with acceptable tolerance and as a result is a low cost mask. Further, some alignment machines can achieve a 0.06 micron tolerance, but only 0.1 micron, because it is considered sufficient for ion implantation masks. In fabricating the anti-fuse transistors and memory arrays shown in FIGS. 4-15, the mask-shaped ends are critical to defining a thin gate oxide region. Current grade OD2 masks used in typical CMOS processes can be used to define thin gate oxide regions of the anti-fuse memory cells described above. However, the error must be taken into account and thus results in a memory cell having a certain minimum size.

In accordance with one embodiment of the present invention, the anti-fuse memory cells of Figures 4-15 use an OD2 mask with a grade corresponding to the mask grade (grade level 2) used for the source / drain implants of the same process . The OD2 mask is preferably identical to the mask grade (grade level 5) used in the diffusion implants of the same process to achieve smaller size memory cells with high reliability. Thus, higher density memory arrays, improved yield, improved performance, and higher reliability are obtained by using high grade OD2 masks. Accuracy can be further improved by ensuring that alignment of the mask is at the highest accuracy level. High alignment accuracy is obtained by using better lithography equipment, lithographic methods and / or other optical wavelengths and other mask types and any possible combination thereof.

The use of higher grade OD2 masks with selective high accuracy alignment provides advantages for the presently disclosed anti-fuse cell embodiments. More specifically, more accurately formed mask-shaped ends using high-grade OD2 masks are advantageously used to minimize certain features, such as thin oxide regions. Since the anti-fuse transistors 500 and 600 must have thin gate oxide regions 512 and 610 with a minimum size, the use of a high grade OD2 mask allows the thin gate oxide region to be minimized, Reliability is improved compared to the same anti-fuse cell fabricated with an OD2 mask.

5A, a more accurate overlap of the OD2 type edge / edge under the polysilicon gate 106 allows a minimized thin oxide region under the polysilicon gate. In particular, the thin oxide region has two opposite sides defined by the width of the active region underneath the polysilicon and two opposite opposite sides defined by the polysilicon gate edge and the OD2 mask shape below the polysilicon, It will be rectangular. The addition of high precision alignment will further minimize the thin oxide region.

For example, an alignment improvement from +/- 0.1 microns to +/- 0.06 microns for a 0.20 micron thin oxide area dimension would allow thinner oxide dimensions of less than 0.04 microns, thereby reducing dimensions to 0.16 microns do. This alone will improve the yield and reliability of the anti-fuse memory cell because both yield and reliability are directly dependent on the entire thin gate oxide region. Yield and reliability improvements appear when alignment is improved to +/- 0.06 microns for 90 nm and 65 nm processes. High grade OD2 masks can be used in the process described in FIG. 6 to fabricate the thin and thick gate oxide regions of the anti-fuse transistor.

The previously described embodiments of the invention describe anti-fuse transistors having thin and thick gate oxides. One of ordinary skill in the art will appreciate that advanced semiconductor fabrication techniques may use additional dielectric materials in addition to, or instead of, oxides to form thin gate oxide regions. One of ordinary skill in the art will recognize that the mask for depositing or growing a dielectric can be formed in the same manner as previously described for the OD2 mask used to define the thin gate oxide region of the anti- It will be appreciated that they may have shaped openings that are positioned as desired.

One of ordinary skill in the art may be an assembly of smaller unit submask forms tiled together in a repeating pattern of OD2 masks with openings defining thin gate oxide regions, It will be appreciated that with a defined full opening or a portion of the opening defined therein, mating of adjacent tiles will cause an enclosed opening.

The previously described embodiments have shown how the OD2 mask can be oriented to minimize the thin gate oxide region of the anti-fuse transistors. According to alternative embodiments, the active area of the anti-fuse transistor underneath the thin gate oxide with a fixed shape and size can be minimized. The presently described techniques make use of undesirable imaging errors and distortion effects that typically occur during optical lithography processes when fabricating semiconductor structures with deep submicron dimensions.

Semiconductor manufacturing processes involve patterning of mask plates to define features corresponding to structures of semiconductor structures formed on a semiconductor substrate. In combination with the lenses, light of various wavelengths including ultraviolet (UV) light is projected through the masts and shapes on the substrate are defined. It is well known that light of a smaller wavelength is used to resolve finer detail patterns. Unfortunately, imaging errors and distortions will cause manufacturing patterns that are substantially different from the desired reference type. For example, the geometric outer corners of the diffusion area polygons in the design can consequently have rounded corners in the fabricated device. In practice, the resulting outer edge has edges that appear to be squashed relative to the reference polygonal design. The inner edges may experience the opposite effect that the resulting inner edge loses any sharp angular definition and has edges that extend beyond the intended design reference design edges. To compensate for these optical lithographic distortions, optical proximity correction (hereinafter referred to as 'OPC') is used to compensate for such imaging errors by changing the shape of the reference design edges. OPC techniques are well known in the art and each process node may have a specific OPC strategy to ensure that the resulting fabricated semiconductor structure has a form that closely matches the original reference form as closely as possible. For example, experimental results or simulations may provide known distortion sizes for certain types. If the type and amount of distortion is predictable, an appropriate OPC strategy can be employed. The application of an exemplary OPC is now provided.

Referring to the exemplary anti-fuse transistors of FIG. 10, fabricating the active region 502 in a substantially geometric rectangular form with a submicron process will require a mask having the shape shown in FIG. 25 shows an exemplary active area pattern 2000 to be formed on a mask plate. Notice immediately that the four outer edges of the rectangular shape are over-emphasized with the corner extensions 2002 having a rectangular shape. Such outer edges form a 90 degree angle to their intersecting edges surrounding the area. These outer edges are different from the inner edges shown in the polygonal shapes, such as the L-shaped active area 852 of FIG. 17A, with an inner edge at a 270 degree angle to the intersecting edges surrounding the area. In L-shape polygonal shapes, inner edges may have polygons removed from them to compensate for the distortions discussed previously. Eventually, the goal of the OPC is to fabricate semiconductor structures that are as close as possible to the reference form.

Referring to Figure 25, a mask pattern for fabricating the active region of the anti-fuse transistor after OPC processing is shown to ensure that the resulting feature of the fabricated active region is as close as possible to the original reference form. The ideal reference form for the active area of the pattern 2000 is a rectangle with outer edges represented by dotted lines. Additional rectangular shapes 2002 are added to each edge for a particular process and manufacturing node. It is assumed that the photolithographic distortion may cause heavily rounded edges in the resulting manufactured structure of known size, which can be compensated by selecting the size of the rectangular shapes 2002 and their placement on the original reference shape . In the present example, the rectangular shapes 2002 are squares. The resulting OPC modification pattern 2000 is applied to the mask plate to fabricate the active area of the anti-fuse transistors. It can be observed that the overall shape of the OPC modification pattern 2000 has a larger area than the reference rectangular area.

FIG. 26 is an exemplary diagram of an anti-fuse transistor that is the result of the OPC modification pattern 200 being used in the fabrication process. In the presently shown example, other structures of the anti-fuse transistor have been fabricated. The anti-fuse transistor is similar to the anti-fuse transistor 100 shown in FIGS. 4 and 5 and is arranged in a back to back configuration as shown in the memory array diagram of FIG. The anti-fuse transistor includes active regions 2010 with portions of polysilicon wordlines 2014 and 2016 and bitline contacts 2012. The anti- The OD2 mask region 2018 represented by the dotted lines defines the region where the thick gate oxide is formed while the regions 2020 and 2022 of the active region 2010 outside the OD2 mask region 2018 are formed It has a thin gate oxide. They are also referred to as thin gate oxide regions of the anti-fuse transistor. As shown in FIG. 26, active region 2010 has a substantially rectangular shape with defined edges. This is due to the use of the OPC modified active area pattern 2000 used during the manufacturing process.

As discussed previously in other embodiments, thin gate oxide regions 2020 and 2022 can be minimized to facilitate gate oxide breakdown. Thus, according to an alternative embodiment of the present invention, reverse optical proximity correction (reverse OPC) is used to further reduce the area of the semiconductor structure. In the inverse optical proximity correction technique of the presently described embodiments, instead of using OPC to obtain the resulting semiconductor structure with substantially the original reference shape, the areas of the reference shape regions are removed or intentionally omitted. This effect can be advantageously used to further reduce selected areas of the semiconductor structure, since most photolithographic distortions result in semiconductor regions having an area reduction to the reference shape. This is the exact opposite of the use of OPC to maintain the desired reference type.

Figure 27 shows a reference shape of an anti-fuse transistor active region after an inverse optical proximity correction process (reverse OPC process) for the purpose of minimizing the area of a thin gate oxide region, in accordance with an embodiment of the present invention. The original rectangular pattern includes the outer edges represented by dotted lines. The inverse optical proximity correction imaging pattern 2030 includes inverted edges 2032 and the inverted edges 2032 are areas of the original rectangular pattern that have been reduced or removed from the reference pattern. For example, the inverted edges appear as notches in the reference pattern. It is presumed that the degree and characteristics of distortion are known in advance through experiments or simulations so that the region reduction can be predetermined based on the size or shape of the inverted edges. Thus, the inverted edges 2032 may be square or rectangular in shape. Thus, the inverse optical proximity correction pattern 2030 has a reduced total area for the reference pattern.

28 is a diagram showing the resultant anti-fuse transistor after the inverse optical proximity correction pattern 2030 of FIG. 27 is used in a known process to have photolithographic distortion effects. The same constructions of Fig. 26 are denoted by the same reference numerals. As shown in FIG. 28, the resulting active region 2034 has rounded gate oxide regions 2036, 2038. The total area of the thin gate oxide regions 2036 and 2038 is smaller than that of the thin gate oxide regions 2020 and 2022 of FIG. Inverse optical proximity correction techniques (inverse OPC techniques) are advantageously used in situations where, for example, due to design rule limits, it is not possible to further narrow the problem area through the layout of reference patterns. It should be noted that a combination of generic OPC and reverse OPC may be used for any reference type. A generic OPC can be used to help maintain the shape of the other parts of the reference pattern while the inverse OPC can be used to minimize certain areas of the reference pattern by further distorting certain parts of the reference pattern.

29 is a flowchart summarizing the inverse OPC method according to the present embodiment. It is assumed that in this method the amount of photolithographic distortion for a particular process is known. The method begins at step 2050, where a reference pattern of a semiconductor structure is designed, typically by designing it as a layout application on a computer workstation. For example, this may be a rectangular active region of the anti-fuse transistor shown in FIG. Thereafter, at step 2052, a selected area of the semiconductor structure is identified for area reduction. The amount of area reduction can be bounded by the minimum and maximum values. For example, it may be the region of the active region of the anti-fuse transistor covered by a thin gate oxide. At step 2054, at least one selected corner area of the selected area of the reference pattern is inverted, which may be accomplished by removing the rectangular area from the reference pattern.

The process of inverting at least one selected edge region may include sub-processes that identify at least one geometric edge of the region selected in step 2056. [ The geometric edges are typically the intersection of two intersecting lines of a pattern that form an angle of 90 degrees with respect to one another. Depending on the shape and size of the selected area, it may only be necessary to invert one outer corner area that includes only geometric edges. Then, at step 2058, the size of at least one inverted corner area is set. The dimensions of each inverted corner region may be different, but the dimensions may be set based on known photolithographic distortions for the current process such that the resulting region falls within the set minimum and maximum values, and / It is ensured not to violate other design rules. In the further enhancement, based on the area reduction, the simulated fabricated structure can appear on the display terminal, thereby allowing the user to see how the resulting structure shape appears. The user may also have the ability to dynamically see changes as the position and size of the inverted edges are manually adjusted.

When the selected edge areas are inverted, a mask plate is created having the inverted edge area (s), referred to as the inverse OPC imaging pattern, In the present example, the mask plate for fabricating the active regions of the anti-fuse transistors may include the reverse OPC pattern 2030 shown in FIG. Finally, in step 2062, the active area structure is fabricated using the active area mask generated in step 2060, so as to have a resultant shape similar to the result of the active area 2034 shown in FIG.

The previously disclosed reverse OPC technique is applied to rectangular shaped structures. The inverse OPC embodiments can be applied to polygons having outer edges, where such polygons can be considered as collection constituent rectangular shapes. This example is illustrated by the exemplary embodiment of FIG. 19, wherein the polygonal shape is divided into a collection of rectangular shapes that are gathered.

Thus, the inverse OPC technique of the present embodiments reduces the area of the selected area of the semiconductor structure using distortions that the general OPCs want to compensate. This is accomplished by reversing the geometric shapes of the edges. In alternative embodiments, a more precise control over the distortion can be obtained by further inverting the edges to achieve a stepped pattern, instead of the original geometric edge.

Reverse OPC techniques may be used in conjunction with the previously described embodiments to reduce the thin gate oxide region of the anti-fuse transistor.

The foregoing embodiments of the invention are intended to be examples only. Modifications, modifications, and variations may be effected to the specific embodiments by those skilled in the art without departing from the scope of the present invention, Quot; is defined only by the claims appended hereto.

Claims (10)

As an inverse optical proximity correction (OPC) method,
A first step of providing a reference pattern of a semiconductor structure, said reference pattern having a rectangular shape;
A second step of selecting a region of the reference pattern for area reduction by photolithographic distortion;
Inverting at least one corner region of the region to form an inverse OPC imaging pattern having an area smaller than the reference pattern; And
And a fourth step of fabricating the semiconductor structure having an area corresponding to the at least one corner area rounded. The method according to claim 1,
Wherein the third step includes removing a predetermined rectangular shape from the at least one corner region of the region. The method according to claim 1,
Wherein the second step includes identifying an anti-fuse transistor programming region. The method according to claim 1,
Further comprising, between the third step and the fourth step, fabricating a mask plate having the reverse OPC imaging pattern. The method of claim 4,
Further comprising the step of fabricating a semiconductor structure using said mask plate. The method of claim 5,
Wherein the resulting fabricated semiconductor structure has a different form from the reference pattern. The method of claim 6,
Wherein the reference pattern of the semiconductor structure corresponds to an active region of an anti-fuse transistor of a memory cell. The method of claim 7,
Wherein a portion of the active region of the anti-fuse transistor is covered with a thin gate oxide and a thick gate oxide having a thickness greater than the thin gate oxide. The method of claim 8,
Wherein the region of the reference pattern corresponds to the thin gate oxide of the anti-fuse transistor. The method according to claim 1,
Further comprising applying optical proximity correction to other portions of the reference pattern to correct for optical lithographic distortion.

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