TWI458090B - Structure and method for manufacturing a crystalline layer on a patterned insulating layer - Google Patents

Structure and method for manufacturing a crystalline layer on a patterned insulating layer Download PDF

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TWI458090B
TWI458090B TW100148016A TW100148016A TWI458090B TW I458090 B TWI458090 B TW I458090B TW 100148016 A TW100148016 A TW 100148016A TW 100148016 A TW100148016 A TW 100148016A TW I458090 B TWI458090 B TW I458090B
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於圖形化絕緣層上覆應變晶質層之結構及其製造方法Structure for covering strained crystal layer on patterned insulating layer and manufacturing method thereof

本發明係有關於一種於圖形化絕緣層上覆應變晶質層之結構及其製造方法,藉由圖形化絕緣層與應變晶質層之結合因而更進一步達到改善基板與磊晶層間之晶格不匹配之功效。The invention relates to a structure for coating a strained crystal layer on a patterned insulating layer and a manufacturing method thereof, and further improving the lattice between the substrate and the epitaxial layer by combining the patterned insulating layer and the strained crystal layer The effect of mismatch.

目前,III-V族化合物半導體於矽基板等不同種類基板上磊晶生長時,兩者之晶格常數差或熱膨脹條數差較大,因此,會產生結晶缺陷,亦稱為異性磊晶(hereroepitaxial)沈積造成的晶格扭曲。所謂的「異性磊晶」沈積層是一種磊晶或是單晶層,此沈積層會沈積在單晶基底上,其與單晶基底具有不同的組成。當沈積的磊晶層受到壓迫而產生一種至少兩個方位與其下方的單晶基底相同的晶格結構,但是與其本來的晶格常數不同時就會被稱為「扭曲」。其中,晶格扭曲的發生是因為當薄膜沈積的方式是讓其晶格結構會與下層的單晶基底相配時,沈積層內的原子會離開原來的位置,也就是在單獨大量材料的晶格結構中原本佔據的位置。舉例來說,在一個單晶矽基底上沈積像是矽鍺或是鍺本身等含鍺材料的異性磊晶一般會產生壓縮的晶格扭曲,因為沈積的含鍺材料其晶格常數比矽基底大,扭曲的程度跟沈積層的厚度以及沈積材料與下層的積底之間的晶格不協調的程度有關。為了能夠降低晶格缺陷,各國學者無所不用其極,其方法主要可分為兩種方式,其一是以多層磊晶結構的方式來減少應力的產生,其二是利用黃光曝光顯影並經由蝕刻方式減少磊晶層與基板間的接觸面積。At present, when a group III-V compound semiconductor is epitaxially grown on a different type of substrate such as a germanium substrate, the difference in lattice constant or the number of thermal expansion between the two is large, and thus crystal defects are generated, which is also called anisotropic epitaxy ( Hereroepitaxial) The lattice distortion caused by deposition. The so-called "heterostatic epitaxial" deposition layer is an epitaxial or single crystal layer deposited on a single crystal substrate having a different composition from the single crystal substrate. When the deposited epitaxial layer is pressed to produce a lattice structure having at least two orientations identical to the single crystal substrate below it, it is referred to as "twisting" when it is different from its original lattice constant. Among them, the lattice distortion occurs because when the film is deposited in such a way that its lattice structure will match the underlying single crystal substrate, the atoms in the deposited layer will leave the original position, that is, the lattice of a large amount of material alone. The position originally occupied by the structure. For example, depositing an epitaxial epitaxial layer of tantalum-containing material such as tantalum or tantalum itself on a single crystal germanium substrate generally produces a compressive lattice distortion because the deposited germanium-containing material has a lattice constant greater than that of the germanium substrate. Large, the degree of distortion is related to the thickness of the deposited layer and the degree of lattice inconsistency between the deposited material and the underlying layer. In order to reduce the lattice defects, scholars from all over the world have no need to use them. The method can be divided into two ways. One is to reduce the stress by multi-layer epitaxial structure, and the other is to use yellow light to develop and The contact area between the epitaxial layer and the substrate is reduced by etching.

請參見美國專利第5,461,243號,名稱為"Substrate for Tensilely Strained Semiconductor",其揭示沉積於其表面之多層應變層,以及滑置底部非常薄矽層於二氧化矽層上。然而,該專利並未對該技術作一詳細之說明,因而限定其後之應用範圍。See U.S. Patent No. 5,461,243, entitled "Substrate for Tensilely Strained Semiconductor", which discloses a multi-layered strained layer deposited on its surface, and a very thin layer of tantalum on the ceria layer. However, this patent does not describe the technique in detail, and thus limits the scope of application thereafter.

另參見美國專利第5,906,951號,名稱為〝Strained Si/SiGe layers on Insulator〞於此作為參考,其係具有多種層沈積,以產生兩堆疊的非平面應變通道。然而,該專利亦並未對該技術作一詳細之說明,因而限定其後之應用範圍。See also U.S. Patent No. 5,906,951, entitled 〝Strained Si/SiGe layers on Insulator, which is incorporated herein by reference for all of the same as the same as the same. However, this patent does not describe the technique in detail, and thus limits the scope of application thereafter.

再參見台灣專利第I297959號,名稱為磊晶結構及其製造方法,其揭示一種磊晶結構及其製造方法。藉由感應式耦合電漿(ICP)等乾式蝕刻技術,對基板上的磊晶層作垂直而精確的蝕刻,得到奈米尺寸及間距的奈米柱。在此奈米柱上進行同質磊晶程序,藉由控制橫向及縱向生長速率可獲得無缺陷的二次磊晶層,並有效提高後續元件製作的良率。然而,奈米柱結構與乾式蝕刻技術皆會增加成本,因而限定其後之應用範圍。Referring again to Taiwan Patent No. I297959, entitled Epitaxial Structure and Manufacturing Method Thereof, an epitaxial structure and a method of fabricating the same are disclosed. The epitaxial layer on the substrate is vertically and accurately etched by a dry etching technique such as inductively coupled plasma (ICP) to obtain a nanometer of nanometer size and pitch. A homogeneous epitaxial process is performed on the nano column, and a defect-free secondary epitaxial layer can be obtained by controlling the lateral and longitudinal growth rates, and the yield of subsequent component fabrication is effectively improved. However, both the nano-pillar structure and the dry etching technique increase the cost and thus limit the range of applications thereafter.

職是之故,申請人乃細心試驗與研究,並一本鍥而不捨的精神,終於研究出一種於圖形化絕緣層上覆應變晶質層之結構及其製造方法,藉由圖形化絕緣層與應變晶質層之結合可進一步改善於基板與磊晶層間之晶格不匹配問題。The job is the reason, the applicant is carefully experimenting and researching, and a perseverance spirit, finally developed a structure of the strained crystalline layer on the patterned insulating layer and its manufacturing method, by patterning the insulating layer and strain The combination of the crystalline layers can further improve the lattice mismatch between the substrate and the epitaxial layer.

本發明之主要目的在於提出一種於圖形化絕緣層上覆應變晶質層之結構及其製造方法,可藉由圖形化絕緣層與應變晶質層之結合可進一步改善於基板與磊晶層間之晶格不匹配問 題。The main object of the present invention is to provide a structure for coating a strained crystalline layer on a patterned insulating layer and a manufacturing method thereof, which can be further improved between the substrate and the epitaxial layer by combining the patterned insulating layer and the strained crystalline layer. Lattice mismatch question.

為達上述之目的,本發明之一種於圖形化絕緣層上覆應變晶質層之結構及其製造方法,其結構部分主要包含有:一基板;一形成於該基板上之絕緣層,該絕緣層係具有圖形化紋路;一形成於該絕緣層上之應變晶質層;以及一形成於該應變晶質層上之磊晶層,可使基板與磊晶層間以絕緣層之圖形化紋路而具有較佳之晶格匹配常數。For the purpose of the present invention, a structure for coating a strained crystalline layer on a patterned insulating layer and a method for fabricating the same according to the present invention comprise: a substrate; an insulating layer formed on the substrate, the insulating layer The layer has a patterned grain; a strained crystalline layer formed on the insulating layer; and an epitaxial layer formed on the strained crystalline layer to pattern the insulating layer between the substrate and the epitaxial layer It has a preferred lattice matching constant.

於本發明上述之結構中,該應變晶質層係選自一矽鍺(SiGe)材料。In the above structure of the present invention, the strained crystal layer is selected from the group consisting of a germanium (SiGe) material.

於本發明上述之結構中,該矽鍺(SiGe)材料包含一拉伸矽鍺與一壓縮矽鍺。In the above structure of the present invention, the germanium (SiGe) material comprises a tensile crucible and a compression crucible.

於本發明上述之結構中,該拉伸矽鍺之鍺濃度係介於5%至20%之間。In the above structure of the present invention, the tensile enthalpy concentration is between 5% and 20%.

於本發明上述之結構中,該壓縮矽鍺之矽濃度係介於50%至80%之間。In the above structure of the present invention, the concentration of the compressed ruthenium is between 50% and 80%.

於本發明上述之結構中,該絕緣層係選自離子植入程序或爐管擴散之方式進行製作。In the above structure of the present invention, the insulating layer is selected from the group consisting of an ion implantation process or a furnace tube diffusion.

其另一結構型態包含有:一基板;一形成於該基板上之絕緣層;一形成於該絕緣層上之緩衝層;一形成於該緩衝層上之應變晶質層;以及一形成於該應變晶質層上之磊晶層。Another structural form includes: a substrate; an insulating layer formed on the substrate; a buffer layer formed on the insulating layer; a strained crystalline layer formed on the buffer layer; and a formed on The strained layer on the strained crystalline layer.

於本發明之另一結構型態中,該緩衝層係選自一矽鍺(SiGe)材料。In another embodiment of the invention, the buffer layer is selected from the group consisting of a germanium (SiGe) material.

於本發明之另一結構型態中,該矽鍺(SiGe)材料包含一拉伸矽鍺與一壓縮矽鍺。In another embodiment of the invention, the germanium (SiGe) material comprises a tensile crucible and a compression crucible.

於本發明之另一結構型態中,該拉伸矽鍺之鍺濃度係介於 5%至20%之間。In another structural form of the present invention, the concentration of the tensile enthalpy is between Between 5% and 20%.

於本發明之另一結構型態中,於本發明之另一結構型態中,該壓縮矽鍺之矽濃度係介於50%至80%之間。In another embodiment of the invention, in another embodiment of the invention, the concentration of the compressed ruthenium is between 50% and 80%.

其製造方法包含下列步驟:(a)提供一基板;(b)沈積一絕緣層於該基板之表面;(c)沈積一應變晶質層於該絕緣層之表面;以及(d)沈積一磊晶層於該應變晶質層之表面。The manufacturing method comprises the steps of: (a) providing a substrate; (b) depositing an insulating layer on the surface of the substrate; (c) depositing a strained crystalline layer on the surface of the insulating layer; and (d) depositing a Lei A seed layer is on the surface of the strained crystalline layer.

於本發明之製造方法中,該步驟(b)更包含使得該絕緣層形成一圖形化紋路,用以改善該基板與該磊晶層間之晶格常數之不匹配。In the manufacturing method of the present invention, the step (b) further comprises forming the insulating layer to form a patterned pattern for improving the mismatch of the lattice constant between the substrate and the epitaxial layer.

於本發明之製造方法中,該圖形化紋路之形成係可採用雷射處理技術。In the manufacturing method of the present invention, the formation of the patterned texture may employ a laser processing technique.

於本發明之製造方法中,該步驟(b)之製作係選自絕緣層係選自離子植入程序或爐管擴散之方式進行製作。In the manufacturing method of the present invention, the production of the step (b) is selected from the group consisting of an insulating layer selected from an ion implantation process or a furnace tube diffusion.

於本發明之製造方法中,該步驟(c)之該應變晶質層係選自一矽鍺(SiGe)材料。In the manufacturing method of the present invention, the strained crystal layer of the step (c) is selected from the group consisting of a germanium (SiGe) material.

於本發明之製造方法中,該步驟(c)之該矽鍺(SiGe)材料包含一拉伸矽鍺與一壓縮矽鍺。In the manufacturing method of the present invention, the bismuth (SiGe) material of the step (c) comprises a tensile enthalpy and a compression enthalpy.

於本發明之製造方法中,該拉伸矽鍺之鍺濃度係介於5%至20%之間。In the manufacturing method of the present invention, the tensile enthalpy concentration is between 5% and 20%.

於本發明之製造方法中,該壓縮矽鍺之矽濃度係介於50%至80%之間。In the manufacturing method of the present invention, the concentration of the compressed ruthenium is between 50% and 80%.

為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉數個較佳實施例,並配合所附圖式,作詳細說明 如下。The above and other objects, features and advantages of the present invention will become more <RTIgt; as follows.

雖然本發明可表現為不同形式之實施例,但附圖所示者及於下文中說明者係為本發明可之較佳實施例,並請了解本文所揭示者係考量為本發明之一範例,且並非意圖用以將本發明限制於圖示及/或所描述之特定實施例中。While the invention may be embodied in various forms, the embodiments illustrated in the drawings It is not intended to limit the invention to the particular embodiments illustrated and/or described.

現請參考第1圖,其顯示為本發明之一種於圖形化絕緣層上覆應變晶質層之結構示意圖,該於圖形化絕緣層上覆應變晶質層之結構100主要包含有:一基板110、一絕緣層120、一應變晶質層130以及一磊晶層140,其中,該基板110材料係選自矽(Si)、藍寶石、碳化矽(SiC)、氮化鋁(AlN)或金剛石所組成之群中的任一種,而以選自矽為最佳;該絕緣層120,形成於該基板110之上,其中絕緣層120之材料係可選自氧化矽(SiOx)、氮化矽(SiNx)、氧化鈦(TiOx)或氧化鋁(AlOx)等氧化物所組成之群中的任一種,而以氧化矽(SiOx)為最佳。一般來說,絕緣層120與基板110的厚度並非發明之關鍵,但較佳是控制厚度高約1微米的絕緣層120;應變晶質層130,形成於該絕緣層120之上;以及一磊晶層140,形成於該應變晶質層130之上。Please refer to FIG. 1 , which is a schematic structural view of a strained crystalline layer on a patterned insulating layer according to the present invention. The structure 100 for overlying the strained crystalline layer on the patterned insulating layer mainly comprises: a substrate 110. An insulating layer 120, a strained crystalline layer 130, and an epitaxial layer 140, wherein the substrate 110 is selected from the group consisting of germanium (Si), sapphire, tantalum carbide (SiC), aluminum nitride (AlN), or diamond. Any one of the group consisting of 矽 is selected as the best; the insulating layer 120 is formed on the substrate 110, wherein the material of the insulating layer 120 is selected from the group consisting of yttrium oxide (SiOx) and tantalum nitride. Any of a group of oxides such as (SiNx), titanium oxide (TiOx), or aluminum oxide (AlOx), and cerium oxide (SiOx) is most preferable. In general, the thickness of the insulating layer 120 and the substrate 110 is not critical to the invention, but it is preferred to control the insulating layer 120 having a thickness of about 1 micrometer; the strained crystalline layer 130 is formed on the insulating layer 120; A crystal layer 140 is formed over the strained crystal layer 130.

現請參考第2圖,其顯示為本發明之一種於圖形化絕緣層上覆應變晶質層之製程方法,其包含下列之步驟:步驟210:提供一基板110;步驟220:沈積一絕緣層120於該基板100之表面; 步驟230:沈積一應變晶質層130於該絕緣層120之表面;以及步驟240:沈積一磊晶層140於該應變晶質層130之表面。Please refer to FIG. 2, which illustrates a method for processing a strained crystalline layer on a patterned insulating layer according to the present invention. The method includes the following steps: Step 210: providing a substrate 110; Step 220: depositing an insulating layer 120 on the surface of the substrate 100; Step 230: depositing a strained crystalline layer 130 on the surface of the insulating layer 120; and step 240: depositing an epitaxial layer 140 on the surface of the strained crystalline layer 130.

其中,該基板110材料係選自矽(Si)、藍寶石、碳化矽(SiC)、氮化鋁(AlN)或金剛石所組成之群中的任一種,而以矽為最佳。值得注意的是,該絕緣層120更可以選自離子植入程序或爐管擴散進行製作,而以離子植入程序為最佳,其中該離子植入程序所使用之離子可以為硼、磷及砷、氬、氫、氦、氮、氧、銦等離子。The material of the substrate 110 is selected from the group consisting of bismuth (Si), sapphire, tantalum carbide (SiC), aluminum nitride (AlN) or diamond, and bismuth is preferred. It should be noted that the insulating layer 120 can be selected from an ion implantation process or a furnace tube diffusion, and the ion implantation process is optimal, wherein the ions used in the ion implantation process can be boron, phosphorus, and Arsenic, argon, hydrogen, helium, nitrogen, oxygen, indium, etc.

於本發明之一實施例中,特徵為絕緣層120係具有圖形化紋路121,用以改善基板110與磊晶層140之晶格常數之不匹,進而避免磊晶層140剝落,進而可降低缺陷密度,且不限定於矽基板,亦即藍寶石、碳化矽(SiC)、氮化鋁(AlN)或金剛石所組成之群中的任一種皆可適用。In an embodiment of the present invention, the insulating layer 120 has a patterned pattern 121 for improving the lattice constant of the substrate 110 and the epitaxial layer 140, thereby preventing the epitaxial layer 140 from peeling off, thereby reducing the thickness of the epitaxial layer 140. The defect density is not limited to the tantalum substrate, that is, any one of a group consisting of sapphire, tantalum carbide (SiC), aluminum nitride (AlN), or diamond.

且該圖形化紋路121之形成係採用一雷射切割處理技術,其中矽材料微細加工蝕刻技術在微機電系統與半導體工業具有重要的地位,傳統常見的矽材料加工研究如:電漿蝕刻的RIE與ICP模式、濕蝕刻的KOH蝕刻、雷射加工的Nd:YAG laser、Ecimer laser或femtosecond laser...等。Moreover, the formation of the patterned grain 121 adopts a laser cutting processing technology, wherein the micro-machining etching technology of the germanium material plays an important role in the micro-electromechanical system and the semiconductor industry, and the conventional common germanium material processing research such as: plasma etching RIE And ICP mode, wet etching KOH etching, laser processing of Nd:YAG laser, Ecimer laser or femtosecond laser...etc.

然而,CO2 雷射因不被矽材料吸收,一般不能被矽材料吸收和進行任何蝕刻的製程。本發明之一實施例中,主要係利用複合式方法改變矽基板材料吸收波長可達CO2 雷射10.6μm範圍而進行矽蝕刻。更進一步地,係採用玻璃輔助CO2 雷射加工(glass assisted CO2 laser processing,簡稱GACLAP)矽材料, 由試片下方放置玻璃,再利用夾置具使兩試片緊密貼合,並調整雷射光聚焦高度,使焦點聚焦在矽晶圓試片表面,改變雷射功率、移動速度和蝕刻次數進行加工,在適合的加工參數即可達成。由於將光束聚焦在矽晶圓試片的表面,由CO2 雷射的波長10.6μm為可穿透至矽材料之波段,底部玻璃可吸收CO2 雷射能量,同時對矽材料加熱升溫,在高溫的矽材料因能隙變小和微結構缺陷能階的出現,進而達到可吸收10.6μm雷射和被蝕刻加工。玻璃同時具有絕熱效果,使雷射光束熱源集中於矽材料試片升至高溫而達成蝕刻與鑽孔效果,進一步形成一圖案化之結構120。其中,該圖案化結構120之深度係為0.1μm至5μm之間。此外,本發明之雷射切割處理亦可減少絕緣層120的內應力,進而修補缺陷。However, CO 2 lasers are generally not absorbed by the tantalum material and are generally not absorbed by the tantalum material and subjected to any etching process. In one embodiment of the present invention, the ruthenium etching is mainly performed by a composite method of changing the absorption wavelength of the ruthenium substrate material to a range of 10.6 μm from the CO 2 laser. Still further, the auxiliary system using CO 2 laser processing glass (glass assisted CO 2 laser processing, referred GACLAP) silicon materials, glass test piece is placed from below, reuse sandwiched with two test pieces to make close contact, and adjust Ray The focus of the light is focused, so that the focus is focused on the surface of the silicon wafer, and the laser power, moving speed and number of etchings are changed for processing, which can be achieved under suitable processing parameters. Since the beam is focused on the surface of the silicon wafer test piece, the wavelength of the CO 2 laser is 10.6 μm, which is a wavelength that can penetrate into the germanium material. The bottom glass can absorb the CO 2 laser energy and heat the germanium material at the same time. High-temperature tantalum materials are capable of absorbing 10.6 μm laser and being etched due to the small energy gap and the appearance of microstructure defect defects. The glass also has an insulating effect, so that the laser beam heat source is concentrated on the enamel material test piece and raised to a high temperature to achieve an etching and drilling effect, and a patterned structure 120 is further formed. The depth of the patterned structure 120 is between 0.1 μm and 5 μm. In addition, the laser cutting process of the present invention can also reduce the internal stress of the insulating layer 120, thereby repairing defects.

該應變晶質層130係選自一矽鍺(SiGe)材料。成長應變晶質層之方法例如使用分子束磊晶法、選擇性磊晶法、化學氣相沈積磊晶法或化學氣相沈積法。由於具有不同晶格常數之各薄膜層間在鬆弛狀態之互相作用,在鬆弛狀態具有較大晶格之半導體薄膜層是處於縮應變情況之下,而具有較小晶格常數之半導體薄膜層是處於壓縮應變情況之下,進而形成一具有應變平衡結構。亦即,在矽層及應變晶質層的薄膜層所組成之堆疊層結構,若應變晶質層130之晶格常數大於矽層之晶格常數,則應變晶質層130的係處於雙軸壓縮應變情況之下,而矽層係處於雙軸拉伸應變情況之下,反之亦然。前述步驟於矽層內形成缺陷區,因此於鬆弛的薄膜層成長時所產生之差排增殖之方向是朝向基底,並非朝向鬆弛的薄膜層,如此即可獲得鬆弛的薄膜層。進一步來說,本發明之矽鍺(SiGe)應變晶質層 130包含一拉伸矽鍺與一壓縮矽鍺。其中,其中該拉伸矽鍺之鍺濃度係介於5%至20%之間;該壓縮矽鍺之矽濃度係介於50%至80%之間;此外,該應變晶質層130之厚度為介於0.01至5微米之間。最後,沈積一磊晶層140於該應變晶質層130之表面,其中本發明可應用於磊晶生長以下材料層之技術,如GaN、GaAs、InP、GaAlAs、InGaAs、AlN、AlGaN或甚至SiGe。此外,該磊晶層140之磊晶方法可選自有機金屬氣相磊晶法(MOCVD)、分子束磊晶(MBE),氣相磊晶法(VPE)及液相磊晶法(LPE)之一,其中LPE及VPE的磊晶長成的速度和量產能力較MOCVD佳,但在磊晶薄度及平整度的控制能力就不如MOCVD好,然而,MOCVD有成本較高,良率低而且原料取得不易等缺點;基於以上因素,造成在不同的產品所應用的磊晶方法也不同,在傳統亮度的LED上(如GaP、GaAsP及AlGaAs)常用LPE(液相磊晶法),若是高亮度LED(如AlGaInP及GaN等)則要求的品質較為嚴格,較佳地則要用有機金屬氣相磊晶法(MOCVD)。The strained crystalline layer 130 is selected from the group consisting of a germanium (SiGe) material. The method of growing the strained crystal layer is, for example, a molecular beam epitaxy method, a selective epitaxial method, a chemical vapor deposition epitaxy method, or a chemical vapor deposition method. Due to the interaction between the thin film layers having different lattice constants in the relaxed state, the semiconductor thin film layer having a larger crystal lattice in the relaxed state is under the condition of shrinkage strain, and the semiconductor thin film layer having a smaller lattice constant is in the Under the condition of compressive strain, a strain-balanced structure is formed. That is, in the stacked layer structure composed of the thin film layer of the tantalum layer and the strained crystal layer, if the lattice constant of the strained crystal layer 130 is larger than the lattice constant of the tantalum layer, the strain of the strained crystal layer 130 is in the biaxial Under compressive strain, the 矽 layer is under biaxial tensile strain and vice versa. The foregoing step forms a defect region in the ruthenium layer, so that the direction in which the diffusion of the relaxed film layer grows is directed toward the substrate, not toward the relaxed film layer, so that a relaxed film layer can be obtained. Further, the bismuth (SiGe) strained crystalline layer of the present invention 130 includes a stretch 矽锗 and a compression 矽锗. Wherein the concentration of the tensile enthalpy is between 5% and 20%; the concentration of the compressed cerium is between 50% and 80%; in addition, the thickness of the strained crystalline layer 130 It is between 0.01 and 5 microns. Finally, an epitaxial layer 140 is deposited on the surface of the strained crystalline layer 130, wherein the invention can be applied to techniques for epitaxially growing a material layer such as GaN, GaAs, InP, GaAlAs, InGaAs, AlN, AlGaN or even SiGe. . In addition, the epitaxial method of the epitaxial layer 140 may be selected from the group consisting of metal metal vapor phase epitaxy (MOCVD), molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), and liquid phase epitaxy (LPE). Among them, the speed and mass production capacity of LPE and VPE are better than MOCVD, but the control ability of epitaxial thinness and flatness is not as good as MOCVD. However, MOCVD has higher cost and lower yield. Moreover, the disadvantages of raw materials are not easy to obtain; based on the above factors, the epitaxial method applied in different products is also different, and LPE (liquid phase epitaxy) is commonly used on conventional brightness LEDs (such as GaP, GaAsP and AlGaAs). High-brightness LEDs (such as AlGaInP and GaN) require more stringent quality, preferably by organometallic vapor phase epitaxy (MOCVD).

接著,請配合參考第3圖,其顯示為本發明之一種於圖形化絕緣層上覆應變晶質層之又一結構示意圖100,其與第1圖並未太大之不同,其差異在於:於該絕緣層120上方更包含一緩衝層122,亦即該緩衝層122形成於該絕緣層120之上。其中,該緩衝層亦選自一矽鍺(SiGe)材料,且亦具有拉伸矽鍺部分與壓縮矽鍺部分之應變晶質層130的結構。應變晶質層130的兩個部分可磊晶地成長或結合在一矽鍺鬆弛緩衝層122的頂部上。在這兩部分的應變係藉由磊晶地成長拉伸矽鍺係具有一鍺濃度,其小於矽鍺鬆弛緩衝層122之 鍺濃度,以及磊晶地成長壓縮應變矽鍺係具有一鍺濃度,其高於矽鍺鬆弛緩衝層122之鍺濃度。結果,壓縮應變矽鍺的鍺濃度總是高於拉伸應變矽鍺。Next, please refer to FIG. 3, which shows another structural diagram 100 of the present invention for covering the strained crystalline layer on the patterned insulating layer, which is not much different from the first one, and the difference is: A buffer layer 122 is further disposed on the insulating layer 120, that is, the buffer layer 122 is formed on the insulating layer 120. Wherein, the buffer layer is also selected from a germanium (SiGe) material, and also has a structure of a tensile layer portion and a strained crystalline layer 130 of a compressed germanium portion. The two portions of the strained crystalline layer 130 can be epitaxially grown or bonded to the top of a relaxed buffer layer 122. The strain strains in the two portions have a germanium concentration by epitaxial growth of the tensile system, which is smaller than the relaxation buffer layer 122. The erbium concentration, as well as the epitaxial growth compressive strain enthalpy, has a enthalpy concentration that is higher than the erbium concentration of the erbium relaxation buffer layer 122. As a result, the enthalpy concentration of the compressive strain 总是 is always higher than the tensile strain 矽锗.

<實施例1><Example 1>

首先,將矽(Si)基板經由RCA Standard Clean,除去基板上之微塵、金屬離子及有機物之雜質。接著,以離子植入程序於矽(Si)基板之表面沉積一層厚為1.2微米二氧化矽絕緣層,其中,離子植入程序所使用之離子為硼離子;接著,採用玻璃輔助CO2 雷射切割(glass assisted CO2 laser processing,簡稱GACLAP)矽基板以形成深度係為0.3μm之圖案化結構;然後,以化學氣相沉積法沉積厚度為3μm矽鍺(SiGe)之應變晶質層。其中該矽鍺(SiGe)材料包含一拉伸矽鍺與一壓縮矽鍺,且該拉伸矽鍺之鍺濃度係為5%,該壓縮矽鍺之矽濃度係為50%。最後,以有機金屬氣相磊晶法(MOCVD)沉積磷化鋁鎵銦(AlGaInP)之磊晶層。藉由此結構與方法可避免磊晶層於該圖形化絕緣層上剝落,解決基板與磊晶層間晶格常數不匹配之問題,且可使錯位密度達1×105 個/cm2 以下。First, the cerium (Si) substrate is subjected to removal of impurities such as fine dust, metal ions, and organic substances on the substrate via RCA Standard Clean. Next, a 1.2 μm thick ceria insulating layer is deposited on the surface of the germanium (Si) substrate by an ion implantation process, wherein the ions used in the ion implantation process are boron ions; then, the glass-assisted CO 2 laser is used. A glass assisted CO 2 laser processing (GACLAP) substrate was formed to form a patterned structure having a depth of 0.3 μm. Then, a strained crystal layer having a thickness of 3 μm of germanium (SiGe) was deposited by chemical vapor deposition. Wherein the bismuth (SiGe) material comprises a tensile enthalpy and a compressed enthalpy, and the enthalpy concentration of the enthalpy is 5%, and the enthalpy concentration of the enthalpy is 50%. Finally, an epitaxial layer of aluminum gallium indium phosphide (AlGaInP) is deposited by organometallic vapor phase epitaxy (MOCVD). The structure and the method can prevent the epitaxial layer from peeling off on the patterned insulating layer, solve the problem that the lattice constant of the substrate and the epitaxial layer does not match, and can make the dislocation density to be 1×10 5 /cm 2 or less.

<實施例2><Example 2>

實施例2大致如實施例1之步驟,其主要差異係:於絕緣層與應變晶質層之間增加一矽鍺(SiGe)緩衝層。藉由此結構與方法可避免磊晶層於該圖形化絕緣層上剝落,解決基板與磊晶層間晶格常數不匹配之問題,且可使錯位密度達0.3×105 個/cm2 以下。Embodiment 2 is substantially as in the step of Embodiment 1, and the main difference is that a germanium (SiGe) buffer layer is added between the insulating layer and the strained crystal layer. The structure and the method can prevent the epitaxial layer from peeling off on the patterned insulating layer, solve the problem that the lattice constant of the substrate and the epitaxial layer does not match, and can make the misalignment density to be 0.3×10 5 /cm 2 or less.

<實施例3><Example 3>

實施例3大致如實施例1之步驟,其主要差異係:該拉伸矽 鍺之鍺濃度改為15%,該壓縮矽鍺之矽濃度改為70%。藉由此結構與方法可避免磊晶層於該圖形化絕緣層上剝落,解決基板與磊晶層間晶格常數不匹配之問題,並可使磊晶層之結晶品質進一步提高,且錯位密度降低22%以上。Example 3 is substantially as the step of Example 1, the main difference is: the stretch 矽 The concentration of ruthenium was changed to 15%, and the concentration of ruthenium was changed to 70%. The structure and the method can prevent the epitaxial layer from peeling off on the patterned insulating layer, solve the problem that the lattice constant of the substrate and the epitaxial layer does not match, and further improve the crystal quality of the epitaxial layer and reduce the dislocation density. 22% or more.

<實施例4><Example 4>

實施例4大致如實施例1之步驟,其主要差異係:圖案化結構之深度係改為3μm。藉由此結構與方法可使錯位密度降低27%以上。Example 4 is substantially as in the step of Example 1, the main difference being that the depth of the patterned structure is changed to 3 μm. By this structure and method, the dislocation density can be reduced by 27% or more.

本發明之一種於圖形化絕緣層上覆應變晶質層之結構及其製造方法具有以下之功效:1.藉由本發明之應變晶質層可避免磊晶層於該圖形化之絕緣層上剝落,解決基板與磊晶層間晶格常數不匹配之問題;2.藉由本發明之雷射處理技術可降低絕緣層之內應力,進而修補缺陷;3.藉由本發明之雷射處理技術可使磊晶層之結晶品質進一步提高;4.相較於先前技術,本發明藉由圖形化絕緣層與應變晶質層之結合可使錯位密度達1×105 個/cm2 以下。The structure of the present invention for coating a strained crystalline layer on a patterned insulating layer and a method for fabricating the same have the following effects: 1. The strained crystalline layer of the present invention can prevent the epitaxial layer from peeling off on the patterned insulating layer. Solving the problem that the lattice constant of the substrate and the epitaxial layer does not match; 2. The laser processing technique of the present invention can reduce the internal stress of the insulating layer and repair the defect; 3. The laser processing technology of the present invention can make the laser The crystal quality of the crystal layer is further improved. 4. Compared with the prior art, the present invention can achieve a dislocation density of 1×10 5 /cm 2 or less by combining the patterned insulating layer and the strained crystal layer.

雖然本發明已以前述較佳實施例揭示,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與修改。如上述的解釋,都可以作各型式的修正與變化,而不會破壞此發明的精神。因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the present invention has been described in its preferred embodiments, it is not intended to limit the scope of the invention, and various modifications and changes can be made without departing from the spirit and scope of the invention. As explained above, various modifications and variations can be made without departing from the spirit of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧於圖形化絕緣層上覆應變晶質層之結構100‧‧‧ Structure of a strained crystalline layer over a patterned insulating layer

110‧‧‧基板110‧‧‧Substrate

120‧‧‧絕緣層120‧‧‧Insulation

121‧‧‧圖形化紋路121‧‧‧Graphic lines

122‧‧‧緩衝層122‧‧‧buffer layer

130‧‧‧應變晶質層130‧‧‧ strained crystalline layer

140‧‧‧磊晶層140‧‧‧ epitaxial layer

210~240‧‧‧步驟210~240‧‧‧Steps

為了讓本發明之上述和其他目的、特徵、和優點能更明顯,下文特舉本發明較佳實施例,並配合所附圖式,作詳細說明如下:第1圖,顯示為本發明之一種於圖形化絕緣層上覆應變晶質層之結構示意圖。The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention. A schematic diagram of the structure of the strained crystalline layer on the patterned insulating layer.

第2圖,顯示為本發明之一種於圖形化絕緣層上覆應變晶質層之製作流程圖。Fig. 2 is a flow chart showing the fabrication of a strained crystalline layer on a patterned insulating layer according to the present invention.

第3圖,顯示為本發明之一種於圖形化絕緣層上覆應變晶質層之另一結構示意圖。Figure 3 is a schematic view showing another structure of the strained crystalline layer on the patterned insulating layer of the present invention.

100‧‧‧於圖形化絕緣層上覆應變晶質層之結構100‧‧‧ Structure of a strained crystalline layer over a patterned insulating layer

110‧‧‧基板110‧‧‧Substrate

120‧‧‧絕緣層120‧‧‧Insulation

121‧‧‧圖形化紋路121‧‧‧Graphic lines

130‧‧‧應變晶質層130‧‧‧ strained crystalline layer

140‧‧‧磊晶層140‧‧‧ epitaxial layer

Claims (13)

一種於圖形化絕緣層上覆應變晶質層之結構,其包含:一基板;一絕緣層,係形成於該基板之上,且該絕緣層係具有圖形化紋路;一應變晶質層,係形成於該絕緣層之上,該應變晶質層係選自一矽鍺(SiGe)材料;以及一磊晶層,係形成於該應變晶質層之上,可使基板與磊晶層間以絕緣層之圖形化紋路而具有較佳之晶格匹配常數;其中,該矽鍺(SiGe)材料包含一拉伸矽鍺與一壓縮矽鍺。 A structure for overlying a strained crystalline layer on a patterned insulating layer, comprising: a substrate; an insulating layer formed on the substrate, wherein the insulating layer has a patterned grain; a strained crystalline layer, Formed on the insulating layer, the strained crystal layer is selected from a germanium (SiGe) material; and an epitaxial layer is formed on the strained crystal layer to insulate between the substrate and the epitaxial layer The patterned trace of the layer has a preferred lattice matching constant; wherein the germanium (SiGe) material comprises a stretched germanium and a compressed germanium. 如申請範圍第1項所述之於圖形化絕緣層上覆應變晶質層之結構,其中,該拉伸矽鍺之鍺濃度係介於5%至20%之間。 The structure of the patterned insulating layer overlying the strained crystalline layer as described in claim 1, wherein the tensile enthalpy concentration is between 5% and 20%. 如申請範圍第2項所述之於圖形化絕緣層上覆應變晶質層之結構,其中,該壓縮矽鍺之矽濃度係介於50%至80%之間。 The structure of the patterned insulating layer overlying the strained crystalline layer as described in claim 2, wherein the compressed crucible has a concentration of between 50% and 80%. 如申請範圍第1項所述之於圖形化絕緣層上覆應變晶質層之結構,其中,該絕緣層係選自離子植入程序或爐管擴散之方式進行製作。 The structure of the patterned insulating layer overlying the strained crystalline layer as described in claim 1 wherein the insulating layer is selected from the group consisting of an ion implantation process or furnace tube diffusion. 一種於圖形化絕緣層上覆應變晶質層之結構,其包含:一基板;一絕緣層,形成於該基板之上;一緩衝層,形成於該絕緣層之上;一應變晶質層,形成於該緩衝層之上;以及一磊晶層,形成於該應變晶質層之上;其中,該緩衝層係選自一矽鍺(SiGe)材料,該矽鍺(SiGe)材料包含一拉伸矽鍺與一壓縮矽鍺。 A structure for overlying a strained crystalline layer on a patterned insulating layer, comprising: a substrate; an insulating layer formed on the substrate; a buffer layer formed on the insulating layer; a strained crystalline layer, Formed on the buffer layer; and an epitaxial layer formed on the strained crystal layer; wherein the buffer layer is selected from a germanium (SiGe) material, and the germanium (SiGe) material comprises a pull Stretching and compressing. 如申請範圍第5項所述之於圖形化絕緣層上覆應變晶質層之結構,其中,該拉伸矽鍺之鍺濃度係介於5%至20%之間。 The structure of the patterned insulating layer overlying the strained crystalline layer as described in claim 5, wherein the tensile enthalpy concentration is between 5% and 20%. 如申請範圍第5項所述之於圖形化絕緣層上覆應變晶質層之結構,其中,該壓縮矽鍺之矽濃度係介於50%至80%之間。 The structure of the overlying strained crystalline layer of the patterned insulating layer as described in claim 5, wherein the compressed germanium has a germanium concentration of between 50% and 80%. 一種於圖形化絕緣層上覆應變晶質層之製造方法,其步驟包含:(a)提供一基板;(b)沈積一絕緣層於該基板之表面,使得該絕緣層形成一圖形化紋路,用以改善該基板與該磊晶層間之晶格常數之不匹配;(c)沈積一應變晶質層於該絕緣層之表面;以及(d)沈積一磊晶層於該應變晶質層之表面;其中,該圖形化紋路之形成係可採用雷射處理技術。 A method for fabricating a strained crystalline layer on a patterned insulating layer, the method comprising: (a) providing a substrate; (b) depositing an insulating layer on a surface of the substrate such that the insulating layer forms a patterned texture, For improving the mismatch of the lattice constant between the substrate and the epitaxial layer; (c) depositing a strained crystalline layer on the surface of the insulating layer; and (d) depositing an epitaxial layer on the strained crystalline layer a surface; wherein the formation of the patterned texture is laser processing technology. 如申請範圍第8項所述之於圖形化絕緣層上覆應變晶質層之製造方法,其中,該步驟(b)之製作係選自絕緣層係選自離子植入程序或爐管擴散之方式進行製作。 The method for manufacturing a patterned insulating layer overlying a strained crystalline layer according to Item 8 of the application, wherein the step (b) is selected from the group consisting of an ion implantation process or a furnace tube diffusion. Way to make. 如申請範圍第8項所述之於圖形化絕緣層上覆應變晶質層之製造方法,其中,該步驟(c)之該應變晶質層係選自一矽鍺(SiGe)材料。 The method for manufacturing a patterned insulating layer overlying a strained crystalline layer as described in claim 8 wherein the strained crystalline layer of the step (c) is selected from the group consisting of a germanium (SiGe) material. 如申請範圍第10項所述之於圖形化絕緣層上覆應變晶質層之製造方法,其中,該步驟(c)之該矽鍺(SiGe)材料包含一拉伸矽鍺與一壓縮矽鍺。 The method for manufacturing a patterned strained crystalline layer on a patterned insulating layer according to claim 10, wherein the germanium (SiGe) material of the step (c) comprises a tensile crucible and a compressed crucible. . 如申請範圍第11項所述之於圖形化絕緣層上覆應變晶質層之製造方法,其中,該拉伸矽鍺之鍺濃度係介於5%至20% 之間。 The method for manufacturing a patterned strained crystalline layer on a patterned insulating layer according to claim 11, wherein the tensile enthalpy concentration is between 5% and 20%. between. 如申請範圍第11項所述之於圖形化絕緣層上覆應變晶質層之製造方法,其中,該壓縮矽鍺之矽濃度係介於50%至80%之間。 The method for manufacturing a patterned strained crystalline layer on a patterned insulating layer according to claim 11, wherein the compressed germanium has a concentration of between 50% and 80%.
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