TWI457985B - Semiconductor structure with stress absorbing buffer layer and manufacturing method thereof - Google Patents

Description

Semiconductor structure having stress absorbing buffer layer and method of fabricating the same

The invention relates to a semiconductor structure with a stress absorbing buffer layer and a manufacturing method thereof, which can eliminate the stress of the buffer layer of the semiconductor structure by a surface treatment technology, thereby reducing the defect density and avoiding cracking or peeling of the epitaxial layer. efficacy.

In recent years, semiconductors represented by compound semiconductors have effectively utilized various characteristics, and the range of applications has been further expanded. For example, a compound semiconductor is useful as a base substrate for laminating an epitaxial layer, and can be used for a semiconductor device such as a light emitting diode (LED) or a laser diode (LD).

However, one problem that typically arises during the fabrication of these materials is the lattice distortion caused by the deposition of hereroepitaxial. The so-called "heterostatic epitaxial" deposition layer is an epitaxial or single crystal layer deposited on a single crystal substrate having a different composition from the single crystal substrate. When the deposited epitaxial layer is pressed to produce a lattice structure having at least two orientations identical to the single crystal substrate below it, but when it is different from its original lattice constant, it is called "distortion"; wherein, the lattice distortion This occurs because when the film is deposited in such a way that its lattice structure will match the underlying single crystal substrate, the atoms in the deposited layer will leave the original position, which is originally occupied by the lattice structure of a large number of materials alone. position. For example, depositing an epitaxial epitaxial layer of tantalum-containing material such as tantalum or tantalum itself on a single crystal germanium substrate generally produces a compressive lattice distortion because the deposited germanium-containing material has a lattice constant greater than that of the germanium substrate. Large, the degree of distortion is related to the thickness of the deposited layer and the degree of lattice inconsistency between the deposited material and the underlying layer.

No. 5,122,845, which discloses a buffer layer for compound semiconductors and light-emitting diodes. Wherein, a buffer layer mainly composed of aluminum nitride (AlN) is deposited between the substrate and the gallium nitride layer, and the crystal structure of the buffer layer is microcrystalline or polycrystalline and is in an amorphous state. The state of the buffer layer is mixed, whereby the crystal structure of the buffer layer can improve the problem of crystal mismatching between the gallium nitride compound layers. However, the buffer layer of this patent needs to be mixed by microcrystalline germanium or polycrystalline germanium in an amorphous state. The disadvantage is that the method is not disclosed in detail.

Another reference to U.S. Patent No. 5,290,393, which discloses a compound semiconductor layer of a photovoltaic element of the main gallium nitride based, for example, _{Ga x Al 1-x N (} 0 <x ≦ 1). However, when the compound semiconductor layer is formed on the substrate in an epitaxial manner, the lattice surface pattern on the substrate is poor and affects the quality of the subsequent fabrication of the blue light-emitting element, and thus, by a buffer layer such as Ga _x Al _{x -1} N to improve the lattice matching problem between the substrate and the compound semiconductor. However, in the above-mentioned prior art, the photoelectric benefit produced has its limitations.

For the sake of his position, the applicant conducted experiments and research, and proposed a semiconductor structure with a stress absorption buffer layer and a manufacturing method thereof, in particular, a surface treatment technique can eliminate the stress of the buffer layer, thereby reducing defects. Density and avoid the effect of cracking or peeling of the epitaxial layer.

The main object of the present invention is to provide a semiconductor structure having a stress absorbing buffer layer and a method for fabricating the same, which are applied to a surface of the buffer layer and the epitaxial layer to perform a surface treatment technique to form a plurality of structures having a plurality of pores. By using the plurality of porous surfaces, the stress of the buffer layer can be eliminated to avoid cracking or peeling of the epitaxial layer.

In order to achieve the above object, the present invention provides a semiconductor structure having a stress absorbing buffer layer, comprising: a substrate, an insulating layer, a buffer layer, and an epitaxial layer; wherein the insulating layer is formed on a surface of the substrate; A buffer layer is formed on a surface of the insulating layer; and the epitaxial layer is formed on a surface of the buffer layer.

In addition, the present invention further provides a method for fabricating a semiconductor structure having a stress absorbing buffer layer, the method comprising: providing a substrate; depositing an insulating layer formed on the surface of the substrate; depositing a buffer layer formed on the surface of the insulating layer; A surface treatment is provided on the surface of the buffer layer to form a plurality of structures having a plurality of pores, and the plurality of structures having a porosity can eliminate the stress of the buffer layer; depositing an epitaxial layer formed on the surface of the buffer layer.

In one embodiment of the invention, the insulating layer is any one of the group consisting of oxides such as SiOx, SiOx (Sixx), Titanium oxide (TiOx) or alumina (AlOx).

In an embodiment of the invention, the buffer layer is selected from the group consisting of germanium or porous germanium, polycrystalline germanium, tantalum carbide (SiC), gallium nitride (GaN), sapphire, aluminum nitride (AlN), germanium (SiGe). One with tantalum nitride.

In an embodiment of the invention, the surface microstructure of the plurality of porous structures may be one of ordered mixed structures of dots, fibers, dendrites or disorder.

In one embodiment of the invention, the surface treatment technique is selected from one of plasma processing techniques, dry etching, wet etching, or a combination thereof.

The above and other objects, features, and advantages of the present invention will become more apparent and understood.

While the invention may be embodied in various forms, the embodiments illustrated in the drawings It is not intended to limit the invention to the particular embodiments illustrated and/or described.

Please refer to FIG. 1 , which shows a schematic diagram of a semiconductor structure having a stress absorption buffer layer according to the present invention. The semiconductor structure 100 having a stress absorbing buffer layer mainly includes: a substrate 110, an insulating layer 120, a buffer layer 130, and an epitaxial layer 140; wherein the insulating layer 120 is formed on a surface of the substrate 110; 130 is formed on the surface of the insulating layer 120; the epitaxial layer 140 is formed on the surface of the buffer layer 130, and the surface of the buffer layer 130 is formed into a plurality of structures 131 having a plurality of pores by a surface treatment technique, and The plurality of porous structures 131 can eliminate the stress of the buffer layer 130, thereby preventing cracking or peeling of the epitaxial layer 140.

Please refer to FIG. 2 again, which shows a manufacturing process diagram of a semiconductor structure having a stress absorbing buffer layer according to the present invention, which includes the following steps: Step 210: providing a substrate 110; Step 220: depositing an insulating layer 120, formed on a surface of the substrate 110; a step 230: depositing a buffer layer 130 on the surface of the insulating layer 120; and step 240: providing a surface treatment on the surface of the buffer layer 130 to form a plurality of structures 131 having a plurality of pores, and The plurality of porous structures 131 can eliminate the stress of the buffer layer 130; and step 250: deposit an epitaxial layer 140 on the surface of the buffer layer 130.

The material of the substrate 110 is selected from the group consisting of bismuth (Si), sapphire, tantalum carbide (SiC), aluminum nitride (AlN) or diamond.

Next, as shown in FIG. 2, the material of the insulating layer 120 is selected from any group consisting of oxides such as SiOx, SiNx, TiOx, or AlOx. . Preferably, yttrium oxide (SiOx) is selected as the insulating layer 120. Although in general, the thickness of the insulating layer 120 and the substrate 110 is not critical to the invention, it is preferred to control the insulating layer 120 having a thickness of about 1 micron. In addition, the deposition method of the insulating layer 120 deposited on the surface of the substrate 110 is selected from one of a sputtering method, an evaporation method, and a chemical vapor deposition method.

The buffer layer 130 material is selected from the group consisting of germanium or porous germanium, polycrystalline germanium, tantalum carbide (SiC), gallium nitride (GaN), sapphire, aluminum nitride (AlN), germanium (SiGe), and tantalum nitride. The deposition method of the buffer layer 130 deposited on the surface of the insulating layer 120 is selected from one of a sputtering method, an evaporation method, and a chemical vapor deposition method.

It is worth noting that simply depositing the epitaxial layer 140 on the buffer layer 130 causes internal stress to be generated such that the defect density is increased, eventually causing the epitaxial layer 140 to flake off. Examples are as follows: the deposited GaN epitaxial layer on sapphire is in compressive stress; the layers obtained on tantalum carbide are under slight tensile stress; the upper layer is under high tension. For layers under compressive stress and tension, this results in cracks that will form and then flake off in the epitaxial film. In particular, the above phenomenon is particularly serious for depositing the epitaxial layer 140 on the crucible. For epitaxial carriers, the limit beyond the occurrence of cracks is from about 1 micron to 2 microns, which is a limiting factor in producing a good quality layer.

Therefore, in order to solve the above problems, a preferred embodiment of the present invention employs a method of SOI (on-insulator), and more particularly, a method of patterning on a germanium substrate. It is worth noting that the patterning method is not limited to the germanium substrate, that is, the same effect can be obtained on the sapphire or tantalum carbide substrate. However, although the above-described method for improving the crystal quality of the epitaxial growth film does not completely and effectively solve the stress problem in the epitaxial growth film.

Therefore, the present invention proposes a solution, which is also an important feature of the present invention: the surface of the buffer layer 130 is formed by a surface treatment technique to form a plurality of structures 131 having a plurality of pores to prevent the epitaxial layer 140 from cracking or peeling off. .

In addition, the plurality of surface microstructures having a porous structure may be one of ordered mixed structures of dots, fibers, dendrites or disorder.

Finally, an epitaxial layer 140 is deposited on the surface of the buffer layer 130. Among them, the present invention can be applied to a technique of epitaxially growing a material layer such as GaN, GaAs, InP, GaAlAs, InGaAs, AlN, AlGaN or even SiGe. In addition, the epitaxial method of the epitaxial layer 140 may be selected from the group consisting of metal metal vapor phase epitaxy (MOCVD), molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), and liquid phase epitaxy (LPE). one. Among them, the speed and mass production capacity of LPE and VPE are better than MOCVD, but the control ability of epitaxial thinness and flatness is not as good as MOCVD. However, MOCVD has disadvantages such as high cost, low yield, and difficulty in obtaining raw materials. Based on the above factors, the epitaxial method applied in different products is also different. LPE (liquid phase epitaxy) is commonly used on conventional brightness LEDs (such as GaP, GaAsP and AlGaAs), and high-brightness LEDs (such as AlGaInP and GaN, etc.) require more stringent quality, preferably by organometallic vapor phase epitaxy (MOCVD).

<Example 1>

First, the cerium (Si) substrate 110 is subjected to removal of impurities such as fine dust, metal ions, and organic substances on the substrate 110 via RCA Standard Clean. Next, a 1 μm thick cerium oxide (SiO ₂ ) insulating layer 120 is deposited on the surface of the ytterbium (Si) substrate 110 by DC magnetron sputtering; then, a buffer layer of polycrystalline germanium is deposited by DC magnetron sputtering. 130, the surface buffer layer 130 has a roughness of 8 nm (on an RMS basis). Wherein, the polysilicon buffer layer 130 is subjected to surface treatment, wherein the surface treatment technology is a plasma processing technology, and the pressure system is generated between 5 mTorr and 30 mTorr, and the plasma frequency is at a bias frequency of 2 MHz or One of the 13.56 MHz. Further, the gas used for the plasma treatment is one of a mixed gas containing fluorine gas or hydrogen fluoride gas and a carrier gas. Wherein, the gas of the fluorine gas may be C ₁ F ₄ , C ₂ F ₂ , C ₂ F ₄ , C ₃ F ₆ , C ₄ F ₆ , C ₄ F ₈ , C ₅ F ₈ , or C ₆ F ₆ a hydrogen fluoride gas may be C ₂ HF ₅ , CHF ₃ , CH ₂ F ₂ , CH ₃ F, C ₃ H ₂ F ₆ , C ₃ H ₂ F ₄ , C ₃ HF ₅ or C ₃ HF ₇ One; the carrier gas may be one of helium, nitrogen, argon, hydrogen or air. The surface of the buffer layer 130 has a preferred roughness of 3.6 nm, which further improves the crystal quality of the epitaxial layer 140. In addition, the surface of the buffer layer 130 is formed by a plurality of ordered dot-like porous surface structures, and the structure can absorb internal stress to prevent the epitaxial layer from being cracked or peeled thereon. Finally, the epitaxial layer 140 of phosphorus gallium arsenide (GaAsP) is deposited by organometallic vapor phase epitaxy (MOCVD) to complete the entire epitaxial semiconductor structure with stress absorption. By comparing the present invention with its previous examples, the present invention does not require an additional complicated structure, and the plasma quality of the epitaxial layer 140 can be further improved by the plasma processing technology to improve the light-emitting characteristics of the overall device. (Note that plasma generation conditions are shown in Table 1)

<Example 2>

First, the cerium (Si) substrate 110 is subjected to removal of impurities such as fine dust, metal ions, and organic substances on the substrate 110 via RCA Standard Clean. Next, a 1.5 μm thick SiO ₂ insulating layer 120 is deposited on the surface of the ytterbium (Si) substrate 110 by RF magnetron sputtering; then, yttrium (SiGe) is deposited by RF magnetron sputtering. The buffer layer 130 has a surface buffer layer 130 having a roughness of 7 nm. Wherein, after the buffer layer 130 of the polysilicon is processed by the plasma, the surface of the buffer layer 130 has a preferred roughness of 4 nm, and the crystal quality of the epitaxial layer 140 can be further improved. In addition, the surface of the buffer layer 130 absorbs stress by forming a plurality of ordered dendritic porous surface structures by a plasma treatment technique, and the internal stress can be absorbed by the structure to prevent the epitaxial layer from peeling off thereon. Thereafter, the epitaxial layer 140 of gallium arsenide (GaAs) is deposited by organometallic vapor phase epitaxy (MOCVD) to complete the entire epitaxial semiconductor structure with stress absorption. By comparing the present invention with its prior examples, the present invention does not require an additional complicated structure, and the plasma quality of the epitaxial layer 140 can be further improved by the plasma treatment technique, and the dislocation density is reduced by more than 15%. (Note that plasma generation conditions are shown in Table 1)

<Example 3>

First, the ruthenium carbide (SiC) substrate 110 is subjected to removal of impurities such as fine dust, metal ions, and organic substances on the substrate 110 via RCA Standard Clean. Next, an insulating layer 120 of 1.5 μm thick tantalum nitride (SiNx) is formed on the surface of the tantalum carbide (SiC) substrate 110 by RF magnetron sputtering; then, germanium (SiGe) is deposited by radio frequency magnetron sputtering. The buffer layer 130 has a surface buffer layer 130 having a roughness of 10 nm. Wherein, the buffer layer 130 of germanium (SiGe) is treated by plasma, and the surface of the buffer layer 130 has a preferred roughness of 3.6 nm, so that the crystal quality of the epitaxial layer 140 can be further improved. In addition, the surface of the buffer layer 130 absorbs stress by forming a plurality of ordered dendritic porous surface structures by a plasma treatment technique, and the internal stress can be absorbed by the structure to prevent the epitaxial layer from peeling off thereon. Finally, the epitaxial layer 140 of gallium arsenide (GaAs) is deposited by organometallic vapor phase epitaxy (MOCVD) to complete the entire epitaxial semiconductor structure with stress absorption. By comparing the present invention with its prior examples, the present invention does not require an additional complicated structure, and the plasma quality of the epitaxial layer 140 can be further improved by the plasma treatment technique, and the dislocation density is reduced by 22% or more. (Note that plasma generation conditions are shown in Table 1)

While the present invention has been described in its preferred embodiments, it is not intended to limit the scope of the invention, and various modifications and changes can be made without departing from the spirit and scope of the invention. As explained above, all types of corrections and changes can be made without destroying the spirit of this creation. Therefore, the scope of the invention is defined by the scope of the appended claims.

100. . . Epitaxial semiconductor structure with stress absorption

110. . . Substrate

120. . . Insulation

130. . . The buffer layer

131. . . Multiple structures with multiple porosity

140. . . Epitaxial layer

210～250. . . Steps of the preparation method

Fig. 1 is a schematic view showing the structure of a semiconductor having a stress absorbing buffer layer of the present invention.

Fig. 2 is a schematic view showing the manufacturing process of the semiconductor structure having the stress absorbing buffer layer of the present invention.

100. . . Epitaxial semiconductor structure with stress absorption

110. . . Substrate

120. . . Insulation

130. . . The buffer layer

140. . . Epitaxial layer

Claims (9)

A semiconductor structure having a stress absorbing buffer layer, comprising: a substrate; an insulating layer formed on a surface of the substrate; a buffer layer formed on a surface of the insulating layer, and the surface of the buffer layer is a surface treatment technique forms a plurality of structures having a plurality of pores and reduces the roughness of the surface of the buffer layer; and an epitaxial layer is formed on the surface of the buffer layer, and the buffer layer can be eliminated by the structure of each porous layer Stress, and thus avoid cracking or spalling of the epitaxial layer. A semiconductor structure having a stress absorbing buffer layer according to claim 1, wherein the insulating layer is made of SiOx, SiNx, TiOx or alumina (AlOx). Any of a group of equal oxides. The semiconductor structure having a stress absorbing buffer layer according to claim 1, wherein the buffer layer is selected from the group consisting of germanium or porous germanium, polycrystalline germanium, tantalum carbide (SiC), gallium nitride (GaN), sapphire, One of aluminum nitride (AlN), germanium (SiGe) and tantalum nitride. The semiconductor structure having a stress absorbing buffer layer according to claim 1, wherein the surface microstructure of the plurality of porous structures may be ordered, fibrous, dendritic or disordered. One of the hybrid structures. A method of fabricating a semiconductor structure having a stress absorbing buffer layer, the method comprising: (a) providing a substrate; (b) depositing an insulating layer formed on a surface of the substrate; (c) depositing a buffer layer formed on the surface of the insulating layer; (d) providing a surface treatment technique on the surface of the buffer layer, forming a plurality of structures having a porosity and reducing the roughness of the surface of the buffer layer, and The plurality of porous structures can eliminate the stress of the buffer layer; and (e) deposit an epitaxial layer formed on the surface of the buffer layer. A method of fabricating a semiconductor structure having a stress absorbing buffer layer according to claim 5, wherein the insulating layer is ruthenium oxide (SiOx), tantalum nitride (SiNx), titanium oxide (TiOx) or aluminum oxide. Any of a group consisting of oxides such as (AlOx). A method of fabricating a semiconductor structure having a stress absorbing buffer layer according to claim 5, wherein the buffer layer is selected from the group consisting of germanium or porous germanium, polycrystalline germanium, tantalum carbide (SiC), gallium nitride (GaN). One of sapphire, aluminum nitride (AlN), germanium (SiGe) and tantalum nitride. The method for fabricating a semiconductor structure having a stress absorbing buffer layer according to claim 5, wherein the surface microstructure of the plurality of porous structures may be ordered dot, fiber, or dendritic Or one of the disordered hybrid structures. The method for fabricating a semiconductor structure having a stress absorbing buffer layer according to claim 5, wherein the surface treatment technique of the step (d) is selected from the group consisting of plasma processing technology, dry etching, wet etching or Its combination.