TWI458056B - 接觸墊支撐結構及積體電路 - Google Patents
接觸墊支撐結構及積體電路 Download PDFInfo
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Description
本發明係有關於一種積體電路,特別係有關於一種接觸墊支撐結構。
積體電路的接觸墊係負責外界與積體電路本身的電力(power)訊號、接地(ground)訊號、輸入(input)訊號或輸出(output)訊號等訊號溝通,且接觸墊可提供接合(bonding)和元件測試等功能。隨著積體電路尺寸持續縮小,產品的複雜性日漸提高,因而需要更小面積和更多數量的接觸墊。因此,接觸墊的可靠度(reliability)為一重要的參數。
第1A和1B圖為習知積體電路的接觸墊支撐結構150的介層孔110的排列方式。習知積體電路的接觸墊支撐結構150係設置於一半導體基板100上,並以一金屬層間介電層104相隔。習知的接觸墊支撐結構150包括以一金屬層間介電層(inter metal dielectric,IMD)108分隔的一金屬層106、一接觸墊金屬層112以及複數個穿過金屬層間介電層108的圓形介層孔插塞110,其中介層孔插塞110係電連接接觸墊金屬層112和金屬層106,介層孔插塞110係以一陣列形式排列,意即每一個介層孔插塞110其相對兩邊相鄰的其他的兩個介層孔插塞具有相同的間距,且沿任一方向之每一個介層孔插塞110為週期性排列。然而,當習知的接觸墊支撐結構150受到強大之接合力(bonding force)或元件測試應力時,會使位於接觸墊金屬層112下方的金屬層間介電層108產生破裂,並會沿著排成陣列形式的介層孔插塞110產生一連續破裂路徑160,無限制地沿著金屬層間介電層108與介層孔插塞110的邊緣傳遞,上述連續破裂路徑160會降低接觸墊的可靠度(reliability)。因而使積體電路測試成本無法降低,且良率無法提升。另外,由於習知的接觸墊支撐結構150的機械強度無法提升,因而設計規則(design rule)並不允許電路設計位於接觸墊下的區域。
在此技術領域中,有需要一種接觸墊支撐結構,其具有較佳的機械強度,以改善接觸墊的可靠度、降低積體電路的測試成本並提升其良率。
有鑑於此,本發明之一實施例係提供一種接觸墊支撐結構,包括一下層之第一導電平板和一上層之第二導電平板,並藉由一第一介電層彼此分隔;由複數個圓環形介層孔插塞組成的複數個圓環形介層孔插塞群組,垂直穿過上述第一介電層,並電性連接至上述第一導電平板和上述第二導電平板,其中每一個上述圓環形介層孔插塞群組的每一個上述圓環形介層孔插塞不以陣列形式排列。
本發明之另一實施例係提供一種積體電路,包括一半導體基板;一接觸墊支撐結構,設置於半導體基板上,上述接觸墊支撐結構包括一下層之第一導電平板和一上層之第二導電平板,並藉由一第一介電層彼此分隔;由複數個圓環形介層孔插塞組成的一圓環形介層孔插塞群組,垂直穿過上述第一介電層,並電性連接至上述第一導電平板和上述第二導電平板,其中上述圓環形介層孔插塞群組的每一個上述圓環形介層孔插塞不以陣列形式排列。
以下以各實施例詳細說明並伴隨著圖式說明之範例,做為本發明之參考依據。在圖式或說明書描述中,相似或相同之部分皆使用相同之圖號。且在圖式中,實施例之形狀或是厚度可擴大,並以簡化或是方便標示。再者,圖式中各元件之部分將以分別描述說明之,值得注意的是,圖中未繪示或描述之元件,為所屬技術領域中具有通常知識者所知的形式,另外,特定之實施例僅為揭示本發明使用之特定方式,其並非用以限定本發明。
第2A圖為本發明一實施例之接觸墊支撐結構500a的上視示意圖,其顯示本發明一實施例之接觸墊支撐結構500a的圓環形介層孔插塞群組220的排列方式,在此為方便顯示圓環形介層孔插塞群組220的排列方式,圓環形介層孔插塞群組220係以實線顯示。第2B圖為沿第2A圖A-A’切線的剖面圖,其顯示本發明一實施例之包含接觸墊支撐結構500a的積體電路。如第2A和2B圖所示,本發明一實施例之包含接觸墊支撐結構500a的積體電路包括一半導體基板200。在本發明一實施例中,半導體基板200可為矽基板。在其他實施例中,可利用鍺化矽(SiGe)、塊狀半導體(bulk semiconductor)、應變半導體(strained semiconductor)、化合物半導體(compound semiconductor)、絕緣層上覆矽(silicon on insulator,SOI),或其他常用之半導體基板做為半導體基板200。半導體基板200可植入P型或N型不純物,以針對設計需要改變其導電類型。在本發明一實施例中,可於半導體基板200上選擇性地設置一電源電路202。在本發明其他實施例中,電源電路202可為包括電晶體、二極體、電容、電感、以及其他主動或非主動半導體元件之多種分離之電路元件組合的電路。一介電層204,設置於半導體基板200上,並覆蓋電源電路202。在本發明一實施例中,介電層204可為金屬層間介電層(inter metal dielectric,IMD),其材質可包括二氧化矽(SiO2
)、氮化矽(SiNX
)、氮氧化矽(SiON)、磷矽玻璃(PSG)、硼磷矽玻璃(BPSG)、含氟之二氧化矽(F-containing SiO2
)或其他類型之介電常數約小3.9之低介電常數(low-k)材料。在本發明其他實施例中,介電層204也可包括旋轉塗佈式無機介電質(spin-on inorganic dielectric)、旋轉塗佈式有機介電質(spin-on organic dielectric)、多孔介電材料(porous dielectric material)、有機聚合物(organic polymer)、有機矽玻璃(organic silica glass)、氟矽玻璃(fluorinated silicate glass,FSG)、類鑽碳(diamond-like carbon)、含氫矽酸鹽類(Hydrogen Silsesquioxane,HSQ)系列材料、含甲基矽酸鹽(methyl silsesquioxane,MSQ)系列材料、或多孔有機系列材料。可利用包括旋轉塗佈(spin-coating)、化學氣相沉積(chemical vapor deposition,CVD)、物理氣相沉積(physical vapor deposition,PVD)、電鍍(plating)等方式形成介電層204。
如第2A和2B圖所示,一接觸墊支撐結構500a,設置於半導體基板200上,並位於介電層204上。接觸墊支撐結構500a包括一下層之第一導電平板206和一上層之第二導電平板212,上述第一導電平板206和第二導電平板212係藉由一介電層208彼此分隔。接觸墊支撐結構500a中的第二導電平板212可視為一接觸墊,其暴露的表面係提供包括接合區域(bonding area)和元件測試區域(probing area)等的一區域,其可用以電性連接至一金屬接觸墊和一接合線(bonding wire)。在本發明一實施例中,第二導電平板212可為積體電路中的頂層金屬層(意即最上層的金屬層),而第一導電平板206可為頂層金屬層下方形成的另一層金屬層,而介電層208可為頂層金屬層間介電層(IMD)(意即最上層的金屬層間介電層)。在本發明其他實施例中,第一導電平板206和第二導電平板212也可為其他層之導電層,而介電層208也可為其他層之頂層金屬層間介電層(IMD)。第一導電平板206和第二導電平板212的材質可包括鋁、鋁合金、銅、銅合金或其他銅基導電材料。而介電層208的材質可與介電層204相同。
如第2A和2B圖所示,接觸墊支撐結構500a包括由複數個圓環形介層孔插塞210組成的複數個圓環形介層孔插塞群組220,垂直穿過介電層208,並電性連接至第一導電平板206和第二導電平板212。在本發明一實施例中,圓環形介層孔插塞210可為積體電路中的頂層介層孔插塞(意即最上層的介層孔插塞)。在本發明其他實施例中,圓環形介層孔插塞210也可為其他層之介層孔插塞。圓環形介層孔插塞210的材質可包括鎢、鋁、銅或其合金。在本發明一實施例中,圓環形介層孔插塞210具有相同的尺寸,其中圓環形介層孔插塞210均一的寬度W可大於或等於設計規則(design rule)所定義之介層孔的臨界尺寸(critical dimension)。如第2A圖所示,本發明實施例的圓環形介層孔插塞210係將部分介電層208包圍成一封閉區域270,因此,當本發明實施例之接觸墊支撐結構500a受到強大之接合力(bonding force)或元件測試應力時,圓環形介層孔插塞210可抑制位於封閉區域280中的介電層208的碎裂路徑不會無限制地沿著介電層208與介層孔插塞的邊緣傳遞。另外,如第2A圖所示,每一個圓環形介層孔插塞群組220的每一個圓環形介層孔插塞210不以陣列形式排列。意即,圓環形介層孔插塞210與其相對兩邊相鄰的其他的兩個環形介層孔插塞210的間距可不相同,每一個圓環形介層孔插塞與其相對兩側相鄰的其他兩個圓環形介層孔插塞的中心可不位於同一直線上。如第2B圖所示,沿任一方向之每一個圓環形介層孔插塞210可不為週期性排列。另外,圓環形介層孔插塞群組220的每一個圓環形介層孔插塞210的設置方式、數量和方向並無限制。舉例來說,如第2A圖所示之五個圓環形介層孔插塞210a、210b、210c、210d、210e可組成一圓環形介層孔插塞群組220a,並排列成一五邊形,圓環形介層孔插塞210a、210b與其他之圓環形介層孔插塞210g、210h、210i也可組成另一五邊形的圓環形介層孔插塞群組220b,而接觸墊支撐結構500a係包括複數個圓環形介層孔插塞群組220,其中圓環形介層孔插塞群組220a或220b的每一個圓環形介層孔插塞與其兩邊相鄰的圓環形介層孔插塞可為交錯排列。由第2A圖可知,當本發明實施例之接觸墊支撐結構500a受到強大之接合力(bonding force)或元件測試應力時,依據本發明實施例之圓環形介層孔插塞群組220的排列方式可使位於圓環形介層孔插塞210之間的例如區域280之區域的部分介電層208的碎裂路徑被其他的圓環形介層孔插塞群組阻擋,使其不會無限制地沿著介電層208與介層孔插塞的邊緣傳遞。另外,圓環形介層孔插塞210的寬度W為均一,並不會產生介層孔插塞填充材料無法完全填滿介層孔的問題。
本發明實施例之接觸墊支撐結構500a可有效地提升接觸墊的機械強度,當其受到強大之接合力(bonding force)或元件測試應力時,接觸墊支撐結構500a可抑制位於接觸墊下方之金屬層間介電層208的碎裂。因此,如第2A所示的電源電路202可設置於接觸墊支撐結構500a正下方的區域,意即電源電路202可設置於接合墊下電路(circuits under pad,CUP)區域,可使晶片面積更有效地應用及縮小晶片尺寸。
第3圖為本發明另一實施例之接觸墊支撐結構500b的上視示意圖,其顯示接觸墊支撐結構500b的圓環形介層孔插塞群組240的排列方式。在本發明一實施例中,圓環形介層孔插塞230具有相同的尺寸,其中圓環形介層孔插塞230均一的寬度W可大於或等於設計規則(design rule)所定義之介層孔的臨界尺寸(critical dimension)。本發明實施例的位於介電層之圓環形介層孔插塞230係將部分介電層包圍成一封閉區域290,因此,當本發明實施例之接觸墊支撐結構500b受到強大之接合力(bonding force)或元件測試應力時,圓環形介層孔插塞230可抑制位於封閉區域290中的介電層的碎裂路徑不會沿著介電層與介層孔插塞的邊緣傳遞。如第3圖所示,圓環形介層孔插塞群組240a可由至少八個圓環形介層孔插塞230a、230b、230c、230d、230e、230f、230g、230h組成,並排列成一四角星形,而圓環形介層孔插塞230b、230c、230d與其他五個圓環形介層孔插塞230i、230j、230k、230l、230m也可組成另一四角星形的圓環形介層孔插塞群組240b,而接觸墊支撐結構500b可包括複數個圓環形介層孔插塞群組240,其中圓環形介層孔插塞群組240a或240b的每一個圓環形介層孔插塞與其兩邊相鄰的圓環形介層孔插塞可為交錯排列。由第3圖可知,當本發明實施例之接觸墊支撐結構500b受到強大之接合力(bonding force)或元件測試應力時,依據本發明實施例之圓環形介層孔插塞群組240的排列方式可使位於圓環形介層孔插塞230之間的例如區域300之區域的部分介電層的碎裂路徑被其他的圓環形介層孔插塞群組阻擋,使其不會無限制地沿著介電層與介層孔插塞的邊緣傳遞。
在其他實施例中,接觸墊支撐結構的圓環形介層孔插塞群組中的每一個圓環形介層孔插塞的設置方式、數量和方向並無限制。只須符合每一個圓環形介層孔插塞群組的每一個圓環形介層孔插塞不以陣列形式排列,意即圓環形介層孔插塞與其相對兩邊相鄰的其他的兩個環形介層孔插塞的間距可不相同即可。另外,圓環形介層孔插塞群組的每一個圓環形介層孔插塞與其相對兩側相鄰的其他兩個圓環形介層孔插塞的中心可不位於同一直線上,且沿任一方向之每一個圓環形介層孔插塞可不為週期性排列。
本發明實施例的積體電路可包括設置於一半導體基板200上的一接觸墊支撐結構500a或500b,上述接觸墊支撐結構500a或500b包括一下層之第一導電平板206和一上層之第二導電平板212,並藉由一介電層208彼此分隔;由複數個圓環形介層孔插塞210或230組成的複數個圓環形介層孔插塞群組230或240,垂直穿過上述介電層208,並電性連接至上述第一導電平板212和上述第二導電平板206,其中上述圓環形介層孔插塞群組230或240的每一個上述圓環形介層孔插塞210或230不以陣列形式排列。本發明實施例的積體電路可更包括一電源電路202,設置於上述半導體基板200和用以分隔半導體基板200和接觸墊支撐結構500a或500b的介電層204之間,其中上述電源電路202係位於上述接觸墊支撐結構500a或500b的正下方。
本發明實施例的接觸墊支撐結構係具有以下優點。本發明實施例的接觸墊支撐結構包含圓環形的介層孔插塞,上述圓環形的介層孔插塞可將位於接觸墊下方之部分介電層包圍成一封閉區域,因此,當本發明實施例之接觸墊支撐結構受到強大之接合力或元件測試應力時,上述圓環形介層孔插塞可抑制位於封閉區域中的介電層的碎裂路徑不會無限制地沿著介電層與介層孔插塞的邊緣傳遞。而每一個圓環形介層孔插塞群組中的每一個圓環形介層孔插塞不以陣列形式排列,當本發明實施例之接觸墊支撐結構受到強大之接合力或元件測試應力時,依據本發明實施例之圓環形介層孔插塞群組的排列方式可使位於接觸墊下方之圓環形介層孔插塞之間的區域的部分介電層的碎裂路徑被其他的圓環形介層孔插塞群組阻擋,使其不會無限制地沿著介電層與介層孔插塞的邊緣傳遞。因而可改善接觸墊的可靠度、降低積體電路的測試成本並提升其良率。另外,本發明實施例之圓環形介層孔插塞的寬度為均一,並不會產生介層孔插塞填充材料無法完全填滿介層孔的問題。並且,本發明實施例之接觸墊支撐結構可有效地提升接觸墊的機械強度,因此可於接合墊下電路(CUP)區域設置電源電路(power circuit),可使晶片面積更有效地應用及縮小晶片尺寸。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定為準。
100...半導體基板
104、108...金屬層間介電層
106...金屬層
110...介層孔插塞
112...接觸墊金屬層
150...接觸墊支撐結構
160...介電層破裂路徑
200...半導體基板
202...電源電路
204、208...介電層
206...第一導電平板
212...第二導電平板
210、210a、210b、210c、210d、210e、210f、210g、210h、210i...圓環形介層孔插塞
220、220a、220b...圓環形介層孔插塞群組
230、230a、230b、230c、230d、230e、230f、230g、230h、230i、230j、230k、2301、230m...圓環形介層孔插塞
240、240a、240b...圓環形介層孔插塞群組
270、280、290、300...區域
500a、500b...接觸墊支撐結構
W...寬度
第1A和1B圖為習知的接觸墊支撐結構的介層孔的排列方式,上述習知的排列方式會造成介電層的連續破裂路徑。
第2A圖為本發明一實施例之接觸墊支撐結構的上視示意圖,其顯示接觸墊支撐結構的圓環形介層孔插塞群組的排列方式。
第2B圖為沿第2A圖A-A’切線的剖面圖,其顯示本發明一實施例之接觸墊支撐結構。
第3圖為本發明另一實施例之接觸墊支撐結構的上視示意圖,其顯示接觸墊支撐結構的圓環形介層孔插塞群組的排列方式。
212...第二導電平板
210、210a、210b、210c、210d、210e、210f、210g、210h、210i...圓環形介層孔插塞
220、220a、220b...圓環形介層孔插塞群組
270、280...區域
500a...接觸墊支撐結構
W...寬度。
Claims (18)
- 一種接觸墊支撐結構,包括:一下層之第一導電平板和一上層之第二導電平板,並藉由一第一介電層彼此分隔;以及由複數個圓環形介層孔插塞組成的複數個圓環形介層孔插塞群組,垂直穿過該第一介電層,並電性連接至該第一導電平板和該第二導電平板,其中每一個該圓環形介層孔插塞群組的每一個該圓環形介層孔插塞不以陣列形式排列,且其中每一個該圓環形介層孔插塞的一上視形狀為圓環形。
- 如申請專利範圍第1項所述之接觸墊支撐結構,其中每一個該圓環形介層孔插塞與其相對兩側相鄰的其他兩個該圓環形介層孔插塞的中心不位於同一直線上。
- 如申請專利範圍第1項所述之接觸墊支撐結構,其中該圓環形介層孔插塞群組之沿一方向的每一個該圓環形介層孔插塞不為週期性排列。
- 如申請專利範圍第1項所述之接觸墊支撐結構,其中該圓環形介層孔插塞群組的每一個該圓環形介層孔插塞與其兩邊相鄰的該圓環形介層孔插塞為交錯排列。
- 如申請專利範圍第1項所述之接觸墊支撐結構,其中該圓環形介層孔插塞群組由至少五個該圓環形介層孔插塞組成,並排列成一五邊形。
- 如申請專利範圍第1項所述之接觸墊支撐結構,其中該圓環形介層孔插塞群組由至少八個該圓環形介層孔插塞組成,並排列成一四角星形。
- 如申請專利範圍第1項所述之接觸墊支撐結構,其中該複數個圓環形介層孔插塞具有相同的尺寸。
- 如申請專利範圍第1項所述之接觸墊支撐結構,更包括:一半導體基板,設置於該第一導電平板的下方,並藉由一第二介電層彼此分隔;以及一電源電路,設置於該半導體基板和該第二介電層之間,其中該電源電路係位於該第一導電平板的正下方。
- 如申請專利範圍第1項所述之接觸墊支撐結構,其中該圓環形介層孔插塞的寬度大於或等於設計規則所定義之介層孔的臨界尺寸。
- 一種積體電路,包括:一半導體基板;以及一接觸墊支撐結構,設置於半導體基板上,該接觸墊支撐結構包括:一下層之第一導電平板和一上層之第二導電平板,並藉由一第一介電層彼此分隔;以及由複數個圓環形介層孔插塞組成的一圓環形介層孔插塞群組,垂直穿過該第一介電層,並電性連接至該第一導電平板和該第二導電平板,其中該圓環形介層孔插塞群組的每一個該圓環形介層孔插塞不以陣列形式排列,且其中每一個該圓環形介層孔插塞的一上視形狀為圓環形。
- 如申請專利範圍第10項所述之積體電路,其中每一個該圓環形介層孔插塞與其相對兩側相鄰的其他兩個該 圓環形介層孔插塞的中心不位於同一直線上。
- 如申請專利範圍第10項所述之積體電路,其中該圓環形介層孔插塞群組之沿一方向的每一個該圓環形介層孔插塞不為週期性排列。
- 如申請專利範圍第10項所述之積體電路,其中該圓環形介層孔插塞群組的每一個該圓環形介層孔插塞與其兩邊相鄰的該圓環形介層孔插塞為交錯排列。
- 如申請專利範圍第10項所述之積體電路,其中該圓環形介層孔插塞群組由至少五個該圓環形介層孔插塞組成,並排列成一五邊形。
- 如申請專利範圍第10項所述之積體電路,其中該圓環形介層孔插塞群組由至少八個該圓環形介層孔插塞組成,並排列成一四角星形。
- 如申請專利範圍第10項所述之積體電路,其中該複數個圓環形介層孔插塞具有相同的尺寸。
- 如申請專利範圍第10項所述之積體電路,更包括:第二介電層,介於該半導體基板與該接觸墊支撐結構之間;以及一電源電路,設置於該半導體基板和該第二介電層之間,其中該電源電路係位於該接觸墊支撐結構的正下方。
- 如申請專利範圍第10項所述之積體電路,其中該圓環形介層孔插塞的寬度大於或等於設計規則所定義之介層孔的臨界尺寸。
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TW098100909A TWI458056B (zh) | 2009-01-12 | 2009-01-12 | 接觸墊支撐結構及積體電路 |
US12/431,636 US8080881B2 (en) | 2009-01-12 | 2009-04-28 | Contact pad supporting structure and integrated circuit for crack suppresion |
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US8791016B2 (en) | 2012-09-25 | 2014-07-29 | International Business Machines Corporation | Through silicon via wafer, contacts and design structures |
US11004812B2 (en) * | 2018-09-18 | 2021-05-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of forming the same |
CN117995816A (zh) * | 2022-10-27 | 2024-05-07 | 长鑫存储技术有限公司 | 半导体结构和半导体结构的制造方法 |
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US5739587A (en) * | 1995-02-21 | 1998-04-14 | Seiko Epson Corporation | Semiconductor device having a multi-latered wiring structure |
US20080246152A1 (en) * | 2007-04-04 | 2008-10-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with bonding pad |
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US5739587A (en) * | 1995-02-21 | 1998-04-14 | Seiko Epson Corporation | Semiconductor device having a multi-latered wiring structure |
US20080246152A1 (en) * | 2007-04-04 | 2008-10-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with bonding pad |
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