TWI456786B - 半導體發光元件之製造方法及半導體發光元件、燈、電子機器、機械裝置 - Google Patents

半導體發光元件之製造方法及半導體發光元件、燈、電子機器、機械裝置 Download PDF

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TWI456786B
TWI456786B TW100103059A TW100103059A TWI456786B TW I456786 B TWI456786 B TW I456786B TW 100103059 A TW100103059 A TW 100103059A TW 100103059 A TW100103059 A TW 100103059A TW I456786 B TWI456786 B TW I456786B
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layer
grown
emitting device
semiconductor light
type semiconductor
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TW201140900A (en
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Hiromitsu Sakai
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Toyoda Gosei Kk
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/305—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table characterised by the doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)
  • Led Device Packages (AREA)

Claims (21)

  1. 一種半導體發光元件之製造方法，其特徵為具備：第一製程，係在第一有機金屬化學氣相成長裝置中，在基板上積層第一n型半導體層；及第二製程，係在第二有機金屬化學氣相成長裝置中，在前述第一n型半導體層上依序積層前述第一n型半導體層的再成長層、第二n型半導體層、發光層、及由p包覆層和p接觸層所構成之p型半導體層，在積層前述再成長層的製程中，依序進行：供給比前述第一n型半導體層形成時還少量的Si作為掺雜劑的製程(2)、及供給與前述第一n型半導體層形成時同量或比它還多量的前述Si作為掺雜劑的製程(3)。
  2. 如申請專利範圍第1項之半導體發光元件之製造方法，其中藉由連同前述再成長層的原料氣體一起供給含有前述Si之掺雜劑氣體，形成前述再成長層。
  3. 如申請專利範圍第1或2項之半導體發光元件之製造方法，其中與開始形成前述再成長層同時地或是從形成途中開始前述製程(2)。
  4. 如申請專利範圍第1或2項之半導體發光元件之製造方法，其中在前述製程(2)之前述掺雜劑氣體的供給量係前述第一n型半導體層形成時的0~1/15倍，在前述製程(3)之前述掺雜劑氣體的供給量係前述第一n型半導體層形成時的1~4倍。
  5. 如申請專利範圍第1或2項之半導體發光元件之製造方法，其中將前述再成長層的膜厚定為0.1μm~3.5μm。
  6. 如申請專利範圍第1或2項之半導體發光元件之製造方法，其中在前述製程(2)中形成膜厚0.05μm~0.5μm的再成長層第二層，在前述製程(3)中形成膜厚0.05μm~1μm的再成長層第三層。
  7. 如申請專利範圍第1或2項之半導體發光元件之製造方法，其中在積層前述再成長層的製程中，在前述製程(2)之前，進行將前述再成長層的成長條件定為與前述第一n型半導體層形成時相同的條件的製程(1)。
  8. 如申請專利範圍第7項之半導體發光元件之製造方法，其中在前述製程(1)中形成膜厚2μm以下的再成長層第一層，在前述製程(2)中形成膜厚0.05μm~0.5μm的再成長層第二層，在前述製程(3)中形成膜厚0.05μm~1μm的再成長層第三層。
  9. 如申請專利範圍第6項之半導體發光元件之製造方法，其中前述再成長層之中，使前述再成長層第二層含有濃度低於1×1017 /cm3 的前述Si，使前述再成長層第三層含有濃度5×1018 /cm3 以上的前述Si。
  10. 如申請專利範圍第8項之半導體發光元件之製造方法，其中前述再成長層之中，使前述再成長層第二層含有濃度低於1×1017 /cm3 的前述Si，使前述再成長層第三層含有濃度5×1018 /cm3 以上的前述Si。
  11. 如申請專利範圍第1或2項之半導體發光元件之製造方 法，其中藉由積層p接觸下層、及p接觸上層來形成前述p接觸層，使前述p接觸下層含有濃度1×1019 ~1×1020 /cm3 左右的Mg，使前述p接觸上層含有濃度1×1020 /cm3 ~3×1020 /cm3 左右的Mg。
  12. 一種半導體發光元件，係在基板上積層有在第一有機金屬化學氣相成長裝置中所積層的第一n型半導體層、和在與前述第一有機金屬化學氣相成長裝置不同的第二有機金屬化學氣相成長裝置所積層的前述第一n型半導體層之再成長層、第二n型半導體層、發光層、及由p包覆層和p接觸層所構成之p型半導體層的半導體發光元件，其特徵為前述再成長層的構成係依序積層：含Si量比前述第一n型半導體層還少之再成長層第二層、及含Si量比前述第一n型半導體層還多之再成長層第三層。
  13. 如申請專利範圍第12項之半導體發光元件，其中前述再成長層之中，分別以0.05μm~0.5μm、及0.05μm~1μm的膜厚形成前述再成長層第二層、及前述再成長層第三層。
  14. 如申請專利範圍第12項之半導體發光元件，其中前述再成長層係將含Si量與第一n型半導體層相同之再成長層第一層，積層在前述再成長層第二層的與前述再成長層第三層的相反側的構成。
  15. 如申請專利範圍第14項之半導體發光元件，其中前述再成長層之中，分別以2μm以下、0.05μm~0.5μm、及0.05 μm~1μm的膜厚形成前述再成長層第一層、前述再成長層第二層、及前述再成長層第三層。
  16. 如申請專利範圍第12至15項中任一項之半導體發光元件，其中前述再成長層之中，使前述再成長層第二層含有濃度低於1×1017 /cm3 的前述Si，使前述再成長層第三層含有濃度5×1018 /cm3 以上的前述Si。
  17. 如申請專利範圍第12至15項中任一項之半導體發光元件，其中前述再成長層的膜厚為0.1μm~3μm。
  18. 如申請專利範圍第12至15項中任一項之半導體發光元件，其中前述p接觸層係積層p接觸下層、及p接觸上層所構成，使前述p接觸下層含有濃度1×1019 ~1×1020 /cm3 左右的Mg，使前述p接觸上層含有濃度1×1020 /cm3 ~3×1020 /cm3 的Mg。
  19. 一種燈，其特徵為具備如申請專利範圍第12至18項中任一項之半導體發光元件。
  20. 一種電子機器，其特徵為組裝有如申請專利範圍第19項之燈。
  21. 一種機械裝置，其特徵為組裝有如申請專利範圍第20項之電子機器。
TW100103059A 2010-02-18 2011-01-27 半導體發光元件之製造方法及半導體發光元件、燈、電子機器、機械裝置 TWI456786B (zh)

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TW472011B (en) * 1999-11-24 2002-01-11 Shimano Kk Bicycle display unit with backlight
US20030205711A1 (en) * 2000-07-03 2003-11-06 Koji Tanizawa N-type nitride semiconductor laminate and semiconductor device using same
US6906352B2 (en) * 2001-01-16 2005-06-14 Cree, Inc. Group III nitride LED with undoped cladding layer and multiple quantum well
US6914272B2 (en) * 1998-06-05 2005-07-05 Lumileds Lighting U.S., Llc Formation of Ohmic contacts in III-nitride light emitting devices
CN100576586C (zh) * 2005-04-07 2009-12-30 昭和电工株式会社 制造ⅲ族氮化物半导体元件的方法

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JP3753793B2 (ja) * 1996-06-14 2006-03-08 豊田合成株式会社 ３族窒化物化合物半導体発光素子
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US6914272B2 (en) * 1998-06-05 2005-07-05 Lumileds Lighting U.S., Llc Formation of Ohmic contacts in III-nitride light emitting devices
TW472011B (en) * 1999-11-24 2002-01-11 Shimano Kk Bicycle display unit with backlight
US20030205711A1 (en) * 2000-07-03 2003-11-06 Koji Tanizawa N-type nitride semiconductor laminate and semiconductor device using same
US6906352B2 (en) * 2001-01-16 2005-06-14 Cree, Inc. Group III nitride LED with undoped cladding layer and multiple quantum well
CN100576586C (zh) * 2005-04-07 2009-12-30 昭和电工株式会社 制造ⅲ族氮化物半导体元件的方法

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